1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3*4882a593Smuzhiyun * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4*4882a593Smuzhiyun * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Permission to use, copy, modify, and distribute this software for any
7*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above
8*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /**************\
21*4882a593Smuzhiyun * Capabilities *
22*4882a593Smuzhiyun \**************/
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "ath5k.h"
25*4882a593Smuzhiyun #include "reg.h"
26*4882a593Smuzhiyun #include "debug.h"
27*4882a593Smuzhiyun #include "../regd.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Fill the capabilities struct
31*4882a593Smuzhiyun * TODO: Merge this with EEPROM code when we are done with it
32*4882a593Smuzhiyun */
ath5k_hw_set_capabilities(struct ath5k_hw * ah)33*4882a593Smuzhiyun int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct ath5k_capabilities *caps = &ah->ah_capabilities;
36*4882a593Smuzhiyun u16 ee_header;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Capabilities stored in the EEPROM */
39*4882a593Smuzhiyun ee_header = caps->cap_eeprom.ee_header;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (ah->ah_version == AR5K_AR5210) {
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * Set radio capabilities
44*4882a593Smuzhiyun * (The AR5110 only supports the middle 5GHz band)
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun caps->cap_range.range_5ghz_min = 5120;
47*4882a593Smuzhiyun caps->cap_range.range_5ghz_max = 5430;
48*4882a593Smuzhiyun caps->cap_range.range_2ghz_min = 0;
49*4882a593Smuzhiyun caps->cap_range.range_2ghz_max = 0;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Set supported modes */
52*4882a593Smuzhiyun __set_bit(AR5K_MODE_11A, caps->cap_mode);
53*4882a593Smuzhiyun } else {
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * XXX The transceiver supports frequencies from 4920 to 6100MHz
56*4882a593Smuzhiyun * XXX and from 2312 to 2732MHz. There are problems with the
57*4882a593Smuzhiyun * XXX current ieee80211 implementation because the IEEE
58*4882a593Smuzhiyun * XXX channel mapping does not support negative channel
59*4882a593Smuzhiyun * XXX numbers (2312MHz is channel -19). Of course, this
60*4882a593Smuzhiyun * XXX doesn't matter because these channels are out of the
61*4882a593Smuzhiyun * XXX legal range.
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Set radio capabilities
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (AR5K_EEPROM_HDR_11A(ee_header)) {
69*4882a593Smuzhiyun if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain))
70*4882a593Smuzhiyun caps->cap_range.range_5ghz_min = 4920;
71*4882a593Smuzhiyun else
72*4882a593Smuzhiyun caps->cap_range.range_5ghz_min = 5005;
73*4882a593Smuzhiyun caps->cap_range.range_5ghz_max = 6100;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Set supported modes */
76*4882a593Smuzhiyun __set_bit(AR5K_MODE_11A, caps->cap_mode);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
80*4882a593Smuzhiyun * connected */
81*4882a593Smuzhiyun if (AR5K_EEPROM_HDR_11B(ee_header) ||
82*4882a593Smuzhiyun (AR5K_EEPROM_HDR_11G(ee_header) &&
83*4882a593Smuzhiyun ah->ah_version != AR5K_AR5211)) {
84*4882a593Smuzhiyun /* 2312 */
85*4882a593Smuzhiyun caps->cap_range.range_2ghz_min = 2412;
86*4882a593Smuzhiyun caps->cap_range.range_2ghz_max = 2732;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Override 2GHz modes on SoCs that need it
89*4882a593Smuzhiyun * NOTE: cap_needs_2GHz_ovr gets set from
90*4882a593Smuzhiyun * ath_ahb_probe */
91*4882a593Smuzhiyun if (!caps->cap_needs_2GHz_ovr) {
92*4882a593Smuzhiyun if (AR5K_EEPROM_HDR_11B(ee_header))
93*4882a593Smuzhiyun __set_bit(AR5K_MODE_11B,
94*4882a593Smuzhiyun caps->cap_mode);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (AR5K_EEPROM_HDR_11G(ee_header) &&
97*4882a593Smuzhiyun ah->ah_version != AR5K_AR5211)
98*4882a593Smuzhiyun __set_bit(AR5K_MODE_11G,
99*4882a593Smuzhiyun caps->cap_mode);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if ((ah->ah_radio_5ghz_revision & 0xf0) == AR5K_SREV_RAD_2112)
105*4882a593Smuzhiyun __clear_bit(AR5K_MODE_11A, caps->cap_mode);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Set number of supported TX queues */
108*4882a593Smuzhiyun if (ah->ah_version == AR5K_AR5210)
109*4882a593Smuzhiyun caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
110*4882a593Smuzhiyun else
111*4882a593Smuzhiyun caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Newer hardware has PHY error counters */
114*4882a593Smuzhiyun if (ah->ah_mac_srev >= AR5K_SREV_AR5213A)
115*4882a593Smuzhiyun caps->cap_has_phyerr_counters = true;
116*4882a593Smuzhiyun else
117*4882a593Smuzhiyun caps->cap_has_phyerr_counters = false;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* MACs since AR5212 have MRR support */
120*4882a593Smuzhiyun if (ah->ah_version == AR5K_AR5212)
121*4882a593Smuzhiyun caps->cap_has_mrr_support = true;
122*4882a593Smuzhiyun else
123*4882a593Smuzhiyun caps->cap_has_mrr_support = false;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /*
129*4882a593Smuzhiyun * TODO: Following functions should be part of a new function
130*4882a593Smuzhiyun * set_capability
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun
ath5k_hw_enable_pspoll(struct ath5k_hw * ah,u8 * bssid,u16 assoc_id)133*4882a593Smuzhiyun int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
134*4882a593Smuzhiyun u16 assoc_id)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun if (ah->ah_version == AR5K_AR5210) {
137*4882a593Smuzhiyun AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
138*4882a593Smuzhiyun AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
139*4882a593Smuzhiyun return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return -EIO;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
ath5k_hw_disable_pspoll(struct ath5k_hw * ah)145*4882a593Smuzhiyun int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun if (ah->ah_version == AR5K_AR5210) {
148*4882a593Smuzhiyun AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
149*4882a593Smuzhiyun AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun return -EIO;
154*4882a593Smuzhiyun }
155