xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath11k/wmi.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef ATH11K_WMI_H
7*4882a593Smuzhiyun #define ATH11K_WMI_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <net/mac80211.h>
10*4882a593Smuzhiyun #include "htc.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun struct ath11k_base;
13*4882a593Smuzhiyun struct ath11k;
14*4882a593Smuzhiyun struct ath11k_fw_stats;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define PSOC_HOST_MAX_NUM_SS (8)
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* defines to set Packet extension values whic can be 0 us, 8 usec or 16 usec */
19*4882a593Smuzhiyun #define MAX_HE_NSS               8
20*4882a593Smuzhiyun #define MAX_HE_MODULATION        8
21*4882a593Smuzhiyun #define MAX_HE_RU                4
22*4882a593Smuzhiyun #define HE_MODULATION_NONE       7
23*4882a593Smuzhiyun #define HE_PET_0_USEC            0
24*4882a593Smuzhiyun #define HE_PET_8_USEC            1
25*4882a593Smuzhiyun #define HE_PET_16_USEC           2
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define WMI_MAX_CHAINS		 8
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define WMI_MAX_NUM_SS                    MAX_HE_NSS
30*4882a593Smuzhiyun #define WMI_MAX_NUM_RU                    MAX_HE_RU
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1)
33*4882a593Smuzhiyun #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1)
34*4882a593Smuzhiyun #define WMI_TLV_CMD_UNSUPPORTED 0
35*4882a593Smuzhiyun #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0
36*4882a593Smuzhiyun #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct wmi_cmd_hdr {
39*4882a593Smuzhiyun 	u32 cmd_id;
40*4882a593Smuzhiyun } __packed;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun struct wmi_tlv {
43*4882a593Smuzhiyun 	u32 header;
44*4882a593Smuzhiyun 	u8 value[];
45*4882a593Smuzhiyun } __packed;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define WMI_TLV_LEN	GENMASK(15, 0)
48*4882a593Smuzhiyun #define WMI_TLV_TAG	GENMASK(31, 16)
49*4882a593Smuzhiyun #define TLV_HDR_SIZE	sizeof_field(struct wmi_tlv, header)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define WMI_CMD_HDR_CMD_ID      GENMASK(23, 0)
52*4882a593Smuzhiyun #define WMI_MAX_MEM_REQS        32
53*4882a593Smuzhiyun #define ATH11K_MAX_HW_LISTEN_INTERVAL 5
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define WLAN_SCAN_MAX_HINT_S_SSID        10
56*4882a593Smuzhiyun #define WLAN_SCAN_MAX_HINT_BSSID         10
57*4882a593Smuzhiyun #define MAX_RNR_BSS                    5
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define WLAN_SCAN_MAX_HINT_S_SSID        10
60*4882a593Smuzhiyun #define WLAN_SCAN_MAX_HINT_BSSID         10
61*4882a593Smuzhiyun #define MAX_RNR_BSS                    5
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define WLAN_SCAN_PARAMS_MAX_SSID    16
64*4882a593Smuzhiyun #define WLAN_SCAN_PARAMS_MAX_BSSID   4
65*4882a593Smuzhiyun #define WLAN_SCAN_PARAMS_MAX_IE_LEN  256
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define WMI_BA_MODE_BUFFER_SIZE_256  3
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun  * HW mode config type replicated from FW header
72*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active.
73*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands,
74*4882a593Smuzhiyun  *                        one in 2G and another in 5G.
75*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in
76*4882a593Smuzhiyun  *                        same band; no tx allowed.
77*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band.
78*4882a593Smuzhiyun  *                        Support for both PHYs within one band is planned
79*4882a593Smuzhiyun  *                        for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES),
80*4882a593Smuzhiyun  *                        but could be extended to other bands in the future.
81*4882a593Smuzhiyun  *                        The separation of the band between the two PHYs needs
82*4882a593Smuzhiyun  *                        to be communicated separately.
83*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS
84*4882a593Smuzhiyun  *                           as in WMI_HW_MODE_SBS, and 3rd on the other band
85*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and
86*4882a593Smuzhiyun  *                        5G. It can support SBS (5G + 5G) OR DBS (5G + 2G).
87*4882a593Smuzhiyun  * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode.
88*4882a593Smuzhiyun  */
89*4882a593Smuzhiyun enum wmi_host_hw_mode_config_type {
90*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_SINGLE       = 0,
91*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_DBS          = 1,
92*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_SBS_PASSIVE  = 2,
93*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_SBS          = 3,
94*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_DBS_SBS      = 4,
95*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_DBS_OR_SBS   = 5,
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* keep last */
98*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_MAX
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* HW mode priority values used to detect the preferred HW mode
102*4882a593Smuzhiyun  * on the available modes.
103*4882a593Smuzhiyun  */
104*4882a593Smuzhiyun enum wmi_host_hw_mode_priority {
105*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_DBS_SBS_PRI,
106*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_DBS_PRI,
107*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_DBS_OR_SBS_PRI,
108*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_SBS_PRI,
109*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_SBS_PASSIVE_PRI,
110*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_SINGLE_PRI,
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	/* keep last the lowest priority */
113*4882a593Smuzhiyun 	WMI_HOST_HW_MODE_MAX_PRI
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun enum {
117*4882a593Smuzhiyun 	WMI_HOST_WLAN_2G_CAP	= 0x1,
118*4882a593Smuzhiyun 	WMI_HOST_WLAN_5G_CAP	= 0x2,
119*4882a593Smuzhiyun 	WMI_HOST_WLAN_2G_5G_CAP	= 0x3,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /*
123*4882a593Smuzhiyun  * wmi command groups.
124*4882a593Smuzhiyun  */
125*4882a593Smuzhiyun enum wmi_cmd_group {
126*4882a593Smuzhiyun 	/* 0 to 2 are reserved */
127*4882a593Smuzhiyun 	WMI_GRP_START = 0x3,
128*4882a593Smuzhiyun 	WMI_GRP_SCAN = WMI_GRP_START,
129*4882a593Smuzhiyun 	WMI_GRP_PDEV		= 0x4,
130*4882a593Smuzhiyun 	WMI_GRP_VDEV           = 0x5,
131*4882a593Smuzhiyun 	WMI_GRP_PEER           = 0x6,
132*4882a593Smuzhiyun 	WMI_GRP_MGMT           = 0x7,
133*4882a593Smuzhiyun 	WMI_GRP_BA_NEG         = 0x8,
134*4882a593Smuzhiyun 	WMI_GRP_STA_PS         = 0x9,
135*4882a593Smuzhiyun 	WMI_GRP_DFS            = 0xa,
136*4882a593Smuzhiyun 	WMI_GRP_ROAM           = 0xb,
137*4882a593Smuzhiyun 	WMI_GRP_OFL_SCAN       = 0xc,
138*4882a593Smuzhiyun 	WMI_GRP_P2P            = 0xd,
139*4882a593Smuzhiyun 	WMI_GRP_AP_PS          = 0xe,
140*4882a593Smuzhiyun 	WMI_GRP_RATE_CTRL      = 0xf,
141*4882a593Smuzhiyun 	WMI_GRP_PROFILE        = 0x10,
142*4882a593Smuzhiyun 	WMI_GRP_SUSPEND        = 0x11,
143*4882a593Smuzhiyun 	WMI_GRP_BCN_FILTER     = 0x12,
144*4882a593Smuzhiyun 	WMI_GRP_WOW            = 0x13,
145*4882a593Smuzhiyun 	WMI_GRP_RTT            = 0x14,
146*4882a593Smuzhiyun 	WMI_GRP_SPECTRAL       = 0x15,
147*4882a593Smuzhiyun 	WMI_GRP_STATS          = 0x16,
148*4882a593Smuzhiyun 	WMI_GRP_ARP_NS_OFL     = 0x17,
149*4882a593Smuzhiyun 	WMI_GRP_NLO_OFL        = 0x18,
150*4882a593Smuzhiyun 	WMI_GRP_GTK_OFL        = 0x19,
151*4882a593Smuzhiyun 	WMI_GRP_CSA_OFL        = 0x1a,
152*4882a593Smuzhiyun 	WMI_GRP_CHATTER        = 0x1b,
153*4882a593Smuzhiyun 	WMI_GRP_TID_ADDBA      = 0x1c,
154*4882a593Smuzhiyun 	WMI_GRP_MISC           = 0x1d,
155*4882a593Smuzhiyun 	WMI_GRP_GPIO           = 0x1e,
156*4882a593Smuzhiyun 	WMI_GRP_FWTEST         = 0x1f,
157*4882a593Smuzhiyun 	WMI_GRP_TDLS           = 0x20,
158*4882a593Smuzhiyun 	WMI_GRP_RESMGR         = 0x21,
159*4882a593Smuzhiyun 	WMI_GRP_STA_SMPS       = 0x22,
160*4882a593Smuzhiyun 	WMI_GRP_WLAN_HB        = 0x23,
161*4882a593Smuzhiyun 	WMI_GRP_RMC            = 0x24,
162*4882a593Smuzhiyun 	WMI_GRP_MHF_OFL        = 0x25,
163*4882a593Smuzhiyun 	WMI_GRP_LOCATION_SCAN  = 0x26,
164*4882a593Smuzhiyun 	WMI_GRP_OEM            = 0x27,
165*4882a593Smuzhiyun 	WMI_GRP_NAN            = 0x28,
166*4882a593Smuzhiyun 	WMI_GRP_COEX           = 0x29,
167*4882a593Smuzhiyun 	WMI_GRP_OBSS_OFL       = 0x2a,
168*4882a593Smuzhiyun 	WMI_GRP_LPI            = 0x2b,
169*4882a593Smuzhiyun 	WMI_GRP_EXTSCAN        = 0x2c,
170*4882a593Smuzhiyun 	WMI_GRP_DHCP_OFL       = 0x2d,
171*4882a593Smuzhiyun 	WMI_GRP_IPA            = 0x2e,
172*4882a593Smuzhiyun 	WMI_GRP_MDNS_OFL       = 0x2f,
173*4882a593Smuzhiyun 	WMI_GRP_SAP_OFL        = 0x30,
174*4882a593Smuzhiyun 	WMI_GRP_OCB            = 0x31,
175*4882a593Smuzhiyun 	WMI_GRP_SOC            = 0x32,
176*4882a593Smuzhiyun 	WMI_GRP_PKT_FILTER     = 0x33,
177*4882a593Smuzhiyun 	WMI_GRP_MAWC           = 0x34,
178*4882a593Smuzhiyun 	WMI_GRP_PMF_OFFLOAD    = 0x35,
179*4882a593Smuzhiyun 	WMI_GRP_BPF_OFFLOAD    = 0x36,
180*4882a593Smuzhiyun 	WMI_GRP_NAN_DATA       = 0x37,
181*4882a593Smuzhiyun 	WMI_GRP_PROTOTYPE      = 0x38,
182*4882a593Smuzhiyun 	WMI_GRP_MONITOR        = 0x39,
183*4882a593Smuzhiyun 	WMI_GRP_REGULATORY     = 0x3a,
184*4882a593Smuzhiyun 	WMI_GRP_HW_DATA_FILTER = 0x3b,
185*4882a593Smuzhiyun 	WMI_GRP_WLM            = 0x3c,
186*4882a593Smuzhiyun 	WMI_GRP_11K_OFFLOAD    = 0x3d,
187*4882a593Smuzhiyun 	WMI_GRP_TWT            = 0x3e,
188*4882a593Smuzhiyun 	WMI_GRP_MOTION_DET     = 0x3f,
189*4882a593Smuzhiyun 	WMI_GRP_SPATIAL_REUSE  = 0x40,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
193*4882a593Smuzhiyun #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun #define WMI_CMD_UNSUPPORTED 0
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun enum wmi_tlv_cmd_id {
198*4882a593Smuzhiyun 	WMI_INIT_CMDID = 0x1,
199*4882a593Smuzhiyun 	WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN),
200*4882a593Smuzhiyun 	WMI_STOP_SCAN_CMDID,
201*4882a593Smuzhiyun 	WMI_SCAN_CHAN_LIST_CMDID,
202*4882a593Smuzhiyun 	WMI_SCAN_SCH_PRIO_TBL_CMDID,
203*4882a593Smuzhiyun 	WMI_SCAN_UPDATE_REQUEST_CMDID,
204*4882a593Smuzhiyun 	WMI_SCAN_PROB_REQ_OUI_CMDID,
205*4882a593Smuzhiyun 	WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID,
206*4882a593Smuzhiyun 	WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV),
207*4882a593Smuzhiyun 	WMI_PDEV_SET_CHANNEL_CMDID,
208*4882a593Smuzhiyun 	WMI_PDEV_SET_PARAM_CMDID,
209*4882a593Smuzhiyun 	WMI_PDEV_PKTLOG_ENABLE_CMDID,
210*4882a593Smuzhiyun 	WMI_PDEV_PKTLOG_DISABLE_CMDID,
211*4882a593Smuzhiyun 	WMI_PDEV_SET_WMM_PARAMS_CMDID,
212*4882a593Smuzhiyun 	WMI_PDEV_SET_HT_CAP_IE_CMDID,
213*4882a593Smuzhiyun 	WMI_PDEV_SET_VHT_CAP_IE_CMDID,
214*4882a593Smuzhiyun 	WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
215*4882a593Smuzhiyun 	WMI_PDEV_SET_QUIET_MODE_CMDID,
216*4882a593Smuzhiyun 	WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
217*4882a593Smuzhiyun 	WMI_PDEV_GET_TPC_CONFIG_CMDID,
218*4882a593Smuzhiyun 	WMI_PDEV_SET_BASE_MACADDR_CMDID,
219*4882a593Smuzhiyun 	WMI_PDEV_DUMP_CMDID,
220*4882a593Smuzhiyun 	WMI_PDEV_SET_LED_CONFIG_CMDID,
221*4882a593Smuzhiyun 	WMI_PDEV_GET_TEMPERATURE_CMDID,
222*4882a593Smuzhiyun 	WMI_PDEV_SET_LED_FLASHING_CMDID,
223*4882a593Smuzhiyun 	WMI_PDEV_SMART_ANT_ENABLE_CMDID,
224*4882a593Smuzhiyun 	WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
225*4882a593Smuzhiyun 	WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
226*4882a593Smuzhiyun 	WMI_PDEV_SET_CTL_TABLE_CMDID,
227*4882a593Smuzhiyun 	WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID,
228*4882a593Smuzhiyun 	WMI_PDEV_FIPS_CMDID,
229*4882a593Smuzhiyun 	WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID,
230*4882a593Smuzhiyun 	WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID,
231*4882a593Smuzhiyun 	WMI_PDEV_GET_NFCAL_POWER_CMDID,
232*4882a593Smuzhiyun 	WMI_PDEV_GET_TPC_CMDID,
233*4882a593Smuzhiyun 	WMI_MIB_STATS_ENABLE_CMDID,
234*4882a593Smuzhiyun 	WMI_PDEV_SET_PCL_CMDID,
235*4882a593Smuzhiyun 	WMI_PDEV_SET_HW_MODE_CMDID,
236*4882a593Smuzhiyun 	WMI_PDEV_SET_MAC_CONFIG_CMDID,
237*4882a593Smuzhiyun 	WMI_PDEV_SET_ANTENNA_MODE_CMDID,
238*4882a593Smuzhiyun 	WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID,
239*4882a593Smuzhiyun 	WMI_PDEV_WAL_POWER_DEBUG_CMDID,
240*4882a593Smuzhiyun 	WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID,
241*4882a593Smuzhiyun 	WMI_PDEV_SET_WAKEUP_CONFIG_CMDID,
242*4882a593Smuzhiyun 	WMI_PDEV_GET_ANTDIV_STATUS_CMDID,
243*4882a593Smuzhiyun 	WMI_PDEV_GET_CHIP_POWER_STATS_CMDID,
244*4882a593Smuzhiyun 	WMI_PDEV_SET_STATS_THRESHOLD_CMDID,
245*4882a593Smuzhiyun 	WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID,
246*4882a593Smuzhiyun 	WMI_PDEV_UPDATE_PKT_ROUTING_CMDID,
247*4882a593Smuzhiyun 	WMI_PDEV_CHECK_CAL_VERSION_CMDID,
248*4882a593Smuzhiyun 	WMI_PDEV_SET_DIVERSITY_GAIN_CMDID,
249*4882a593Smuzhiyun 	WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID,
250*4882a593Smuzhiyun 	WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
251*4882a593Smuzhiyun 	WMI_PDEV_UPDATE_PMK_CACHE_CMDID,
252*4882a593Smuzhiyun 	WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID,
253*4882a593Smuzhiyun 	WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID,
254*4882a593Smuzhiyun 	WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID,
255*4882a593Smuzhiyun 	WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID,
256*4882a593Smuzhiyun 	WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID,
257*4882a593Smuzhiyun 	WMI_PDEV_DMA_RING_CFG_REQ_CMDID,
258*4882a593Smuzhiyun 	WMI_PDEV_HE_TB_ACTION_FRM_CMDID,
259*4882a593Smuzhiyun 	WMI_PDEV_PKTLOG_FILTER_CMDID,
260*4882a593Smuzhiyun 	WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV),
261*4882a593Smuzhiyun 	WMI_VDEV_DELETE_CMDID,
262*4882a593Smuzhiyun 	WMI_VDEV_START_REQUEST_CMDID,
263*4882a593Smuzhiyun 	WMI_VDEV_RESTART_REQUEST_CMDID,
264*4882a593Smuzhiyun 	WMI_VDEV_UP_CMDID,
265*4882a593Smuzhiyun 	WMI_VDEV_STOP_CMDID,
266*4882a593Smuzhiyun 	WMI_VDEV_DOWN_CMDID,
267*4882a593Smuzhiyun 	WMI_VDEV_SET_PARAM_CMDID,
268*4882a593Smuzhiyun 	WMI_VDEV_INSTALL_KEY_CMDID,
269*4882a593Smuzhiyun 	WMI_VDEV_WNM_SLEEPMODE_CMDID,
270*4882a593Smuzhiyun 	WMI_VDEV_WMM_ADDTS_CMDID,
271*4882a593Smuzhiyun 	WMI_VDEV_WMM_DELTS_CMDID,
272*4882a593Smuzhiyun 	WMI_VDEV_SET_WMM_PARAMS_CMDID,
273*4882a593Smuzhiyun 	WMI_VDEV_SET_GTX_PARAMS_CMDID,
274*4882a593Smuzhiyun 	WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID,
275*4882a593Smuzhiyun 	WMI_VDEV_PLMREQ_START_CMDID,
276*4882a593Smuzhiyun 	WMI_VDEV_PLMREQ_STOP_CMDID,
277*4882a593Smuzhiyun 	WMI_VDEV_TSF_TSTAMP_ACTION_CMDID,
278*4882a593Smuzhiyun 	WMI_VDEV_SET_IE_CMDID,
279*4882a593Smuzhiyun 	WMI_VDEV_RATEMASK_CMDID,
280*4882a593Smuzhiyun 	WMI_VDEV_ATF_REQUEST_CMDID,
281*4882a593Smuzhiyun 	WMI_VDEV_SET_DSCP_TID_MAP_CMDID,
282*4882a593Smuzhiyun 	WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID,
283*4882a593Smuzhiyun 	WMI_VDEV_SET_QUIET_MODE_CMDID,
284*4882a593Smuzhiyun 	WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID,
285*4882a593Smuzhiyun 	WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID,
286*4882a593Smuzhiyun 	WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID,
287*4882a593Smuzhiyun 	WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER),
288*4882a593Smuzhiyun 	WMI_PEER_DELETE_CMDID,
289*4882a593Smuzhiyun 	WMI_PEER_FLUSH_TIDS_CMDID,
290*4882a593Smuzhiyun 	WMI_PEER_SET_PARAM_CMDID,
291*4882a593Smuzhiyun 	WMI_PEER_ASSOC_CMDID,
292*4882a593Smuzhiyun 	WMI_PEER_ADD_WDS_ENTRY_CMDID,
293*4882a593Smuzhiyun 	WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
294*4882a593Smuzhiyun 	WMI_PEER_MCAST_GROUP_CMDID,
295*4882a593Smuzhiyun 	WMI_PEER_INFO_REQ_CMDID,
296*4882a593Smuzhiyun 	WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID,
297*4882a593Smuzhiyun 	WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID,
298*4882a593Smuzhiyun 	WMI_PEER_UPDATE_WDS_ENTRY_CMDID,
299*4882a593Smuzhiyun 	WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID,
300*4882a593Smuzhiyun 	WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
301*4882a593Smuzhiyun 	WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
302*4882a593Smuzhiyun 	WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
303*4882a593Smuzhiyun 	WMI_PEER_ATF_REQUEST_CMDID,
304*4882a593Smuzhiyun 	WMI_PEER_BWF_REQUEST_CMDID,
305*4882a593Smuzhiyun 	WMI_PEER_REORDER_QUEUE_SETUP_CMDID,
306*4882a593Smuzhiyun 	WMI_PEER_REORDER_QUEUE_REMOVE_CMDID,
307*4882a593Smuzhiyun 	WMI_PEER_SET_RX_BLOCKSIZE_CMDID,
308*4882a593Smuzhiyun 	WMI_PEER_ANTDIV_INFO_REQ_CMDID,
309*4882a593Smuzhiyun 	WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT),
310*4882a593Smuzhiyun 	WMI_PDEV_SEND_BCN_CMDID,
311*4882a593Smuzhiyun 	WMI_BCN_TMPL_CMDID,
312*4882a593Smuzhiyun 	WMI_BCN_FILTER_RX_CMDID,
313*4882a593Smuzhiyun 	WMI_PRB_REQ_FILTER_RX_CMDID,
314*4882a593Smuzhiyun 	WMI_MGMT_TX_CMDID,
315*4882a593Smuzhiyun 	WMI_PRB_TMPL_CMDID,
316*4882a593Smuzhiyun 	WMI_MGMT_TX_SEND_CMDID,
317*4882a593Smuzhiyun 	WMI_OFFCHAN_DATA_TX_SEND_CMDID,
318*4882a593Smuzhiyun 	WMI_PDEV_SEND_FD_CMDID,
319*4882a593Smuzhiyun 	WMI_BCN_OFFLOAD_CTRL_CMDID,
320*4882a593Smuzhiyun 	WMI_BSS_COLOR_CHANGE_ENABLE_CMDID,
321*4882a593Smuzhiyun 	WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID,
322*4882a593Smuzhiyun 	WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
323*4882a593Smuzhiyun 	WMI_ADDBA_SEND_CMDID,
324*4882a593Smuzhiyun 	WMI_ADDBA_STATUS_CMDID,
325*4882a593Smuzhiyun 	WMI_DELBA_SEND_CMDID,
326*4882a593Smuzhiyun 	WMI_ADDBA_SET_RESP_CMDID,
327*4882a593Smuzhiyun 	WMI_SEND_SINGLEAMSDU_CMDID,
328*4882a593Smuzhiyun 	WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS),
329*4882a593Smuzhiyun 	WMI_STA_POWERSAVE_PARAM_CMDID,
330*4882a593Smuzhiyun 	WMI_STA_MIMO_PS_MODE_CMDID,
331*4882a593Smuzhiyun 	WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS),
332*4882a593Smuzhiyun 	WMI_PDEV_DFS_DISABLE_CMDID,
333*4882a593Smuzhiyun 	WMI_DFS_PHYERR_FILTER_ENA_CMDID,
334*4882a593Smuzhiyun 	WMI_DFS_PHYERR_FILTER_DIS_CMDID,
335*4882a593Smuzhiyun 	WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID,
336*4882a593Smuzhiyun 	WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID,
337*4882a593Smuzhiyun 	WMI_VDEV_ADFS_CH_CFG_CMDID,
338*4882a593Smuzhiyun 	WMI_VDEV_ADFS_OCAC_ABORT_CMDID,
339*4882a593Smuzhiyun 	WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM),
340*4882a593Smuzhiyun 	WMI_ROAM_SCAN_RSSI_THRESHOLD,
341*4882a593Smuzhiyun 	WMI_ROAM_SCAN_PERIOD,
342*4882a593Smuzhiyun 	WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
343*4882a593Smuzhiyun 	WMI_ROAM_AP_PROFILE,
344*4882a593Smuzhiyun 	WMI_ROAM_CHAN_LIST,
345*4882a593Smuzhiyun 	WMI_ROAM_SCAN_CMD,
346*4882a593Smuzhiyun 	WMI_ROAM_SYNCH_COMPLETE,
347*4882a593Smuzhiyun 	WMI_ROAM_SET_RIC_REQUEST_CMDID,
348*4882a593Smuzhiyun 	WMI_ROAM_INVOKE_CMDID,
349*4882a593Smuzhiyun 	WMI_ROAM_FILTER_CMDID,
350*4882a593Smuzhiyun 	WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID,
351*4882a593Smuzhiyun 	WMI_ROAM_CONFIGURE_MAWC_CMDID,
352*4882a593Smuzhiyun 	WMI_ROAM_SET_MBO_PARAM_CMDID,
353*4882a593Smuzhiyun 	WMI_ROAM_PER_CONFIG_CMDID,
354*4882a593Smuzhiyun 	WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN),
355*4882a593Smuzhiyun 	WMI_OFL_SCAN_REMOVE_AP_PROFILE,
356*4882a593Smuzhiyun 	WMI_OFL_SCAN_PERIOD,
357*4882a593Smuzhiyun 	WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P),
358*4882a593Smuzhiyun 	WMI_P2P_DEV_SET_DISCOVERABILITY,
359*4882a593Smuzhiyun 	WMI_P2P_GO_SET_BEACON_IE,
360*4882a593Smuzhiyun 	WMI_P2P_GO_SET_PROBE_RESP_IE,
361*4882a593Smuzhiyun 	WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
362*4882a593Smuzhiyun 	WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID,
363*4882a593Smuzhiyun 	WMI_P2P_DISC_OFFLOAD_APPIE_CMDID,
364*4882a593Smuzhiyun 	WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID,
365*4882a593Smuzhiyun 	WMI_P2P_SET_OPPPS_PARAM_CMDID,
366*4882a593Smuzhiyun 	WMI_P2P_LISTEN_OFFLOAD_START_CMDID,
367*4882a593Smuzhiyun 	WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID,
368*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS),
369*4882a593Smuzhiyun 	WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
370*4882a593Smuzhiyun 	WMI_AP_PS_EGAP_PARAM_CMDID,
371*4882a593Smuzhiyun 	WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL),
372*4882a593Smuzhiyun 	WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE),
373*4882a593Smuzhiyun 	WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
374*4882a593Smuzhiyun 	WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
375*4882a593Smuzhiyun 	WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
376*4882a593Smuzhiyun 	WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
377*4882a593Smuzhiyun 	WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
378*4882a593Smuzhiyun 	WMI_PDEV_RESUME_CMDID,
379*4882a593Smuzhiyun 	WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER),
380*4882a593Smuzhiyun 	WMI_RMV_BCN_FILTER_CMDID,
381*4882a593Smuzhiyun 	WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW),
382*4882a593Smuzhiyun 	WMI_WOW_DEL_WAKE_PATTERN_CMDID,
383*4882a593Smuzhiyun 	WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
384*4882a593Smuzhiyun 	WMI_WOW_ENABLE_CMDID,
385*4882a593Smuzhiyun 	WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
386*4882a593Smuzhiyun 	WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID,
387*4882a593Smuzhiyun 	WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID,
388*4882a593Smuzhiyun 	WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID,
389*4882a593Smuzhiyun 	WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID,
390*4882a593Smuzhiyun 	WMI_D0_WOW_ENABLE_DISABLE_CMDID,
391*4882a593Smuzhiyun 	WMI_EXTWOW_ENABLE_CMDID,
392*4882a593Smuzhiyun 	WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID,
393*4882a593Smuzhiyun 	WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID,
394*4882a593Smuzhiyun 	WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID,
395*4882a593Smuzhiyun 	WMI_WOW_UDP_SVC_OFLD_CMDID,
396*4882a593Smuzhiyun 	WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID,
397*4882a593Smuzhiyun 	WMI_WOW_SET_ACTION_WAKE_UP_CMDID,
398*4882a593Smuzhiyun 	WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT),
399*4882a593Smuzhiyun 	WMI_RTT_TSF_CMDID,
400*4882a593Smuzhiyun 	WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL),
401*4882a593Smuzhiyun 	WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
402*4882a593Smuzhiyun 	WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS),
403*4882a593Smuzhiyun 	WMI_MCC_SCHED_TRAFFIC_STATS_CMDID,
404*4882a593Smuzhiyun 	WMI_REQUEST_STATS_EXT_CMDID,
405*4882a593Smuzhiyun 	WMI_REQUEST_LINK_STATS_CMDID,
406*4882a593Smuzhiyun 	WMI_START_LINK_STATS_CMDID,
407*4882a593Smuzhiyun 	WMI_CLEAR_LINK_STATS_CMDID,
408*4882a593Smuzhiyun 	WMI_GET_FW_MEM_DUMP_CMDID,
409*4882a593Smuzhiyun 	WMI_DEBUG_MESG_FLUSH_CMDID,
410*4882a593Smuzhiyun 	WMI_DIAG_EVENT_LOG_CONFIG_CMDID,
411*4882a593Smuzhiyun 	WMI_REQUEST_WLAN_STATS_CMDID,
412*4882a593Smuzhiyun 	WMI_REQUEST_RCPI_CMDID,
413*4882a593Smuzhiyun 	WMI_REQUEST_PEER_STATS_INFO_CMDID,
414*4882a593Smuzhiyun 	WMI_REQUEST_RADIO_CHAN_STATS_CMDID,
415*4882a593Smuzhiyun 	WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL),
416*4882a593Smuzhiyun 	WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID,
417*4882a593Smuzhiyun 	WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID,
418*4882a593Smuzhiyun 	WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
419*4882a593Smuzhiyun 	WMI_APFIND_CMDID,
420*4882a593Smuzhiyun 	WMI_PASSPOINT_LIST_CONFIG_CMDID,
421*4882a593Smuzhiyun 	WMI_NLO_CONFIGURE_MAWC_CMDID,
422*4882a593Smuzhiyun 	WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
423*4882a593Smuzhiyun 	WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
424*4882a593Smuzhiyun 	WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
425*4882a593Smuzhiyun 	WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER),
426*4882a593Smuzhiyun 	WMI_CHATTER_ADD_COALESCING_FILTER_CMDID,
427*4882a593Smuzhiyun 	WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID,
428*4882a593Smuzhiyun 	WMI_CHATTER_COALESCING_QUERY_CMDID,
429*4882a593Smuzhiyun 	WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA),
430*4882a593Smuzhiyun 	WMI_PEER_TID_DELBA_CMDID,
431*4882a593Smuzhiyun 	WMI_STA_DTIM_PS_METHOD_CMDID,
432*4882a593Smuzhiyun 	WMI_STA_UAPSD_AUTO_TRIG_CMDID,
433*4882a593Smuzhiyun 	WMI_STA_KEEPALIVE_CMDID,
434*4882a593Smuzhiyun 	WMI_BA_REQ_SSN_CMDID,
435*4882a593Smuzhiyun 	WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC),
436*4882a593Smuzhiyun 	WMI_PDEV_UTF_CMDID,
437*4882a593Smuzhiyun 	WMI_DBGLOG_CFG_CMDID,
438*4882a593Smuzhiyun 	WMI_PDEV_QVIT_CMDID,
439*4882a593Smuzhiyun 	WMI_PDEV_FTM_INTG_CMDID,
440*4882a593Smuzhiyun 	WMI_VDEV_SET_KEEPALIVE_CMDID,
441*4882a593Smuzhiyun 	WMI_VDEV_GET_KEEPALIVE_CMDID,
442*4882a593Smuzhiyun 	WMI_FORCE_FW_HANG_CMDID,
443*4882a593Smuzhiyun 	WMI_SET_MCASTBCAST_FILTER_CMDID,
444*4882a593Smuzhiyun 	WMI_THERMAL_MGMT_CMDID,
445*4882a593Smuzhiyun 	WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID,
446*4882a593Smuzhiyun 	WMI_TPC_CHAINMASK_CONFIG_CMDID,
447*4882a593Smuzhiyun 	WMI_SET_ANTENNA_DIVERSITY_CMDID,
448*4882a593Smuzhiyun 	WMI_OCB_SET_SCHED_CMDID,
449*4882a593Smuzhiyun 	WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID,
450*4882a593Smuzhiyun 	WMI_LRO_CONFIG_CMDID,
451*4882a593Smuzhiyun 	WMI_TRANSFER_DATA_TO_FLASH_CMDID,
452*4882a593Smuzhiyun 	WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID,
453*4882a593Smuzhiyun 	WMI_VDEV_WISA_CMDID,
454*4882a593Smuzhiyun 	WMI_DBGLOG_TIME_STAMP_SYNC_CMDID,
455*4882a593Smuzhiyun 	WMI_SET_MULTIPLE_MCAST_FILTER_CMDID,
456*4882a593Smuzhiyun 	WMI_READ_DATA_FROM_FLASH_CMDID,
457*4882a593Smuzhiyun 	WMI_THERM_THROT_SET_CONF_CMDID,
458*4882a593Smuzhiyun 	WMI_RUNTIME_DPD_RECAL_CMDID,
459*4882a593Smuzhiyun 	WMI_GET_TPC_POWER_CMDID,
460*4882a593Smuzhiyun 	WMI_IDLE_TRIGGER_MONITOR_CMDID,
461*4882a593Smuzhiyun 	WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO),
462*4882a593Smuzhiyun 	WMI_GPIO_OUTPUT_CMDID,
463*4882a593Smuzhiyun 	WMI_TXBF_CMDID,
464*4882a593Smuzhiyun 	WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST),
465*4882a593Smuzhiyun 	WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID,
466*4882a593Smuzhiyun 	WMI_UNIT_TEST_CMDID,
467*4882a593Smuzhiyun 	WMI_FWTEST_CMDID,
468*4882a593Smuzhiyun 	WMI_QBOOST_CFG_CMDID,
469*4882a593Smuzhiyun 	WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS),
470*4882a593Smuzhiyun 	WMI_TDLS_PEER_UPDATE_CMDID,
471*4882a593Smuzhiyun 	WMI_TDLS_SET_OFFCHAN_MODE_CMDID,
472*4882a593Smuzhiyun 	WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR),
473*4882a593Smuzhiyun 	WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID,
474*4882a593Smuzhiyun 	WMI_RESMGR_SET_CHAN_LATENCY_CMDID,
475*4882a593Smuzhiyun 	WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
476*4882a593Smuzhiyun 	WMI_STA_SMPS_PARAM_CMDID,
477*4882a593Smuzhiyun 	WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB),
478*4882a593Smuzhiyun 	WMI_HB_SET_TCP_PARAMS_CMDID,
479*4882a593Smuzhiyun 	WMI_HB_SET_TCP_PKT_FILTER_CMDID,
480*4882a593Smuzhiyun 	WMI_HB_SET_UDP_PARAMS_CMDID,
481*4882a593Smuzhiyun 	WMI_HB_SET_UDP_PKT_FILTER_CMDID,
482*4882a593Smuzhiyun 	WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC),
483*4882a593Smuzhiyun 	WMI_RMC_SET_ACTION_PERIOD_CMDID,
484*4882a593Smuzhiyun 	WMI_RMC_CONFIG_CMDID,
485*4882a593Smuzhiyun 	WMI_RMC_SET_MANUAL_LEADER_CMDID,
486*4882a593Smuzhiyun 	WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL),
487*4882a593Smuzhiyun 	WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID,
488*4882a593Smuzhiyun 	WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
489*4882a593Smuzhiyun 	WMI_BATCH_SCAN_DISABLE_CMDID,
490*4882a593Smuzhiyun 	WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID,
491*4882a593Smuzhiyun 	WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM),
492*4882a593Smuzhiyun 	WMI_OEM_REQUEST_CMDID,
493*4882a593Smuzhiyun 	WMI_LPI_OEM_REQ_CMDID,
494*4882a593Smuzhiyun 	WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN),
495*4882a593Smuzhiyun 	WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX),
496*4882a593Smuzhiyun 	WMI_CHAN_AVOID_UPDATE_CMDID,
497*4882a593Smuzhiyun 	WMI_COEX_CONFIG_CMDID,
498*4882a593Smuzhiyun 	WMI_CHAN_AVOID_RPT_ALLOW_CMDID,
499*4882a593Smuzhiyun 	WMI_COEX_GET_ANTENNA_ISOLATION_CMDID,
500*4882a593Smuzhiyun 	WMI_SAR_LIMITS_CMDID,
501*4882a593Smuzhiyun 	WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL),
502*4882a593Smuzhiyun 	WMI_OBSS_SCAN_DISABLE_CMDID,
503*4882a593Smuzhiyun 	WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID,
504*4882a593Smuzhiyun 	WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI),
505*4882a593Smuzhiyun 	WMI_LPI_START_SCAN_CMDID,
506*4882a593Smuzhiyun 	WMI_LPI_STOP_SCAN_CMDID,
507*4882a593Smuzhiyun 	WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
508*4882a593Smuzhiyun 	WMI_EXTSCAN_STOP_CMDID,
509*4882a593Smuzhiyun 	WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID,
510*4882a593Smuzhiyun 	WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID,
511*4882a593Smuzhiyun 	WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID,
512*4882a593Smuzhiyun 	WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID,
513*4882a593Smuzhiyun 	WMI_EXTSCAN_SET_CAPABILITIES_CMDID,
514*4882a593Smuzhiyun 	WMI_EXTSCAN_GET_CAPABILITIES_CMDID,
515*4882a593Smuzhiyun 	WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID,
516*4882a593Smuzhiyun 	WMI_EXTSCAN_CONFIGURE_MAWC_CMDID,
517*4882a593Smuzhiyun 	WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL),
518*4882a593Smuzhiyun 	WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA),
519*4882a593Smuzhiyun 	WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
520*4882a593Smuzhiyun 	WMI_MDNS_SET_FQDN_CMDID,
521*4882a593Smuzhiyun 	WMI_MDNS_SET_RESPONSE_CMDID,
522*4882a593Smuzhiyun 	WMI_MDNS_GET_STATS_CMDID,
523*4882a593Smuzhiyun 	WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
524*4882a593Smuzhiyun 	WMI_SAP_SET_BLACKLIST_PARAM_CMDID,
525*4882a593Smuzhiyun 	WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB),
526*4882a593Smuzhiyun 	WMI_OCB_SET_UTC_TIME_CMDID,
527*4882a593Smuzhiyun 	WMI_OCB_START_TIMING_ADVERT_CMDID,
528*4882a593Smuzhiyun 	WMI_OCB_STOP_TIMING_ADVERT_CMDID,
529*4882a593Smuzhiyun 	WMI_OCB_GET_TSF_TIMER_CMDID,
530*4882a593Smuzhiyun 	WMI_DCC_GET_STATS_CMDID,
531*4882a593Smuzhiyun 	WMI_DCC_CLEAR_STATS_CMDID,
532*4882a593Smuzhiyun 	WMI_DCC_UPDATE_NDL_CMDID,
533*4882a593Smuzhiyun 	WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC),
534*4882a593Smuzhiyun 	WMI_SOC_SET_HW_MODE_CMDID,
535*4882a593Smuzhiyun 	WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID,
536*4882a593Smuzhiyun 	WMI_SOC_SET_ANTENNA_MODE_CMDID,
537*4882a593Smuzhiyun 	WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER),
538*4882a593Smuzhiyun 	WMI_PACKET_FILTER_ENABLE_CMDID,
539*4882a593Smuzhiyun 	WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC),
540*4882a593Smuzhiyun 	WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD),
541*4882a593Smuzhiyun 	WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
542*4882a593Smuzhiyun 	WMI_BPF_GET_VDEV_STATS_CMDID,
543*4882a593Smuzhiyun 	WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID,
544*4882a593Smuzhiyun 	WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID,
545*4882a593Smuzhiyun 	WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID,
546*4882a593Smuzhiyun 	WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR),
547*4882a593Smuzhiyun 	WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
548*4882a593Smuzhiyun 	WMI_11D_SCAN_START_CMDID,
549*4882a593Smuzhiyun 	WMI_11D_SCAN_STOP_CMDID,
550*4882a593Smuzhiyun 	WMI_SET_INIT_COUNTRY_CMDID,
551*4882a593Smuzhiyun 	WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
552*4882a593Smuzhiyun 	WMI_NDP_INITIATOR_REQ_CMDID,
553*4882a593Smuzhiyun 	WMI_NDP_RESPONDER_REQ_CMDID,
554*4882a593Smuzhiyun 	WMI_NDP_END_REQ_CMDID,
555*4882a593Smuzhiyun 	WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER),
556*4882a593Smuzhiyun 	WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT),
557*4882a593Smuzhiyun 	WMI_TWT_DISABLE_CMDID,
558*4882a593Smuzhiyun 	WMI_TWT_ADD_DIALOG_CMDID,
559*4882a593Smuzhiyun 	WMI_TWT_DEL_DIALOG_CMDID,
560*4882a593Smuzhiyun 	WMI_TWT_PAUSE_DIALOG_CMDID,
561*4882a593Smuzhiyun 	WMI_TWT_RESUME_DIALOG_CMDID,
562*4882a593Smuzhiyun 	WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID =
563*4882a593Smuzhiyun 				WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE),
564*4882a593Smuzhiyun 	WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID,
565*4882a593Smuzhiyun };
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun enum wmi_tlv_event_id {
568*4882a593Smuzhiyun 	WMI_SERVICE_READY_EVENTID = 0x1,
569*4882a593Smuzhiyun 	WMI_READY_EVENTID,
570*4882a593Smuzhiyun 	WMI_SERVICE_AVAILABLE_EVENTID,
571*4882a593Smuzhiyun 	WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
572*4882a593Smuzhiyun 	WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV),
573*4882a593Smuzhiyun 	WMI_CHAN_INFO_EVENTID,
574*4882a593Smuzhiyun 	WMI_PHYERR_EVENTID,
575*4882a593Smuzhiyun 	WMI_PDEV_DUMP_EVENTID,
576*4882a593Smuzhiyun 	WMI_TX_PAUSE_EVENTID,
577*4882a593Smuzhiyun 	WMI_DFS_RADAR_EVENTID,
578*4882a593Smuzhiyun 	WMI_PDEV_L1SS_TRACK_EVENTID,
579*4882a593Smuzhiyun 	WMI_PDEV_TEMPERATURE_EVENTID,
580*4882a593Smuzhiyun 	WMI_SERVICE_READY_EXT_EVENTID,
581*4882a593Smuzhiyun 	WMI_PDEV_FIPS_EVENTID,
582*4882a593Smuzhiyun 	WMI_PDEV_CHANNEL_HOPPING_EVENTID,
583*4882a593Smuzhiyun 	WMI_PDEV_ANI_CCK_LEVEL_EVENTID,
584*4882a593Smuzhiyun 	WMI_PDEV_ANI_OFDM_LEVEL_EVENTID,
585*4882a593Smuzhiyun 	WMI_PDEV_TPC_EVENTID,
586*4882a593Smuzhiyun 	WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
587*4882a593Smuzhiyun 	WMI_PDEV_SET_HW_MODE_RESP_EVENTID,
588*4882a593Smuzhiyun 	WMI_PDEV_HW_MODE_TRANSITION_EVENTID,
589*4882a593Smuzhiyun 	WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID,
590*4882a593Smuzhiyun 	WMI_PDEV_ANTDIV_STATUS_EVENTID,
591*4882a593Smuzhiyun 	WMI_PDEV_CHIP_POWER_STATS_EVENTID,
592*4882a593Smuzhiyun 	WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID,
593*4882a593Smuzhiyun 	WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID,
594*4882a593Smuzhiyun 	WMI_PDEV_CHECK_CAL_VERSION_EVENTID,
595*4882a593Smuzhiyun 	WMI_PDEV_DIV_RSSI_ANTID_EVENTID,
596*4882a593Smuzhiyun 	WMI_PDEV_BSS_CHAN_INFO_EVENTID,
597*4882a593Smuzhiyun 	WMI_PDEV_UPDATE_CTLTABLE_EVENTID,
598*4882a593Smuzhiyun 	WMI_PDEV_DMA_RING_CFG_RSP_EVENTID,
599*4882a593Smuzhiyun 	WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
600*4882a593Smuzhiyun 	WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
601*4882a593Smuzhiyun 	WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
602*4882a593Smuzhiyun 	WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
603*4882a593Smuzhiyun 	WMI_PDEV_RAP_INFO_EVENTID,
604*4882a593Smuzhiyun 	WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
605*4882a593Smuzhiyun 	WMI_SERVICE_READY_EXT2_EVENTID,
606*4882a593Smuzhiyun 	WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV),
607*4882a593Smuzhiyun 	WMI_VDEV_STOPPED_EVENTID,
608*4882a593Smuzhiyun 	WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
609*4882a593Smuzhiyun 	WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID,
610*4882a593Smuzhiyun 	WMI_VDEV_TSF_REPORT_EVENTID,
611*4882a593Smuzhiyun 	WMI_VDEV_DELETE_RESP_EVENTID,
612*4882a593Smuzhiyun 	WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID,
613*4882a593Smuzhiyun 	WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID,
614*4882a593Smuzhiyun 	WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER),
615*4882a593Smuzhiyun 	WMI_PEER_INFO_EVENTID,
616*4882a593Smuzhiyun 	WMI_PEER_TX_FAIL_CNT_THR_EVENTID,
617*4882a593Smuzhiyun 	WMI_PEER_ESTIMATED_LINKSPEED_EVENTID,
618*4882a593Smuzhiyun 	WMI_PEER_STATE_EVENTID,
619*4882a593Smuzhiyun 	WMI_PEER_ASSOC_CONF_EVENTID,
620*4882a593Smuzhiyun 	WMI_PEER_DELETE_RESP_EVENTID,
621*4882a593Smuzhiyun 	WMI_PEER_RATECODE_LIST_EVENTID,
622*4882a593Smuzhiyun 	WMI_WDS_PEER_EVENTID,
623*4882a593Smuzhiyun 	WMI_PEER_STA_PS_STATECHG_EVENTID,
624*4882a593Smuzhiyun 	WMI_PEER_ANTDIV_INFO_EVENTID,
625*4882a593Smuzhiyun 	WMI_PEER_RESERVED0_EVENTID,
626*4882a593Smuzhiyun 	WMI_PEER_RESERVED1_EVENTID,
627*4882a593Smuzhiyun 	WMI_PEER_RESERVED2_EVENTID,
628*4882a593Smuzhiyun 	WMI_PEER_RESERVED3_EVENTID,
629*4882a593Smuzhiyun 	WMI_PEER_RESERVED4_EVENTID,
630*4882a593Smuzhiyun 	WMI_PEER_RESERVED5_EVENTID,
631*4882a593Smuzhiyun 	WMI_PEER_RESERVED6_EVENTID,
632*4882a593Smuzhiyun 	WMI_PEER_RESERVED7_EVENTID,
633*4882a593Smuzhiyun 	WMI_PEER_RESERVED8_EVENTID,
634*4882a593Smuzhiyun 	WMI_PEER_RESERVED9_EVENTID,
635*4882a593Smuzhiyun 	WMI_PEER_RESERVED10_EVENTID,
636*4882a593Smuzhiyun 	WMI_PEER_OPER_MODE_CHANGE_EVENTID,
637*4882a593Smuzhiyun 	WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT),
638*4882a593Smuzhiyun 	WMI_HOST_SWBA_EVENTID,
639*4882a593Smuzhiyun 	WMI_TBTTOFFSET_UPDATE_EVENTID,
640*4882a593Smuzhiyun 	WMI_OFFLOAD_BCN_TX_STATUS_EVENTID,
641*4882a593Smuzhiyun 	WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID,
642*4882a593Smuzhiyun 	WMI_MGMT_TX_COMPLETION_EVENTID,
643*4882a593Smuzhiyun 	WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID,
644*4882a593Smuzhiyun 	WMI_TBTTOFFSET_EXT_UPDATE_EVENTID,
645*4882a593Smuzhiyun 	WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
646*4882a593Smuzhiyun 	WMI_TX_ADDBA_COMPLETE_EVENTID,
647*4882a593Smuzhiyun 	WMI_BA_RSP_SSN_EVENTID,
648*4882a593Smuzhiyun 	WMI_AGGR_STATE_TRIG_EVENTID,
649*4882a593Smuzhiyun 	WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM),
650*4882a593Smuzhiyun 	WMI_PROFILE_MATCH,
651*4882a593Smuzhiyun 	WMI_ROAM_SYNCH_EVENTID,
652*4882a593Smuzhiyun 	WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P),
653*4882a593Smuzhiyun 	WMI_P2P_NOA_EVENTID,
654*4882a593Smuzhiyun 	WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID,
655*4882a593Smuzhiyun 	WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS),
656*4882a593Smuzhiyun 	WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
657*4882a593Smuzhiyun 	WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW),
658*4882a593Smuzhiyun 	WMI_D0_WOW_DISABLE_ACK_EVENTID,
659*4882a593Smuzhiyun 	WMI_WOW_INITIAL_WAKEUP_EVENTID,
660*4882a593Smuzhiyun 	WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT),
661*4882a593Smuzhiyun 	WMI_TSF_MEASUREMENT_REPORT_EVENTID,
662*4882a593Smuzhiyun 	WMI_RTT_ERROR_REPORT_EVENTID,
663*4882a593Smuzhiyun 	WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS),
664*4882a593Smuzhiyun 	WMI_IFACE_LINK_STATS_EVENTID,
665*4882a593Smuzhiyun 	WMI_PEER_LINK_STATS_EVENTID,
666*4882a593Smuzhiyun 	WMI_RADIO_LINK_STATS_EVENTID,
667*4882a593Smuzhiyun 	WMI_UPDATE_FW_MEM_DUMP_EVENTID,
668*4882a593Smuzhiyun 	WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID,
669*4882a593Smuzhiyun 	WMI_INST_RSSI_STATS_EVENTID,
670*4882a593Smuzhiyun 	WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID,
671*4882a593Smuzhiyun 	WMI_REPORT_STATS_EVENTID,
672*4882a593Smuzhiyun 	WMI_UPDATE_RCPI_EVENTID,
673*4882a593Smuzhiyun 	WMI_PEER_STATS_INFO_EVENTID,
674*4882a593Smuzhiyun 	WMI_RADIO_CHAN_STATS_EVENTID,
675*4882a593Smuzhiyun 	WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
676*4882a593Smuzhiyun 	WMI_NLO_SCAN_COMPLETE_EVENTID,
677*4882a593Smuzhiyun 	WMI_APFIND_EVENTID,
678*4882a593Smuzhiyun 	WMI_PASSPOINT_MATCH_EVENTID,
679*4882a593Smuzhiyun 	WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
680*4882a593Smuzhiyun 	WMI_GTK_REKEY_FAIL_EVENTID,
681*4882a593Smuzhiyun 	WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
682*4882a593Smuzhiyun 	WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER),
683*4882a593Smuzhiyun 	WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS),
684*4882a593Smuzhiyun 	WMI_VDEV_DFS_CAC_COMPLETE_EVENTID,
685*4882a593Smuzhiyun 	WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID,
686*4882a593Smuzhiyun 	WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC),
687*4882a593Smuzhiyun 	WMI_PDEV_UTF_EVENTID,
688*4882a593Smuzhiyun 	WMI_DEBUG_MESG_EVENTID,
689*4882a593Smuzhiyun 	WMI_UPDATE_STATS_EVENTID,
690*4882a593Smuzhiyun 	WMI_DEBUG_PRINT_EVENTID,
691*4882a593Smuzhiyun 	WMI_DCS_INTERFERENCE_EVENTID,
692*4882a593Smuzhiyun 	WMI_PDEV_QVIT_EVENTID,
693*4882a593Smuzhiyun 	WMI_WLAN_PROFILE_DATA_EVENTID,
694*4882a593Smuzhiyun 	WMI_PDEV_FTM_INTG_EVENTID,
695*4882a593Smuzhiyun 	WMI_WLAN_FREQ_AVOID_EVENTID,
696*4882a593Smuzhiyun 	WMI_VDEV_GET_KEEPALIVE_EVENTID,
697*4882a593Smuzhiyun 	WMI_THERMAL_MGMT_EVENTID,
698*4882a593Smuzhiyun 	WMI_DIAG_DATA_CONTAINER_EVENTID,
699*4882a593Smuzhiyun 	WMI_HOST_AUTO_SHUTDOWN_EVENTID,
700*4882a593Smuzhiyun 	WMI_UPDATE_WHAL_MIB_STATS_EVENTID,
701*4882a593Smuzhiyun 	WMI_UPDATE_VDEV_RATE_STATS_EVENTID,
702*4882a593Smuzhiyun 	WMI_DIAG_EVENTID,
703*4882a593Smuzhiyun 	WMI_OCB_SET_SCHED_EVENTID,
704*4882a593Smuzhiyun 	WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID,
705*4882a593Smuzhiyun 	WMI_RSSI_BREACH_EVENTID,
706*4882a593Smuzhiyun 	WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
707*4882a593Smuzhiyun 	WMI_PDEV_UTF_SCPC_EVENTID,
708*4882a593Smuzhiyun 	WMI_READ_DATA_FROM_FLASH_EVENTID,
709*4882a593Smuzhiyun 	WMI_REPORT_RX_AGGR_FAILURE_EVENTID,
710*4882a593Smuzhiyun 	WMI_PKGID_EVENTID,
711*4882a593Smuzhiyun 	WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO),
712*4882a593Smuzhiyun 	WMI_UPLOADH_EVENTID,
713*4882a593Smuzhiyun 	WMI_CAPTUREH_EVENTID,
714*4882a593Smuzhiyun 	WMI_RFKILL_STATE_CHANGE_EVENTID,
715*4882a593Smuzhiyun 	WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS),
716*4882a593Smuzhiyun 	WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
717*4882a593Smuzhiyun 	WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
718*4882a593Smuzhiyun 	WMI_BATCH_SCAN_RESULT_EVENTID,
719*4882a593Smuzhiyun 	WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM),
720*4882a593Smuzhiyun 	WMI_OEM_MEASUREMENT_REPORT_EVENTID,
721*4882a593Smuzhiyun 	WMI_OEM_ERROR_REPORT_EVENTID,
722*4882a593Smuzhiyun 	WMI_OEM_RESPONSE_EVENTID,
723*4882a593Smuzhiyun 	WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN),
724*4882a593Smuzhiyun 	WMI_NAN_DISC_IFACE_CREATED_EVENTID,
725*4882a593Smuzhiyun 	WMI_NAN_DISC_IFACE_DELETED_EVENTID,
726*4882a593Smuzhiyun 	WMI_NAN_STARTED_CLUSTER_EVENTID,
727*4882a593Smuzhiyun 	WMI_NAN_JOINED_CLUSTER_EVENTID,
728*4882a593Smuzhiyun 	WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX),
729*4882a593Smuzhiyun 	WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI),
730*4882a593Smuzhiyun 	WMI_LPI_STATUS_EVENTID,
731*4882a593Smuzhiyun 	WMI_LPI_HANDOFF_EVENTID,
732*4882a593Smuzhiyun 	WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
733*4882a593Smuzhiyun 	WMI_EXTSCAN_OPERATION_EVENTID,
734*4882a593Smuzhiyun 	WMI_EXTSCAN_TABLE_USAGE_EVENTID,
735*4882a593Smuzhiyun 	WMI_EXTSCAN_CACHED_RESULTS_EVENTID,
736*4882a593Smuzhiyun 	WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID,
737*4882a593Smuzhiyun 	WMI_EXTSCAN_HOTLIST_MATCH_EVENTID,
738*4882a593Smuzhiyun 	WMI_EXTSCAN_CAPABILITIES_EVENTID,
739*4882a593Smuzhiyun 	WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID,
740*4882a593Smuzhiyun 	WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
741*4882a593Smuzhiyun 	WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
742*4882a593Smuzhiyun 	WMI_SAP_OFL_DEL_STA_EVENTID,
743*4882a593Smuzhiyun 	WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB),
744*4882a593Smuzhiyun 	WMI_OCB_GET_TSF_TIMER_RESP_EVENTID,
745*4882a593Smuzhiyun 	WMI_DCC_GET_STATS_RESP_EVENTID,
746*4882a593Smuzhiyun 	WMI_DCC_UPDATE_NDL_RESP_EVENTID,
747*4882a593Smuzhiyun 	WMI_DCC_STATS_EVENTID,
748*4882a593Smuzhiyun 	WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC),
749*4882a593Smuzhiyun 	WMI_SOC_HW_MODE_TRANSITION_EVENTID,
750*4882a593Smuzhiyun 	WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID,
751*4882a593Smuzhiyun 	WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC),
752*4882a593Smuzhiyun 	WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
753*4882a593Smuzhiyun 	WMI_BPF_VDEV_STATS_INFO_EVENTID,
754*4882a593Smuzhiyun 	WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC),
755*4882a593Smuzhiyun 	WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
756*4882a593Smuzhiyun 	WMI_11D_NEW_COUNTRY_EVENTID,
757*4882a593Smuzhiyun 	WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
758*4882a593Smuzhiyun 	WMI_NDP_INITIATOR_RSP_EVENTID,
759*4882a593Smuzhiyun 	WMI_NDP_RESPONDER_RSP_EVENTID,
760*4882a593Smuzhiyun 	WMI_NDP_END_RSP_EVENTID,
761*4882a593Smuzhiyun 	WMI_NDP_INDICATION_EVENTID,
762*4882a593Smuzhiyun 	WMI_NDP_CONFIRM_EVENTID,
763*4882a593Smuzhiyun 	WMI_NDP_END_INDICATION_EVENTID,
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT),
766*4882a593Smuzhiyun 	WMI_TWT_DISABLE_EVENTID,
767*4882a593Smuzhiyun 	WMI_TWT_ADD_DIALOG_EVENTID,
768*4882a593Smuzhiyun 	WMI_TWT_DEL_DIALOG_EVENTID,
769*4882a593Smuzhiyun 	WMI_TWT_PAUSE_DIALOG_EVENTID,
770*4882a593Smuzhiyun 	WMI_TWT_RESUME_DIALOG_EVENTID,
771*4882a593Smuzhiyun };
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun enum wmi_tlv_pdev_param {
774*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
775*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RX_CHAIN_MASK,
776*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
777*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
778*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TXPOWER_SCALE,
779*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BEACON_GEN_MODE,
780*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BEACON_TX_MODE,
781*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
782*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PROTECTION_MODE,
783*4882a593Smuzhiyun 	WMI_PDEV_PARAM_DYNAMIC_BW,
784*4882a593Smuzhiyun 	WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
785*4882a593Smuzhiyun 	WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
786*4882a593Smuzhiyun 	WMI_PDEV_PARAM_STA_KICKOUT_TH,
787*4882a593Smuzhiyun 	WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
788*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_ENABLE,
789*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
790*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
791*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
792*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
793*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
794*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
795*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
796*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
797*4882a593Smuzhiyun 	WMI_PDEV_PARAM_L1SS_ENABLE,
798*4882a593Smuzhiyun 	WMI_PDEV_PARAM_DSLEEP_ENABLE,
799*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
800*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
801*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
802*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
803*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
804*4882a593Smuzhiyun 	WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
805*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
806*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
807*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PMF_QOS,
808*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
809*4882a593Smuzhiyun 	WMI_PDEV_PARAM_DCS,
810*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANI_ENABLE,
811*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANI_POLL_PERIOD,
812*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
813*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
814*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANI_CCK_LEVEL,
815*4882a593Smuzhiyun 	WMI_PDEV_PARAM_DYNTXCHAIN,
816*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PROXY_STA,
817*4882a593Smuzhiyun 	WMI_PDEV_PARAM_IDLE_PS_CONFIG,
818*4882a593Smuzhiyun 	WMI_PDEV_PARAM_POWER_GATING_SLEEP,
819*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RFKILL_ENABLE,
820*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BURST_DUR,
821*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BURST_ENABLE,
822*4882a593Smuzhiyun 	WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
823*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE,
824*4882a593Smuzhiyun 	WMI_PDEV_PARAM_L1SS_TRACK,
825*4882a593Smuzhiyun 	WMI_PDEV_PARAM_HYST_EN,
826*4882a593Smuzhiyun 	WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE,
827*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LED_SYS_STATE,
828*4882a593Smuzhiyun 	WMI_PDEV_PARAM_LED_ENABLE,
829*4882a593Smuzhiyun 	WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY,
830*4882a593Smuzhiyun 	WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE,
831*4882a593Smuzhiyun 	WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE,
832*4882a593Smuzhiyun 	WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD,
833*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CTS_CBW,
834*4882a593Smuzhiyun 	WMI_PDEV_PARAM_WNTS_CONFIG,
835*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE,
836*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP,
837*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP,
838*4882a593Smuzhiyun 	WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP,
839*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE,
840*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT,
841*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP,
842*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT,
843*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE,
844*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE,
845*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_CHAIN_MASK_2G,
846*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RX_CHAIN_MASK_2G,
847*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_CHAIN_MASK_5G,
848*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RX_CHAIN_MASK_5G,
849*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK,
850*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS,
851*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG,
852*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TXPOWER_DECR_DB,
853*4882a593Smuzhiyun 	WMI_PDEV_PARAM_AGGR_BURST,
854*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RX_DECAP_MODE,
855*4882a593Smuzhiyun 	WMI_PDEV_PARAM_FAST_CHANNEL_RESET,
856*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
857*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANTENNA_GAIN,
858*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RX_FILTER,
859*4882a593Smuzhiyun 	WMI_PDEV_SET_MCAST_TO_UCAST_TID,
860*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PROXY_STA_MODE,
861*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE,
862*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
863*4882a593Smuzhiyun 	WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
864*4882a593Smuzhiyun 	WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE,
865*4882a593Smuzhiyun 	WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE,
866*4882a593Smuzhiyun 	WMI_PDEV_PARAM_BLOCK_INTERBSS,
867*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID,
868*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID,
869*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID,
870*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID,
871*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
872*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_BURST_MODE_CMDID,
873*4882a593Smuzhiyun 	WMI_PDEV_PARAM_EN_STATS,
874*4882a593Smuzhiyun 	WMI_PDEV_PARAM_MU_GROUP_POLICY,
875*4882a593Smuzhiyun 	WMI_PDEV_PARAM_NOISE_DETECTION,
876*4882a593Smuzhiyun 	WMI_PDEV_PARAM_NOISE_THRESHOLD,
877*4882a593Smuzhiyun 	WMI_PDEV_PARAM_DPD_ENABLE,
878*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO,
879*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ATF_STRICT_SCH,
880*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ATF_SCHED_DURATION,
881*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANT_PLZN,
882*4882a593Smuzhiyun 	WMI_PDEV_PARAM_MGMT_RETRY_LIMIT,
883*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SENSITIVITY_LEVEL,
884*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SIGNED_TXPOWER_2G,
885*4882a593Smuzhiyun 	WMI_PDEV_PARAM_SIGNED_TXPOWER_5G,
886*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU,
887*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU,
888*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CCA_THRESHOLD,
889*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RTS_FIXED_RATE,
890*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PDEV_RESET,
891*4882a593Smuzhiyun 	WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET,
892*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ARP_DBG_SRCADDR,
893*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ARP_DBG_DSTADDR,
894*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH,
895*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR,
896*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CUST_TXPOWER_SCALE,
897*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
898*4882a593Smuzhiyun 	WMI_PDEV_PARAM_CTRL_RETRY_LIMIT,
899*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PROPAGATION_DELAY,
900*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ENA_ANT_DIV,
901*4882a593Smuzhiyun 	WMI_PDEV_PARAM_FORCE_CHAIN_ANT,
902*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANT_DIV_SELFTEST,
903*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL,
904*4882a593Smuzhiyun 	WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD,
905*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS,
906*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN,
907*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN,
908*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN,
909*4882a593Smuzhiyun 	WMI_PDEV_PARAM_TX_SCH_DELAY,
910*4882a593Smuzhiyun 	WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING,
911*4882a593Smuzhiyun 	WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU,
912*4882a593Smuzhiyun 	WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE,
913*4882a593Smuzhiyun 	WMI_PDEV_PARAM_FAST_PWR_TRANSITION,
914*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE,
915*4882a593Smuzhiyun 	WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE,
916*4882a593Smuzhiyun 	WMI_PDEV_PARAM_MESH_MCAST_ENABLE,
917*4882a593Smuzhiyun };
918*4882a593Smuzhiyun 
919*4882a593Smuzhiyun enum wmi_tlv_vdev_param {
920*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
921*4882a593Smuzhiyun 	WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
922*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BEACON_INTERVAL,
923*4882a593Smuzhiyun 	WMI_VDEV_PARAM_LISTEN_INTERVAL,
924*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MULTICAST_RATE,
925*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MGMT_TX_RATE,
926*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SLOT_TIME,
927*4882a593Smuzhiyun 	WMI_VDEV_PARAM_PREAMBLE,
928*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SWBA_TIME,
929*4882a593Smuzhiyun 	WMI_VDEV_STATS_UPDATE_PERIOD,
930*4882a593Smuzhiyun 	WMI_VDEV_PWRSAVE_AGEOUT_TIME,
931*4882a593Smuzhiyun 	WMI_VDEV_HOST_SWBA_INTERVAL,
932*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DTIM_PERIOD,
933*4882a593Smuzhiyun 	WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
934*4882a593Smuzhiyun 	WMI_VDEV_PARAM_WDS,
935*4882a593Smuzhiyun 	WMI_VDEV_PARAM_ATIM_WINDOW,
936*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BMISS_COUNT_MAX,
937*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
938*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
939*4882a593Smuzhiyun 	WMI_VDEV_PARAM_FEATURE_WMM,
940*4882a593Smuzhiyun 	WMI_VDEV_PARAM_CHWIDTH,
941*4882a593Smuzhiyun 	WMI_VDEV_PARAM_CHEXTOFFSET,
942*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
943*4882a593Smuzhiyun 	WMI_VDEV_PARAM_STA_QUICKKICKOUT,
944*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MGMT_RATE,
945*4882a593Smuzhiyun 	WMI_VDEV_PARAM_PROTECTION_MODE,
946*4882a593Smuzhiyun 	WMI_VDEV_PARAM_FIXED_RATE,
947*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SGI,
948*4882a593Smuzhiyun 	WMI_VDEV_PARAM_LDPC,
949*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TX_STBC,
950*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RX_STBC,
951*4882a593Smuzhiyun 	WMI_VDEV_PARAM_INTRA_BSS_FWD,
952*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DEF_KEYID,
953*4882a593Smuzhiyun 	WMI_VDEV_PARAM_NSS,
954*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BCAST_DATA_RATE,
955*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MCAST_DATA_RATE,
956*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MCAST_INDICATE,
957*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DHCP_INDICATE,
958*4882a593Smuzhiyun 	WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
959*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
960*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
961*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
962*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
963*4882a593Smuzhiyun 	WMI_VDEV_PARAM_ENABLE_RTSCTS,
964*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TXBF,
965*4882a593Smuzhiyun 	WMI_VDEV_PARAM_PACKET_POWERSAVE,
966*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DROP_UNENCRY,
967*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TX_ENCAP_TYPE,
968*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
969*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE,
970*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM,
971*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE,
972*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP,
973*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP,
974*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE,
975*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TX_PWRLIMIT,
976*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SNR_NUM_FOR_CAL,
977*4882a593Smuzhiyun 	WMI_VDEV_PARAM_ROAM_FW_OFFLOAD,
978*4882a593Smuzhiyun 	WMI_VDEV_PARAM_ENABLE_RMC,
979*4882a593Smuzhiyun 	WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS,
980*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MAX_RATE,
981*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE,
982*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR,
983*4882a593Smuzhiyun 	WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT,
984*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE,
985*4882a593Smuzhiyun 	WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED,
986*4882a593Smuzhiyun 	WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED,
987*4882a593Smuzhiyun 	WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED,
988*4882a593Smuzhiyun 	WMI_VDEV_PARAM_INACTIVITY_CNT,
989*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS,
990*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DTIM_POLICY,
991*4882a593Smuzhiyun 	WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS,
992*4882a593Smuzhiyun 	WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE,
993*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RX_LEAK_WINDOW,
994*4882a593Smuzhiyun 	WMI_VDEV_PARAM_STATS_AVG_FACTOR,
995*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DISCONNECT_TH,
996*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RTSCTS_RATE,
997*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE,
998*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE,
999*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TXPOWER_SCALE,
1000*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB,
1001*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MCAST2UCAST_SET,
1002*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RC_NUM_RETRIES,
1003*4882a593Smuzhiyun 	WMI_VDEV_PARAM_CABQ_MAXDUR,
1004*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MFPTEST_SET,
1005*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RTS_FIXED_RATE,
1006*4882a593Smuzhiyun 	WMI_VDEV_PARAM_VHT_SGIMASK,
1007*4882a593Smuzhiyun 	WMI_VDEV_PARAM_VHT80_RATEMASK,
1008*4882a593Smuzhiyun 	WMI_VDEV_PARAM_PROXY_STA,
1009*4882a593Smuzhiyun 	WMI_VDEV_PARAM_VIRTUAL_CELL_MODE,
1010*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RX_DECAP_TYPE,
1011*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BW_NSS_RATEMASK,
1012*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SENSOR_AP,
1013*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BEACON_RATE,
1014*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DTIM_ENABLE_CTS,
1015*4882a593Smuzhiyun 	WMI_VDEV_PARAM_STA_KICKOUT,
1016*4882a593Smuzhiyun 	WMI_VDEV_PARAM_CAPABILITIES,
1017*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TSF_INCREMENT,
1018*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AMPDU_PER_AC,
1019*4882a593Smuzhiyun 	WMI_VDEV_PARAM_RX_FILTER,
1020*4882a593Smuzhiyun 	WMI_VDEV_PARAM_MGMT_TX_POWER,
1021*4882a593Smuzhiyun 	WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH,
1022*4882a593Smuzhiyun 	WMI_VDEV_PARAM_AGG_SW_RETRY_TH,
1023*4882a593Smuzhiyun 	WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS,
1024*4882a593Smuzhiyun 	WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY,
1025*4882a593Smuzhiyun 	WMI_VDEV_PARAM_HE_DCM,
1026*4882a593Smuzhiyun 	WMI_VDEV_PARAM_HE_RANGE_EXT,
1027*4882a593Smuzhiyun 	WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE,
1028*4882a593Smuzhiyun 	WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME,
1029*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BA_MODE = 0x7e,
1030*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87,
1031*4882a593Smuzhiyun 	WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99,
1032*4882a593Smuzhiyun 	WMI_VDEV_PARAM_PROTOTYPE = 0x8000,
1033*4882a593Smuzhiyun 	WMI_VDEV_PARAM_BSS_COLOR,
1034*4882a593Smuzhiyun 	WMI_VDEV_PARAM_SET_HEMU_MODE,
1035*4882a593Smuzhiyun 	WMI_VDEV_PARAM_TX_OFDMA_CPLEN,
1036*4882a593Smuzhiyun };
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun enum wmi_tlv_peer_flags {
1039*4882a593Smuzhiyun 	WMI_TLV_PEER_AUTH = 0x00000001,
1040*4882a593Smuzhiyun 	WMI_TLV_PEER_QOS = 0x00000002,
1041*4882a593Smuzhiyun 	WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004,
1042*4882a593Smuzhiyun 	WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010,
1043*4882a593Smuzhiyun 	WMI_TLV_PEER_APSD = 0x00000800,
1044*4882a593Smuzhiyun 	WMI_TLV_PEER_HT = 0x00001000,
1045*4882a593Smuzhiyun 	WMI_TLV_PEER_40MHZ = 0x00002000,
1046*4882a593Smuzhiyun 	WMI_TLV_PEER_STBC = 0x00008000,
1047*4882a593Smuzhiyun 	WMI_TLV_PEER_LDPC = 0x00010000,
1048*4882a593Smuzhiyun 	WMI_TLV_PEER_DYN_MIMOPS = 0x00020000,
1049*4882a593Smuzhiyun 	WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000,
1050*4882a593Smuzhiyun 	WMI_TLV_PEER_SPATIAL_MUX = 0x00200000,
1051*4882a593Smuzhiyun 	WMI_TLV_PEER_VHT = 0x02000000,
1052*4882a593Smuzhiyun 	WMI_TLV_PEER_80MHZ = 0x04000000,
1053*4882a593Smuzhiyun 	WMI_TLV_PEER_PMF = 0x08000000,
1054*4882a593Smuzhiyun 	WMI_PEER_IS_P2P_CAPABLE = 0x20000000,
1055*4882a593Smuzhiyun 	WMI_PEER_160MHZ         = 0x40000000,
1056*4882a593Smuzhiyun 	WMI_PEER_SAFEMODE_EN    = 0x80000000,
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun };
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun /** Enum list of TLV Tags for each parameter structure type. */
1061*4882a593Smuzhiyun enum wmi_tlv_tag {
1062*4882a593Smuzhiyun 	WMI_TAG_LAST_RESERVED = 15,
1063*4882a593Smuzhiyun 	WMI_TAG_FIRST_ARRAY_ENUM,
1064*4882a593Smuzhiyun 	WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM,
1065*4882a593Smuzhiyun 	WMI_TAG_ARRAY_BYTE,
1066*4882a593Smuzhiyun 	WMI_TAG_ARRAY_STRUCT,
1067*4882a593Smuzhiyun 	WMI_TAG_ARRAY_FIXED_STRUCT,
1068*4882a593Smuzhiyun 	WMI_TAG_LAST_ARRAY_ENUM = 31,
1069*4882a593Smuzhiyun 	WMI_TAG_SERVICE_READY_EVENT,
1070*4882a593Smuzhiyun 	WMI_TAG_HAL_REG_CAPABILITIES,
1071*4882a593Smuzhiyun 	WMI_TAG_WLAN_HOST_MEM_REQ,
1072*4882a593Smuzhiyun 	WMI_TAG_READY_EVENT,
1073*4882a593Smuzhiyun 	WMI_TAG_SCAN_EVENT,
1074*4882a593Smuzhiyun 	WMI_TAG_PDEV_TPC_CONFIG_EVENT,
1075*4882a593Smuzhiyun 	WMI_TAG_CHAN_INFO_EVENT,
1076*4882a593Smuzhiyun 	WMI_TAG_COMB_PHYERR_RX_HDR,
1077*4882a593Smuzhiyun 	WMI_TAG_VDEV_START_RESPONSE_EVENT,
1078*4882a593Smuzhiyun 	WMI_TAG_VDEV_STOPPED_EVENT,
1079*4882a593Smuzhiyun 	WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT,
1080*4882a593Smuzhiyun 	WMI_TAG_PEER_STA_KICKOUT_EVENT,
1081*4882a593Smuzhiyun 	WMI_TAG_MGMT_RX_HDR,
1082*4882a593Smuzhiyun 	WMI_TAG_TBTT_OFFSET_EVENT,
1083*4882a593Smuzhiyun 	WMI_TAG_TX_DELBA_COMPLETE_EVENT,
1084*4882a593Smuzhiyun 	WMI_TAG_TX_ADDBA_COMPLETE_EVENT,
1085*4882a593Smuzhiyun 	WMI_TAG_ROAM_EVENT,
1086*4882a593Smuzhiyun 	WMI_TAG_WOW_EVENT_INFO,
1087*4882a593Smuzhiyun 	WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP,
1088*4882a593Smuzhiyun 	WMI_TAG_RTT_EVENT_HEADER,
1089*4882a593Smuzhiyun 	WMI_TAG_RTT_ERROR_REPORT_EVENT,
1090*4882a593Smuzhiyun 	WMI_TAG_RTT_MEAS_EVENT,
1091*4882a593Smuzhiyun 	WMI_TAG_ECHO_EVENT,
1092*4882a593Smuzhiyun 	WMI_TAG_FTM_INTG_EVENT,
1093*4882a593Smuzhiyun 	WMI_TAG_VDEV_GET_KEEPALIVE_EVENT,
1094*4882a593Smuzhiyun 	WMI_TAG_GPIO_INPUT_EVENT,
1095*4882a593Smuzhiyun 	WMI_TAG_CSA_EVENT,
1096*4882a593Smuzhiyun 	WMI_TAG_GTK_OFFLOAD_STATUS_EVENT,
1097*4882a593Smuzhiyun 	WMI_TAG_IGTK_INFO,
1098*4882a593Smuzhiyun 	WMI_TAG_DCS_INTERFERENCE_EVENT,
1099*4882a593Smuzhiyun 	WMI_TAG_ATH_DCS_CW_INT,
1100*4882a593Smuzhiyun 	WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */
1101*4882a593Smuzhiyun 		WMI_TAG_ATH_DCS_CW_INT,
1102*4882a593Smuzhiyun 	WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1103*4882a593Smuzhiyun 	WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */
1104*4882a593Smuzhiyun 		WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1105*4882a593Smuzhiyun 	WMI_TAG_WLAN_PROFILE_CTX_T,
1106*4882a593Smuzhiyun 	WMI_TAG_WLAN_PROFILE_T,
1107*4882a593Smuzhiyun 	WMI_TAG_PDEV_QVIT_EVENT,
1108*4882a593Smuzhiyun 	WMI_TAG_HOST_SWBA_EVENT,
1109*4882a593Smuzhiyun 	WMI_TAG_TIM_INFO,
1110*4882a593Smuzhiyun 	WMI_TAG_P2P_NOA_INFO,
1111*4882a593Smuzhiyun 	WMI_TAG_STATS_EVENT,
1112*4882a593Smuzhiyun 	WMI_TAG_AVOID_FREQ_RANGES_EVENT,
1113*4882a593Smuzhiyun 	WMI_TAG_AVOID_FREQ_RANGE_DESC,
1114*4882a593Smuzhiyun 	WMI_TAG_GTK_REKEY_FAIL_EVENT,
1115*4882a593Smuzhiyun 	WMI_TAG_INIT_CMD,
1116*4882a593Smuzhiyun 	WMI_TAG_RESOURCE_CONFIG,
1117*4882a593Smuzhiyun 	WMI_TAG_WLAN_HOST_MEMORY_CHUNK,
1118*4882a593Smuzhiyun 	WMI_TAG_START_SCAN_CMD,
1119*4882a593Smuzhiyun 	WMI_TAG_STOP_SCAN_CMD,
1120*4882a593Smuzhiyun 	WMI_TAG_SCAN_CHAN_LIST_CMD,
1121*4882a593Smuzhiyun 	WMI_TAG_CHANNEL,
1122*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_REGDOMAIN_CMD,
1123*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_PARAM_CMD,
1124*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_WMM_PARAMS_CMD,
1125*4882a593Smuzhiyun 	WMI_TAG_WMM_PARAMS,
1126*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_QUIET_CMD,
1127*4882a593Smuzhiyun 	WMI_TAG_VDEV_CREATE_CMD,
1128*4882a593Smuzhiyun 	WMI_TAG_VDEV_DELETE_CMD,
1129*4882a593Smuzhiyun 	WMI_TAG_VDEV_START_REQUEST_CMD,
1130*4882a593Smuzhiyun 	WMI_TAG_P2P_NOA_DESCRIPTOR,
1131*4882a593Smuzhiyun 	WMI_TAG_P2P_GO_SET_BEACON_IE,
1132*4882a593Smuzhiyun 	WMI_TAG_GTK_OFFLOAD_CMD,
1133*4882a593Smuzhiyun 	WMI_TAG_VDEV_UP_CMD,
1134*4882a593Smuzhiyun 	WMI_TAG_VDEV_STOP_CMD,
1135*4882a593Smuzhiyun 	WMI_TAG_VDEV_DOWN_CMD,
1136*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_PARAM_CMD,
1137*4882a593Smuzhiyun 	WMI_TAG_VDEV_INSTALL_KEY_CMD,
1138*4882a593Smuzhiyun 	WMI_TAG_PEER_CREATE_CMD,
1139*4882a593Smuzhiyun 	WMI_TAG_PEER_DELETE_CMD,
1140*4882a593Smuzhiyun 	WMI_TAG_PEER_FLUSH_TIDS_CMD,
1141*4882a593Smuzhiyun 	WMI_TAG_PEER_SET_PARAM_CMD,
1142*4882a593Smuzhiyun 	WMI_TAG_PEER_ASSOC_COMPLETE_CMD,
1143*4882a593Smuzhiyun 	WMI_TAG_VHT_RATE_SET,
1144*4882a593Smuzhiyun 	WMI_TAG_BCN_TMPL_CMD,
1145*4882a593Smuzhiyun 	WMI_TAG_PRB_TMPL_CMD,
1146*4882a593Smuzhiyun 	WMI_TAG_BCN_PRB_INFO,
1147*4882a593Smuzhiyun 	WMI_TAG_PEER_TID_ADDBA_CMD,
1148*4882a593Smuzhiyun 	WMI_TAG_PEER_TID_DELBA_CMD,
1149*4882a593Smuzhiyun 	WMI_TAG_STA_POWERSAVE_MODE_CMD,
1150*4882a593Smuzhiyun 	WMI_TAG_STA_POWERSAVE_PARAM_CMD,
1151*4882a593Smuzhiyun 	WMI_TAG_STA_DTIM_PS_METHOD_CMD,
1152*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_MODE,
1153*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD,
1154*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_PERIOD,
1155*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
1156*4882a593Smuzhiyun 	WMI_TAG_PDEV_SUSPEND_CMD,
1157*4882a593Smuzhiyun 	WMI_TAG_PDEV_RESUME_CMD,
1158*4882a593Smuzhiyun 	WMI_TAG_ADD_BCN_FILTER_CMD,
1159*4882a593Smuzhiyun 	WMI_TAG_RMV_BCN_FILTER_CMD,
1160*4882a593Smuzhiyun 	WMI_TAG_WOW_ENABLE_CMD,
1161*4882a593Smuzhiyun 	WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD,
1162*4882a593Smuzhiyun 	WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD,
1163*4882a593Smuzhiyun 	WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM,
1164*4882a593Smuzhiyun 	WMI_TAG_SET_ARP_NS_OFFLOAD_CMD,
1165*4882a593Smuzhiyun 	WMI_TAG_ARP_OFFLOAD_TUPLE,
1166*4882a593Smuzhiyun 	WMI_TAG_NS_OFFLOAD_TUPLE,
1167*4882a593Smuzhiyun 	WMI_TAG_FTM_INTG_CMD,
1168*4882a593Smuzhiyun 	WMI_TAG_STA_KEEPALIVE_CMD,
1169*4882a593Smuzhiyun 	WMI_TAG_STA_KEEPALVE_ARP_RESPONSE,
1170*4882a593Smuzhiyun 	WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD,
1171*4882a593Smuzhiyun 	WMI_TAG_AP_PS_PEER_CMD,
1172*4882a593Smuzhiyun 	WMI_TAG_PEER_RATE_RETRY_SCHED_CMD,
1173*4882a593Smuzhiyun 	WMI_TAG_WLAN_PROFILE_TRIGGER_CMD,
1174*4882a593Smuzhiyun 	WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD,
1175*4882a593Smuzhiyun 	WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD,
1176*4882a593Smuzhiyun 	WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD,
1177*4882a593Smuzhiyun 	WMI_TAG_WOW_DEL_PATTERN_CMD,
1178*4882a593Smuzhiyun 	WMI_TAG_WOW_ADD_DEL_EVT_CMD,
1179*4882a593Smuzhiyun 	WMI_TAG_RTT_MEASREQ_HEAD,
1180*4882a593Smuzhiyun 	WMI_TAG_RTT_MEASREQ_BODY,
1181*4882a593Smuzhiyun 	WMI_TAG_RTT_TSF_CMD,
1182*4882a593Smuzhiyun 	WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD,
1183*4882a593Smuzhiyun 	WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD,
1184*4882a593Smuzhiyun 	WMI_TAG_REQUEST_STATS_CMD,
1185*4882a593Smuzhiyun 	WMI_TAG_NLO_CONFIG_CMD,
1186*4882a593Smuzhiyun 	WMI_TAG_NLO_CONFIGURED_PARAMETERS,
1187*4882a593Smuzhiyun 	WMI_TAG_CSA_OFFLOAD_ENABLE_CMD,
1188*4882a593Smuzhiyun 	WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD,
1189*4882a593Smuzhiyun 	WMI_TAG_CHATTER_SET_MODE_CMD,
1190*4882a593Smuzhiyun 	WMI_TAG_ECHO_CMD,
1191*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_KEEPALIVE_CMD,
1192*4882a593Smuzhiyun 	WMI_TAG_VDEV_GET_KEEPALIVE_CMD,
1193*4882a593Smuzhiyun 	WMI_TAG_FORCE_FW_HANG_CMD,
1194*4882a593Smuzhiyun 	WMI_TAG_GPIO_CONFIG_CMD,
1195*4882a593Smuzhiyun 	WMI_TAG_GPIO_OUTPUT_CMD,
1196*4882a593Smuzhiyun 	WMI_TAG_PEER_ADD_WDS_ENTRY_CMD,
1197*4882a593Smuzhiyun 	WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD,
1198*4882a593Smuzhiyun 	WMI_TAG_BCN_TX_HDR,
1199*4882a593Smuzhiyun 	WMI_TAG_BCN_SEND_FROM_HOST_CMD,
1200*4882a593Smuzhiyun 	WMI_TAG_MGMT_TX_HDR,
1201*4882a593Smuzhiyun 	WMI_TAG_ADDBA_CLEAR_RESP_CMD,
1202*4882a593Smuzhiyun 	WMI_TAG_ADDBA_SEND_CMD,
1203*4882a593Smuzhiyun 	WMI_TAG_DELBA_SEND_CMD,
1204*4882a593Smuzhiyun 	WMI_TAG_ADDBA_SETRESPONSE_CMD,
1205*4882a593Smuzhiyun 	WMI_TAG_SEND_SINGLEAMSDU_CMD,
1206*4882a593Smuzhiyun 	WMI_TAG_PDEV_PKTLOG_ENABLE_CMD,
1207*4882a593Smuzhiyun 	WMI_TAG_PDEV_PKTLOG_DISABLE_CMD,
1208*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_HT_IE_CMD,
1209*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_VHT_IE_CMD,
1210*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD,
1211*4882a593Smuzhiyun 	WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD,
1212*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_TPC_CONFIG_CMD,
1213*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_BASE_MACADDR_CMD,
1214*4882a593Smuzhiyun 	WMI_TAG_PEER_MCAST_GROUP_CMD,
1215*4882a593Smuzhiyun 	WMI_TAG_ROAM_AP_PROFILE,
1216*4882a593Smuzhiyun 	WMI_TAG_AP_PROFILE,
1217*4882a593Smuzhiyun 	WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD,
1218*4882a593Smuzhiyun 	WMI_TAG_PDEV_DFS_ENABLE_CMD,
1219*4882a593Smuzhiyun 	WMI_TAG_PDEV_DFS_DISABLE_CMD,
1220*4882a593Smuzhiyun 	WMI_TAG_WOW_ADD_PATTERN_CMD,
1221*4882a593Smuzhiyun 	WMI_TAG_WOW_BITMAP_PATTERN_T,
1222*4882a593Smuzhiyun 	WMI_TAG_WOW_IPV4_SYNC_PATTERN_T,
1223*4882a593Smuzhiyun 	WMI_TAG_WOW_IPV6_SYNC_PATTERN_T,
1224*4882a593Smuzhiyun 	WMI_TAG_WOW_MAGIC_PATTERN_CMD,
1225*4882a593Smuzhiyun 	WMI_TAG_SCAN_UPDATE_REQUEST_CMD,
1226*4882a593Smuzhiyun 	WMI_TAG_CHATTER_PKT_COALESCING_FILTER,
1227*4882a593Smuzhiyun 	WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD,
1228*4882a593Smuzhiyun 	WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD,
1229*4882a593Smuzhiyun 	WMI_TAG_CHATTER_COALESCING_QUERY_CMD,
1230*4882a593Smuzhiyun 	WMI_TAG_TXBF_CMD,
1231*4882a593Smuzhiyun 	WMI_TAG_DEBUG_LOG_CONFIG_CMD,
1232*4882a593Smuzhiyun 	WMI_TAG_NLO_EVENT,
1233*4882a593Smuzhiyun 	WMI_TAG_CHATTER_QUERY_REPLY_EVENT,
1234*4882a593Smuzhiyun 	WMI_TAG_UPLOAD_H_HDR,
1235*4882a593Smuzhiyun 	WMI_TAG_CAPTURE_H_EVENT_HDR,
1236*4882a593Smuzhiyun 	WMI_TAG_VDEV_WNM_SLEEPMODE_CMD,
1237*4882a593Smuzhiyun 	WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD,
1238*4882a593Smuzhiyun 	WMI_TAG_VDEV_WMM_ADDTS_CMD,
1239*4882a593Smuzhiyun 	WMI_TAG_VDEV_WMM_DELTS_CMD,
1240*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
1241*4882a593Smuzhiyun 	WMI_TAG_TDLS_SET_STATE_CMD,
1242*4882a593Smuzhiyun 	WMI_TAG_TDLS_PEER_UPDATE_CMD,
1243*4882a593Smuzhiyun 	WMI_TAG_TDLS_PEER_EVENT,
1244*4882a593Smuzhiyun 	WMI_TAG_TDLS_PEER_CAPABILITIES,
1245*4882a593Smuzhiyun 	WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD,
1246*4882a593Smuzhiyun 	WMI_TAG_ROAM_CHAN_LIST,
1247*4882a593Smuzhiyun 	WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT,
1248*4882a593Smuzhiyun 	WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD,
1249*4882a593Smuzhiyun 	WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD,
1250*4882a593Smuzhiyun 	WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD,
1251*4882a593Smuzhiyun 	WMI_TAG_BA_REQ_SSN_CMD,
1252*4882a593Smuzhiyun 	WMI_TAG_BA_RSP_SSN_EVENT,
1253*4882a593Smuzhiyun 	WMI_TAG_STA_SMPS_FORCE_MODE_CMD,
1254*4882a593Smuzhiyun 	WMI_TAG_SET_MCASTBCAST_FILTER_CMD,
1255*4882a593Smuzhiyun 	WMI_TAG_P2P_SET_OPPPS_CMD,
1256*4882a593Smuzhiyun 	WMI_TAG_P2P_SET_NOA_CMD,
1257*4882a593Smuzhiyun 	WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM,
1258*4882a593Smuzhiyun 	WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM,
1259*4882a593Smuzhiyun 	WMI_TAG_STA_SMPS_PARAM_CMD,
1260*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_GTX_PARAMS_CMD,
1261*4882a593Smuzhiyun 	WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD,
1262*4882a593Smuzhiyun 	WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS,
1263*4882a593Smuzhiyun 	WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT,
1264*4882a593Smuzhiyun 	WMI_TAG_P2P_NOA_EVENT,
1265*4882a593Smuzhiyun 	WMI_TAG_HB_SET_ENABLE_CMD,
1266*4882a593Smuzhiyun 	WMI_TAG_HB_SET_TCP_PARAMS_CMD,
1267*4882a593Smuzhiyun 	WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD,
1268*4882a593Smuzhiyun 	WMI_TAG_HB_SET_UDP_PARAMS_CMD,
1269*4882a593Smuzhiyun 	WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD,
1270*4882a593Smuzhiyun 	WMI_TAG_HB_IND_EVENT,
1271*4882a593Smuzhiyun 	WMI_TAG_TX_PAUSE_EVENT,
1272*4882a593Smuzhiyun 	WMI_TAG_RFKILL_EVENT,
1273*4882a593Smuzhiyun 	WMI_TAG_DFS_RADAR_EVENT,
1274*4882a593Smuzhiyun 	WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD,
1275*4882a593Smuzhiyun 	WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD,
1276*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST,
1277*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO,
1278*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_ENABLE_CMD,
1279*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_DISABLE_CMD,
1280*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD,
1281*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_ENABLED_EVENT,
1282*4882a593Smuzhiyun 	WMI_TAG_BATCH_SCAN_RESULT_EVENT,
1283*4882a593Smuzhiyun 	WMI_TAG_VDEV_PLMREQ_START_CMD,
1284*4882a593Smuzhiyun 	WMI_TAG_VDEV_PLMREQ_STOP_CMD,
1285*4882a593Smuzhiyun 	WMI_TAG_THERMAL_MGMT_CMD,
1286*4882a593Smuzhiyun 	WMI_TAG_THERMAL_MGMT_EVENT,
1287*4882a593Smuzhiyun 	WMI_TAG_PEER_INFO_REQ_CMD,
1288*4882a593Smuzhiyun 	WMI_TAG_PEER_INFO_EVENT,
1289*4882a593Smuzhiyun 	WMI_TAG_PEER_INFO,
1290*4882a593Smuzhiyun 	WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT,
1291*4882a593Smuzhiyun 	WMI_TAG_RMC_SET_MODE_CMD,
1292*4882a593Smuzhiyun 	WMI_TAG_RMC_SET_ACTION_PERIOD_CMD,
1293*4882a593Smuzhiyun 	WMI_TAG_RMC_CONFIG_CMD,
1294*4882a593Smuzhiyun 	WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD,
1295*4882a593Smuzhiyun 	WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD,
1296*4882a593Smuzhiyun 	WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD,
1297*4882a593Smuzhiyun 	WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD,
1298*4882a593Smuzhiyun 	WMI_TAG_NAN_CMD_PARAM,
1299*4882a593Smuzhiyun 	WMI_TAG_NAN_EVENT_HDR,
1300*4882a593Smuzhiyun 	WMI_TAG_PDEV_L1SS_TRACK_EVENT,
1301*4882a593Smuzhiyun 	WMI_TAG_DIAG_DATA_CONTAINER_EVENT,
1302*4882a593Smuzhiyun 	WMI_TAG_MODEM_POWER_STATE_CMD_PARAM,
1303*4882a593Smuzhiyun 	WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD,
1304*4882a593Smuzhiyun 	WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT,
1305*4882a593Smuzhiyun 	WMI_TAG_AGGR_STATE_TRIG_EVENT,
1306*4882a593Smuzhiyun 	WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY,
1307*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_CMD,
1308*4882a593Smuzhiyun 	WMI_TAG_REQ_STATS_EXT_CMD,
1309*4882a593Smuzhiyun 	WMI_TAG_STATS_EXT_EVENT,
1310*4882a593Smuzhiyun 	WMI_TAG_OBSS_SCAN_ENABLE_CMD,
1311*4882a593Smuzhiyun 	WMI_TAG_OBSS_SCAN_DISABLE_CMD,
1312*4882a593Smuzhiyun 	WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT,
1313*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_LED_CONFIG_CMD,
1314*4882a593Smuzhiyun 	WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD,
1315*4882a593Smuzhiyun 	WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT,
1316*4882a593Smuzhiyun 	WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT,
1317*4882a593Smuzhiyun 	WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM,
1318*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_PKT_PATTERN_T,
1319*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_TMR_PATTERN_T,
1320*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD,
1321*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD,
1322*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_KEEPALIVE_T,
1323*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD,
1324*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD,
1325*4882a593Smuzhiyun 	WMI_TAG_START_LINK_STATS_CMD,
1326*4882a593Smuzhiyun 	WMI_TAG_CLEAR_LINK_STATS_CMD,
1327*4882a593Smuzhiyun 	WMI_TAG_REQUEST_LINK_STATS_CMD,
1328*4882a593Smuzhiyun 	WMI_TAG_IFACE_LINK_STATS_EVENT,
1329*4882a593Smuzhiyun 	WMI_TAG_RADIO_LINK_STATS_EVENT,
1330*4882a593Smuzhiyun 	WMI_TAG_PEER_STATS_EVENT,
1331*4882a593Smuzhiyun 	WMI_TAG_CHANNEL_STATS,
1332*4882a593Smuzhiyun 	WMI_TAG_RADIO_LINK_STATS,
1333*4882a593Smuzhiyun 	WMI_TAG_RATE_STATS,
1334*4882a593Smuzhiyun 	WMI_TAG_PEER_LINK_STATS,
1335*4882a593Smuzhiyun 	WMI_TAG_WMM_AC_STATS,
1336*4882a593Smuzhiyun 	WMI_TAG_IFACE_LINK_STATS,
1337*4882a593Smuzhiyun 	WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD,
1338*4882a593Smuzhiyun 	WMI_TAG_LPI_START_SCAN_CMD,
1339*4882a593Smuzhiyun 	WMI_TAG_LPI_STOP_SCAN_CMD,
1340*4882a593Smuzhiyun 	WMI_TAG_LPI_RESULT_EVENT,
1341*4882a593Smuzhiyun 	WMI_TAG_PEER_STATE_EVENT,
1342*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_BUCKET_CMD,
1343*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT,
1344*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_START_CMD,
1345*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_STOP_CMD,
1346*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD,
1347*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD,
1348*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD,
1349*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD,
1350*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD,
1351*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD,
1352*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD,
1353*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_OPERATION_EVENT,
1354*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_START_STOP_EVENT,
1355*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT,
1356*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT,
1357*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_RSSI_INFO_EVENT,
1358*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT,
1359*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT,
1360*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT,
1361*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT,
1362*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CAPABILITIES_EVENT,
1363*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT,
1364*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT,
1365*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT,
1366*4882a593Smuzhiyun 	WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD,
1367*4882a593Smuzhiyun 	WMI_TAG_D0_WOW_DISABLE_ACK_EVENT,
1368*4882a593Smuzhiyun 	WMI_TAG_UNIT_TEST_CMD,
1369*4882a593Smuzhiyun 	WMI_TAG_ROAM_OFFLOAD_TLV_PARAM,
1370*4882a593Smuzhiyun 	WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM,
1371*4882a593Smuzhiyun 	WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM,
1372*4882a593Smuzhiyun 	WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM,
1373*4882a593Smuzhiyun 	WMI_TAG_ROAM_SYNCH_EVENT,
1374*4882a593Smuzhiyun 	WMI_TAG_ROAM_SYNCH_COMPLETE,
1375*4882a593Smuzhiyun 	WMI_TAG_EXTWOW_ENABLE_CMD,
1376*4882a593Smuzhiyun 	WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD,
1377*4882a593Smuzhiyun 	WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD,
1378*4882a593Smuzhiyun 	WMI_TAG_LPI_STATUS_EVENT,
1379*4882a593Smuzhiyun 	WMI_TAG_LPI_HANDOFF_EVENT,
1380*4882a593Smuzhiyun 	WMI_TAG_VDEV_RATE_STATS_EVENT,
1381*4882a593Smuzhiyun 	WMI_TAG_VDEV_RATE_HT_INFO,
1382*4882a593Smuzhiyun 	WMI_TAG_RIC_REQUEST,
1383*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_TEMPERATURE_CMD,
1384*4882a593Smuzhiyun 	WMI_TAG_PDEV_TEMPERATURE_EVENT,
1385*4882a593Smuzhiyun 	WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD,
1386*4882a593Smuzhiyun 	WMI_TAG_TPC_CHAINMASK_CONFIG_CMD,
1387*4882a593Smuzhiyun 	WMI_TAG_RIC_TSPEC,
1388*4882a593Smuzhiyun 	WMI_TAG_TPC_CHAINMASK_CONFIG,
1389*4882a593Smuzhiyun 	WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD,
1390*4882a593Smuzhiyun 	WMI_TAG_SCAN_PROB_REQ_OUI_CMD,
1391*4882a593Smuzhiyun 	WMI_TAG_KEY_MATERIAL,
1392*4882a593Smuzhiyun 	WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD,
1393*4882a593Smuzhiyun 	WMI_TAG_SET_LED_FLASHING_CMD,
1394*4882a593Smuzhiyun 	WMI_TAG_MDNS_OFFLOAD_CMD,
1395*4882a593Smuzhiyun 	WMI_TAG_MDNS_SET_FQDN_CMD,
1396*4882a593Smuzhiyun 	WMI_TAG_MDNS_SET_RESP_CMD,
1397*4882a593Smuzhiyun 	WMI_TAG_MDNS_GET_STATS_CMD,
1398*4882a593Smuzhiyun 	WMI_TAG_MDNS_STATS_EVENT,
1399*4882a593Smuzhiyun 	WMI_TAG_ROAM_INVOKE_CMD,
1400*4882a593Smuzhiyun 	WMI_TAG_PDEV_RESUME_EVENT,
1401*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD,
1402*4882a593Smuzhiyun 	WMI_TAG_SAP_OFL_ENABLE_CMD,
1403*4882a593Smuzhiyun 	WMI_TAG_SAP_OFL_ADD_STA_EVENT,
1404*4882a593Smuzhiyun 	WMI_TAG_SAP_OFL_DEL_STA_EVENT,
1405*4882a593Smuzhiyun 	WMI_TAG_APFIND_CMD_PARAM,
1406*4882a593Smuzhiyun 	WMI_TAG_APFIND_EVENT_HDR,
1407*4882a593Smuzhiyun 	WMI_TAG_OCB_SET_SCHED_CMD,
1408*4882a593Smuzhiyun 	WMI_TAG_OCB_SET_SCHED_EVENT,
1409*4882a593Smuzhiyun 	WMI_TAG_OCB_SET_CONFIG_CMD,
1410*4882a593Smuzhiyun 	WMI_TAG_OCB_SET_CONFIG_RESP_EVENT,
1411*4882a593Smuzhiyun 	WMI_TAG_OCB_SET_UTC_TIME_CMD,
1412*4882a593Smuzhiyun 	WMI_TAG_OCB_START_TIMING_ADVERT_CMD,
1413*4882a593Smuzhiyun 	WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD,
1414*4882a593Smuzhiyun 	WMI_TAG_OCB_GET_TSF_TIMER_CMD,
1415*4882a593Smuzhiyun 	WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT,
1416*4882a593Smuzhiyun 	WMI_TAG_DCC_GET_STATS_CMD,
1417*4882a593Smuzhiyun 	WMI_TAG_DCC_CHANNEL_STATS_REQUEST,
1418*4882a593Smuzhiyun 	WMI_TAG_DCC_GET_STATS_RESP_EVENT,
1419*4882a593Smuzhiyun 	WMI_TAG_DCC_CLEAR_STATS_CMD,
1420*4882a593Smuzhiyun 	WMI_TAG_DCC_UPDATE_NDL_CMD,
1421*4882a593Smuzhiyun 	WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT,
1422*4882a593Smuzhiyun 	WMI_TAG_DCC_STATS_EVENT,
1423*4882a593Smuzhiyun 	WMI_TAG_OCB_CHANNEL,
1424*4882a593Smuzhiyun 	WMI_TAG_OCB_SCHEDULE_ELEMENT,
1425*4882a593Smuzhiyun 	WMI_TAG_DCC_NDL_STATS_PER_CHANNEL,
1426*4882a593Smuzhiyun 	WMI_TAG_DCC_NDL_CHAN,
1427*4882a593Smuzhiyun 	WMI_TAG_QOS_PARAMETER,
1428*4882a593Smuzhiyun 	WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG,
1429*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM,
1430*4882a593Smuzhiyun 	WMI_TAG_ROAM_FILTER,
1431*4882a593Smuzhiyun 	WMI_TAG_PASSPOINT_CONFIG_CMD,
1432*4882a593Smuzhiyun 	WMI_TAG_PASSPOINT_EVENT_HDR,
1433*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD,
1434*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT,
1435*4882a593Smuzhiyun 	WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD,
1436*4882a593Smuzhiyun 	WMI_TAG_VDEV_TSF_REPORT_EVENT,
1437*4882a593Smuzhiyun 	WMI_TAG_GET_FW_MEM_DUMP,
1438*4882a593Smuzhiyun 	WMI_TAG_UPDATE_FW_MEM_DUMP,
1439*4882a593Smuzhiyun 	WMI_TAG_FW_MEM_DUMP_PARAMS,
1440*4882a593Smuzhiyun 	WMI_TAG_DEBUG_MESG_FLUSH,
1441*4882a593Smuzhiyun 	WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE,
1442*4882a593Smuzhiyun 	WMI_TAG_PEER_SET_RATE_REPORT_CONDITION,
1443*4882a593Smuzhiyun 	WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG,
1444*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_IE_CMD,
1445*4882a593Smuzhiyun 	WMI_TAG_RSSI_BREACH_MONITOR_CONFIG,
1446*4882a593Smuzhiyun 	WMI_TAG_RSSI_BREACH_EVENT,
1447*4882a593Smuzhiyun 	WMI_TAG_WOW_EVENT_INITIAL_WAKEUP,
1448*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_PCL_CMD,
1449*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_HW_MODE_CMD,
1450*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT,
1451*4882a593Smuzhiyun 	WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT,
1452*4882a593Smuzhiyun 	WMI_TAG_VDEV_TXRX_STREAMS,
1453*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1454*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD,
1455*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT,
1456*4882a593Smuzhiyun 	WMI_TAG_WOW_IOAC_SOCK_PATTERN_T,
1457*4882a593Smuzhiyun 	WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD,
1458*4882a593Smuzhiyun 	WMI_TAG_DIAG_EVENT_LOG_CONFIG,
1459*4882a593Smuzhiyun 	WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS,
1460*4882a593Smuzhiyun 	WMI_TAG_PACKET_FILTER_CONFIG,
1461*4882a593Smuzhiyun 	WMI_TAG_PACKET_FILTER_ENABLE,
1462*4882a593Smuzhiyun 	WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD,
1463*4882a593Smuzhiyun 	WMI_TAG_MGMT_TX_SEND_CMD,
1464*4882a593Smuzhiyun 	WMI_TAG_MGMT_TX_COMPL_EVENT,
1465*4882a593Smuzhiyun 	WMI_TAG_SOC_SET_ANTENNA_MODE_CMD,
1466*4882a593Smuzhiyun 	WMI_TAG_WOW_UDP_SVC_OFLD_CMD,
1467*4882a593Smuzhiyun 	WMI_TAG_LRO_INFO_CMD,
1468*4882a593Smuzhiyun 	WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM,
1469*4882a593Smuzhiyun 	WMI_TAG_SERVICE_READY_EXT_EVENT,
1470*4882a593Smuzhiyun 	WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD,
1471*4882a593Smuzhiyun 	WMI_TAG_MAWC_ENABLE_SENSOR_EVENT,
1472*4882a593Smuzhiyun 	WMI_TAG_ROAM_CONFIGURE_MAWC_CMD,
1473*4882a593Smuzhiyun 	WMI_TAG_NLO_CONFIGURE_MAWC_CMD,
1474*4882a593Smuzhiyun 	WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD,
1475*4882a593Smuzhiyun 	WMI_TAG_PEER_ASSOC_CONF_EVENT,
1476*4882a593Smuzhiyun 	WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD,
1477*4882a593Smuzhiyun 	WMI_TAG_AP_PS_EGAP_PARAM_CMD,
1478*4882a593Smuzhiyun 	WMI_TAG_AP_PS_EGAP_INFO_EVENT,
1479*4882a593Smuzhiyun 	WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD,
1480*4882a593Smuzhiyun 	WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD,
1481*4882a593Smuzhiyun 	WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT,
1482*4882a593Smuzhiyun 	WMI_TAG_SCPC_EVENT,
1483*4882a593Smuzhiyun 	WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST,
1484*4882a593Smuzhiyun 	WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT,
1485*4882a593Smuzhiyun 	WMI_TAG_BPF_GET_CAPABILITY_CMD,
1486*4882a593Smuzhiyun 	WMI_TAG_BPF_CAPABILITY_INFO_EVT,
1487*4882a593Smuzhiyun 	WMI_TAG_BPF_GET_VDEV_STATS_CMD,
1488*4882a593Smuzhiyun 	WMI_TAG_BPF_VDEV_STATS_INFO_EVT,
1489*4882a593Smuzhiyun 	WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD,
1490*4882a593Smuzhiyun 	WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD,
1491*4882a593Smuzhiyun 	WMI_TAG_VDEV_DELETE_RESP_EVENT,
1492*4882a593Smuzhiyun 	WMI_TAG_PEER_DELETE_RESP_EVENT,
1493*4882a593Smuzhiyun 	WMI_TAG_ROAM_DENSE_THRES_PARAM,
1494*4882a593Smuzhiyun 	WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM,
1495*4882a593Smuzhiyun 	WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD,
1496*4882a593Smuzhiyun 	WMI_TAG_VDEV_CONFIG_RATEMASK,
1497*4882a593Smuzhiyun 	WMI_TAG_PDEV_FIPS_CMD,
1498*4882a593Smuzhiyun 	WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD,
1499*4882a593Smuzhiyun 	WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD,
1500*4882a593Smuzhiyun 	WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD,
1501*4882a593Smuzhiyun 	WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD,
1502*4882a593Smuzhiyun 	WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD,
1503*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD,
1504*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_CTL_TABLE_CMD,
1505*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD,
1506*4882a593Smuzhiyun 	WMI_TAG_FWTEST_SET_PARAM_CMD,
1507*4882a593Smuzhiyun 	WMI_TAG_PEER_ATF_REQUEST,
1508*4882a593Smuzhiyun 	WMI_TAG_VDEV_ATF_REQUEST,
1509*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD,
1510*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD,
1511*4882a593Smuzhiyun 	WMI_TAG_INST_RSSI_STATS_RESP,
1512*4882a593Smuzhiyun 	WMI_TAG_MED_UTIL_REPORT_EVENT,
1513*4882a593Smuzhiyun 	WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT,
1514*4882a593Smuzhiyun 	WMI_TAG_WDS_ADDR_EVENT,
1515*4882a593Smuzhiyun 	WMI_TAG_PEER_RATECODE_LIST_EVENT,
1516*4882a593Smuzhiyun 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT,
1517*4882a593Smuzhiyun 	WMI_TAG_PDEV_TPC_EVENT,
1518*4882a593Smuzhiyun 	WMI_TAG_ANI_OFDM_EVENT,
1519*4882a593Smuzhiyun 	WMI_TAG_ANI_CCK_EVENT,
1520*4882a593Smuzhiyun 	WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT,
1521*4882a593Smuzhiyun 	WMI_TAG_PDEV_FIPS_EVENT,
1522*4882a593Smuzhiyun 	WMI_TAG_ATF_PEER_INFO,
1523*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_TPC_CMD,
1524*4882a593Smuzhiyun 	WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD,
1525*4882a593Smuzhiyun 	WMI_TAG_QBOOST_CFG_CMD,
1526*4882a593Smuzhiyun 	WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE,
1527*4882a593Smuzhiyun 	WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES,
1528*4882a593Smuzhiyun 	WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM,
1529*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN,
1530*4882a593Smuzhiyun 	WMI_TAG_PEER_CCK_OFDM_RATE_INFO,
1531*4882a593Smuzhiyun 	WMI_TAG_PEER_MCS_RATE_INFO,
1532*4882a593Smuzhiyun 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR,
1533*4882a593Smuzhiyun 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM,
1534*4882a593Smuzhiyun 	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM,
1535*4882a593Smuzhiyun 	WMI_TAG_MU_REPORT_TOTAL_MU,
1536*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD,
1537*4882a593Smuzhiyun 	WMI_TAG_ROAM_SET_MBO,
1538*4882a593Smuzhiyun 	WMI_TAG_MIB_STATS_ENABLE_CMD,
1539*4882a593Smuzhiyun 	WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT,
1540*4882a593Smuzhiyun 	WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT,
1541*4882a593Smuzhiyun 	WMI_TAG_NAN_STARTED_CLUSTER_EVENT,
1542*4882a593Smuzhiyun 	WMI_TAG_NAN_JOINED_CLUSTER_EVENT,
1543*4882a593Smuzhiyun 	WMI_TAG_NDI_GET_CAP_REQ,
1544*4882a593Smuzhiyun 	WMI_TAG_NDP_INITIATOR_REQ,
1545*4882a593Smuzhiyun 	WMI_TAG_NDP_RESPONDER_REQ,
1546*4882a593Smuzhiyun 	WMI_TAG_NDP_END_REQ,
1547*4882a593Smuzhiyun 	WMI_TAG_NDI_CAP_RSP_EVENT,
1548*4882a593Smuzhiyun 	WMI_TAG_NDP_INITIATOR_RSP_EVENT,
1549*4882a593Smuzhiyun 	WMI_TAG_NDP_RESPONDER_RSP_EVENT,
1550*4882a593Smuzhiyun 	WMI_TAG_NDP_END_RSP_EVENT,
1551*4882a593Smuzhiyun 	WMI_TAG_NDP_INDICATION_EVENT,
1552*4882a593Smuzhiyun 	WMI_TAG_NDP_CONFIRM_EVENT,
1553*4882a593Smuzhiyun 	WMI_TAG_NDP_END_INDICATION_EVENT,
1554*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_QUIET_CMD,
1555*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_PCL_CMD,
1556*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_HW_MODE_CMD,
1557*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_MAC_CONFIG_CMD,
1558*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD,
1559*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT,
1560*4882a593Smuzhiyun 	WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT,
1561*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1562*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT,
1563*4882a593Smuzhiyun 	WMI_TAG_COEX_CONFIG_CMD,
1564*4882a593Smuzhiyun 	WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER,
1565*4882a593Smuzhiyun 	WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD,
1566*4882a593Smuzhiyun 	WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG,
1567*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD,
1568*4882a593Smuzhiyun 	WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD,
1569*4882a593Smuzhiyun 	WMI_TAG_MAC_PHY_CAPABILITIES,
1570*4882a593Smuzhiyun 	WMI_TAG_HW_MODE_CAPABILITIES,
1571*4882a593Smuzhiyun 	WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS,
1572*4882a593Smuzhiyun 	WMI_TAG_HAL_REG_CAPABILITIES_EXT,
1573*4882a593Smuzhiyun 	WMI_TAG_SOC_HAL_REG_CAPABILITIES,
1574*4882a593Smuzhiyun 	WMI_TAG_VDEV_WISA_CMD,
1575*4882a593Smuzhiyun 	WMI_TAG_TX_POWER_LEVEL_STATS_EVT,
1576*4882a593Smuzhiyun 	WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV,
1577*4882a593Smuzhiyun 	WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG,
1578*4882a593Smuzhiyun 	WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD,
1579*4882a593Smuzhiyun 	WMI_TAG_NDP_END_RSP_PER_NDI,
1580*4882a593Smuzhiyun 	WMI_TAG_PEER_BWF_REQUEST,
1581*4882a593Smuzhiyun 	WMI_TAG_BWF_PEER_INFO,
1582*4882a593Smuzhiyun 	WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD,
1583*4882a593Smuzhiyun 	WMI_TAG_RMC_SET_LEADER_CMD,
1584*4882a593Smuzhiyun 	WMI_TAG_RMC_MANUAL_LEADER_EVENT,
1585*4882a593Smuzhiyun 	WMI_TAG_PER_CHAIN_RSSI_STATS,
1586*4882a593Smuzhiyun 	WMI_TAG_RSSI_STATS,
1587*4882a593Smuzhiyun 	WMI_TAG_P2P_LO_START_CMD,
1588*4882a593Smuzhiyun 	WMI_TAG_P2P_LO_STOP_CMD,
1589*4882a593Smuzhiyun 	WMI_TAG_P2P_LO_STOPPED_EVENT,
1590*4882a593Smuzhiyun 	WMI_TAG_REORDER_QUEUE_SETUP_CMD,
1591*4882a593Smuzhiyun 	WMI_TAG_REORDER_QUEUE_REMOVE_CMD,
1592*4882a593Smuzhiyun 	WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD,
1593*4882a593Smuzhiyun 	WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT,
1594*4882a593Smuzhiyun 	WMI_TAG_READ_DATA_FROM_FLASH_CMD,
1595*4882a593Smuzhiyun 	WMI_TAG_READ_DATA_FROM_FLASH_EVENT,
1596*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD,
1597*4882a593Smuzhiyun 	WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD,
1598*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID,
1599*4882a593Smuzhiyun 	WMI_TAG_TLV_BUF_LEN_PARAM,
1600*4882a593Smuzhiyun 	WMI_TAG_SERVICE_AVAILABLE_EVENT,
1601*4882a593Smuzhiyun 	WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD,
1602*4882a593Smuzhiyun 	WMI_TAG_PEER_ANTDIV_INFO_EVENT,
1603*4882a593Smuzhiyun 	WMI_TAG_PEER_ANTDIV_INFO,
1604*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD,
1605*4882a593Smuzhiyun 	WMI_TAG_PDEV_ANTDIV_STATUS_EVENT,
1606*4882a593Smuzhiyun 	WMI_TAG_MNT_FILTER_CMD,
1607*4882a593Smuzhiyun 	WMI_TAG_GET_CHIP_POWER_STATS_CMD,
1608*4882a593Smuzhiyun 	WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT,
1609*4882a593Smuzhiyun 	WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD,
1610*4882a593Smuzhiyun 	WMI_TAG_COEX_REPORT_ISOLATION_EVENT,
1611*4882a593Smuzhiyun 	WMI_TAG_CHAN_CCA_STATS,
1612*4882a593Smuzhiyun 	WMI_TAG_PEER_SIGNAL_STATS,
1613*4882a593Smuzhiyun 	WMI_TAG_TX_STATS,
1614*4882a593Smuzhiyun 	WMI_TAG_PEER_AC_TX_STATS,
1615*4882a593Smuzhiyun 	WMI_TAG_RX_STATS,
1616*4882a593Smuzhiyun 	WMI_TAG_PEER_AC_RX_STATS,
1617*4882a593Smuzhiyun 	WMI_TAG_REPORT_STATS_EVENT,
1618*4882a593Smuzhiyun 	WMI_TAG_CHAN_CCA_STATS_THRESH,
1619*4882a593Smuzhiyun 	WMI_TAG_PEER_SIGNAL_STATS_THRESH,
1620*4882a593Smuzhiyun 	WMI_TAG_TX_STATS_THRESH,
1621*4882a593Smuzhiyun 	WMI_TAG_RX_STATS_THRESH,
1622*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD,
1623*4882a593Smuzhiyun 	WMI_TAG_REQUEST_WLAN_STATS_CMD,
1624*4882a593Smuzhiyun 	WMI_TAG_RX_AGGR_FAILURE_EVENT,
1625*4882a593Smuzhiyun 	WMI_TAG_RX_AGGR_FAILURE_INFO,
1626*4882a593Smuzhiyun 	WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD,
1627*4882a593Smuzhiyun 	WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT,
1628*4882a593Smuzhiyun 	WMI_TAG_PDEV_BAND_TO_MAC,
1629*4882a593Smuzhiyun 	WMI_TAG_TBTT_OFFSET_INFO,
1630*4882a593Smuzhiyun 	WMI_TAG_TBTT_OFFSET_EXT_EVENT,
1631*4882a593Smuzhiyun 	WMI_TAG_SAR_LIMITS_CMD,
1632*4882a593Smuzhiyun 	WMI_TAG_SAR_LIMIT_CMD_ROW,
1633*4882a593Smuzhiyun 	WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
1634*4882a593Smuzhiyun 	WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD,
1635*4882a593Smuzhiyun 	WMI_TAG_VDEV_ADFS_CH_CFG_CMD,
1636*4882a593Smuzhiyun 	WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD,
1637*4882a593Smuzhiyun 	WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT,
1638*4882a593Smuzhiyun 	WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT,
1639*4882a593Smuzhiyun 	WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT,
1640*4882a593Smuzhiyun 	WMI_TAG_VENDOR_OUI,
1641*4882a593Smuzhiyun 	WMI_TAG_REQUEST_RCPI_CMD,
1642*4882a593Smuzhiyun 	WMI_TAG_UPDATE_RCPI_EVENT,
1643*4882a593Smuzhiyun 	WMI_TAG_REQUEST_PEER_STATS_INFO_CMD,
1644*4882a593Smuzhiyun 	WMI_TAG_PEER_STATS_INFO,
1645*4882a593Smuzhiyun 	WMI_TAG_PEER_STATS_INFO_EVENT,
1646*4882a593Smuzhiyun 	WMI_TAG_PKGID_EVENT,
1647*4882a593Smuzhiyun 	WMI_TAG_CONNECTED_NLO_RSSI_PARAMS,
1648*4882a593Smuzhiyun 	WMI_TAG_SET_CURRENT_COUNTRY_CMD,
1649*4882a593Smuzhiyun 	WMI_TAG_REGULATORY_RULE_STRUCT,
1650*4882a593Smuzhiyun 	WMI_TAG_REG_CHAN_LIST_CC_EVENT,
1651*4882a593Smuzhiyun 	WMI_TAG_11D_SCAN_START_CMD,
1652*4882a593Smuzhiyun 	WMI_TAG_11D_SCAN_STOP_CMD,
1653*4882a593Smuzhiyun 	WMI_TAG_11D_NEW_COUNTRY_EVENT,
1654*4882a593Smuzhiyun 	WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD,
1655*4882a593Smuzhiyun 	WMI_TAG_RADIO_CHAN_STATS,
1656*4882a593Smuzhiyun 	WMI_TAG_RADIO_CHAN_STATS_EVENT,
1657*4882a593Smuzhiyun 	WMI_TAG_ROAM_PER_CONFIG,
1658*4882a593Smuzhiyun 	WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD,
1659*4882a593Smuzhiyun 	WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT,
1660*4882a593Smuzhiyun 	WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD,
1661*4882a593Smuzhiyun 	WMI_TAG_HW_DATA_FILTER_CMD,
1662*4882a593Smuzhiyun 	WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF,
1663*4882a593Smuzhiyun 	WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT,
1664*4882a593Smuzhiyun 	WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED,
1665*4882a593Smuzhiyun 	WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD,
1666*4882a593Smuzhiyun 	WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT,
1667*4882a593Smuzhiyun 	WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD,
1668*4882a593Smuzhiyun 	WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD,
1669*4882a593Smuzhiyun 	WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT,
1670*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD,
1671*4882a593Smuzhiyun 	WMI_TAG_MAC_PHY_CHAINMASK_COMBO,
1672*4882a593Smuzhiyun 	WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY,
1673*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_ARP_STATS_CMD,
1674*4882a593Smuzhiyun 	WMI_TAG_VDEV_GET_ARP_STATS_CMD,
1675*4882a593Smuzhiyun 	WMI_TAG_VDEV_GET_ARP_STATS_EVENT,
1676*4882a593Smuzhiyun 	WMI_TAG_IFACE_OFFLOAD_STATS,
1677*4882a593Smuzhiyun 	WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM,
1678*4882a593Smuzhiyun 	WMI_TAG_RSSI_CTL_EXT,
1679*4882a593Smuzhiyun 	WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR,
1680*4882a593Smuzhiyun 	WMI_TAG_COEX_BT_ACTIVITY_EVENT,
1681*4882a593Smuzhiyun 	WMI_TAG_VDEV_GET_TX_POWER_CMD,
1682*4882a593Smuzhiyun 	WMI_TAG_VDEV_TX_POWER_EVENT,
1683*4882a593Smuzhiyun 	WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT,
1684*4882a593Smuzhiyun 	WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD,
1685*4882a593Smuzhiyun 	WMI_TAG_TX_SEND_PARAMS,
1686*4882a593Smuzhiyun 	WMI_TAG_HE_RATE_SET,
1687*4882a593Smuzhiyun 	WMI_TAG_CONGESTION_STATS,
1688*4882a593Smuzhiyun 	WMI_TAG_SET_INIT_COUNTRY_CMD,
1689*4882a593Smuzhiyun 	WMI_TAG_SCAN_DBS_DUTY_CYCLE,
1690*4882a593Smuzhiyun 	WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV,
1691*4882a593Smuzhiyun 	WMI_TAG_PDEV_DIV_GET_RSSI_ANTID,
1692*4882a593Smuzhiyun 	WMI_TAG_THERM_THROT_CONFIG_REQUEST,
1693*4882a593Smuzhiyun 	WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO,
1694*4882a593Smuzhiyun 	WMI_TAG_THERM_THROT_STATS_EVENT,
1695*4882a593Smuzhiyun 	WMI_TAG_THERM_THROT_LEVEL_STATS_INFO,
1696*4882a593Smuzhiyun 	WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT,
1697*4882a593Smuzhiyun 	WMI_TAG_OEM_DMA_RING_CAPABILITIES,
1698*4882a593Smuzhiyun 	WMI_TAG_OEM_DMA_RING_CFG_REQ,
1699*4882a593Smuzhiyun 	WMI_TAG_OEM_DMA_RING_CFG_RSP,
1700*4882a593Smuzhiyun 	WMI_TAG_OEM_INDIRECT_DATA,
1701*4882a593Smuzhiyun 	WMI_TAG_OEM_DMA_BUF_RELEASE,
1702*4882a593Smuzhiyun 	WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY,
1703*4882a593Smuzhiyun 	WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST,
1704*4882a593Smuzhiyun 	WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT,
1705*4882a593Smuzhiyun 	WMI_TAG_ROAM_LCA_DISALLOW_CONFIG,
1706*4882a593Smuzhiyun 	WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD,
1707*4882a593Smuzhiyun 	WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG,
1708*4882a593Smuzhiyun 	WMI_TAG_UNIT_TEST_EVENT,
1709*4882a593Smuzhiyun 	WMI_TAG_ROAM_FILS_OFFLOAD,
1710*4882a593Smuzhiyun 	WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD,
1711*4882a593Smuzhiyun 	WMI_TAG_PMK_CACHE,
1712*4882a593Smuzhiyun 	WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD,
1713*4882a593Smuzhiyun 	WMI_TAG_ROAM_FILS_SYNCH,
1714*4882a593Smuzhiyun 	WMI_TAG_GTK_OFFLOAD_EXTENDED,
1715*4882a593Smuzhiyun 	WMI_TAG_ROAM_BG_SCAN_ROAMING,
1716*4882a593Smuzhiyun 	WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD,
1717*4882a593Smuzhiyun 	WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD,
1718*4882a593Smuzhiyun 	WMI_TAG_OIC_PING_HANDOFF_EVENT,
1719*4882a593Smuzhiyun 	WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD,
1720*4882a593Smuzhiyun 	WMI_TAG_DHCP_LEASE_RENEW_EVENT,
1721*4882a593Smuzhiyun 	WMI_TAG_BTM_CONFIG,
1722*4882a593Smuzhiyun 	WMI_TAG_DEBUG_MESG_FW_DATA_STALL,
1723*4882a593Smuzhiyun 	WMI_TAG_WLM_CONFIG_CMD,
1724*4882a593Smuzhiyun 	WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST,
1725*4882a593Smuzhiyun 	WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT,
1726*4882a593Smuzhiyun 	WMI_TAG_ROAM_CND_SCORING_PARAM,
1727*4882a593Smuzhiyun 	WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION,
1728*4882a593Smuzhiyun 	WMI_TAG_VENDOR_OUI_EXT,
1729*4882a593Smuzhiyun 	WMI_TAG_ROAM_SYNCH_FRAME_EVENT,
1730*4882a593Smuzhiyun 	WMI_TAG_FD_SEND_FROM_HOST_CMD,
1731*4882a593Smuzhiyun 	WMI_TAG_ENABLE_FILS_CMD,
1732*4882a593Smuzhiyun 	WMI_TAG_HOST_SWFDA_EVENT,
1733*4882a593Smuzhiyun 	WMI_TAG_BCN_OFFLOAD_CTRL_CMD,
1734*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD,
1735*4882a593Smuzhiyun 	WMI_TAG_STATS_PERIOD,
1736*4882a593Smuzhiyun 	WMI_TAG_NDL_SCHEDULE_UPDATE,
1737*4882a593Smuzhiyun 	WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD,
1738*4882a593Smuzhiyun 	WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE,
1739*4882a593Smuzhiyun 	WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD,
1740*4882a593Smuzhiyun 	WMI_TAG_SAR2_RESULT_EVENT,
1741*4882a593Smuzhiyun 	WMI_TAG_SAR_CAPABILITIES,
1742*4882a593Smuzhiyun 	WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD,
1743*4882a593Smuzhiyun 	WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT,
1744*4882a593Smuzhiyun 	WMI_TAG_DMA_RING_CAPABILITIES,
1745*4882a593Smuzhiyun 	WMI_TAG_DMA_RING_CFG_REQ,
1746*4882a593Smuzhiyun 	WMI_TAG_DMA_RING_CFG_RSP,
1747*4882a593Smuzhiyun 	WMI_TAG_DMA_BUF_RELEASE,
1748*4882a593Smuzhiyun 	WMI_TAG_DMA_BUF_RELEASE_ENTRY,
1749*4882a593Smuzhiyun 	WMI_TAG_SAR_GET_LIMITS_CMD,
1750*4882a593Smuzhiyun 	WMI_TAG_SAR_GET_LIMITS_EVENT,
1751*4882a593Smuzhiyun 	WMI_TAG_SAR_GET_LIMITS_EVENT_ROW,
1752*4882a593Smuzhiyun 	WMI_TAG_OFFLOAD_11K_REPORT,
1753*4882a593Smuzhiyun 	WMI_TAG_INVOKE_NEIGHBOR_REPORT,
1754*4882a593Smuzhiyun 	WMI_TAG_NEIGHBOR_REPORT_OFFLOAD,
1755*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS,
1756*4882a593Smuzhiyun 	WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS,
1757*4882a593Smuzhiyun 	WMI_TAG_BPF_SET_VDEV_ENABLE_CMD,
1758*4882a593Smuzhiyun 	WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD,
1759*4882a593Smuzhiyun 	WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD,
1760*4882a593Smuzhiyun 	WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT,
1761*4882a593Smuzhiyun 	WMI_TAG_PDEV_GET_NFCAL_POWER,
1762*4882a593Smuzhiyun 	WMI_TAG_BSS_COLOR_CHANGE_ENABLE,
1763*4882a593Smuzhiyun 	WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG,
1764*4882a593Smuzhiyun 	WMI_TAG_OBSS_COLOR_COLLISION_EVT,
1765*4882a593Smuzhiyun 	WMI_TAG_RUNTIME_DPD_RECAL_CMD,
1766*4882a593Smuzhiyun 	WMI_TAG_TWT_ENABLE_CMD,
1767*4882a593Smuzhiyun 	WMI_TAG_TWT_DISABLE_CMD,
1768*4882a593Smuzhiyun 	WMI_TAG_TWT_ADD_DIALOG_CMD,
1769*4882a593Smuzhiyun 	WMI_TAG_TWT_DEL_DIALOG_CMD,
1770*4882a593Smuzhiyun 	WMI_TAG_TWT_PAUSE_DIALOG_CMD,
1771*4882a593Smuzhiyun 	WMI_TAG_TWT_RESUME_DIALOG_CMD,
1772*4882a593Smuzhiyun 	WMI_TAG_TWT_ENABLE_COMPLETE_EVENT,
1773*4882a593Smuzhiyun 	WMI_TAG_TWT_DISABLE_COMPLETE_EVENT,
1774*4882a593Smuzhiyun 	WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT,
1775*4882a593Smuzhiyun 	WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT,
1776*4882a593Smuzhiyun 	WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT,
1777*4882a593Smuzhiyun 	WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT,
1778*4882a593Smuzhiyun 	WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD,
1779*4882a593Smuzhiyun 	WMI_TAG_ROAM_SCAN_STATS_EVENT,
1780*4882a593Smuzhiyun 	WMI_TAG_PEER_TID_CONFIGURATIONS_CMD,
1781*4882a593Smuzhiyun 	WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD,
1782*4882a593Smuzhiyun 	WMI_TAG_GET_TPC_POWER_CMD,
1783*4882a593Smuzhiyun 	WMI_TAG_GET_TPC_POWER_EVENT,
1784*4882a593Smuzhiyun 	WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA,
1785*4882a593Smuzhiyun 	WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD,
1786*4882a593Smuzhiyun 	WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD,
1787*4882a593Smuzhiyun 	WMI_TAG_MOTION_DET_START_STOP_CMD,
1788*4882a593Smuzhiyun 	WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD,
1789*4882a593Smuzhiyun 	WMI_TAG_MOTION_DET_EVENT,
1790*4882a593Smuzhiyun 	WMI_TAG_MOTION_DET_BASE_LINE_EVENT,
1791*4882a593Smuzhiyun 	WMI_TAG_NDP_TRANSPORT_IP,
1792*4882a593Smuzhiyun 	WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD,
1793*4882a593Smuzhiyun 	WMI_TAG_ESP_ESTIMATE_EVENT,
1794*4882a593Smuzhiyun 	WMI_TAG_NAN_HOST_CONFIG,
1795*4882a593Smuzhiyun 	WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS,
1796*4882a593Smuzhiyun 	WMI_TAG_PEER_CFR_CAPTURE_CMD,
1797*4882a593Smuzhiyun 	WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD,
1798*4882a593Smuzhiyun 	WMI_TAG_CHAN_WIDTH_PEER_LIST,
1799*4882a593Smuzhiyun 	WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD,
1800*4882a593Smuzhiyun 	WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD,
1801*4882a593Smuzhiyun 	WMI_TAG_PEER_EXTD2_STATS,
1802*4882a593Smuzhiyun 	WMI_TAG_HPCS_PULSE_START_CMD,
1803*4882a593Smuzhiyun 	WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT,
1804*4882a593Smuzhiyun 	WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD,
1805*4882a593Smuzhiyun 	WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD,
1806*4882a593Smuzhiyun 	WMI_TAG_NAN_EVENT_INFO,
1807*4882a593Smuzhiyun 	WMI_TAG_NDP_CHANNEL_INFO,
1808*4882a593Smuzhiyun 	WMI_TAG_NDP_CMD,
1809*4882a593Smuzhiyun 	WMI_TAG_NDP_EVENT,
1810*4882a593Smuzhiyun 	/* TODO add all the missing cmds */
1811*4882a593Smuzhiyun 	WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301,
1812*4882a593Smuzhiyun 	WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO,
1813*4882a593Smuzhiyun 	WMI_TAG_MAX
1814*4882a593Smuzhiyun };
1815*4882a593Smuzhiyun 
1816*4882a593Smuzhiyun enum wmi_tlv_service {
1817*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BEACON_OFFLOAD = 0,
1818*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SCAN_OFFLOAD = 1,
1819*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2,
1820*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3,
1821*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_PWRSAVE = 4,
1822*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5,
1823*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AP_UAPSD = 6,
1824*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AP_DFS = 7,
1825*4882a593Smuzhiyun 	WMI_TLV_SERVICE_11AC = 8,
1826*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BLOCKACK = 9,
1827*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PHYERR = 10,
1828*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BCN_FILTER = 11,
1829*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RTT = 12,
1830*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WOW = 13,
1831*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RATECTRL_CACHE = 14,
1832*4882a593Smuzhiyun 	WMI_TLV_SERVICE_IRAM_TIDS = 15,
1833*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16,
1834*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NLO = 17,
1835*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GTK_OFFLOAD = 18,
1836*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SCAN_SCH = 19,
1837*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CSA_OFFLOAD = 20,
1838*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CHATTER = 21,
1839*4882a593Smuzhiyun 	WMI_TLV_SERVICE_COEX_FREQAVOID = 22,
1840*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23,
1841*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FORCE_FW_HANG = 24,
1842*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GPIO = 25,
1843*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
1844*4882a593Smuzhiyun 	WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
1845*4882a593Smuzhiyun 	WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
1846*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29,
1847*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_ENCAP = 30,
1848*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
1849*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EARLY_RX = 32,
1850*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_SMPS = 33,
1851*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FWTEST = 34,
1852*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_WMMAC = 35,
1853*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TDLS = 36,
1854*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BURST = 37,
1855*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
1856*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ADAPTIVE_OCS = 39,
1857*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40,
1858*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
1859*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WLAN_HB = 42,
1860*4882a593Smuzhiyun 	WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
1861*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BATCH_SCAN = 44,
1862*4882a593Smuzhiyun 	WMI_TLV_SERVICE_QPOWER = 45,
1863*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PLMREQ = 46,
1864*4882a593Smuzhiyun 	WMI_TLV_SERVICE_THERMAL_MGMT = 47,
1865*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RMC = 48,
1866*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MHF_OFFLOAD = 49,
1867*4882a593Smuzhiyun 	WMI_TLV_SERVICE_COEX_SAR = 50,
1868*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51,
1869*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NAN = 52,
1870*4882a593Smuzhiyun 	WMI_TLV_SERVICE_L1SS_STAT = 53,
1871*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54,
1872*4882a593Smuzhiyun 	WMI_TLV_SERVICE_OBSS_SCAN = 55,
1873*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TDLS_OFFCHAN = 56,
1874*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
1875*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
1876*4882a593Smuzhiyun 	WMI_TLV_SERVICE_IBSS_PWRSAVE = 59,
1877*4882a593Smuzhiyun 	WMI_TLV_SERVICE_LPASS = 60,
1878*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EXTSCAN = 61,
1879*4882a593Smuzhiyun 	WMI_TLV_SERVICE_D0WOW = 62,
1880*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HSOFFLOAD = 63,
1881*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64,
1882*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RX_FULL_REORDER = 65,
1883*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DHCP_OFFLOAD = 66,
1884*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
1885*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MDNS_OFFLOAD = 68,
1886*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69,
1887*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
1888*4882a593Smuzhiyun 	WMI_TLV_SERVICE_OCB = 71,
1889*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72,
1890*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
1891*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74,
1892*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MGMT_TX_HTT = 75,
1893*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MGMT_TX_WMI = 76,
1894*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EXT_MSG = 77,
1895*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MAWC = 78,
1896*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79,
1897*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EGAP = 80,
1898*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81,
1899*4882a593Smuzhiyun 	WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
1900*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83,
1901*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ATF = 84,
1902*4882a593Smuzhiyun 	WMI_TLV_SERVICE_COEX_GPIO = 85,
1903*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86,
1904*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87,
1905*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88,
1906*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ENTERPRISE_MESH = 89,
1907*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90,
1908*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BPF_OFFLOAD = 91,
1909*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92,
1910*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
1911*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
1912*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
1913*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NAN_DATA = 96,
1914*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NAN_RTT = 97,
1915*4882a593Smuzhiyun 	WMI_TLV_SERVICE_11AX = 98,
1916*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99,
1917*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
1918*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101,
1919*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
1920*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MESH_11S = 103,
1921*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
1922*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VDEV_RX_FILTER = 105,
1923*4882a593Smuzhiyun 	WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
1924*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
1925*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
1926*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109,
1927*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110,
1928*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111,
1929*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
1930*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113,
1931*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RCPI_SUPPORT = 114,
1932*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115,
1933*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PEER_STATS_INFO = 116,
1934*4882a593Smuzhiyun 	WMI_TLV_SERVICE_REGULATORY_DB = 117,
1935*4882a593Smuzhiyun 	WMI_TLV_SERVICE_11D_OFFLOAD = 118,
1936*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HW_DATA_FILTERING = 119,
1937*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120,
1938*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PKT_ROUTING = 121,
1939*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122,
1940*4882a593Smuzhiyun 	WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123,
1941*4882a593Smuzhiyun 	WMI_TLV_SERVICE_8SS_TX_BFEE  =  124,
1942*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125,
1943*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ACK_TIMEOUT = 126,
1944*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127,
1945*4882a593Smuzhiyun 
1946*4882a593Smuzhiyun 	WMI_MAX_SERVICE = 128,
1947*4882a593Smuzhiyun 
1948*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128,
1949*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129,
1950*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130,
1951*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FILS_SUPPORT = 131,
1952*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132,
1953*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133,
1954*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MAWC_SUPPORT = 134,
1955*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135,
1956*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136,
1957*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137,
1958*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138,
1959*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139,
1960*4882a593Smuzhiyun 	WMI_TLV_SERVICE_THERM_THROT = 140,
1961*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141,
1962*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142,
1963*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143,
1964*4882a593Smuzhiyun 	WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144,
1965*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145,
1966*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146,
1967*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147,
1968*4882a593Smuzhiyun 	WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148,
1969*4882a593Smuzhiyun 	WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149,
1970*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150,
1971*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151,
1972*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_TWT = 152,
1973*4882a593Smuzhiyun 	WMI_TLV_SERVICE_AP_TWT = 153,
1974*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154,
1975*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155,
1976*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156,
1977*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157,
1978*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158,
1979*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159,
1980*4882a593Smuzhiyun 	WMI_TLV_SERVICE_MOTION_DET = 160,
1981*4882a593Smuzhiyun 	WMI_TLV_SERVICE_INFRA_MBSSID = 161,
1982*4882a593Smuzhiyun 	WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162,
1983*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163,
1984*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164,
1985*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165,
1986*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166,
1987*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167,
1988*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168,
1989*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169,
1990*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ESP_SUPPORT = 170,
1991*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171,
1992*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172,
1993*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173,
1994*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174,
1995*4882a593Smuzhiyun 	WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175,
1996*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176,
1997*4882a593Smuzhiyun 	WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177,
1998*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
1999*4882a593Smuzhiyun 	WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179,
2000*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180,
2001*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FETCH_TX_PN = 181,
2002*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182,
2003*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183,
2004*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184,
2005*4882a593Smuzhiyun 	WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185,
2006*4882a593Smuzhiyun 	WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186,
2007*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187,
2008*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188,
2009*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189,
2010*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190,
2011*4882a593Smuzhiyun 	WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191,
2012*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192,
2013*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193,
2014*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194,
2015*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195,
2016*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196,
2017*4882a593Smuzhiyun 	WMI_TLV_SERVICE_VOW_ENABLE = 197,
2018*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198,
2019*4882a593Smuzhiyun 	WMI_TLV_SERVICE_BROADCAST_TWT = 199,
2020*4882a593Smuzhiyun 	WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200,
2021*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PS_TDCC = 201,
2022*4882a593Smuzhiyun 	WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY   = 202,
2023*4882a593Smuzhiyun 	WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203,
2024*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204,
2025*4882a593Smuzhiyun 	WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205,
2026*4882a593Smuzhiyun 	WMI_TLV_SERVICE_WPA3_FT_FILS = 206,
2027*4882a593Smuzhiyun 	WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207,
2028*4882a593Smuzhiyun 	WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208,
2029*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209,
2030*4882a593Smuzhiyun 	WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210,
2031*4882a593Smuzhiyun 	WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211,
2032*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212,
2033*4882a593Smuzhiyun 	WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213,
2034*4882a593Smuzhiyun 	WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219,
2035*4882a593Smuzhiyun 	WMI_TLV_SERVICE_EXT2_MSG = 220,
2036*4882a593Smuzhiyun 
2037*4882a593Smuzhiyun 	WMI_MAX_EXT_SERVICE
2038*4882a593Smuzhiyun };
2039*4882a593Smuzhiyun 
2040*4882a593Smuzhiyun enum {
2041*4882a593Smuzhiyun 	WMI_SMPS_FORCED_MODE_NONE = 0,
2042*4882a593Smuzhiyun 	WMI_SMPS_FORCED_MODE_DISABLED,
2043*4882a593Smuzhiyun 	WMI_SMPS_FORCED_MODE_STATIC,
2044*4882a593Smuzhiyun 	WMI_SMPS_FORCED_MODE_DYNAMIC
2045*4882a593Smuzhiyun };
2046*4882a593Smuzhiyun 
2047*4882a593Smuzhiyun #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G      0
2048*4882a593Smuzhiyun #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G      1
2049*4882a593Smuzhiyun #define WMI_NUM_SUPPORTED_BAND_MAX 2
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun #define WMI_PEER_MIMO_PS_STATE                          0x1
2052*4882a593Smuzhiyun #define WMI_PEER_AMPDU                                  0x2
2053*4882a593Smuzhiyun #define WMI_PEER_AUTHORIZE                              0x3
2054*4882a593Smuzhiyun #define WMI_PEER_CHWIDTH                                0x4
2055*4882a593Smuzhiyun #define WMI_PEER_NSS                                    0x5
2056*4882a593Smuzhiyun #define WMI_PEER_USE_4ADDR                              0x6
2057*4882a593Smuzhiyun #define WMI_PEER_MEMBERSHIP                             0x7
2058*4882a593Smuzhiyun #define WMI_PEER_USERPOS                                0x8
2059*4882a593Smuzhiyun #define WMI_PEER_CRIT_PROTO_HINT_ENABLED                0x9
2060*4882a593Smuzhiyun #define WMI_PEER_TX_FAIL_CNT_THR                        0xA
2061*4882a593Smuzhiyun #define WMI_PEER_SET_HW_RETRY_CTS2S                     0xB
2062*4882a593Smuzhiyun #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH                0xC
2063*4882a593Smuzhiyun #define WMI_PEER_PHYMODE                                0xD
2064*4882a593Smuzhiyun #define WMI_PEER_USE_FIXED_PWR                          0xE
2065*4882a593Smuzhiyun #define WMI_PEER_PARAM_FIXED_RATE                       0xF
2066*4882a593Smuzhiyun #define WMI_PEER_SET_MU_WHITELIST                       0x10
2067*4882a593Smuzhiyun #define WMI_PEER_SET_MAX_TX_RATE                        0x11
2068*4882a593Smuzhiyun #define WMI_PEER_SET_MIN_TX_RATE                        0x12
2069*4882a593Smuzhiyun #define WMI_PEER_SET_DEFAULT_ROUTING                    0x13
2070*4882a593Smuzhiyun 
2071*4882a593Smuzhiyun /* slot time long */
2072*4882a593Smuzhiyun #define WMI_VDEV_SLOT_TIME_LONG         0x1
2073*4882a593Smuzhiyun /* slot time short */
2074*4882a593Smuzhiyun #define WMI_VDEV_SLOT_TIME_SHORT        0x2
2075*4882a593Smuzhiyun /* preablbe long */
2076*4882a593Smuzhiyun #define WMI_VDEV_PREAMBLE_LONG          0x1
2077*4882a593Smuzhiyun /* preablbe short */
2078*4882a593Smuzhiyun #define WMI_VDEV_PREAMBLE_SHORT         0x2
2079*4882a593Smuzhiyun 
2080*4882a593Smuzhiyun enum wmi_peer_smps_state {
2081*4882a593Smuzhiyun 	WMI_PEER_SMPS_PS_NONE = 0x0,
2082*4882a593Smuzhiyun 	WMI_PEER_SMPS_STATIC  = 0x1,
2083*4882a593Smuzhiyun 	WMI_PEER_SMPS_DYNAMIC = 0x2
2084*4882a593Smuzhiyun };
2085*4882a593Smuzhiyun 
2086*4882a593Smuzhiyun enum wmi_peer_chwidth {
2087*4882a593Smuzhiyun 	WMI_PEER_CHWIDTH_20MHZ = 0,
2088*4882a593Smuzhiyun 	WMI_PEER_CHWIDTH_40MHZ = 1,
2089*4882a593Smuzhiyun 	WMI_PEER_CHWIDTH_80MHZ = 2,
2090*4882a593Smuzhiyun 	WMI_PEER_CHWIDTH_160MHZ = 3,
2091*4882a593Smuzhiyun };
2092*4882a593Smuzhiyun 
2093*4882a593Smuzhiyun enum wmi_beacon_gen_mode {
2094*4882a593Smuzhiyun 	WMI_BEACON_STAGGERED_MODE = 0,
2095*4882a593Smuzhiyun 	WMI_BEACON_BURST_MODE = 1
2096*4882a593Smuzhiyun };
2097*4882a593Smuzhiyun 
2098*4882a593Smuzhiyun enum wmi_direct_buffer_module {
2099*4882a593Smuzhiyun 	WMI_DIRECT_BUF_SPECTRAL = 0,
2100*4882a593Smuzhiyun 	WMI_DIRECT_BUF_CFR = 1,
2101*4882a593Smuzhiyun 
2102*4882a593Smuzhiyun 	/* keep it last */
2103*4882a593Smuzhiyun 	WMI_DIRECT_BUF_MAX
2104*4882a593Smuzhiyun };
2105*4882a593Smuzhiyun 
2106*4882a593Smuzhiyun struct wmi_host_pdev_band_to_mac {
2107*4882a593Smuzhiyun 	u32 pdev_id;
2108*4882a593Smuzhiyun 	u32 start_freq;
2109*4882a593Smuzhiyun 	u32 end_freq;
2110*4882a593Smuzhiyun };
2111*4882a593Smuzhiyun 
2112*4882a593Smuzhiyun struct ath11k_ppe_threshold {
2113*4882a593Smuzhiyun 	u32 numss_m1;
2114*4882a593Smuzhiyun 	u32 ru_bit_mask;
2115*4882a593Smuzhiyun 	u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2116*4882a593Smuzhiyun };
2117*4882a593Smuzhiyun 
2118*4882a593Smuzhiyun struct ath11k_service_ext_param {
2119*4882a593Smuzhiyun 	u32 default_conc_scan_config_bits;
2120*4882a593Smuzhiyun 	u32 default_fw_config_bits;
2121*4882a593Smuzhiyun 	struct ath11k_ppe_threshold ppet;
2122*4882a593Smuzhiyun 	u32 he_cap_info;
2123*4882a593Smuzhiyun 	u32 mpdu_density;
2124*4882a593Smuzhiyun 	u32 max_bssid_rx_filters;
2125*4882a593Smuzhiyun 	u32 num_hw_modes;
2126*4882a593Smuzhiyun 	u32 num_phy;
2127*4882a593Smuzhiyun };
2128*4882a593Smuzhiyun 
2129*4882a593Smuzhiyun struct ath11k_hw_mode_caps {
2130*4882a593Smuzhiyun 	u32 hw_mode_id;
2131*4882a593Smuzhiyun 	u32 phy_id_map;
2132*4882a593Smuzhiyun 	u32 hw_mode_config_type;
2133*4882a593Smuzhiyun };
2134*4882a593Smuzhiyun 
2135*4882a593Smuzhiyun #define PSOC_HOST_MAX_PHY_SIZE (3)
2136*4882a593Smuzhiyun #define ATH11K_11B_SUPPORT                 BIT(0)
2137*4882a593Smuzhiyun #define ATH11K_11G_SUPPORT                 BIT(1)
2138*4882a593Smuzhiyun #define ATH11K_11A_SUPPORT                 BIT(2)
2139*4882a593Smuzhiyun #define ATH11K_11N_SUPPORT                 BIT(3)
2140*4882a593Smuzhiyun #define ATH11K_11AC_SUPPORT                BIT(4)
2141*4882a593Smuzhiyun #define ATH11K_11AX_SUPPORT                BIT(5)
2142*4882a593Smuzhiyun 
2143*4882a593Smuzhiyun struct ath11k_hal_reg_capabilities_ext {
2144*4882a593Smuzhiyun 	u32 phy_id;
2145*4882a593Smuzhiyun 	u32 eeprom_reg_domain;
2146*4882a593Smuzhiyun 	u32 eeprom_reg_domain_ext;
2147*4882a593Smuzhiyun 	u32 regcap1;
2148*4882a593Smuzhiyun 	u32 regcap2;
2149*4882a593Smuzhiyun 	u32 wireless_modes;
2150*4882a593Smuzhiyun 	u32 low_2ghz_chan;
2151*4882a593Smuzhiyun 	u32 high_2ghz_chan;
2152*4882a593Smuzhiyun 	u32 low_5ghz_chan;
2153*4882a593Smuzhiyun 	u32 high_5ghz_chan;
2154*4882a593Smuzhiyun };
2155*4882a593Smuzhiyun 
2156*4882a593Smuzhiyun #define WMI_HOST_MAX_PDEV 3
2157*4882a593Smuzhiyun 
2158*4882a593Smuzhiyun struct wlan_host_mem_chunk {
2159*4882a593Smuzhiyun 	u32 tlv_header;
2160*4882a593Smuzhiyun 	u32 req_id;
2161*4882a593Smuzhiyun 	u32 ptr;
2162*4882a593Smuzhiyun 	u32 size;
2163*4882a593Smuzhiyun } __packed;
2164*4882a593Smuzhiyun 
2165*4882a593Smuzhiyun struct wmi_host_mem_chunk {
2166*4882a593Smuzhiyun 	void *vaddr;
2167*4882a593Smuzhiyun 	dma_addr_t paddr;
2168*4882a593Smuzhiyun 	u32 len;
2169*4882a593Smuzhiyun 	u32 req_id;
2170*4882a593Smuzhiyun };
2171*4882a593Smuzhiyun 
2172*4882a593Smuzhiyun struct wmi_init_cmd_param {
2173*4882a593Smuzhiyun 	u32 tlv_header;
2174*4882a593Smuzhiyun 	struct target_resource_config *res_cfg;
2175*4882a593Smuzhiyun 	u8 num_mem_chunks;
2176*4882a593Smuzhiyun 	struct wmi_host_mem_chunk *mem_chunks;
2177*4882a593Smuzhiyun 	u32 hw_mode_id;
2178*4882a593Smuzhiyun 	u32 num_band_to_mac;
2179*4882a593Smuzhiyun 	struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV];
2180*4882a593Smuzhiyun };
2181*4882a593Smuzhiyun 
2182*4882a593Smuzhiyun struct wmi_pdev_band_to_mac {
2183*4882a593Smuzhiyun 	u32 tlv_header;
2184*4882a593Smuzhiyun 	u32 pdev_id;
2185*4882a593Smuzhiyun 	u32 start_freq;
2186*4882a593Smuzhiyun 	u32 end_freq;
2187*4882a593Smuzhiyun } __packed;
2188*4882a593Smuzhiyun 
2189*4882a593Smuzhiyun struct wmi_pdev_set_hw_mode_cmd_param {
2190*4882a593Smuzhiyun 	u32 tlv_header;
2191*4882a593Smuzhiyun 	u32 pdev_id;
2192*4882a593Smuzhiyun 	u32 hw_mode_index;
2193*4882a593Smuzhiyun 	u32 num_band_to_mac;
2194*4882a593Smuzhiyun } __packed;
2195*4882a593Smuzhiyun 
2196*4882a593Smuzhiyun struct wmi_ppe_threshold {
2197*4882a593Smuzhiyun 	u32 numss_m1; /** NSS - 1*/
2198*4882a593Smuzhiyun 	union {
2199*4882a593Smuzhiyun 		u32 ru_count;
2200*4882a593Smuzhiyun 		u32 ru_mask;
2201*4882a593Smuzhiyun 	} __packed;
2202*4882a593Smuzhiyun 	u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2203*4882a593Smuzhiyun } __packed;
2204*4882a593Smuzhiyun 
2205*4882a593Smuzhiyun #define HW_BD_INFO_SIZE       5
2206*4882a593Smuzhiyun 
2207*4882a593Smuzhiyun struct wmi_abi_version {
2208*4882a593Smuzhiyun 	u32 abi_version_0;
2209*4882a593Smuzhiyun 	u32 abi_version_1;
2210*4882a593Smuzhiyun 	u32 abi_version_ns_0;
2211*4882a593Smuzhiyun 	u32 abi_version_ns_1;
2212*4882a593Smuzhiyun 	u32 abi_version_ns_2;
2213*4882a593Smuzhiyun 	u32 abi_version_ns_3;
2214*4882a593Smuzhiyun } __packed;
2215*4882a593Smuzhiyun 
2216*4882a593Smuzhiyun struct wmi_init_cmd {
2217*4882a593Smuzhiyun 	u32 tlv_header;
2218*4882a593Smuzhiyun 	struct wmi_abi_version host_abi_vers;
2219*4882a593Smuzhiyun 	u32 num_host_mem_chunks;
2220*4882a593Smuzhiyun } __packed;
2221*4882a593Smuzhiyun 
2222*4882a593Smuzhiyun struct wmi_resource_config {
2223*4882a593Smuzhiyun 	u32 tlv_header;
2224*4882a593Smuzhiyun 	u32 num_vdevs;
2225*4882a593Smuzhiyun 	u32 num_peers;
2226*4882a593Smuzhiyun 	u32 num_offload_peers;
2227*4882a593Smuzhiyun 	u32 num_offload_reorder_buffs;
2228*4882a593Smuzhiyun 	u32 num_peer_keys;
2229*4882a593Smuzhiyun 	u32 num_tids;
2230*4882a593Smuzhiyun 	u32 ast_skid_limit;
2231*4882a593Smuzhiyun 	u32 tx_chain_mask;
2232*4882a593Smuzhiyun 	u32 rx_chain_mask;
2233*4882a593Smuzhiyun 	u32 rx_timeout_pri[4];
2234*4882a593Smuzhiyun 	u32 rx_decap_mode;
2235*4882a593Smuzhiyun 	u32 scan_max_pending_req;
2236*4882a593Smuzhiyun 	u32 bmiss_offload_max_vdev;
2237*4882a593Smuzhiyun 	u32 roam_offload_max_vdev;
2238*4882a593Smuzhiyun 	u32 roam_offload_max_ap_profiles;
2239*4882a593Smuzhiyun 	u32 num_mcast_groups;
2240*4882a593Smuzhiyun 	u32 num_mcast_table_elems;
2241*4882a593Smuzhiyun 	u32 mcast2ucast_mode;
2242*4882a593Smuzhiyun 	u32 tx_dbg_log_size;
2243*4882a593Smuzhiyun 	u32 num_wds_entries;
2244*4882a593Smuzhiyun 	u32 dma_burst_size;
2245*4882a593Smuzhiyun 	u32 mac_aggr_delim;
2246*4882a593Smuzhiyun 	u32 rx_skip_defrag_timeout_dup_detection_check;
2247*4882a593Smuzhiyun 	u32 vow_config;
2248*4882a593Smuzhiyun 	u32 gtk_offload_max_vdev;
2249*4882a593Smuzhiyun 	u32 num_msdu_desc;
2250*4882a593Smuzhiyun 	u32 max_frag_entries;
2251*4882a593Smuzhiyun 	u32 num_tdls_vdevs;
2252*4882a593Smuzhiyun 	u32 num_tdls_conn_table_entries;
2253*4882a593Smuzhiyun 	u32 beacon_tx_offload_max_vdev;
2254*4882a593Smuzhiyun 	u32 num_multicast_filter_entries;
2255*4882a593Smuzhiyun 	u32 num_wow_filters;
2256*4882a593Smuzhiyun 	u32 num_keep_alive_pattern;
2257*4882a593Smuzhiyun 	u32 keep_alive_pattern_size;
2258*4882a593Smuzhiyun 	u32 max_tdls_concurrent_sleep_sta;
2259*4882a593Smuzhiyun 	u32 max_tdls_concurrent_buffer_sta;
2260*4882a593Smuzhiyun 	u32 wmi_send_separate;
2261*4882a593Smuzhiyun 	u32 num_ocb_vdevs;
2262*4882a593Smuzhiyun 	u32 num_ocb_channels;
2263*4882a593Smuzhiyun 	u32 num_ocb_schedules;
2264*4882a593Smuzhiyun 	u32 flag1;
2265*4882a593Smuzhiyun 	u32 smart_ant_cap;
2266*4882a593Smuzhiyun 	u32 bk_minfree;
2267*4882a593Smuzhiyun 	u32 be_minfree;
2268*4882a593Smuzhiyun 	u32 vi_minfree;
2269*4882a593Smuzhiyun 	u32 vo_minfree;
2270*4882a593Smuzhiyun 	u32 alloc_frag_desc_for_data_pkt;
2271*4882a593Smuzhiyun 	u32 num_ns_ext_tuples_cfg;
2272*4882a593Smuzhiyun 	u32 bpf_instruction_size;
2273*4882a593Smuzhiyun 	u32 max_bssid_rx_filters;
2274*4882a593Smuzhiyun 	u32 use_pdev_id;
2275*4882a593Smuzhiyun 	u32 max_num_dbs_scan_duty_cycle;
2276*4882a593Smuzhiyun 	u32 max_num_group_keys;
2277*4882a593Smuzhiyun 	u32 peer_map_unmap_v2_support;
2278*4882a593Smuzhiyun 	u32 sched_params;
2279*4882a593Smuzhiyun 	u32 twt_ap_pdev_count;
2280*4882a593Smuzhiyun 	u32 twt_ap_sta_count;
2281*4882a593Smuzhiyun } __packed;
2282*4882a593Smuzhiyun 
2283*4882a593Smuzhiyun struct wmi_service_ready_event {
2284*4882a593Smuzhiyun 	u32 fw_build_vers;
2285*4882a593Smuzhiyun 	struct wmi_abi_version fw_abi_vers;
2286*4882a593Smuzhiyun 	u32 phy_capability;
2287*4882a593Smuzhiyun 	u32 max_frag_entry;
2288*4882a593Smuzhiyun 	u32 num_rf_chains;
2289*4882a593Smuzhiyun 	u32 ht_cap_info;
2290*4882a593Smuzhiyun 	u32 vht_cap_info;
2291*4882a593Smuzhiyun 	u32 vht_supp_mcs;
2292*4882a593Smuzhiyun 	u32 hw_min_tx_power;
2293*4882a593Smuzhiyun 	u32 hw_max_tx_power;
2294*4882a593Smuzhiyun 	u32 sys_cap_info;
2295*4882a593Smuzhiyun 	u32 min_pkt_size_enable;
2296*4882a593Smuzhiyun 	u32 max_bcn_ie_size;
2297*4882a593Smuzhiyun 	u32 num_mem_reqs;
2298*4882a593Smuzhiyun 	u32 max_num_scan_channels;
2299*4882a593Smuzhiyun 	u32 hw_bd_id;
2300*4882a593Smuzhiyun 	u32 hw_bd_info[HW_BD_INFO_SIZE];
2301*4882a593Smuzhiyun 	u32 max_supported_macs;
2302*4882a593Smuzhiyun 	u32 wmi_fw_sub_feat_caps;
2303*4882a593Smuzhiyun 	u32 num_dbs_hw_modes;
2304*4882a593Smuzhiyun 	/* txrx_chainmask
2305*4882a593Smuzhiyun 	 *    [7:0]   - 2G band tx chain mask
2306*4882a593Smuzhiyun 	 *    [15:8]  - 2G band rx chain mask
2307*4882a593Smuzhiyun 	 *    [23:16] - 5G band tx chain mask
2308*4882a593Smuzhiyun 	 *    [31:24] - 5G band rx chain mask
2309*4882a593Smuzhiyun 	 */
2310*4882a593Smuzhiyun 	u32 txrx_chainmask;
2311*4882a593Smuzhiyun 	u32 default_dbs_hw_mode_index;
2312*4882a593Smuzhiyun 	u32 num_msdu_desc;
2313*4882a593Smuzhiyun } __packed;
2314*4882a593Smuzhiyun 
2315*4882a593Smuzhiyun #define WMI_SERVICE_BM_SIZE	((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2316*4882a593Smuzhiyun 
2317*4882a593Smuzhiyun #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2318*4882a593Smuzhiyun #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2319*4882a593Smuzhiyun #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32
2320*4882a593Smuzhiyun #define WMI_SERVICE_BITS_IN_SIZE32 4
2321*4882a593Smuzhiyun 
2322*4882a593Smuzhiyun struct wmi_service_ready_ext_event {
2323*4882a593Smuzhiyun 	u32 default_conc_scan_config_bits;
2324*4882a593Smuzhiyun 	u32 default_fw_config_bits;
2325*4882a593Smuzhiyun 	struct wmi_ppe_threshold ppet;
2326*4882a593Smuzhiyun 	u32 he_cap_info;
2327*4882a593Smuzhiyun 	u32 mpdu_density;
2328*4882a593Smuzhiyun 	u32 max_bssid_rx_filters;
2329*4882a593Smuzhiyun 	u32 fw_build_vers_ext;
2330*4882a593Smuzhiyun 	u32 max_nlo_ssids;
2331*4882a593Smuzhiyun 	u32 max_bssid_indicator;
2332*4882a593Smuzhiyun 	u32 he_cap_info_ext;
2333*4882a593Smuzhiyun } __packed;
2334*4882a593Smuzhiyun 
2335*4882a593Smuzhiyun struct wmi_soc_mac_phy_hw_mode_caps {
2336*4882a593Smuzhiyun 	u32 num_hw_modes;
2337*4882a593Smuzhiyun 	u32 num_chainmask_tables;
2338*4882a593Smuzhiyun } __packed;
2339*4882a593Smuzhiyun 
2340*4882a593Smuzhiyun struct wmi_hw_mode_capabilities {
2341*4882a593Smuzhiyun 	u32 tlv_header;
2342*4882a593Smuzhiyun 	u32 hw_mode_id;
2343*4882a593Smuzhiyun 	u32 phy_id_map;
2344*4882a593Smuzhiyun 	u32 hw_mode_config_type;
2345*4882a593Smuzhiyun } __packed;
2346*4882a593Smuzhiyun 
2347*4882a593Smuzhiyun #define WMI_MAX_HECAP_PHY_SIZE                 (3)
2348*4882a593Smuzhiyun 
2349*4882a593Smuzhiyun struct wmi_mac_phy_capabilities {
2350*4882a593Smuzhiyun 	u32 hw_mode_id;
2351*4882a593Smuzhiyun 	u32 pdev_id;
2352*4882a593Smuzhiyun 	u32 phy_id;
2353*4882a593Smuzhiyun 	u32 supported_flags;
2354*4882a593Smuzhiyun 	u32 supported_bands;
2355*4882a593Smuzhiyun 	u32 ampdu_density;
2356*4882a593Smuzhiyun 	u32 max_bw_supported_2g;
2357*4882a593Smuzhiyun 	u32 ht_cap_info_2g;
2358*4882a593Smuzhiyun 	u32 vht_cap_info_2g;
2359*4882a593Smuzhiyun 	u32 vht_supp_mcs_2g;
2360*4882a593Smuzhiyun 	u32 he_cap_info_2g;
2361*4882a593Smuzhiyun 	u32 he_supp_mcs_2g;
2362*4882a593Smuzhiyun 	u32 tx_chain_mask_2g;
2363*4882a593Smuzhiyun 	u32 rx_chain_mask_2g;
2364*4882a593Smuzhiyun 	u32 max_bw_supported_5g;
2365*4882a593Smuzhiyun 	u32 ht_cap_info_5g;
2366*4882a593Smuzhiyun 	u32 vht_cap_info_5g;
2367*4882a593Smuzhiyun 	u32 vht_supp_mcs_5g;
2368*4882a593Smuzhiyun 	u32 he_cap_info_5g;
2369*4882a593Smuzhiyun 	u32 he_supp_mcs_5g;
2370*4882a593Smuzhiyun 	u32 tx_chain_mask_5g;
2371*4882a593Smuzhiyun 	u32 rx_chain_mask_5g;
2372*4882a593Smuzhiyun 	u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2373*4882a593Smuzhiyun 	u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2374*4882a593Smuzhiyun 	struct wmi_ppe_threshold he_ppet2g;
2375*4882a593Smuzhiyun 	struct wmi_ppe_threshold he_ppet5g;
2376*4882a593Smuzhiyun 	u32 chainmask_table_id;
2377*4882a593Smuzhiyun 	u32 lmac_id;
2378*4882a593Smuzhiyun 	u32 he_cap_info_2g_ext;
2379*4882a593Smuzhiyun 	u32 he_cap_info_5g_ext;
2380*4882a593Smuzhiyun 	u32 he_cap_info_internal;
2381*4882a593Smuzhiyun } __packed;
2382*4882a593Smuzhiyun 
2383*4882a593Smuzhiyun struct wmi_hal_reg_capabilities_ext {
2384*4882a593Smuzhiyun 	u32 tlv_header;
2385*4882a593Smuzhiyun 	u32 phy_id;
2386*4882a593Smuzhiyun 	u32 eeprom_reg_domain;
2387*4882a593Smuzhiyun 	u32 eeprom_reg_domain_ext;
2388*4882a593Smuzhiyun 	u32 regcap1;
2389*4882a593Smuzhiyun 	u32 regcap2;
2390*4882a593Smuzhiyun 	u32 wireless_modes;
2391*4882a593Smuzhiyun 	u32 low_2ghz_chan;
2392*4882a593Smuzhiyun 	u32 high_2ghz_chan;
2393*4882a593Smuzhiyun 	u32 low_5ghz_chan;
2394*4882a593Smuzhiyun 	u32 high_5ghz_chan;
2395*4882a593Smuzhiyun } __packed;
2396*4882a593Smuzhiyun 
2397*4882a593Smuzhiyun struct wmi_soc_hal_reg_capabilities {
2398*4882a593Smuzhiyun 	u32 num_phy;
2399*4882a593Smuzhiyun } __packed;
2400*4882a593Smuzhiyun 
2401*4882a593Smuzhiyun /* 2 word representation of MAC addr */
2402*4882a593Smuzhiyun struct wmi_mac_addr {
2403*4882a593Smuzhiyun 	union {
2404*4882a593Smuzhiyun 		u8 addr[6];
2405*4882a593Smuzhiyun 		struct {
2406*4882a593Smuzhiyun 			u32 word0;
2407*4882a593Smuzhiyun 			u32 word1;
2408*4882a593Smuzhiyun 		} __packed;
2409*4882a593Smuzhiyun 	} __packed;
2410*4882a593Smuzhiyun } __packed;
2411*4882a593Smuzhiyun 
2412*4882a593Smuzhiyun struct wmi_dma_ring_capabilities {
2413*4882a593Smuzhiyun 	u32 tlv_header;
2414*4882a593Smuzhiyun 	u32 pdev_id;
2415*4882a593Smuzhiyun 	u32 module_id;
2416*4882a593Smuzhiyun 	u32 min_elem;
2417*4882a593Smuzhiyun 	u32 min_buf_sz;
2418*4882a593Smuzhiyun 	u32 min_buf_align;
2419*4882a593Smuzhiyun } __packed;
2420*4882a593Smuzhiyun 
2421*4882a593Smuzhiyun struct wmi_ready_event_min {
2422*4882a593Smuzhiyun 	struct wmi_abi_version fw_abi_vers;
2423*4882a593Smuzhiyun 	struct wmi_mac_addr mac_addr;
2424*4882a593Smuzhiyun 	u32 status;
2425*4882a593Smuzhiyun 	u32 num_dscp_table;
2426*4882a593Smuzhiyun 	u32 num_extra_mac_addr;
2427*4882a593Smuzhiyun 	u32 num_total_peers;
2428*4882a593Smuzhiyun 	u32 num_extra_peers;
2429*4882a593Smuzhiyun } __packed;
2430*4882a593Smuzhiyun 
2431*4882a593Smuzhiyun struct wmi_ready_event {
2432*4882a593Smuzhiyun 	struct wmi_ready_event_min ready_event_min;
2433*4882a593Smuzhiyun 	u32 max_ast_index;
2434*4882a593Smuzhiyun 	u32 pktlog_defs_checksum;
2435*4882a593Smuzhiyun } __packed;
2436*4882a593Smuzhiyun 
2437*4882a593Smuzhiyun struct wmi_service_available_event {
2438*4882a593Smuzhiyun 	u32 wmi_service_segment_offset;
2439*4882a593Smuzhiyun 	u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2440*4882a593Smuzhiyun } __packed;
2441*4882a593Smuzhiyun 
2442*4882a593Smuzhiyun struct ath11k_pdev_wmi {
2443*4882a593Smuzhiyun 	struct ath11k_wmi_base *wmi_ab;
2444*4882a593Smuzhiyun 	enum ath11k_htc_ep_id eid;
2445*4882a593Smuzhiyun 	const struct wmi_peer_flags_map *peer_flags;
2446*4882a593Smuzhiyun 	u32 rx_decap_mode;
2447*4882a593Smuzhiyun };
2448*4882a593Smuzhiyun 
2449*4882a593Smuzhiyun struct vdev_create_params {
2450*4882a593Smuzhiyun 	u8 if_id;
2451*4882a593Smuzhiyun 	u32 type;
2452*4882a593Smuzhiyun 	u32 subtype;
2453*4882a593Smuzhiyun 	struct {
2454*4882a593Smuzhiyun 		u8 tx;
2455*4882a593Smuzhiyun 		u8 rx;
2456*4882a593Smuzhiyun 	} chains[NUM_NL80211_BANDS];
2457*4882a593Smuzhiyun 	u32 pdev_id;
2458*4882a593Smuzhiyun };
2459*4882a593Smuzhiyun 
2460*4882a593Smuzhiyun struct wmi_vdev_create_cmd {
2461*4882a593Smuzhiyun 	u32 tlv_header;
2462*4882a593Smuzhiyun 	u32 vdev_id;
2463*4882a593Smuzhiyun 	u32 vdev_type;
2464*4882a593Smuzhiyun 	u32 vdev_subtype;
2465*4882a593Smuzhiyun 	struct wmi_mac_addr vdev_macaddr;
2466*4882a593Smuzhiyun 	u32 num_cfg_txrx_streams;
2467*4882a593Smuzhiyun 	u32 pdev_id;
2468*4882a593Smuzhiyun } __packed;
2469*4882a593Smuzhiyun 
2470*4882a593Smuzhiyun struct wmi_vdev_txrx_streams {
2471*4882a593Smuzhiyun 	u32 tlv_header;
2472*4882a593Smuzhiyun 	u32 band;
2473*4882a593Smuzhiyun 	u32 supported_tx_streams;
2474*4882a593Smuzhiyun 	u32 supported_rx_streams;
2475*4882a593Smuzhiyun } __packed;
2476*4882a593Smuzhiyun 
2477*4882a593Smuzhiyun struct wmi_vdev_delete_cmd {
2478*4882a593Smuzhiyun 	u32 tlv_header;
2479*4882a593Smuzhiyun 	u32 vdev_id;
2480*4882a593Smuzhiyun } __packed;
2481*4882a593Smuzhiyun 
2482*4882a593Smuzhiyun struct wmi_vdev_up_cmd {
2483*4882a593Smuzhiyun 	u32 tlv_header;
2484*4882a593Smuzhiyun 	u32 vdev_id;
2485*4882a593Smuzhiyun 	u32 vdev_assoc_id;
2486*4882a593Smuzhiyun 	struct wmi_mac_addr vdev_bssid;
2487*4882a593Smuzhiyun 	struct wmi_mac_addr trans_bssid;
2488*4882a593Smuzhiyun 	u32 profile_idx;
2489*4882a593Smuzhiyun 	u32 profile_num;
2490*4882a593Smuzhiyun } __packed;
2491*4882a593Smuzhiyun 
2492*4882a593Smuzhiyun struct wmi_vdev_stop_cmd {
2493*4882a593Smuzhiyun 	u32 tlv_header;
2494*4882a593Smuzhiyun 	u32 vdev_id;
2495*4882a593Smuzhiyun } __packed;
2496*4882a593Smuzhiyun 
2497*4882a593Smuzhiyun struct wmi_vdev_down_cmd {
2498*4882a593Smuzhiyun 	u32 tlv_header;
2499*4882a593Smuzhiyun 	u32 vdev_id;
2500*4882a593Smuzhiyun } __packed;
2501*4882a593Smuzhiyun 
2502*4882a593Smuzhiyun #define WMI_VDEV_START_HIDDEN_SSID  BIT(0)
2503*4882a593Smuzhiyun #define WMI_VDEV_START_PMF_ENABLED  BIT(1)
2504*4882a593Smuzhiyun #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
2505*4882a593Smuzhiyun 
2506*4882a593Smuzhiyun struct wmi_ssid {
2507*4882a593Smuzhiyun 	u32 ssid_len;
2508*4882a593Smuzhiyun 	u32 ssid[8];
2509*4882a593Smuzhiyun } __packed;
2510*4882a593Smuzhiyun 
2511*4882a593Smuzhiyun #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ)
2512*4882a593Smuzhiyun 
2513*4882a593Smuzhiyun struct wmi_vdev_start_request_cmd {
2514*4882a593Smuzhiyun 	u32 tlv_header;
2515*4882a593Smuzhiyun 	u32 vdev_id;
2516*4882a593Smuzhiyun 	u32 requestor_id;
2517*4882a593Smuzhiyun 	u32 beacon_interval;
2518*4882a593Smuzhiyun 	u32 dtim_period;
2519*4882a593Smuzhiyun 	u32 flags;
2520*4882a593Smuzhiyun 	struct wmi_ssid ssid;
2521*4882a593Smuzhiyun 	u32 bcn_tx_rate;
2522*4882a593Smuzhiyun 	u32 bcn_txpower;
2523*4882a593Smuzhiyun 	u32 num_noa_descriptors;
2524*4882a593Smuzhiyun 	u32 disable_hw_ack;
2525*4882a593Smuzhiyun 	u32 preferred_tx_streams;
2526*4882a593Smuzhiyun 	u32 preferred_rx_streams;
2527*4882a593Smuzhiyun 	u32 he_ops;
2528*4882a593Smuzhiyun 	u32 cac_duration_ms;
2529*4882a593Smuzhiyun 	u32 regdomain;
2530*4882a593Smuzhiyun } __packed;
2531*4882a593Smuzhiyun 
2532*4882a593Smuzhiyun #define MGMT_TX_DL_FRM_LEN		     64
2533*4882a593Smuzhiyun #define WMI_MAC_MAX_SSID_LENGTH              32
2534*4882a593Smuzhiyun struct mac_ssid {
2535*4882a593Smuzhiyun 	u8 length;
2536*4882a593Smuzhiyun 	u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH];
2537*4882a593Smuzhiyun } __packed;
2538*4882a593Smuzhiyun 
2539*4882a593Smuzhiyun struct wmi_p2p_noa_descriptor {
2540*4882a593Smuzhiyun 	u32 type_count;
2541*4882a593Smuzhiyun 	u32 duration;
2542*4882a593Smuzhiyun 	u32 interval;
2543*4882a593Smuzhiyun 	u32 start_time;
2544*4882a593Smuzhiyun };
2545*4882a593Smuzhiyun 
2546*4882a593Smuzhiyun struct channel_param {
2547*4882a593Smuzhiyun 	u8 chan_id;
2548*4882a593Smuzhiyun 	u8 pwr;
2549*4882a593Smuzhiyun 	u32 mhz;
2550*4882a593Smuzhiyun 	u32 half_rate:1,
2551*4882a593Smuzhiyun 	    quarter_rate:1,
2552*4882a593Smuzhiyun 	    dfs_set:1,
2553*4882a593Smuzhiyun 	    dfs_set_cfreq2:1,
2554*4882a593Smuzhiyun 	    is_chan_passive:1,
2555*4882a593Smuzhiyun 	    allow_ht:1,
2556*4882a593Smuzhiyun 	    allow_vht:1,
2557*4882a593Smuzhiyun 	    allow_he:1,
2558*4882a593Smuzhiyun 	    set_agile:1,
2559*4882a593Smuzhiyun 	    psc_channel:1;
2560*4882a593Smuzhiyun 	u32 phy_mode;
2561*4882a593Smuzhiyun 	u32 cfreq1;
2562*4882a593Smuzhiyun 	u32 cfreq2;
2563*4882a593Smuzhiyun 	char   maxpower;
2564*4882a593Smuzhiyun 	char   minpower;
2565*4882a593Smuzhiyun 	char   maxregpower;
2566*4882a593Smuzhiyun 	u8  antennamax;
2567*4882a593Smuzhiyun 	u8  reg_class_id;
2568*4882a593Smuzhiyun } __packed;
2569*4882a593Smuzhiyun 
2570*4882a593Smuzhiyun enum wmi_phy_mode {
2571*4882a593Smuzhiyun 	MODE_11A        = 0,
2572*4882a593Smuzhiyun 	MODE_11G        = 1,   /* 11b/g Mode */
2573*4882a593Smuzhiyun 	MODE_11B        = 2,   /* 11b Mode */
2574*4882a593Smuzhiyun 	MODE_11GONLY    = 3,   /* 11g only Mode */
2575*4882a593Smuzhiyun 	MODE_11NA_HT20   = 4,
2576*4882a593Smuzhiyun 	MODE_11NG_HT20   = 5,
2577*4882a593Smuzhiyun 	MODE_11NA_HT40   = 6,
2578*4882a593Smuzhiyun 	MODE_11NG_HT40   = 7,
2579*4882a593Smuzhiyun 	MODE_11AC_VHT20 = 8,
2580*4882a593Smuzhiyun 	MODE_11AC_VHT40 = 9,
2581*4882a593Smuzhiyun 	MODE_11AC_VHT80 = 10,
2582*4882a593Smuzhiyun 	MODE_11AC_VHT20_2G = 11,
2583*4882a593Smuzhiyun 	MODE_11AC_VHT40_2G = 12,
2584*4882a593Smuzhiyun 	MODE_11AC_VHT80_2G = 13,
2585*4882a593Smuzhiyun 	MODE_11AC_VHT80_80 = 14,
2586*4882a593Smuzhiyun 	MODE_11AC_VHT160 = 15,
2587*4882a593Smuzhiyun 	MODE_11AX_HE20 = 16,
2588*4882a593Smuzhiyun 	MODE_11AX_HE40 = 17,
2589*4882a593Smuzhiyun 	MODE_11AX_HE80 = 18,
2590*4882a593Smuzhiyun 	MODE_11AX_HE80_80 = 19,
2591*4882a593Smuzhiyun 	MODE_11AX_HE160 = 20,
2592*4882a593Smuzhiyun 	MODE_11AX_HE20_2G = 21,
2593*4882a593Smuzhiyun 	MODE_11AX_HE40_2G = 22,
2594*4882a593Smuzhiyun 	MODE_11AX_HE80_2G = 23,
2595*4882a593Smuzhiyun 	MODE_UNKNOWN = 24,
2596*4882a593Smuzhiyun 	MODE_MAX = 24
2597*4882a593Smuzhiyun };
2598*4882a593Smuzhiyun 
ath11k_wmi_phymode_str(enum wmi_phy_mode mode)2599*4882a593Smuzhiyun static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode)
2600*4882a593Smuzhiyun {
2601*4882a593Smuzhiyun 	switch (mode) {
2602*4882a593Smuzhiyun 	case MODE_11A:
2603*4882a593Smuzhiyun 		return "11a";
2604*4882a593Smuzhiyun 	case MODE_11G:
2605*4882a593Smuzhiyun 		return "11g";
2606*4882a593Smuzhiyun 	case MODE_11B:
2607*4882a593Smuzhiyun 		return "11b";
2608*4882a593Smuzhiyun 	case MODE_11GONLY:
2609*4882a593Smuzhiyun 		return "11gonly";
2610*4882a593Smuzhiyun 	case MODE_11NA_HT20:
2611*4882a593Smuzhiyun 		return "11na-ht20";
2612*4882a593Smuzhiyun 	case MODE_11NG_HT20:
2613*4882a593Smuzhiyun 		return "11ng-ht20";
2614*4882a593Smuzhiyun 	case MODE_11NA_HT40:
2615*4882a593Smuzhiyun 		return "11na-ht40";
2616*4882a593Smuzhiyun 	case MODE_11NG_HT40:
2617*4882a593Smuzhiyun 		return "11ng-ht40";
2618*4882a593Smuzhiyun 	case MODE_11AC_VHT20:
2619*4882a593Smuzhiyun 		return "11ac-vht20";
2620*4882a593Smuzhiyun 	case MODE_11AC_VHT40:
2621*4882a593Smuzhiyun 		return "11ac-vht40";
2622*4882a593Smuzhiyun 	case MODE_11AC_VHT80:
2623*4882a593Smuzhiyun 		return "11ac-vht80";
2624*4882a593Smuzhiyun 	case MODE_11AC_VHT160:
2625*4882a593Smuzhiyun 		return "11ac-vht160";
2626*4882a593Smuzhiyun 	case MODE_11AC_VHT80_80:
2627*4882a593Smuzhiyun 		return "11ac-vht80+80";
2628*4882a593Smuzhiyun 	case MODE_11AC_VHT20_2G:
2629*4882a593Smuzhiyun 		return "11ac-vht20-2g";
2630*4882a593Smuzhiyun 	case MODE_11AC_VHT40_2G:
2631*4882a593Smuzhiyun 		return "11ac-vht40-2g";
2632*4882a593Smuzhiyun 	case MODE_11AC_VHT80_2G:
2633*4882a593Smuzhiyun 		return "11ac-vht80-2g";
2634*4882a593Smuzhiyun 	case MODE_11AX_HE20:
2635*4882a593Smuzhiyun 		return "11ax-he20";
2636*4882a593Smuzhiyun 	case MODE_11AX_HE40:
2637*4882a593Smuzhiyun 		return "11ax-he40";
2638*4882a593Smuzhiyun 	case MODE_11AX_HE80:
2639*4882a593Smuzhiyun 		return "11ax-he80";
2640*4882a593Smuzhiyun 	case MODE_11AX_HE80_80:
2641*4882a593Smuzhiyun 		return "11ax-he80+80";
2642*4882a593Smuzhiyun 	case MODE_11AX_HE160:
2643*4882a593Smuzhiyun 		return "11ax-he160";
2644*4882a593Smuzhiyun 	case MODE_11AX_HE20_2G:
2645*4882a593Smuzhiyun 		return "11ax-he20-2g";
2646*4882a593Smuzhiyun 	case MODE_11AX_HE40_2G:
2647*4882a593Smuzhiyun 		return "11ax-he40-2g";
2648*4882a593Smuzhiyun 	case MODE_11AX_HE80_2G:
2649*4882a593Smuzhiyun 		return "11ax-he80-2g";
2650*4882a593Smuzhiyun 	case MODE_UNKNOWN:
2651*4882a593Smuzhiyun 		/* skip */
2652*4882a593Smuzhiyun 		break;
2653*4882a593Smuzhiyun 
2654*4882a593Smuzhiyun 		/* no default handler to allow compiler to check that the
2655*4882a593Smuzhiyun 		 * enum is fully handled
2656*4882a593Smuzhiyun 		 */
2657*4882a593Smuzhiyun 	}
2658*4882a593Smuzhiyun 
2659*4882a593Smuzhiyun 	return "<unknown>";
2660*4882a593Smuzhiyun }
2661*4882a593Smuzhiyun 
2662*4882a593Smuzhiyun struct wmi_channel_arg {
2663*4882a593Smuzhiyun 	u32 freq;
2664*4882a593Smuzhiyun 	u32 band_center_freq1;
2665*4882a593Smuzhiyun 	u32 band_center_freq2;
2666*4882a593Smuzhiyun 	bool passive;
2667*4882a593Smuzhiyun 	bool allow_ibss;
2668*4882a593Smuzhiyun 	bool allow_ht;
2669*4882a593Smuzhiyun 	bool allow_vht;
2670*4882a593Smuzhiyun 	bool ht40plus;
2671*4882a593Smuzhiyun 	bool chan_radar;
2672*4882a593Smuzhiyun 	bool freq2_radar;
2673*4882a593Smuzhiyun 	bool allow_he;
2674*4882a593Smuzhiyun 	u32 min_power;
2675*4882a593Smuzhiyun 	u32 max_power;
2676*4882a593Smuzhiyun 	u32 max_reg_power;
2677*4882a593Smuzhiyun 	u32 max_antenna_gain;
2678*4882a593Smuzhiyun 	enum wmi_phy_mode mode;
2679*4882a593Smuzhiyun };
2680*4882a593Smuzhiyun 
2681*4882a593Smuzhiyun struct wmi_vdev_start_req_arg {
2682*4882a593Smuzhiyun 	u32 vdev_id;
2683*4882a593Smuzhiyun 	struct wmi_channel_arg channel;
2684*4882a593Smuzhiyun 	u32 bcn_intval;
2685*4882a593Smuzhiyun 	u32 dtim_period;
2686*4882a593Smuzhiyun 	u8 *ssid;
2687*4882a593Smuzhiyun 	u32 ssid_len;
2688*4882a593Smuzhiyun 	u32 bcn_tx_rate;
2689*4882a593Smuzhiyun 	u32 bcn_tx_power;
2690*4882a593Smuzhiyun 	bool disable_hw_ack;
2691*4882a593Smuzhiyun 	bool hidden_ssid;
2692*4882a593Smuzhiyun 	bool pmf_enabled;
2693*4882a593Smuzhiyun 	u32 he_ops;
2694*4882a593Smuzhiyun 	u32 cac_duration_ms;
2695*4882a593Smuzhiyun 	u32 regdomain;
2696*4882a593Smuzhiyun 	u32 pref_rx_streams;
2697*4882a593Smuzhiyun 	u32 pref_tx_streams;
2698*4882a593Smuzhiyun 	u32 num_noa_descriptors;
2699*4882a593Smuzhiyun };
2700*4882a593Smuzhiyun 
2701*4882a593Smuzhiyun struct peer_create_params {
2702*4882a593Smuzhiyun 	const u8 *peer_addr;
2703*4882a593Smuzhiyun 	u32 peer_type;
2704*4882a593Smuzhiyun 	u32 vdev_id;
2705*4882a593Smuzhiyun };
2706*4882a593Smuzhiyun 
2707*4882a593Smuzhiyun struct peer_delete_params {
2708*4882a593Smuzhiyun 	u8 vdev_id;
2709*4882a593Smuzhiyun };
2710*4882a593Smuzhiyun 
2711*4882a593Smuzhiyun struct peer_flush_params {
2712*4882a593Smuzhiyun 	u32 peer_tid_bitmap;
2713*4882a593Smuzhiyun 	u8 vdev_id;
2714*4882a593Smuzhiyun };
2715*4882a593Smuzhiyun 
2716*4882a593Smuzhiyun struct pdev_set_regdomain_params {
2717*4882a593Smuzhiyun 	u16 current_rd_in_use;
2718*4882a593Smuzhiyun 	u16 current_rd_2g;
2719*4882a593Smuzhiyun 	u16 current_rd_5g;
2720*4882a593Smuzhiyun 	u32 ctl_2g;
2721*4882a593Smuzhiyun 	u32 ctl_5g;
2722*4882a593Smuzhiyun 	u8 dfs_domain;
2723*4882a593Smuzhiyun 	u32 pdev_id;
2724*4882a593Smuzhiyun };
2725*4882a593Smuzhiyun 
2726*4882a593Smuzhiyun struct rx_reorder_queue_remove_params {
2727*4882a593Smuzhiyun 	u8 *peer_macaddr;
2728*4882a593Smuzhiyun 	u16 vdev_id;
2729*4882a593Smuzhiyun 	u32 peer_tid_bitmap;
2730*4882a593Smuzhiyun };
2731*4882a593Smuzhiyun 
2732*4882a593Smuzhiyun #define WMI_HOST_PDEV_ID_SOC 0xFF
2733*4882a593Smuzhiyun #define WMI_HOST_PDEV_ID_0   0
2734*4882a593Smuzhiyun #define WMI_HOST_PDEV_ID_1   1
2735*4882a593Smuzhiyun #define WMI_HOST_PDEV_ID_2   2
2736*4882a593Smuzhiyun 
2737*4882a593Smuzhiyun #define WMI_PDEV_ID_SOC         0
2738*4882a593Smuzhiyun #define WMI_PDEV_ID_1ST         1
2739*4882a593Smuzhiyun #define WMI_PDEV_ID_2ND         2
2740*4882a593Smuzhiyun #define WMI_PDEV_ID_3RD         3
2741*4882a593Smuzhiyun 
2742*4882a593Smuzhiyun /* Freq units in MHz */
2743*4882a593Smuzhiyun #define REG_RULE_START_FREQ			0x0000ffff
2744*4882a593Smuzhiyun #define REG_RULE_END_FREQ			0xffff0000
2745*4882a593Smuzhiyun #define REG_RULE_FLAGS				0x0000ffff
2746*4882a593Smuzhiyun #define REG_RULE_MAX_BW				0x0000ffff
2747*4882a593Smuzhiyun #define REG_RULE_REG_PWR			0x00ff0000
2748*4882a593Smuzhiyun #define REG_RULE_ANT_GAIN			0xff000000
2749*4882a593Smuzhiyun 
2750*4882a593Smuzhiyun #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
2751*4882a593Smuzhiyun #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
2752*4882a593Smuzhiyun #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
2753*4882a593Smuzhiyun #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
2754*4882a593Smuzhiyun 
2755*4882a593Smuzhiyun #define HECAP_PHYDWORD_0	0
2756*4882a593Smuzhiyun #define HECAP_PHYDWORD_1	1
2757*4882a593Smuzhiyun #define HECAP_PHYDWORD_2	2
2758*4882a593Smuzhiyun 
2759*4882a593Smuzhiyun #define HECAP_PHY_SU_BFER		BIT(31)
2760*4882a593Smuzhiyun #define HECAP_PHY_SU_BFEE		BIT(0)
2761*4882a593Smuzhiyun #define HECAP_PHY_MU_BFER		BIT(1)
2762*4882a593Smuzhiyun #define HECAP_PHY_UL_MUMIMO		BIT(22)
2763*4882a593Smuzhiyun #define HECAP_PHY_UL_MUOFDMA		BIT(23)
2764*4882a593Smuzhiyun 
2765*4882a593Smuzhiyun #define HECAP_PHY_SUBFMR_GET(hecap_phy) \
2766*4882a593Smuzhiyun 	FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HECAP_PHYDWORD_0])
2767*4882a593Smuzhiyun 
2768*4882a593Smuzhiyun #define HECAP_PHY_SUBFME_GET(hecap_phy) \
2769*4882a593Smuzhiyun 	FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HECAP_PHYDWORD_1])
2770*4882a593Smuzhiyun 
2771*4882a593Smuzhiyun #define HECAP_PHY_MUBFMR_GET(hecap_phy) \
2772*4882a593Smuzhiyun 	FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HECAP_PHYDWORD_1])
2773*4882a593Smuzhiyun 
2774*4882a593Smuzhiyun #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \
2775*4882a593Smuzhiyun 	FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HECAP_PHYDWORD_0])
2776*4882a593Smuzhiyun 
2777*4882a593Smuzhiyun #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \
2778*4882a593Smuzhiyun 	FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HECAP_PHYDWORD_0])
2779*4882a593Smuzhiyun 
2780*4882a593Smuzhiyun #define HE_MODE_SU_TX_BFEE	BIT(0)
2781*4882a593Smuzhiyun #define HE_MODE_SU_TX_BFER	BIT(1)
2782*4882a593Smuzhiyun #define HE_MODE_MU_TX_BFEE	BIT(2)
2783*4882a593Smuzhiyun #define HE_MODE_MU_TX_BFER	BIT(3)
2784*4882a593Smuzhiyun #define HE_MODE_DL_OFDMA	BIT(4)
2785*4882a593Smuzhiyun #define HE_MODE_UL_OFDMA	BIT(5)
2786*4882a593Smuzhiyun #define HE_MODE_UL_MUMIMO	BIT(6)
2787*4882a593Smuzhiyun 
2788*4882a593Smuzhiyun #define HE_DL_MUOFDMA_ENABLE	1
2789*4882a593Smuzhiyun #define HE_UL_MUOFDMA_ENABLE	1
2790*4882a593Smuzhiyun #define HE_DL_MUMIMO_ENABLE	1
2791*4882a593Smuzhiyun #define HE_MU_BFEE_ENABLE	1
2792*4882a593Smuzhiyun #define HE_SU_BFEE_ENABLE	1
2793*4882a593Smuzhiyun 
2794*4882a593Smuzhiyun #define HE_VHT_SOUNDING_MODE_ENABLE		1
2795*4882a593Smuzhiyun #define HE_SU_MU_SOUNDING_MODE_ENABLE		1
2796*4882a593Smuzhiyun #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE	1
2797*4882a593Smuzhiyun 
2798*4882a593Smuzhiyun /* HE or VHT Sounding */
2799*4882a593Smuzhiyun #define HE_VHT_SOUNDING_MODE		BIT(0)
2800*4882a593Smuzhiyun /* SU or MU Sounding */
2801*4882a593Smuzhiyun #define HE_SU_MU_SOUNDING_MODE		BIT(2)
2802*4882a593Smuzhiyun /* Trig or Non-Trig Sounding */
2803*4882a593Smuzhiyun #define HE_TRIG_NONTRIG_SOUNDING_MODE	BIT(3)
2804*4882a593Smuzhiyun 
2805*4882a593Smuzhiyun #define WMI_TXBF_STS_CAP_OFFSET_LSB	4
2806*4882a593Smuzhiyun #define WMI_TXBF_STS_CAP_OFFSET_MASK	0x70
2807*4882a593Smuzhiyun #define WMI_BF_SOUND_DIM_OFFSET_LSB	8
2808*4882a593Smuzhiyun #define WMI_BF_SOUND_DIM_OFFSET_MASK	0x700
2809*4882a593Smuzhiyun 
2810*4882a593Smuzhiyun struct pdev_params {
2811*4882a593Smuzhiyun 	u32 param_id;
2812*4882a593Smuzhiyun 	u32 param_value;
2813*4882a593Smuzhiyun };
2814*4882a593Smuzhiyun 
2815*4882a593Smuzhiyun enum wmi_peer_type {
2816*4882a593Smuzhiyun 	WMI_PEER_TYPE_DEFAULT = 0,
2817*4882a593Smuzhiyun 	WMI_PEER_TYPE_BSS = 1,
2818*4882a593Smuzhiyun 	WMI_PEER_TYPE_TDLS = 2,
2819*4882a593Smuzhiyun };
2820*4882a593Smuzhiyun 
2821*4882a593Smuzhiyun struct wmi_peer_create_cmd {
2822*4882a593Smuzhiyun 	u32 tlv_header;
2823*4882a593Smuzhiyun 	u32 vdev_id;
2824*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2825*4882a593Smuzhiyun 	u32 peer_type;
2826*4882a593Smuzhiyun } __packed;
2827*4882a593Smuzhiyun 
2828*4882a593Smuzhiyun struct wmi_peer_delete_cmd {
2829*4882a593Smuzhiyun 	u32 tlv_header;
2830*4882a593Smuzhiyun 	u32 vdev_id;
2831*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2832*4882a593Smuzhiyun } __packed;
2833*4882a593Smuzhiyun 
2834*4882a593Smuzhiyun struct wmi_peer_reorder_queue_setup_cmd {
2835*4882a593Smuzhiyun 	u32 tlv_header;
2836*4882a593Smuzhiyun 	u32 vdev_id;
2837*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2838*4882a593Smuzhiyun 	u32 tid;
2839*4882a593Smuzhiyun 	u32 queue_ptr_lo;
2840*4882a593Smuzhiyun 	u32 queue_ptr_hi;
2841*4882a593Smuzhiyun 	u32 queue_no;
2842*4882a593Smuzhiyun 	u32 ba_window_size_valid;
2843*4882a593Smuzhiyun 	u32 ba_window_size;
2844*4882a593Smuzhiyun } __packed;
2845*4882a593Smuzhiyun 
2846*4882a593Smuzhiyun struct wmi_peer_reorder_queue_remove_cmd {
2847*4882a593Smuzhiyun 	u32 tlv_header;
2848*4882a593Smuzhiyun 	u32 vdev_id;
2849*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2850*4882a593Smuzhiyun 	u32 tid_mask;
2851*4882a593Smuzhiyun } __packed;
2852*4882a593Smuzhiyun 
2853*4882a593Smuzhiyun struct gpio_config_params {
2854*4882a593Smuzhiyun 	u32 gpio_num;
2855*4882a593Smuzhiyun 	u32 input;
2856*4882a593Smuzhiyun 	u32 pull_type;
2857*4882a593Smuzhiyun 	u32 intr_mode;
2858*4882a593Smuzhiyun };
2859*4882a593Smuzhiyun 
2860*4882a593Smuzhiyun enum wmi_gpio_type {
2861*4882a593Smuzhiyun 	WMI_GPIO_PULL_NONE,
2862*4882a593Smuzhiyun 	WMI_GPIO_PULL_UP,
2863*4882a593Smuzhiyun 	WMI_GPIO_PULL_DOWN
2864*4882a593Smuzhiyun };
2865*4882a593Smuzhiyun 
2866*4882a593Smuzhiyun enum wmi_gpio_intr_type {
2867*4882a593Smuzhiyun 	WMI_GPIO_INTTYPE_DISABLE,
2868*4882a593Smuzhiyun 	WMI_GPIO_INTTYPE_RISING_EDGE,
2869*4882a593Smuzhiyun 	WMI_GPIO_INTTYPE_FALLING_EDGE,
2870*4882a593Smuzhiyun 	WMI_GPIO_INTTYPE_BOTH_EDGE,
2871*4882a593Smuzhiyun 	WMI_GPIO_INTTYPE_LEVEL_LOW,
2872*4882a593Smuzhiyun 	WMI_GPIO_INTTYPE_LEVEL_HIGH
2873*4882a593Smuzhiyun };
2874*4882a593Smuzhiyun 
2875*4882a593Smuzhiyun enum wmi_bss_chan_info_req_type {
2876*4882a593Smuzhiyun 	WMI_BSS_SURVEY_REQ_TYPE_READ = 1,
2877*4882a593Smuzhiyun 	WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR,
2878*4882a593Smuzhiyun };
2879*4882a593Smuzhiyun 
2880*4882a593Smuzhiyun struct wmi_gpio_config_cmd_param {
2881*4882a593Smuzhiyun 	u32 tlv_header;
2882*4882a593Smuzhiyun 	u32 gpio_num;
2883*4882a593Smuzhiyun 	u32 input;
2884*4882a593Smuzhiyun 	u32 pull_type;
2885*4882a593Smuzhiyun 	u32 intr_mode;
2886*4882a593Smuzhiyun };
2887*4882a593Smuzhiyun 
2888*4882a593Smuzhiyun struct gpio_output_params {
2889*4882a593Smuzhiyun 	u32 gpio_num;
2890*4882a593Smuzhiyun 	u32 set;
2891*4882a593Smuzhiyun };
2892*4882a593Smuzhiyun 
2893*4882a593Smuzhiyun struct wmi_gpio_output_cmd_param {
2894*4882a593Smuzhiyun 	u32 tlv_header;
2895*4882a593Smuzhiyun 	u32 gpio_num;
2896*4882a593Smuzhiyun 	u32 set;
2897*4882a593Smuzhiyun };
2898*4882a593Smuzhiyun 
2899*4882a593Smuzhiyun struct set_fwtest_params {
2900*4882a593Smuzhiyun 	u32 arg;
2901*4882a593Smuzhiyun 	u32 value;
2902*4882a593Smuzhiyun };
2903*4882a593Smuzhiyun 
2904*4882a593Smuzhiyun struct wmi_fwtest_set_param_cmd_param {
2905*4882a593Smuzhiyun 	u32 tlv_header;
2906*4882a593Smuzhiyun 	u32 param_id;
2907*4882a593Smuzhiyun 	u32 param_value;
2908*4882a593Smuzhiyun };
2909*4882a593Smuzhiyun 
2910*4882a593Smuzhiyun struct wmi_pdev_set_param_cmd {
2911*4882a593Smuzhiyun 	u32 tlv_header;
2912*4882a593Smuzhiyun 	u32 pdev_id;
2913*4882a593Smuzhiyun 	u32 param_id;
2914*4882a593Smuzhiyun 	u32 param_value;
2915*4882a593Smuzhiyun } __packed;
2916*4882a593Smuzhiyun 
2917*4882a593Smuzhiyun struct wmi_pdev_set_ps_mode_cmd {
2918*4882a593Smuzhiyun 	u32 tlv_header;
2919*4882a593Smuzhiyun 	u32 vdev_id;
2920*4882a593Smuzhiyun 	u32 sta_ps_mode;
2921*4882a593Smuzhiyun } __packed;
2922*4882a593Smuzhiyun 
2923*4882a593Smuzhiyun struct wmi_pdev_suspend_cmd {
2924*4882a593Smuzhiyun 	u32 tlv_header;
2925*4882a593Smuzhiyun 	u32 pdev_id;
2926*4882a593Smuzhiyun 	u32 suspend_opt;
2927*4882a593Smuzhiyun } __packed;
2928*4882a593Smuzhiyun 
2929*4882a593Smuzhiyun struct wmi_pdev_resume_cmd {
2930*4882a593Smuzhiyun 	u32 tlv_header;
2931*4882a593Smuzhiyun 	u32 pdev_id;
2932*4882a593Smuzhiyun } __packed;
2933*4882a593Smuzhiyun 
2934*4882a593Smuzhiyun struct wmi_pdev_bss_chan_info_req_cmd {
2935*4882a593Smuzhiyun 	u32 tlv_header;
2936*4882a593Smuzhiyun 	/* ref wmi_bss_chan_info_req_type */
2937*4882a593Smuzhiyun 	u32 req_type;
2938*4882a593Smuzhiyun 	u32 pdev_id;
2939*4882a593Smuzhiyun } __packed;
2940*4882a593Smuzhiyun 
2941*4882a593Smuzhiyun struct wmi_ap_ps_peer_cmd {
2942*4882a593Smuzhiyun 	u32 tlv_header;
2943*4882a593Smuzhiyun 	u32 vdev_id;
2944*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2945*4882a593Smuzhiyun 	u32 param;
2946*4882a593Smuzhiyun 	u32 value;
2947*4882a593Smuzhiyun } __packed;
2948*4882a593Smuzhiyun 
2949*4882a593Smuzhiyun struct wmi_sta_powersave_param_cmd {
2950*4882a593Smuzhiyun 	u32 tlv_header;
2951*4882a593Smuzhiyun 	u32 vdev_id;
2952*4882a593Smuzhiyun 	u32 param;
2953*4882a593Smuzhiyun 	u32 value;
2954*4882a593Smuzhiyun } __packed;
2955*4882a593Smuzhiyun 
2956*4882a593Smuzhiyun struct wmi_pdev_set_regdomain_cmd {
2957*4882a593Smuzhiyun 	u32 tlv_header;
2958*4882a593Smuzhiyun 	u32 pdev_id;
2959*4882a593Smuzhiyun 	u32 reg_domain;
2960*4882a593Smuzhiyun 	u32 reg_domain_2g;
2961*4882a593Smuzhiyun 	u32 reg_domain_5g;
2962*4882a593Smuzhiyun 	u32 conformance_test_limit_2g;
2963*4882a593Smuzhiyun 	u32 conformance_test_limit_5g;
2964*4882a593Smuzhiyun 	u32 dfs_domain;
2965*4882a593Smuzhiyun } __packed;
2966*4882a593Smuzhiyun 
2967*4882a593Smuzhiyun struct wmi_peer_set_param_cmd {
2968*4882a593Smuzhiyun 	u32 tlv_header;
2969*4882a593Smuzhiyun 	u32 vdev_id;
2970*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2971*4882a593Smuzhiyun 	u32 param_id;
2972*4882a593Smuzhiyun 	u32 param_value;
2973*4882a593Smuzhiyun } __packed;
2974*4882a593Smuzhiyun 
2975*4882a593Smuzhiyun struct wmi_peer_flush_tids_cmd {
2976*4882a593Smuzhiyun 	u32 tlv_header;
2977*4882a593Smuzhiyun 	u32 vdev_id;
2978*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
2979*4882a593Smuzhiyun 	u32 peer_tid_bitmap;
2980*4882a593Smuzhiyun } __packed;
2981*4882a593Smuzhiyun 
2982*4882a593Smuzhiyun struct wmi_dfs_phyerr_offload_cmd {
2983*4882a593Smuzhiyun 	u32 tlv_header;
2984*4882a593Smuzhiyun 	u32 pdev_id;
2985*4882a593Smuzhiyun } __packed;
2986*4882a593Smuzhiyun 
2987*4882a593Smuzhiyun struct wmi_bcn_offload_ctrl_cmd {
2988*4882a593Smuzhiyun 	u32 tlv_header;
2989*4882a593Smuzhiyun 	u32 vdev_id;
2990*4882a593Smuzhiyun 	u32 bcn_ctrl_op;
2991*4882a593Smuzhiyun } __packed;
2992*4882a593Smuzhiyun 
2993*4882a593Smuzhiyun enum scan_dwelltime_adaptive_mode {
2994*4882a593Smuzhiyun 	SCAN_DWELL_MODE_DEFAULT = 0,
2995*4882a593Smuzhiyun 	SCAN_DWELL_MODE_CONSERVATIVE = 1,
2996*4882a593Smuzhiyun 	SCAN_DWELL_MODE_MODERATE = 2,
2997*4882a593Smuzhiyun 	SCAN_DWELL_MODE_AGGRESSIVE = 3,
2998*4882a593Smuzhiyun 	SCAN_DWELL_MODE_STATIC = 4
2999*4882a593Smuzhiyun };
3000*4882a593Smuzhiyun 
3001*4882a593Smuzhiyun #define WLAN_SCAN_MAX_NUM_SSID          10
3002*4882a593Smuzhiyun #define WLAN_SCAN_MAX_NUM_BSSID         10
3003*4882a593Smuzhiyun #define WLAN_SCAN_MAX_NUM_CHANNELS      40
3004*4882a593Smuzhiyun 
3005*4882a593Smuzhiyun #define WLAN_SSID_MAX_LEN 32
3006*4882a593Smuzhiyun 
3007*4882a593Smuzhiyun struct element_info {
3008*4882a593Smuzhiyun 	u32 len;
3009*4882a593Smuzhiyun 	u8 *ptr;
3010*4882a593Smuzhiyun };
3011*4882a593Smuzhiyun 
3012*4882a593Smuzhiyun struct wlan_ssid {
3013*4882a593Smuzhiyun 	u8 length;
3014*4882a593Smuzhiyun 	u8 ssid[WLAN_SSID_MAX_LEN];
3015*4882a593Smuzhiyun };
3016*4882a593Smuzhiyun 
3017*4882a593Smuzhiyun #define WMI_IE_BITMAP_SIZE             8
3018*4882a593Smuzhiyun 
3019*4882a593Smuzhiyun #define WMI_SCAN_MAX_NUM_SSID                0x0A
3020*4882a593Smuzhiyun /* prefix used by scan requestor ids on the host */
3021*4882a593Smuzhiyun #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
3022*4882a593Smuzhiyun 
3023*4882a593Smuzhiyun /* prefix used by scan request ids generated on the host */
3024*4882a593Smuzhiyun /* host cycles through the lower 12 bits to generate ids */
3025*4882a593Smuzhiyun #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
3026*4882a593Smuzhiyun 
3027*4882a593Smuzhiyun #define WLAN_SCAN_PARAMS_MAX_SSID    16
3028*4882a593Smuzhiyun #define WLAN_SCAN_PARAMS_MAX_BSSID   4
3029*4882a593Smuzhiyun #define WLAN_SCAN_PARAMS_MAX_IE_LEN  256
3030*4882a593Smuzhiyun 
3031*4882a593Smuzhiyun /* Values lower than this may be refused by some firmware revisions with a scan
3032*4882a593Smuzhiyun  * completion with a timedout reason.
3033*4882a593Smuzhiyun  */
3034*4882a593Smuzhiyun #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40
3035*4882a593Smuzhiyun 
3036*4882a593Smuzhiyun /* Scan priority numbers must be sequential, starting with 0 */
3037*4882a593Smuzhiyun enum wmi_scan_priority {
3038*4882a593Smuzhiyun 	WMI_SCAN_PRIORITY_VERY_LOW = 0,
3039*4882a593Smuzhiyun 	WMI_SCAN_PRIORITY_LOW,
3040*4882a593Smuzhiyun 	WMI_SCAN_PRIORITY_MEDIUM,
3041*4882a593Smuzhiyun 	WMI_SCAN_PRIORITY_HIGH,
3042*4882a593Smuzhiyun 	WMI_SCAN_PRIORITY_VERY_HIGH,
3043*4882a593Smuzhiyun 	WMI_SCAN_PRIORITY_COUNT   /* number of priorities supported */
3044*4882a593Smuzhiyun };
3045*4882a593Smuzhiyun 
3046*4882a593Smuzhiyun enum wmi_scan_event_type {
3047*4882a593Smuzhiyun 	WMI_SCAN_EVENT_STARTED              = BIT(0),
3048*4882a593Smuzhiyun 	WMI_SCAN_EVENT_COMPLETED            = BIT(1),
3049*4882a593Smuzhiyun 	WMI_SCAN_EVENT_BSS_CHANNEL          = BIT(2),
3050*4882a593Smuzhiyun 	WMI_SCAN_EVENT_FOREIGN_CHAN         = BIT(3),
3051*4882a593Smuzhiyun 	WMI_SCAN_EVENT_DEQUEUED             = BIT(4),
3052*4882a593Smuzhiyun 	/* possibly by high-prio scan */
3053*4882a593Smuzhiyun 	WMI_SCAN_EVENT_PREEMPTED            = BIT(5),
3054*4882a593Smuzhiyun 	WMI_SCAN_EVENT_START_FAILED         = BIT(6),
3055*4882a593Smuzhiyun 	WMI_SCAN_EVENT_RESTARTED            = BIT(7),
3056*4882a593Smuzhiyun 	WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT    = BIT(8),
3057*4882a593Smuzhiyun 	WMI_SCAN_EVENT_SUSPENDED            = BIT(9),
3058*4882a593Smuzhiyun 	WMI_SCAN_EVENT_RESUMED              = BIT(10),
3059*4882a593Smuzhiyun 	WMI_SCAN_EVENT_MAX                  = BIT(15),
3060*4882a593Smuzhiyun };
3061*4882a593Smuzhiyun 
3062*4882a593Smuzhiyun enum wmi_scan_completion_reason {
3063*4882a593Smuzhiyun 	WMI_SCAN_REASON_COMPLETED,
3064*4882a593Smuzhiyun 	WMI_SCAN_REASON_CANCELLED,
3065*4882a593Smuzhiyun 	WMI_SCAN_REASON_PREEMPTED,
3066*4882a593Smuzhiyun 	WMI_SCAN_REASON_TIMEDOUT,
3067*4882a593Smuzhiyun 	WMI_SCAN_REASON_INTERNAL_FAILURE,
3068*4882a593Smuzhiyun 	WMI_SCAN_REASON_MAX,
3069*4882a593Smuzhiyun };
3070*4882a593Smuzhiyun 
3071*4882a593Smuzhiyun struct  wmi_start_scan_cmd {
3072*4882a593Smuzhiyun 	u32 tlv_header;
3073*4882a593Smuzhiyun 	u32 scan_id;
3074*4882a593Smuzhiyun 	u32 scan_req_id;
3075*4882a593Smuzhiyun 	u32 vdev_id;
3076*4882a593Smuzhiyun 	u32 scan_priority;
3077*4882a593Smuzhiyun 	u32 notify_scan_events;
3078*4882a593Smuzhiyun 	u32 dwell_time_active;
3079*4882a593Smuzhiyun 	u32 dwell_time_passive;
3080*4882a593Smuzhiyun 	u32 min_rest_time;
3081*4882a593Smuzhiyun 	u32 max_rest_time;
3082*4882a593Smuzhiyun 	u32 repeat_probe_time;
3083*4882a593Smuzhiyun 	u32 probe_spacing_time;
3084*4882a593Smuzhiyun 	u32 idle_time;
3085*4882a593Smuzhiyun 	u32 max_scan_time;
3086*4882a593Smuzhiyun 	u32 probe_delay;
3087*4882a593Smuzhiyun 	u32 scan_ctrl_flags;
3088*4882a593Smuzhiyun 	u32 burst_duration;
3089*4882a593Smuzhiyun 	u32 num_chan;
3090*4882a593Smuzhiyun 	u32 num_bssid;
3091*4882a593Smuzhiyun 	u32 num_ssids;
3092*4882a593Smuzhiyun 	u32 ie_len;
3093*4882a593Smuzhiyun 	u32 n_probes;
3094*4882a593Smuzhiyun 	struct wmi_mac_addr mac_addr;
3095*4882a593Smuzhiyun 	struct wmi_mac_addr mac_mask;
3096*4882a593Smuzhiyun 	u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3097*4882a593Smuzhiyun 	u32 num_vendor_oui;
3098*4882a593Smuzhiyun 	u32 scan_ctrl_flags_ext;
3099*4882a593Smuzhiyun 	u32 dwell_time_active_2g;
3100*4882a593Smuzhiyun 	u32 dwell_time_active_6g;
3101*4882a593Smuzhiyun 	u32 dwell_time_passive_6g;
3102*4882a593Smuzhiyun 	u32 scan_start_offset;
3103*4882a593Smuzhiyun } __packed;
3104*4882a593Smuzhiyun 
3105*4882a593Smuzhiyun #define WMI_SCAN_FLAG_PASSIVE        0x1
3106*4882a593Smuzhiyun #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
3107*4882a593Smuzhiyun #define WMI_SCAN_ADD_CCK_RATES       0x4
3108*4882a593Smuzhiyun #define WMI_SCAN_ADD_OFDM_RATES      0x8
3109*4882a593Smuzhiyun #define WMI_SCAN_CHAN_STAT_EVENT     0x10
3110*4882a593Smuzhiyun #define WMI_SCAN_FILTER_PROBE_REQ    0x20
3111*4882a593Smuzhiyun #define WMI_SCAN_BYPASS_DFS_CHN      0x40
3112*4882a593Smuzhiyun #define WMI_SCAN_CONTINUE_ON_ERROR   0x80
3113*4882a593Smuzhiyun #define WMI_SCAN_FILTER_PROMISCUOS   0x100
3114*4882a593Smuzhiyun #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200
3115*4882a593Smuzhiyun #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ  0x400
3116*4882a593Smuzhiyun #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ   0x800
3117*4882a593Smuzhiyun #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ   0x1000
3118*4882a593Smuzhiyun #define WMI_SCAN_OFFCHAN_MGMT_TX    0x2000
3119*4882a593Smuzhiyun #define WMI_SCAN_OFFCHAN_DATA_TX    0x4000
3120*4882a593Smuzhiyun #define WMI_SCAN_CAPTURE_PHY_ERROR  0x8000
3121*4882a593Smuzhiyun #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000
3122*4882a593Smuzhiyun #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT      0x20000
3123*4882a593Smuzhiyun #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT   0x40000
3124*4882a593Smuzhiyun #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000
3125*4882a593Smuzhiyun #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000
3126*4882a593Smuzhiyun 
3127*4882a593Smuzhiyun #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000
3128*4882a593Smuzhiyun #define WMI_SCAN_DWELL_MODE_SHIFT        21
3129*4882a593Smuzhiyun 
3130*4882a593Smuzhiyun enum {
3131*4882a593Smuzhiyun 	WMI_SCAN_DWELL_MODE_DEFAULT      = 0,
3132*4882a593Smuzhiyun 	WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1,
3133*4882a593Smuzhiyun 	WMI_SCAN_DWELL_MODE_MODERATE     = 2,
3134*4882a593Smuzhiyun 	WMI_SCAN_DWELL_MODE_AGGRESSIVE   = 3,
3135*4882a593Smuzhiyun 	WMI_SCAN_DWELL_MODE_STATIC       = 4,
3136*4882a593Smuzhiyun };
3137*4882a593Smuzhiyun 
3138*4882a593Smuzhiyun #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \
3139*4882a593Smuzhiyun 	((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \
3140*4882a593Smuzhiyun 		    WMI_SCAN_DWELL_MODE_MASK))
3141*4882a593Smuzhiyun 
3142*4882a593Smuzhiyun struct hint_short_ssid {
3143*4882a593Smuzhiyun 	u32 freq_flags;
3144*4882a593Smuzhiyun 	u32 short_ssid;
3145*4882a593Smuzhiyun };
3146*4882a593Smuzhiyun 
3147*4882a593Smuzhiyun struct hint_bssid {
3148*4882a593Smuzhiyun 	u32 freq_flags;
3149*4882a593Smuzhiyun 	struct wmi_mac_addr bssid;
3150*4882a593Smuzhiyun };
3151*4882a593Smuzhiyun 
3152*4882a593Smuzhiyun struct scan_req_params {
3153*4882a593Smuzhiyun 	u32 scan_id;
3154*4882a593Smuzhiyun 	u32 scan_req_id;
3155*4882a593Smuzhiyun 	u32 vdev_id;
3156*4882a593Smuzhiyun 	u32 pdev_id;
3157*4882a593Smuzhiyun 	enum wmi_scan_priority scan_priority;
3158*4882a593Smuzhiyun 	union {
3159*4882a593Smuzhiyun 		struct {
3160*4882a593Smuzhiyun 			u32 scan_ev_started:1,
3161*4882a593Smuzhiyun 			    scan_ev_completed:1,
3162*4882a593Smuzhiyun 			    scan_ev_bss_chan:1,
3163*4882a593Smuzhiyun 			    scan_ev_foreign_chan:1,
3164*4882a593Smuzhiyun 			    scan_ev_dequeued:1,
3165*4882a593Smuzhiyun 			    scan_ev_preempted:1,
3166*4882a593Smuzhiyun 			    scan_ev_start_failed:1,
3167*4882a593Smuzhiyun 			    scan_ev_restarted:1,
3168*4882a593Smuzhiyun 			    scan_ev_foreign_chn_exit:1,
3169*4882a593Smuzhiyun 			    scan_ev_invalid:1,
3170*4882a593Smuzhiyun 			    scan_ev_gpio_timeout:1,
3171*4882a593Smuzhiyun 			    scan_ev_suspended:1,
3172*4882a593Smuzhiyun 			    scan_ev_resumed:1;
3173*4882a593Smuzhiyun 		};
3174*4882a593Smuzhiyun 		u32 scan_events;
3175*4882a593Smuzhiyun 	};
3176*4882a593Smuzhiyun 	u32 dwell_time_active;
3177*4882a593Smuzhiyun 	u32 dwell_time_active_2g;
3178*4882a593Smuzhiyun 	u32 dwell_time_passive;
3179*4882a593Smuzhiyun 	u32 dwell_time_active_6g;
3180*4882a593Smuzhiyun 	u32 dwell_time_passive_6g;
3181*4882a593Smuzhiyun 	u32 min_rest_time;
3182*4882a593Smuzhiyun 	u32 max_rest_time;
3183*4882a593Smuzhiyun 	u32 repeat_probe_time;
3184*4882a593Smuzhiyun 	u32 probe_spacing_time;
3185*4882a593Smuzhiyun 	u32 idle_time;
3186*4882a593Smuzhiyun 	u32 max_scan_time;
3187*4882a593Smuzhiyun 	u32 probe_delay;
3188*4882a593Smuzhiyun 	union {
3189*4882a593Smuzhiyun 		struct {
3190*4882a593Smuzhiyun 			u32 scan_f_passive:1,
3191*4882a593Smuzhiyun 			    scan_f_bcast_probe:1,
3192*4882a593Smuzhiyun 			    scan_f_cck_rates:1,
3193*4882a593Smuzhiyun 			    scan_f_ofdm_rates:1,
3194*4882a593Smuzhiyun 			    scan_f_chan_stat_evnt:1,
3195*4882a593Smuzhiyun 			    scan_f_filter_prb_req:1,
3196*4882a593Smuzhiyun 			    scan_f_bypass_dfs_chn:1,
3197*4882a593Smuzhiyun 			    scan_f_continue_on_err:1,
3198*4882a593Smuzhiyun 			    scan_f_offchan_mgmt_tx:1,
3199*4882a593Smuzhiyun 			    scan_f_offchan_data_tx:1,
3200*4882a593Smuzhiyun 			    scan_f_promisc_mode:1,
3201*4882a593Smuzhiyun 			    scan_f_capture_phy_err:1,
3202*4882a593Smuzhiyun 			    scan_f_strict_passive_pch:1,
3203*4882a593Smuzhiyun 			    scan_f_half_rate:1,
3204*4882a593Smuzhiyun 			    scan_f_quarter_rate:1,
3205*4882a593Smuzhiyun 			    scan_f_force_active_dfs_chn:1,
3206*4882a593Smuzhiyun 			    scan_f_add_tpc_ie_in_probe:1,
3207*4882a593Smuzhiyun 			    scan_f_add_ds_ie_in_probe:1,
3208*4882a593Smuzhiyun 			    scan_f_add_spoofed_mac_in_probe:1,
3209*4882a593Smuzhiyun 			    scan_f_add_rand_seq_in_probe:1,
3210*4882a593Smuzhiyun 			    scan_f_en_ie_whitelist_in_probe:1,
3211*4882a593Smuzhiyun 			    scan_f_forced:1,
3212*4882a593Smuzhiyun 			    scan_f_2ghz:1,
3213*4882a593Smuzhiyun 			    scan_f_5ghz:1,
3214*4882a593Smuzhiyun 			    scan_f_80mhz:1;
3215*4882a593Smuzhiyun 		};
3216*4882a593Smuzhiyun 		u32 scan_flags;
3217*4882a593Smuzhiyun 	};
3218*4882a593Smuzhiyun 	enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode;
3219*4882a593Smuzhiyun 	u32 burst_duration;
3220*4882a593Smuzhiyun 	u32 num_chan;
3221*4882a593Smuzhiyun 	u32 num_bssid;
3222*4882a593Smuzhiyun 	u32 num_ssids;
3223*4882a593Smuzhiyun 	u32 n_probes;
3224*4882a593Smuzhiyun 	u32 chan_list[WLAN_SCAN_MAX_NUM_CHANNELS];
3225*4882a593Smuzhiyun 	u32 notify_scan_events;
3226*4882a593Smuzhiyun 	struct wlan_ssid ssid[WLAN_SCAN_MAX_NUM_SSID];
3227*4882a593Smuzhiyun 	struct wmi_mac_addr bssid_list[WLAN_SCAN_MAX_NUM_BSSID];
3228*4882a593Smuzhiyun 	struct element_info extraie;
3229*4882a593Smuzhiyun 	struct element_info htcap;
3230*4882a593Smuzhiyun 	struct element_info vhtcap;
3231*4882a593Smuzhiyun 	u32 num_hint_s_ssid;
3232*4882a593Smuzhiyun 	u32 num_hint_bssid;
3233*4882a593Smuzhiyun 	struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID];
3234*4882a593Smuzhiyun 	struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID];
3235*4882a593Smuzhiyun };
3236*4882a593Smuzhiyun 
3237*4882a593Smuzhiyun struct wmi_ssid_arg {
3238*4882a593Smuzhiyun 	int len;
3239*4882a593Smuzhiyun 	const u8 *ssid;
3240*4882a593Smuzhiyun };
3241*4882a593Smuzhiyun 
3242*4882a593Smuzhiyun struct wmi_bssid_arg {
3243*4882a593Smuzhiyun 	const u8 *bssid;
3244*4882a593Smuzhiyun };
3245*4882a593Smuzhiyun 
3246*4882a593Smuzhiyun struct wmi_start_scan_arg {
3247*4882a593Smuzhiyun 	u32 scan_id;
3248*4882a593Smuzhiyun 	u32 scan_req_id;
3249*4882a593Smuzhiyun 	u32 vdev_id;
3250*4882a593Smuzhiyun 	u32 scan_priority;
3251*4882a593Smuzhiyun 	u32 notify_scan_events;
3252*4882a593Smuzhiyun 	u32 dwell_time_active;
3253*4882a593Smuzhiyun 	u32 dwell_time_passive;
3254*4882a593Smuzhiyun 	u32 min_rest_time;
3255*4882a593Smuzhiyun 	u32 max_rest_time;
3256*4882a593Smuzhiyun 	u32 repeat_probe_time;
3257*4882a593Smuzhiyun 	u32 probe_spacing_time;
3258*4882a593Smuzhiyun 	u32 idle_time;
3259*4882a593Smuzhiyun 	u32 max_scan_time;
3260*4882a593Smuzhiyun 	u32 probe_delay;
3261*4882a593Smuzhiyun 	u32 scan_ctrl_flags;
3262*4882a593Smuzhiyun 
3263*4882a593Smuzhiyun 	u32 ie_len;
3264*4882a593Smuzhiyun 	u32 n_channels;
3265*4882a593Smuzhiyun 	u32 n_ssids;
3266*4882a593Smuzhiyun 	u32 n_bssids;
3267*4882a593Smuzhiyun 
3268*4882a593Smuzhiyun 	u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
3269*4882a593Smuzhiyun 	u32 channels[64];
3270*4882a593Smuzhiyun 	struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
3271*4882a593Smuzhiyun 	struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
3272*4882a593Smuzhiyun };
3273*4882a593Smuzhiyun 
3274*4882a593Smuzhiyun #define WMI_SCAN_STOP_ONE       0x00000000
3275*4882a593Smuzhiyun #define WMI_SCN_STOP_VAP_ALL    0x01000000
3276*4882a593Smuzhiyun #define WMI_SCAN_STOP_ALL       0x04000000
3277*4882a593Smuzhiyun 
3278*4882a593Smuzhiyun /* Prefix 0xA000 indicates that the scan request
3279*4882a593Smuzhiyun  * is trigger by HOST
3280*4882a593Smuzhiyun  */
3281*4882a593Smuzhiyun #define ATH11K_SCAN_ID          0xA000
3282*4882a593Smuzhiyun 
3283*4882a593Smuzhiyun enum scan_cancel_req_type {
3284*4882a593Smuzhiyun 	WLAN_SCAN_CANCEL_SINGLE = 1,
3285*4882a593Smuzhiyun 	WLAN_SCAN_CANCEL_VDEV_ALL,
3286*4882a593Smuzhiyun 	WLAN_SCAN_CANCEL_PDEV_ALL,
3287*4882a593Smuzhiyun };
3288*4882a593Smuzhiyun 
3289*4882a593Smuzhiyun struct scan_cancel_param {
3290*4882a593Smuzhiyun 	u32 requester;
3291*4882a593Smuzhiyun 	u32 scan_id;
3292*4882a593Smuzhiyun 	enum scan_cancel_req_type req_type;
3293*4882a593Smuzhiyun 	u32 vdev_id;
3294*4882a593Smuzhiyun 	u32 pdev_id;
3295*4882a593Smuzhiyun };
3296*4882a593Smuzhiyun 
3297*4882a593Smuzhiyun struct  wmi_bcn_send_from_host_cmd {
3298*4882a593Smuzhiyun 	u32 tlv_header;
3299*4882a593Smuzhiyun 	u32 vdev_id;
3300*4882a593Smuzhiyun 	u32 data_len;
3301*4882a593Smuzhiyun 	union {
3302*4882a593Smuzhiyun 		u32 frag_ptr;
3303*4882a593Smuzhiyun 		u32 frag_ptr_lo;
3304*4882a593Smuzhiyun 	};
3305*4882a593Smuzhiyun 	u32 frame_ctrl;
3306*4882a593Smuzhiyun 	u32 dtim_flag;
3307*4882a593Smuzhiyun 	u32 bcn_antenna;
3308*4882a593Smuzhiyun 	u32 frag_ptr_hi;
3309*4882a593Smuzhiyun };
3310*4882a593Smuzhiyun 
3311*4882a593Smuzhiyun #define WMI_CHAN_INFO_MODE		GENMASK(5, 0)
3312*4882a593Smuzhiyun #define WMI_CHAN_INFO_HT40_PLUS		BIT(6)
3313*4882a593Smuzhiyun #define WMI_CHAN_INFO_PASSIVE		BIT(7)
3314*4882a593Smuzhiyun #define WMI_CHAN_INFO_ADHOC_ALLOWED	BIT(8)
3315*4882a593Smuzhiyun #define WMI_CHAN_INFO_AP_DISABLED	BIT(9)
3316*4882a593Smuzhiyun #define WMI_CHAN_INFO_DFS		BIT(10)
3317*4882a593Smuzhiyun #define WMI_CHAN_INFO_ALLOW_HT		BIT(11)
3318*4882a593Smuzhiyun #define WMI_CHAN_INFO_ALLOW_VHT		BIT(12)
3319*4882a593Smuzhiyun #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA	BIT(13)
3320*4882a593Smuzhiyun #define WMI_CHAN_INFO_HALF_RATE		BIT(14)
3321*4882a593Smuzhiyun #define WMI_CHAN_INFO_QUARTER_RATE	BIT(15)
3322*4882a593Smuzhiyun #define WMI_CHAN_INFO_DFS_FREQ2		BIT(16)
3323*4882a593Smuzhiyun #define WMI_CHAN_INFO_ALLOW_HE		BIT(17)
3324*4882a593Smuzhiyun #define WMI_CHAN_INFO_PSC		BIT(18)
3325*4882a593Smuzhiyun 
3326*4882a593Smuzhiyun #define WMI_CHAN_REG_INFO1_MIN_PWR	GENMASK(7, 0)
3327*4882a593Smuzhiyun #define WMI_CHAN_REG_INFO1_MAX_PWR	GENMASK(15, 8)
3328*4882a593Smuzhiyun #define WMI_CHAN_REG_INFO1_MAX_REG_PWR	GENMASK(23, 16)
3329*4882a593Smuzhiyun #define WMI_CHAN_REG_INFO1_REG_CLS	GENMASK(31, 24)
3330*4882a593Smuzhiyun 
3331*4882a593Smuzhiyun #define WMI_CHAN_REG_INFO2_ANT_MAX	GENMASK(7, 0)
3332*4882a593Smuzhiyun #define WMI_CHAN_REG_INFO2_MAX_TX_PWR	GENMASK(15, 8)
3333*4882a593Smuzhiyun 
3334*4882a593Smuzhiyun struct wmi_channel {
3335*4882a593Smuzhiyun 	u32 tlv_header;
3336*4882a593Smuzhiyun 	u32 mhz;
3337*4882a593Smuzhiyun 	u32 band_center_freq1;
3338*4882a593Smuzhiyun 	u32 band_center_freq2;
3339*4882a593Smuzhiyun 	u32 info;
3340*4882a593Smuzhiyun 	u32 reg_info_1;
3341*4882a593Smuzhiyun 	u32 reg_info_2;
3342*4882a593Smuzhiyun } __packed;
3343*4882a593Smuzhiyun 
3344*4882a593Smuzhiyun struct wmi_mgmt_params {
3345*4882a593Smuzhiyun 	void *tx_frame;
3346*4882a593Smuzhiyun 	u16 frm_len;
3347*4882a593Smuzhiyun 	u8 vdev_id;
3348*4882a593Smuzhiyun 	u16 chanfreq;
3349*4882a593Smuzhiyun 	void *pdata;
3350*4882a593Smuzhiyun 	u16 desc_id;
3351*4882a593Smuzhiyun 	u8 *macaddr;
3352*4882a593Smuzhiyun 	void *qdf_ctx;
3353*4882a593Smuzhiyun };
3354*4882a593Smuzhiyun 
3355*4882a593Smuzhiyun enum wmi_sta_ps_mode {
3356*4882a593Smuzhiyun 	WMI_STA_PS_MODE_DISABLED = 0,
3357*4882a593Smuzhiyun 	WMI_STA_PS_MODE_ENABLED = 1,
3358*4882a593Smuzhiyun };
3359*4882a593Smuzhiyun 
3360*4882a593Smuzhiyun #define WMI_SMPS_MASK_LOWER_16BITS 0xFF
3361*4882a593Smuzhiyun #define WMI_SMPS_MASK_UPPER_3BITS 0x7
3362*4882a593Smuzhiyun #define WMI_SMPS_PARAM_VALUE_SHIFT 29
3363*4882a593Smuzhiyun 
3364*4882a593Smuzhiyun #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1
3365*4882a593Smuzhiyun #define ATH11K_WMI_FW_HANG_DELAY 0
3366*4882a593Smuzhiyun 
3367*4882a593Smuzhiyun /* type, 0:unused 1: ASSERT 2: not respond detect command
3368*4882a593Smuzhiyun  * delay_time_ms, the simulate will delay time
3369*4882a593Smuzhiyun  */
3370*4882a593Smuzhiyun 
3371*4882a593Smuzhiyun struct wmi_force_fw_hang_cmd {
3372*4882a593Smuzhiyun 	u32 tlv_header;
3373*4882a593Smuzhiyun 	u32 type;
3374*4882a593Smuzhiyun 	u32 delay_time_ms;
3375*4882a593Smuzhiyun };
3376*4882a593Smuzhiyun 
3377*4882a593Smuzhiyun struct wmi_vdev_set_param_cmd {
3378*4882a593Smuzhiyun 	u32 tlv_header;
3379*4882a593Smuzhiyun 	u32 vdev_id;
3380*4882a593Smuzhiyun 	u32 param_id;
3381*4882a593Smuzhiyun 	u32 param_value;
3382*4882a593Smuzhiyun } __packed;
3383*4882a593Smuzhiyun 
3384*4882a593Smuzhiyun enum wmi_stats_id {
3385*4882a593Smuzhiyun 	WMI_REQUEST_PEER_STAT			= BIT(0),
3386*4882a593Smuzhiyun 	WMI_REQUEST_AP_STAT			= BIT(1),
3387*4882a593Smuzhiyun 	WMI_REQUEST_PDEV_STAT			= BIT(2),
3388*4882a593Smuzhiyun 	WMI_REQUEST_VDEV_STAT			= BIT(3),
3389*4882a593Smuzhiyun 	WMI_REQUEST_BCNFLT_STAT			= BIT(4),
3390*4882a593Smuzhiyun 	WMI_REQUEST_VDEV_RATE_STAT		= BIT(5),
3391*4882a593Smuzhiyun 	WMI_REQUEST_INST_STAT			= BIT(6),
3392*4882a593Smuzhiyun 	WMI_REQUEST_MIB_STAT			= BIT(7),
3393*4882a593Smuzhiyun 	WMI_REQUEST_RSSI_PER_CHAIN_STAT		= BIT(8),
3394*4882a593Smuzhiyun 	WMI_REQUEST_CONGESTION_STAT		= BIT(9),
3395*4882a593Smuzhiyun 	WMI_REQUEST_PEER_EXTD_STAT		= BIT(10),
3396*4882a593Smuzhiyun 	WMI_REQUEST_BCN_STAT			= BIT(11),
3397*4882a593Smuzhiyun 	WMI_REQUEST_BCN_STAT_RESET		= BIT(12),
3398*4882a593Smuzhiyun 	WMI_REQUEST_PEER_EXTD2_STAT		= BIT(13),
3399*4882a593Smuzhiyun };
3400*4882a593Smuzhiyun 
3401*4882a593Smuzhiyun struct wmi_request_stats_cmd {
3402*4882a593Smuzhiyun 	u32 tlv_header;
3403*4882a593Smuzhiyun 	enum wmi_stats_id stats_id;
3404*4882a593Smuzhiyun 	u32 vdev_id;
3405*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3406*4882a593Smuzhiyun 	u32 pdev_id;
3407*4882a593Smuzhiyun } __packed;
3408*4882a593Smuzhiyun 
3409*4882a593Smuzhiyun struct wmi_get_pdev_temperature_cmd {
3410*4882a593Smuzhiyun 	u32 tlv_header;
3411*4882a593Smuzhiyun 	u32 param;
3412*4882a593Smuzhiyun 	u32 pdev_id;
3413*4882a593Smuzhiyun } __packed;
3414*4882a593Smuzhiyun 
3415*4882a593Smuzhiyun #define WMI_BEACON_TX_BUFFER_SIZE	512
3416*4882a593Smuzhiyun 
3417*4882a593Smuzhiyun struct wmi_bcn_tmpl_cmd {
3418*4882a593Smuzhiyun 	u32 tlv_header;
3419*4882a593Smuzhiyun 	u32 vdev_id;
3420*4882a593Smuzhiyun 	u32 tim_ie_offset;
3421*4882a593Smuzhiyun 	u32 buf_len;
3422*4882a593Smuzhiyun 	u32 csa_switch_count_offset;
3423*4882a593Smuzhiyun 	u32 ext_csa_switch_count_offset;
3424*4882a593Smuzhiyun 	u32 csa_event_bitmap;
3425*4882a593Smuzhiyun 	u32 mbssid_ie_offset;
3426*4882a593Smuzhiyun 	u32 esp_ie_offset;
3427*4882a593Smuzhiyun } __packed;
3428*4882a593Smuzhiyun 
3429*4882a593Smuzhiyun struct wmi_key_seq_counter {
3430*4882a593Smuzhiyun 	u32 key_seq_counter_l;
3431*4882a593Smuzhiyun 	u32 key_seq_counter_h;
3432*4882a593Smuzhiyun } __packed;
3433*4882a593Smuzhiyun 
3434*4882a593Smuzhiyun struct wmi_vdev_install_key_cmd {
3435*4882a593Smuzhiyun 	u32 tlv_header;
3436*4882a593Smuzhiyun 	u32 vdev_id;
3437*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3438*4882a593Smuzhiyun 	u32 key_idx;
3439*4882a593Smuzhiyun 	u32 key_flags;
3440*4882a593Smuzhiyun 	u32 key_cipher;
3441*4882a593Smuzhiyun 	struct wmi_key_seq_counter key_rsc_counter;
3442*4882a593Smuzhiyun 	struct wmi_key_seq_counter key_global_rsc_counter;
3443*4882a593Smuzhiyun 	struct wmi_key_seq_counter key_tsc_counter;
3444*4882a593Smuzhiyun 	u8 wpi_key_rsc_counter[16];
3445*4882a593Smuzhiyun 	u8 wpi_key_tsc_counter[16];
3446*4882a593Smuzhiyun 	u32 key_len;
3447*4882a593Smuzhiyun 	u32 key_txmic_len;
3448*4882a593Smuzhiyun 	u32 key_rxmic_len;
3449*4882a593Smuzhiyun 	u32 is_group_key_id_valid;
3450*4882a593Smuzhiyun 	u32 group_key_id;
3451*4882a593Smuzhiyun 
3452*4882a593Smuzhiyun 	/* Followed by key_data containing key followed by
3453*4882a593Smuzhiyun 	 * tx mic and then rx mic
3454*4882a593Smuzhiyun 	 */
3455*4882a593Smuzhiyun } __packed;
3456*4882a593Smuzhiyun 
3457*4882a593Smuzhiyun struct wmi_vdev_install_key_arg {
3458*4882a593Smuzhiyun 	u32 vdev_id;
3459*4882a593Smuzhiyun 	const u8 *macaddr;
3460*4882a593Smuzhiyun 	u32 key_idx;
3461*4882a593Smuzhiyun 	u32 key_flags;
3462*4882a593Smuzhiyun 	u32 key_cipher;
3463*4882a593Smuzhiyun 	u32 key_len;
3464*4882a593Smuzhiyun 	u32 key_txmic_len;
3465*4882a593Smuzhiyun 	u32 key_rxmic_len;
3466*4882a593Smuzhiyun 	u64 key_rsc_counter;
3467*4882a593Smuzhiyun 	const void *key_data;
3468*4882a593Smuzhiyun };
3469*4882a593Smuzhiyun 
3470*4882a593Smuzhiyun #define WMI_MAX_SUPPORTED_RATES			128
3471*4882a593Smuzhiyun #define WMI_HOST_MAX_HECAP_PHY_SIZE		3
3472*4882a593Smuzhiyun #define WMI_HOST_MAX_HE_RATE_SET		3
3473*4882a593Smuzhiyun #define WMI_HECAP_TXRX_MCS_NSS_IDX_80		0
3474*4882a593Smuzhiyun #define WMI_HECAP_TXRX_MCS_NSS_IDX_160		1
3475*4882a593Smuzhiyun #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80	2
3476*4882a593Smuzhiyun 
3477*4882a593Smuzhiyun struct wmi_rate_set_arg {
3478*4882a593Smuzhiyun 	u32 num_rates;
3479*4882a593Smuzhiyun 	u8 rates[WMI_MAX_SUPPORTED_RATES];
3480*4882a593Smuzhiyun };
3481*4882a593Smuzhiyun 
3482*4882a593Smuzhiyun struct peer_assoc_params {
3483*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3484*4882a593Smuzhiyun 	u32 vdev_id;
3485*4882a593Smuzhiyun 	u32 peer_new_assoc;
3486*4882a593Smuzhiyun 	u32 peer_associd;
3487*4882a593Smuzhiyun 	u32 peer_flags;
3488*4882a593Smuzhiyun 	u32 peer_caps;
3489*4882a593Smuzhiyun 	u32 peer_listen_intval;
3490*4882a593Smuzhiyun 	u32 peer_ht_caps;
3491*4882a593Smuzhiyun 	u32 peer_max_mpdu;
3492*4882a593Smuzhiyun 	u32 peer_mpdu_density;
3493*4882a593Smuzhiyun 	u32 peer_rate_caps;
3494*4882a593Smuzhiyun 	u32 peer_nss;
3495*4882a593Smuzhiyun 	u32 peer_vht_caps;
3496*4882a593Smuzhiyun 	u32 peer_phymode;
3497*4882a593Smuzhiyun 	u32 peer_ht_info[2];
3498*4882a593Smuzhiyun 	struct wmi_rate_set_arg peer_legacy_rates;
3499*4882a593Smuzhiyun 	struct wmi_rate_set_arg peer_ht_rates;
3500*4882a593Smuzhiyun 	u32 rx_max_rate;
3501*4882a593Smuzhiyun 	u32 rx_mcs_set;
3502*4882a593Smuzhiyun 	u32 tx_max_rate;
3503*4882a593Smuzhiyun 	u32 tx_mcs_set;
3504*4882a593Smuzhiyun 	u8 vht_capable;
3505*4882a593Smuzhiyun 	u8 min_data_rate;
3506*4882a593Smuzhiyun 	u32 tx_max_mcs_nss;
3507*4882a593Smuzhiyun 	u32 peer_bw_rxnss_override;
3508*4882a593Smuzhiyun 	bool is_pmf_enabled;
3509*4882a593Smuzhiyun 	bool is_wme_set;
3510*4882a593Smuzhiyun 	bool qos_flag;
3511*4882a593Smuzhiyun 	bool apsd_flag;
3512*4882a593Smuzhiyun 	bool ht_flag;
3513*4882a593Smuzhiyun 	bool bw_40;
3514*4882a593Smuzhiyun 	bool bw_80;
3515*4882a593Smuzhiyun 	bool bw_160;
3516*4882a593Smuzhiyun 	bool stbc_flag;
3517*4882a593Smuzhiyun 	bool ldpc_flag;
3518*4882a593Smuzhiyun 	bool static_mimops_flag;
3519*4882a593Smuzhiyun 	bool dynamic_mimops_flag;
3520*4882a593Smuzhiyun 	bool spatial_mux_flag;
3521*4882a593Smuzhiyun 	bool vht_flag;
3522*4882a593Smuzhiyun 	bool vht_ng_flag;
3523*4882a593Smuzhiyun 	bool need_ptk_4_way;
3524*4882a593Smuzhiyun 	bool need_gtk_2_way;
3525*4882a593Smuzhiyun 	bool auth_flag;
3526*4882a593Smuzhiyun 	bool safe_mode_enabled;
3527*4882a593Smuzhiyun 	bool amsdu_disable;
3528*4882a593Smuzhiyun 	/* Use common structure */
3529*4882a593Smuzhiyun 	u8 peer_mac[ETH_ALEN];
3530*4882a593Smuzhiyun 
3531*4882a593Smuzhiyun 	bool he_flag;
3532*4882a593Smuzhiyun 	u32 peer_he_cap_macinfo[2];
3533*4882a593Smuzhiyun 	u32 peer_he_cap_macinfo_internal;
3534*4882a593Smuzhiyun 	u32 peer_he_caps_6ghz;
3535*4882a593Smuzhiyun 	u32 peer_he_ops;
3536*4882a593Smuzhiyun 	u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3537*4882a593Smuzhiyun 	u32 peer_he_mcs_count;
3538*4882a593Smuzhiyun 	u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3539*4882a593Smuzhiyun 	u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3540*4882a593Smuzhiyun 	bool twt_responder;
3541*4882a593Smuzhiyun 	bool twt_requester;
3542*4882a593Smuzhiyun 	struct ath11k_ppe_threshold peer_ppet;
3543*4882a593Smuzhiyun };
3544*4882a593Smuzhiyun 
3545*4882a593Smuzhiyun struct  wmi_peer_assoc_complete_cmd {
3546*4882a593Smuzhiyun 	u32 tlv_header;
3547*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3548*4882a593Smuzhiyun 	u32 vdev_id;
3549*4882a593Smuzhiyun 	u32 peer_new_assoc;
3550*4882a593Smuzhiyun 	u32 peer_associd;
3551*4882a593Smuzhiyun 	u32 peer_flags;
3552*4882a593Smuzhiyun 	u32 peer_caps;
3553*4882a593Smuzhiyun 	u32 peer_listen_intval;
3554*4882a593Smuzhiyun 	u32 peer_ht_caps;
3555*4882a593Smuzhiyun 	u32 peer_max_mpdu;
3556*4882a593Smuzhiyun 	u32 peer_mpdu_density;
3557*4882a593Smuzhiyun 	u32 peer_rate_caps;
3558*4882a593Smuzhiyun 	u32 peer_nss;
3559*4882a593Smuzhiyun 	u32 peer_vht_caps;
3560*4882a593Smuzhiyun 	u32 peer_phymode;
3561*4882a593Smuzhiyun 	u32 peer_ht_info[2];
3562*4882a593Smuzhiyun 	u32 num_peer_legacy_rates;
3563*4882a593Smuzhiyun 	u32 num_peer_ht_rates;
3564*4882a593Smuzhiyun 	u32 peer_bw_rxnss_override;
3565*4882a593Smuzhiyun 	struct  wmi_ppe_threshold peer_ppet;
3566*4882a593Smuzhiyun 	u32 peer_he_cap_info;
3567*4882a593Smuzhiyun 	u32 peer_he_ops;
3568*4882a593Smuzhiyun 	u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3569*4882a593Smuzhiyun 	u32 peer_he_mcs;
3570*4882a593Smuzhiyun 	u32 peer_he_cap_info_ext;
3571*4882a593Smuzhiyun 	u32 peer_he_cap_info_internal;
3572*4882a593Smuzhiyun 	u32 min_data_rate;
3573*4882a593Smuzhiyun 	u32 peer_he_caps_6ghz;
3574*4882a593Smuzhiyun } __packed;
3575*4882a593Smuzhiyun 
3576*4882a593Smuzhiyun struct wmi_stop_scan_cmd {
3577*4882a593Smuzhiyun 	u32 tlv_header;
3578*4882a593Smuzhiyun 	u32 requestor;
3579*4882a593Smuzhiyun 	u32 scan_id;
3580*4882a593Smuzhiyun 	u32 req_type;
3581*4882a593Smuzhiyun 	u32 vdev_id;
3582*4882a593Smuzhiyun 	u32 pdev_id;
3583*4882a593Smuzhiyun };
3584*4882a593Smuzhiyun 
3585*4882a593Smuzhiyun struct scan_chan_list_params {
3586*4882a593Smuzhiyun 	u32 pdev_id;
3587*4882a593Smuzhiyun 	u16 nallchans;
3588*4882a593Smuzhiyun 	struct channel_param ch_param[1];
3589*4882a593Smuzhiyun };
3590*4882a593Smuzhiyun 
3591*4882a593Smuzhiyun struct wmi_scan_chan_list_cmd {
3592*4882a593Smuzhiyun 	u32 tlv_header;
3593*4882a593Smuzhiyun 	u32 num_scan_chans;
3594*4882a593Smuzhiyun 	u32 flags;
3595*4882a593Smuzhiyun 	u32 pdev_id;
3596*4882a593Smuzhiyun } __packed;
3597*4882a593Smuzhiyun 
3598*4882a593Smuzhiyun #define WMI_MGMT_SEND_DOWNLD_LEN	64
3599*4882a593Smuzhiyun 
3600*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD0_POWER		GENMASK(7, 0)
3601*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD0_MCS_MASK		GENMASK(19, 8)
3602*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD0_NSS_MASK		GENMASK(27, 20)
3603*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT	GENMASK(31, 28)
3604*4882a593Smuzhiyun 
3605*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK		GENMASK(7, 0)
3606*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD1_BW_MASK		GENMASK(14, 8)
3607*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE	GENMASK(19, 15)
3608*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE		BIT(20)
3609*4882a593Smuzhiyun #define WMI_TX_PARAMS_DWORD1_RSVD		GENMASK(31, 21)
3610*4882a593Smuzhiyun 
3611*4882a593Smuzhiyun struct wmi_mgmt_send_params {
3612*4882a593Smuzhiyun 	u32 tlv_header;
3613*4882a593Smuzhiyun 	u32 tx_params_dword0;
3614*4882a593Smuzhiyun 	u32 tx_params_dword1;
3615*4882a593Smuzhiyun };
3616*4882a593Smuzhiyun 
3617*4882a593Smuzhiyun struct wmi_mgmt_send_cmd {
3618*4882a593Smuzhiyun 	u32 tlv_header;
3619*4882a593Smuzhiyun 	u32 vdev_id;
3620*4882a593Smuzhiyun 	u32 desc_id;
3621*4882a593Smuzhiyun 	u32 chanfreq;
3622*4882a593Smuzhiyun 	u32 paddr_lo;
3623*4882a593Smuzhiyun 	u32 paddr_hi;
3624*4882a593Smuzhiyun 	u32 frame_len;
3625*4882a593Smuzhiyun 	u32 buf_len;
3626*4882a593Smuzhiyun 	u32 tx_params_valid;
3627*4882a593Smuzhiyun 
3628*4882a593Smuzhiyun 	/* This TLV is followed by struct wmi_mgmt_frame */
3629*4882a593Smuzhiyun 
3630*4882a593Smuzhiyun 	/* Followed by struct wmi_mgmt_send_params */
3631*4882a593Smuzhiyun } __packed;
3632*4882a593Smuzhiyun 
3633*4882a593Smuzhiyun struct wmi_sta_powersave_mode_cmd {
3634*4882a593Smuzhiyun 	u32 tlv_header;
3635*4882a593Smuzhiyun 	u32 vdev_id;
3636*4882a593Smuzhiyun 	u32 sta_ps_mode;
3637*4882a593Smuzhiyun };
3638*4882a593Smuzhiyun 
3639*4882a593Smuzhiyun struct wmi_sta_smps_force_mode_cmd {
3640*4882a593Smuzhiyun 	u32 tlv_header;
3641*4882a593Smuzhiyun 	u32 vdev_id;
3642*4882a593Smuzhiyun 	u32 forced_mode;
3643*4882a593Smuzhiyun };
3644*4882a593Smuzhiyun 
3645*4882a593Smuzhiyun struct wmi_sta_smps_param_cmd {
3646*4882a593Smuzhiyun 	u32 tlv_header;
3647*4882a593Smuzhiyun 	u32 vdev_id;
3648*4882a593Smuzhiyun 	u32 param;
3649*4882a593Smuzhiyun 	u32 value;
3650*4882a593Smuzhiyun };
3651*4882a593Smuzhiyun 
3652*4882a593Smuzhiyun struct wmi_bcn_prb_info {
3653*4882a593Smuzhiyun 	u32 tlv_header;
3654*4882a593Smuzhiyun 	u32 caps;
3655*4882a593Smuzhiyun 	u32 erp;
3656*4882a593Smuzhiyun } __packed;
3657*4882a593Smuzhiyun 
3658*4882a593Smuzhiyun enum {
3659*4882a593Smuzhiyun 	WMI_PDEV_SUSPEND,
3660*4882a593Smuzhiyun 	WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
3661*4882a593Smuzhiyun };
3662*4882a593Smuzhiyun 
3663*4882a593Smuzhiyun struct green_ap_ps_params {
3664*4882a593Smuzhiyun 	u32 value;
3665*4882a593Smuzhiyun };
3666*4882a593Smuzhiyun 
3667*4882a593Smuzhiyun struct wmi_pdev_green_ap_ps_enable_cmd_param {
3668*4882a593Smuzhiyun 	u32 tlv_header;
3669*4882a593Smuzhiyun 	u32 pdev_id;
3670*4882a593Smuzhiyun 	u32 enable;
3671*4882a593Smuzhiyun };
3672*4882a593Smuzhiyun 
3673*4882a593Smuzhiyun struct ap_ps_params {
3674*4882a593Smuzhiyun 	u32 vdev_id;
3675*4882a593Smuzhiyun 	u32 param;
3676*4882a593Smuzhiyun 	u32 value;
3677*4882a593Smuzhiyun };
3678*4882a593Smuzhiyun 
3679*4882a593Smuzhiyun struct vdev_set_params {
3680*4882a593Smuzhiyun 	u32 if_id;
3681*4882a593Smuzhiyun 	u32 param_id;
3682*4882a593Smuzhiyun 	u32 param_value;
3683*4882a593Smuzhiyun };
3684*4882a593Smuzhiyun 
3685*4882a593Smuzhiyun struct stats_request_params {
3686*4882a593Smuzhiyun 	u32 stats_id;
3687*4882a593Smuzhiyun 	u32 vdev_id;
3688*4882a593Smuzhiyun 	u32 pdev_id;
3689*4882a593Smuzhiyun };
3690*4882a593Smuzhiyun 
3691*4882a593Smuzhiyun enum set_init_cc_type {
3692*4882a593Smuzhiyun 	WMI_COUNTRY_INFO_TYPE_ALPHA,
3693*4882a593Smuzhiyun 	WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE,
3694*4882a593Smuzhiyun 	WMI_COUNTRY_INFO_TYPE_REGDOMAIN,
3695*4882a593Smuzhiyun };
3696*4882a593Smuzhiyun 
3697*4882a593Smuzhiyun enum set_init_cc_flags {
3698*4882a593Smuzhiyun 	INVALID_CC,
3699*4882a593Smuzhiyun 	CC_IS_SET,
3700*4882a593Smuzhiyun 	REGDMN_IS_SET,
3701*4882a593Smuzhiyun 	ALPHA_IS_SET,
3702*4882a593Smuzhiyun };
3703*4882a593Smuzhiyun 
3704*4882a593Smuzhiyun struct wmi_init_country_params {
3705*4882a593Smuzhiyun 	union {
3706*4882a593Smuzhiyun 		u16 country_code;
3707*4882a593Smuzhiyun 		u16 regdom_id;
3708*4882a593Smuzhiyun 		u8 alpha2[3];
3709*4882a593Smuzhiyun 	} cc_info;
3710*4882a593Smuzhiyun 	enum set_init_cc_flags flags;
3711*4882a593Smuzhiyun };
3712*4882a593Smuzhiyun 
3713*4882a593Smuzhiyun struct wmi_init_country_cmd {
3714*4882a593Smuzhiyun 	u32 tlv_header;
3715*4882a593Smuzhiyun 	u32 pdev_id;
3716*4882a593Smuzhiyun 	u32 init_cc_type;
3717*4882a593Smuzhiyun 	union {
3718*4882a593Smuzhiyun 		u32 country_code;
3719*4882a593Smuzhiyun 		u32 regdom_id;
3720*4882a593Smuzhiyun 		u32 alpha2;
3721*4882a593Smuzhiyun 	} cc_info;
3722*4882a593Smuzhiyun } __packed;
3723*4882a593Smuzhiyun 
3724*4882a593Smuzhiyun #define THERMAL_LEVELS  1
3725*4882a593Smuzhiyun struct tt_level_config {
3726*4882a593Smuzhiyun 	u32 tmplwm;
3727*4882a593Smuzhiyun 	u32 tmphwm;
3728*4882a593Smuzhiyun 	u32 dcoffpercent;
3729*4882a593Smuzhiyun 	u32 priority;
3730*4882a593Smuzhiyun };
3731*4882a593Smuzhiyun 
3732*4882a593Smuzhiyun struct thermal_mitigation_params {
3733*4882a593Smuzhiyun 	u32 pdev_id;
3734*4882a593Smuzhiyun 	u32 enable;
3735*4882a593Smuzhiyun 	u32 dc;
3736*4882a593Smuzhiyun 	u32 dc_per_event;
3737*4882a593Smuzhiyun 	struct tt_level_config levelconf[THERMAL_LEVELS];
3738*4882a593Smuzhiyun };
3739*4882a593Smuzhiyun 
3740*4882a593Smuzhiyun struct wmi_therm_throt_config_request_cmd {
3741*4882a593Smuzhiyun 	u32 tlv_header;
3742*4882a593Smuzhiyun 	u32 pdev_id;
3743*4882a593Smuzhiyun 	u32 enable;
3744*4882a593Smuzhiyun 	u32 dc;
3745*4882a593Smuzhiyun 	u32 dc_per_event;
3746*4882a593Smuzhiyun 	u32 therm_throt_levels;
3747*4882a593Smuzhiyun } __packed;
3748*4882a593Smuzhiyun 
3749*4882a593Smuzhiyun struct wmi_therm_throt_level_config_info {
3750*4882a593Smuzhiyun 	u32 tlv_header;
3751*4882a593Smuzhiyun 	u32 temp_lwm;
3752*4882a593Smuzhiyun 	u32 temp_hwm;
3753*4882a593Smuzhiyun 	u32 dc_off_percent;
3754*4882a593Smuzhiyun 	u32 prio;
3755*4882a593Smuzhiyun } __packed;
3756*4882a593Smuzhiyun 
3757*4882a593Smuzhiyun struct wmi_delba_send_cmd {
3758*4882a593Smuzhiyun 	u32 tlv_header;
3759*4882a593Smuzhiyun 	u32 vdev_id;
3760*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3761*4882a593Smuzhiyun 	u32 tid;
3762*4882a593Smuzhiyun 	u32 initiator;
3763*4882a593Smuzhiyun 	u32 reasoncode;
3764*4882a593Smuzhiyun } __packed;
3765*4882a593Smuzhiyun 
3766*4882a593Smuzhiyun struct wmi_addba_setresponse_cmd {
3767*4882a593Smuzhiyun 	u32 tlv_header;
3768*4882a593Smuzhiyun 	u32 vdev_id;
3769*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3770*4882a593Smuzhiyun 	u32 tid;
3771*4882a593Smuzhiyun 	u32 statuscode;
3772*4882a593Smuzhiyun } __packed;
3773*4882a593Smuzhiyun 
3774*4882a593Smuzhiyun struct wmi_addba_send_cmd {
3775*4882a593Smuzhiyun 	u32 tlv_header;
3776*4882a593Smuzhiyun 	u32 vdev_id;
3777*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3778*4882a593Smuzhiyun 	u32 tid;
3779*4882a593Smuzhiyun 	u32 buffersize;
3780*4882a593Smuzhiyun } __packed;
3781*4882a593Smuzhiyun 
3782*4882a593Smuzhiyun struct wmi_addba_clear_resp_cmd {
3783*4882a593Smuzhiyun 	u32 tlv_header;
3784*4882a593Smuzhiyun 	u32 vdev_id;
3785*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3786*4882a593Smuzhiyun } __packed;
3787*4882a593Smuzhiyun 
3788*4882a593Smuzhiyun struct wmi_pdev_pktlog_filter_info {
3789*4882a593Smuzhiyun 	u32 tlv_header;
3790*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
3791*4882a593Smuzhiyun } __packed;
3792*4882a593Smuzhiyun 
3793*4882a593Smuzhiyun struct wmi_pdev_pktlog_filter_cmd {
3794*4882a593Smuzhiyun 	u32 tlv_header;
3795*4882a593Smuzhiyun 	u32 pdev_id;
3796*4882a593Smuzhiyun 	u32 enable;
3797*4882a593Smuzhiyun 	u32 filter_type;
3798*4882a593Smuzhiyun 	u32 num_mac;
3799*4882a593Smuzhiyun } __packed;
3800*4882a593Smuzhiyun 
3801*4882a593Smuzhiyun enum ath11k_wmi_pktlog_enable {
3802*4882a593Smuzhiyun 	ATH11K_WMI_PKTLOG_ENABLE_AUTO  = 0,
3803*4882a593Smuzhiyun 	ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1,
3804*4882a593Smuzhiyun };
3805*4882a593Smuzhiyun 
3806*4882a593Smuzhiyun struct wmi_pktlog_enable_cmd {
3807*4882a593Smuzhiyun 	u32 tlv_header;
3808*4882a593Smuzhiyun 	u32 pdev_id;
3809*4882a593Smuzhiyun 	u32 evlist; /* WMI_PKTLOG_EVENT */
3810*4882a593Smuzhiyun 	u32 enable;
3811*4882a593Smuzhiyun } __packed;
3812*4882a593Smuzhiyun 
3813*4882a593Smuzhiyun struct wmi_pktlog_disable_cmd {
3814*4882a593Smuzhiyun 	u32 tlv_header;
3815*4882a593Smuzhiyun 	u32 pdev_id;
3816*4882a593Smuzhiyun } __packed;
3817*4882a593Smuzhiyun 
3818*4882a593Smuzhiyun #define DFS_PHYERR_UNIT_TEST_CMD 0
3819*4882a593Smuzhiyun #define DFS_UNIT_TEST_MODULE	0x2b
3820*4882a593Smuzhiyun #define DFS_UNIT_TEST_TOKEN	0xAA
3821*4882a593Smuzhiyun 
3822*4882a593Smuzhiyun enum dfs_test_args_idx {
3823*4882a593Smuzhiyun 	DFS_TEST_CMDID = 0,
3824*4882a593Smuzhiyun 	DFS_TEST_PDEV_ID,
3825*4882a593Smuzhiyun 	DFS_TEST_RADAR_PARAM,
3826*4882a593Smuzhiyun 	DFS_MAX_TEST_ARGS,
3827*4882a593Smuzhiyun };
3828*4882a593Smuzhiyun 
3829*4882a593Smuzhiyun struct wmi_dfs_unit_test_arg {
3830*4882a593Smuzhiyun 	u32 cmd_id;
3831*4882a593Smuzhiyun 	u32 pdev_id;
3832*4882a593Smuzhiyun 	u32 radar_param;
3833*4882a593Smuzhiyun };
3834*4882a593Smuzhiyun 
3835*4882a593Smuzhiyun struct wmi_unit_test_cmd {
3836*4882a593Smuzhiyun 	u32 tlv_header;
3837*4882a593Smuzhiyun 	u32 vdev_id;
3838*4882a593Smuzhiyun 	u32 module_id;
3839*4882a593Smuzhiyun 	u32 num_args;
3840*4882a593Smuzhiyun 	u32 diag_token;
3841*4882a593Smuzhiyun 	/* Followed by test args*/
3842*4882a593Smuzhiyun } __packed;
3843*4882a593Smuzhiyun 
3844*4882a593Smuzhiyun #define MAX_SUPPORTED_RATES 128
3845*4882a593Smuzhiyun 
3846*4882a593Smuzhiyun #define WMI_PEER_AUTH		0x00000001
3847*4882a593Smuzhiyun #define WMI_PEER_QOS		0x00000002
3848*4882a593Smuzhiyun #define WMI_PEER_NEED_PTK_4_WAY	0x00000004
3849*4882a593Smuzhiyun #define WMI_PEER_NEED_GTK_2_WAY	0x00000010
3850*4882a593Smuzhiyun #define WMI_PEER_HE		0x00000400
3851*4882a593Smuzhiyun #define WMI_PEER_APSD		0x00000800
3852*4882a593Smuzhiyun #define WMI_PEER_HT		0x00001000
3853*4882a593Smuzhiyun #define WMI_PEER_40MHZ		0x00002000
3854*4882a593Smuzhiyun #define WMI_PEER_STBC		0x00008000
3855*4882a593Smuzhiyun #define WMI_PEER_LDPC		0x00010000
3856*4882a593Smuzhiyun #define WMI_PEER_DYN_MIMOPS	0x00020000
3857*4882a593Smuzhiyun #define WMI_PEER_STATIC_MIMOPS	0x00040000
3858*4882a593Smuzhiyun #define WMI_PEER_SPATIAL_MUX	0x00200000
3859*4882a593Smuzhiyun #define WMI_PEER_TWT_REQ	0x00400000
3860*4882a593Smuzhiyun #define WMI_PEER_TWT_RESP	0x00800000
3861*4882a593Smuzhiyun #define WMI_PEER_VHT		0x02000000
3862*4882a593Smuzhiyun #define WMI_PEER_80MHZ		0x04000000
3863*4882a593Smuzhiyun #define WMI_PEER_PMF		0x08000000
3864*4882a593Smuzhiyun /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000.
3865*4882a593Smuzhiyun  * Need to be cleaned up
3866*4882a593Smuzhiyun  */
3867*4882a593Smuzhiyun #define WMI_PEER_IS_P2P_CAPABLE	0x20000000
3868*4882a593Smuzhiyun #define WMI_PEER_160MHZ		0x40000000
3869*4882a593Smuzhiyun #define WMI_PEER_SAFEMODE_EN	0x80000000
3870*4882a593Smuzhiyun 
3871*4882a593Smuzhiyun struct beacon_tmpl_params {
3872*4882a593Smuzhiyun 	u8 vdev_id;
3873*4882a593Smuzhiyun 	u32 tim_ie_offset;
3874*4882a593Smuzhiyun 	u32 tmpl_len;
3875*4882a593Smuzhiyun 	u32 tmpl_len_aligned;
3876*4882a593Smuzhiyun 	u32 csa_switch_count_offset;
3877*4882a593Smuzhiyun 	u32 ext_csa_switch_count_offset;
3878*4882a593Smuzhiyun 	u8 *frm;
3879*4882a593Smuzhiyun };
3880*4882a593Smuzhiyun 
3881*4882a593Smuzhiyun struct wmi_rate_set {
3882*4882a593Smuzhiyun 	u32 num_rates;
3883*4882a593Smuzhiyun 	u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
3884*4882a593Smuzhiyun };
3885*4882a593Smuzhiyun 
3886*4882a593Smuzhiyun struct wmi_vht_rate_set {
3887*4882a593Smuzhiyun 	u32 tlv_header;
3888*4882a593Smuzhiyun 	u32 rx_max_rate;
3889*4882a593Smuzhiyun 	u32 rx_mcs_set;
3890*4882a593Smuzhiyun 	u32 tx_max_rate;
3891*4882a593Smuzhiyun 	u32 tx_mcs_set;
3892*4882a593Smuzhiyun 	u32 tx_max_mcs_nss;
3893*4882a593Smuzhiyun } __packed;
3894*4882a593Smuzhiyun 
3895*4882a593Smuzhiyun struct wmi_he_rate_set {
3896*4882a593Smuzhiyun 	u32 tlv_header;
3897*4882a593Smuzhiyun 	u32 rx_mcs_set;
3898*4882a593Smuzhiyun 	u32 tx_mcs_set;
3899*4882a593Smuzhiyun } __packed;
3900*4882a593Smuzhiyun 
3901*4882a593Smuzhiyun #define MAX_REG_RULES 10
3902*4882a593Smuzhiyun #define REG_ALPHA2_LEN 2
3903*4882a593Smuzhiyun 
3904*4882a593Smuzhiyun enum wmi_start_event_param {
3905*4882a593Smuzhiyun 	WMI_VDEV_START_RESP_EVENT = 0,
3906*4882a593Smuzhiyun 	WMI_VDEV_RESTART_RESP_EVENT,
3907*4882a593Smuzhiyun };
3908*4882a593Smuzhiyun 
3909*4882a593Smuzhiyun struct wmi_vdev_start_resp_event {
3910*4882a593Smuzhiyun 	u32 vdev_id;
3911*4882a593Smuzhiyun 	u32 requestor_id;
3912*4882a593Smuzhiyun 	enum wmi_start_event_param resp_type;
3913*4882a593Smuzhiyun 	u32 status;
3914*4882a593Smuzhiyun 	u32 chain_mask;
3915*4882a593Smuzhiyun 	u32 smps_mode;
3916*4882a593Smuzhiyun 	union {
3917*4882a593Smuzhiyun 		u32 mac_id;
3918*4882a593Smuzhiyun 		u32 pdev_id;
3919*4882a593Smuzhiyun 	};
3920*4882a593Smuzhiyun 	u32 cfgd_tx_streams;
3921*4882a593Smuzhiyun 	u32 cfgd_rx_streams;
3922*4882a593Smuzhiyun } __packed;
3923*4882a593Smuzhiyun 
3924*4882a593Smuzhiyun /* VDEV start response status codes */
3925*4882a593Smuzhiyun enum wmi_vdev_start_resp_status_code {
3926*4882a593Smuzhiyun 	WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0,
3927*4882a593Smuzhiyun 	WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1,
3928*4882a593Smuzhiyun 	WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2,
3929*4882a593Smuzhiyun 	WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3,
3930*4882a593Smuzhiyun 	WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4,
3931*4882a593Smuzhiyun };
3932*4882a593Smuzhiyun 
3933*4882a593Smuzhiyun ;
3934*4882a593Smuzhiyun enum cc_setting_code {
3935*4882a593Smuzhiyun 	REG_SET_CC_STATUS_PASS = 0,
3936*4882a593Smuzhiyun 	REG_CURRENT_ALPHA2_NOT_FOUND = 1,
3937*4882a593Smuzhiyun 	REG_INIT_ALPHA2_NOT_FOUND = 2,
3938*4882a593Smuzhiyun 	REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
3939*4882a593Smuzhiyun 	REG_SET_CC_STATUS_NO_MEMORY = 4,
3940*4882a593Smuzhiyun 	REG_SET_CC_STATUS_FAIL = 5,
3941*4882a593Smuzhiyun };
3942*4882a593Smuzhiyun 
3943*4882a593Smuzhiyun /* Regaulatory Rule Flags Passed by FW */
3944*4882a593Smuzhiyun #define REGULATORY_CHAN_DISABLED     BIT(0)
3945*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_IR        BIT(1)
3946*4882a593Smuzhiyun #define REGULATORY_CHAN_RADAR        BIT(3)
3947*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_OFDM      BIT(6)
3948*4882a593Smuzhiyun #define REGULATORY_CHAN_INDOOR_ONLY  BIT(9)
3949*4882a593Smuzhiyun 
3950*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_HT40      BIT(4)
3951*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_80MHZ     BIT(7)
3952*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_160MHZ    BIT(8)
3953*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_20MHZ     BIT(11)
3954*4882a593Smuzhiyun #define REGULATORY_CHAN_NO_10MHZ     BIT(12)
3955*4882a593Smuzhiyun 
3956*4882a593Smuzhiyun enum {
3957*4882a593Smuzhiyun 	WMI_REG_SET_CC_STATUS_PASS = 0,
3958*4882a593Smuzhiyun 	WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1,
3959*4882a593Smuzhiyun 	WMI_REG_INIT_ALPHA2_NOT_FOUND = 2,
3960*4882a593Smuzhiyun 	WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
3961*4882a593Smuzhiyun 	WMI_REG_SET_CC_STATUS_NO_MEMORY = 4,
3962*4882a593Smuzhiyun 	WMI_REG_SET_CC_STATUS_FAIL = 5,
3963*4882a593Smuzhiyun };
3964*4882a593Smuzhiyun 
3965*4882a593Smuzhiyun struct cur_reg_rule {
3966*4882a593Smuzhiyun 	u16 start_freq;
3967*4882a593Smuzhiyun 	u16 end_freq;
3968*4882a593Smuzhiyun 	u16 max_bw;
3969*4882a593Smuzhiyun 	u8 reg_power;
3970*4882a593Smuzhiyun 	u8 ant_gain;
3971*4882a593Smuzhiyun 	u16 flags;
3972*4882a593Smuzhiyun };
3973*4882a593Smuzhiyun 
3974*4882a593Smuzhiyun struct cur_regulatory_info {
3975*4882a593Smuzhiyun 	enum cc_setting_code status_code;
3976*4882a593Smuzhiyun 	u8 num_phy;
3977*4882a593Smuzhiyun 	u8 phy_id;
3978*4882a593Smuzhiyun 	u16 reg_dmn_pair;
3979*4882a593Smuzhiyun 	u16 ctry_code;
3980*4882a593Smuzhiyun 	u8 alpha2[REG_ALPHA2_LEN + 1];
3981*4882a593Smuzhiyun 	u32 dfs_region;
3982*4882a593Smuzhiyun 	u32 phybitmap;
3983*4882a593Smuzhiyun 	u32 min_bw_2g;
3984*4882a593Smuzhiyun 	u32 max_bw_2g;
3985*4882a593Smuzhiyun 	u32 min_bw_5g;
3986*4882a593Smuzhiyun 	u32 max_bw_5g;
3987*4882a593Smuzhiyun 	u32 num_2g_reg_rules;
3988*4882a593Smuzhiyun 	u32 num_5g_reg_rules;
3989*4882a593Smuzhiyun 	struct cur_reg_rule *reg_rules_2g_ptr;
3990*4882a593Smuzhiyun 	struct cur_reg_rule *reg_rules_5g_ptr;
3991*4882a593Smuzhiyun };
3992*4882a593Smuzhiyun 
3993*4882a593Smuzhiyun struct wmi_reg_chan_list_cc_event {
3994*4882a593Smuzhiyun 	u32 status_code;
3995*4882a593Smuzhiyun 	u32 phy_id;
3996*4882a593Smuzhiyun 	u32 alpha2;
3997*4882a593Smuzhiyun 	u32 num_phy;
3998*4882a593Smuzhiyun 	u32 country_id;
3999*4882a593Smuzhiyun 	u32 domain_code;
4000*4882a593Smuzhiyun 	u32 dfs_region;
4001*4882a593Smuzhiyun 	u32 phybitmap;
4002*4882a593Smuzhiyun 	u32 min_bw_2g;
4003*4882a593Smuzhiyun 	u32 max_bw_2g;
4004*4882a593Smuzhiyun 	u32 min_bw_5g;
4005*4882a593Smuzhiyun 	u32 max_bw_5g;
4006*4882a593Smuzhiyun 	u32 num_2g_reg_rules;
4007*4882a593Smuzhiyun 	u32 num_5g_reg_rules;
4008*4882a593Smuzhiyun } __packed;
4009*4882a593Smuzhiyun 
4010*4882a593Smuzhiyun struct wmi_regulatory_rule_struct {
4011*4882a593Smuzhiyun 	u32  tlv_header;
4012*4882a593Smuzhiyun 	u32  freq_info;
4013*4882a593Smuzhiyun 	u32  bw_pwr_info;
4014*4882a593Smuzhiyun 	u32  flag_info;
4015*4882a593Smuzhiyun };
4016*4882a593Smuzhiyun 
4017*4882a593Smuzhiyun struct wmi_peer_delete_resp_event {
4018*4882a593Smuzhiyun 	u32 vdev_id;
4019*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
4020*4882a593Smuzhiyun } __packed;
4021*4882a593Smuzhiyun 
4022*4882a593Smuzhiyun struct wmi_bcn_tx_status_event {
4023*4882a593Smuzhiyun 	u32 vdev_id;
4024*4882a593Smuzhiyun 	u32 tx_status;
4025*4882a593Smuzhiyun } __packed;
4026*4882a593Smuzhiyun 
4027*4882a593Smuzhiyun struct wmi_vdev_stopped_event {
4028*4882a593Smuzhiyun 	u32 vdev_id;
4029*4882a593Smuzhiyun } __packed;
4030*4882a593Smuzhiyun 
4031*4882a593Smuzhiyun struct wmi_pdev_bss_chan_info_event {
4032*4882a593Smuzhiyun 	u32 freq;	/* Units in MHz */
4033*4882a593Smuzhiyun 	u32 noise_floor;	/* units are dBm */
4034*4882a593Smuzhiyun 	/* rx clear - how often the channel was unused */
4035*4882a593Smuzhiyun 	u32 rx_clear_count_low;
4036*4882a593Smuzhiyun 	u32 rx_clear_count_high;
4037*4882a593Smuzhiyun 	/* cycle count - elapsed time during measured period, in clock ticks */
4038*4882a593Smuzhiyun 	u32 cycle_count_low;
4039*4882a593Smuzhiyun 	u32 cycle_count_high;
4040*4882a593Smuzhiyun 	/* tx cycle count - elapsed time spent in tx, in clock ticks */
4041*4882a593Smuzhiyun 	u32 tx_cycle_count_low;
4042*4882a593Smuzhiyun 	u32 tx_cycle_count_high;
4043*4882a593Smuzhiyun 	/* rx cycle count - elapsed time spent in rx, in clock ticks */
4044*4882a593Smuzhiyun 	u32 rx_cycle_count_low;
4045*4882a593Smuzhiyun 	u32 rx_cycle_count_high;
4046*4882a593Smuzhiyun 	/*rx_cycle cnt for my bss in 64bits format */
4047*4882a593Smuzhiyun 	u32 rx_bss_cycle_count_low;
4048*4882a593Smuzhiyun 	u32 rx_bss_cycle_count_high;
4049*4882a593Smuzhiyun 	u32 pdev_id;
4050*4882a593Smuzhiyun } __packed;
4051*4882a593Smuzhiyun 
4052*4882a593Smuzhiyun #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0
4053*4882a593Smuzhiyun 
4054*4882a593Smuzhiyun struct wmi_vdev_install_key_compl_event {
4055*4882a593Smuzhiyun 	u32 vdev_id;
4056*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
4057*4882a593Smuzhiyun 	u32 key_idx;
4058*4882a593Smuzhiyun 	u32 key_flags;
4059*4882a593Smuzhiyun 	u32 status;
4060*4882a593Smuzhiyun } __packed;
4061*4882a593Smuzhiyun 
4062*4882a593Smuzhiyun struct wmi_vdev_install_key_complete_arg {
4063*4882a593Smuzhiyun 	u32 vdev_id;
4064*4882a593Smuzhiyun 	const u8 *macaddr;
4065*4882a593Smuzhiyun 	u32 key_idx;
4066*4882a593Smuzhiyun 	u32 key_flags;
4067*4882a593Smuzhiyun 	u32 status;
4068*4882a593Smuzhiyun };
4069*4882a593Smuzhiyun 
4070*4882a593Smuzhiyun struct wmi_peer_assoc_conf_event {
4071*4882a593Smuzhiyun 	u32 vdev_id;
4072*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
4073*4882a593Smuzhiyun } __packed;
4074*4882a593Smuzhiyun 
4075*4882a593Smuzhiyun struct wmi_peer_assoc_conf_arg {
4076*4882a593Smuzhiyun 	u32 vdev_id;
4077*4882a593Smuzhiyun 	const u8 *macaddr;
4078*4882a593Smuzhiyun };
4079*4882a593Smuzhiyun 
4080*4882a593Smuzhiyun /*
4081*4882a593Smuzhiyun  * PDEV statistics
4082*4882a593Smuzhiyun  */
4083*4882a593Smuzhiyun struct wmi_pdev_stats_base {
4084*4882a593Smuzhiyun 	s32 chan_nf;
4085*4882a593Smuzhiyun 	u32 tx_frame_count; /* Cycles spent transmitting frames */
4086*4882a593Smuzhiyun 	u32 rx_frame_count; /* Cycles spent receiving frames */
4087*4882a593Smuzhiyun 	u32 rx_clear_count; /* Total channel busy time, evidently */
4088*4882a593Smuzhiyun 	u32 cycle_count; /* Total on-channel time */
4089*4882a593Smuzhiyun 	u32 phy_err_count;
4090*4882a593Smuzhiyun 	u32 chan_tx_pwr;
4091*4882a593Smuzhiyun } __packed;
4092*4882a593Smuzhiyun 
4093*4882a593Smuzhiyun struct wmi_pdev_stats_extra {
4094*4882a593Smuzhiyun 	u32 ack_rx_bad;
4095*4882a593Smuzhiyun 	u32 rts_bad;
4096*4882a593Smuzhiyun 	u32 rts_good;
4097*4882a593Smuzhiyun 	u32 fcs_bad;
4098*4882a593Smuzhiyun 	u32 no_beacons;
4099*4882a593Smuzhiyun 	u32 mib_int_count;
4100*4882a593Smuzhiyun } __packed;
4101*4882a593Smuzhiyun 
4102*4882a593Smuzhiyun struct wmi_pdev_stats_tx {
4103*4882a593Smuzhiyun 	/* Num HTT cookies queued to dispatch list */
4104*4882a593Smuzhiyun 	s32 comp_queued;
4105*4882a593Smuzhiyun 
4106*4882a593Smuzhiyun 	/* Num HTT cookies dispatched */
4107*4882a593Smuzhiyun 	s32 comp_delivered;
4108*4882a593Smuzhiyun 
4109*4882a593Smuzhiyun 	/* Num MSDU queued to WAL */
4110*4882a593Smuzhiyun 	s32 msdu_enqued;
4111*4882a593Smuzhiyun 
4112*4882a593Smuzhiyun 	/* Num MPDU queue to WAL */
4113*4882a593Smuzhiyun 	s32 mpdu_enqued;
4114*4882a593Smuzhiyun 
4115*4882a593Smuzhiyun 	/* Num MSDUs dropped by WMM limit */
4116*4882a593Smuzhiyun 	s32 wmm_drop;
4117*4882a593Smuzhiyun 
4118*4882a593Smuzhiyun 	/* Num Local frames queued */
4119*4882a593Smuzhiyun 	s32 local_enqued;
4120*4882a593Smuzhiyun 
4121*4882a593Smuzhiyun 	/* Num Local frames done */
4122*4882a593Smuzhiyun 	s32 local_freed;
4123*4882a593Smuzhiyun 
4124*4882a593Smuzhiyun 	/* Num queued to HW */
4125*4882a593Smuzhiyun 	s32 hw_queued;
4126*4882a593Smuzhiyun 
4127*4882a593Smuzhiyun 	/* Num PPDU reaped from HW */
4128*4882a593Smuzhiyun 	s32 hw_reaped;
4129*4882a593Smuzhiyun 
4130*4882a593Smuzhiyun 	/* Num underruns */
4131*4882a593Smuzhiyun 	s32 underrun;
4132*4882a593Smuzhiyun 
4133*4882a593Smuzhiyun 	/* Num PPDUs cleaned up in TX abort */
4134*4882a593Smuzhiyun 	s32 tx_abort;
4135*4882a593Smuzhiyun 
4136*4882a593Smuzhiyun 	/* Num MPDUs requed by SW */
4137*4882a593Smuzhiyun 	s32 mpdus_requed;
4138*4882a593Smuzhiyun 
4139*4882a593Smuzhiyun 	/* excessive retries */
4140*4882a593Smuzhiyun 	u32 tx_ko;
4141*4882a593Smuzhiyun 
4142*4882a593Smuzhiyun 	/* data hw rate code */
4143*4882a593Smuzhiyun 	u32 data_rc;
4144*4882a593Smuzhiyun 
4145*4882a593Smuzhiyun 	/* Scheduler self triggers */
4146*4882a593Smuzhiyun 	u32 self_triggers;
4147*4882a593Smuzhiyun 
4148*4882a593Smuzhiyun 	/* frames dropped due to excessive sw retries */
4149*4882a593Smuzhiyun 	u32 sw_retry_failure;
4150*4882a593Smuzhiyun 
4151*4882a593Smuzhiyun 	/* illegal rate phy errors  */
4152*4882a593Smuzhiyun 	u32 illgl_rate_phy_err;
4153*4882a593Smuzhiyun 
4154*4882a593Smuzhiyun 	/* wal pdev continuous xretry */
4155*4882a593Smuzhiyun 	u32 pdev_cont_xretry;
4156*4882a593Smuzhiyun 
4157*4882a593Smuzhiyun 	/* wal pdev tx timeouts */
4158*4882a593Smuzhiyun 	u32 pdev_tx_timeout;
4159*4882a593Smuzhiyun 
4160*4882a593Smuzhiyun 	/* wal pdev resets  */
4161*4882a593Smuzhiyun 	u32 pdev_resets;
4162*4882a593Smuzhiyun 
4163*4882a593Smuzhiyun 	/* frames dropped due to non-availability of stateless TIDs */
4164*4882a593Smuzhiyun 	u32 stateless_tid_alloc_failure;
4165*4882a593Smuzhiyun 
4166*4882a593Smuzhiyun 	/* PhY/BB underrun */
4167*4882a593Smuzhiyun 	u32 phy_underrun;
4168*4882a593Smuzhiyun 
4169*4882a593Smuzhiyun 	/* MPDU is more than txop limit */
4170*4882a593Smuzhiyun 	u32 txop_ovf;
4171*4882a593Smuzhiyun } __packed;
4172*4882a593Smuzhiyun 
4173*4882a593Smuzhiyun struct wmi_pdev_stats_rx {
4174*4882a593Smuzhiyun 	/* Cnts any change in ring routing mid-ppdu */
4175*4882a593Smuzhiyun 	s32 mid_ppdu_route_change;
4176*4882a593Smuzhiyun 
4177*4882a593Smuzhiyun 	/* Total number of statuses processed */
4178*4882a593Smuzhiyun 	s32 status_rcvd;
4179*4882a593Smuzhiyun 
4180*4882a593Smuzhiyun 	/* Extra frags on rings 0-3 */
4181*4882a593Smuzhiyun 	s32 r0_frags;
4182*4882a593Smuzhiyun 	s32 r1_frags;
4183*4882a593Smuzhiyun 	s32 r2_frags;
4184*4882a593Smuzhiyun 	s32 r3_frags;
4185*4882a593Smuzhiyun 
4186*4882a593Smuzhiyun 	/* MSDUs / MPDUs delivered to HTT */
4187*4882a593Smuzhiyun 	s32 htt_msdus;
4188*4882a593Smuzhiyun 	s32 htt_mpdus;
4189*4882a593Smuzhiyun 
4190*4882a593Smuzhiyun 	/* MSDUs / MPDUs delivered to local stack */
4191*4882a593Smuzhiyun 	s32 loc_msdus;
4192*4882a593Smuzhiyun 	s32 loc_mpdus;
4193*4882a593Smuzhiyun 
4194*4882a593Smuzhiyun 	/* AMSDUs that have more MSDUs than the status ring size */
4195*4882a593Smuzhiyun 	s32 oversize_amsdu;
4196*4882a593Smuzhiyun 
4197*4882a593Smuzhiyun 	/* Number of PHY errors */
4198*4882a593Smuzhiyun 	s32 phy_errs;
4199*4882a593Smuzhiyun 
4200*4882a593Smuzhiyun 	/* Number of PHY errors drops */
4201*4882a593Smuzhiyun 	s32 phy_err_drop;
4202*4882a593Smuzhiyun 
4203*4882a593Smuzhiyun 	/* Number of mpdu errors - FCS, MIC, ENC etc. */
4204*4882a593Smuzhiyun 	s32 mpdu_errs;
4205*4882a593Smuzhiyun } __packed;
4206*4882a593Smuzhiyun 
4207*4882a593Smuzhiyun struct wmi_pdev_stats {
4208*4882a593Smuzhiyun 	struct wmi_pdev_stats_base base;
4209*4882a593Smuzhiyun 	struct wmi_pdev_stats_tx tx;
4210*4882a593Smuzhiyun 	struct wmi_pdev_stats_rx rx;
4211*4882a593Smuzhiyun } __packed;
4212*4882a593Smuzhiyun 
4213*4882a593Smuzhiyun #define WLAN_MAX_AC 4
4214*4882a593Smuzhiyun #define MAX_TX_RATE_VALUES 10
4215*4882a593Smuzhiyun #define MAX_TX_RATE_VALUES 10
4216*4882a593Smuzhiyun 
4217*4882a593Smuzhiyun struct wmi_vdev_stats {
4218*4882a593Smuzhiyun 	u32 vdev_id;
4219*4882a593Smuzhiyun 	u32 beacon_snr;
4220*4882a593Smuzhiyun 	u32 data_snr;
4221*4882a593Smuzhiyun 	u32 num_tx_frames[WLAN_MAX_AC];
4222*4882a593Smuzhiyun 	u32 num_rx_frames;
4223*4882a593Smuzhiyun 	u32 num_tx_frames_retries[WLAN_MAX_AC];
4224*4882a593Smuzhiyun 	u32 num_tx_frames_failures[WLAN_MAX_AC];
4225*4882a593Smuzhiyun 	u32 num_rts_fail;
4226*4882a593Smuzhiyun 	u32 num_rts_success;
4227*4882a593Smuzhiyun 	u32 num_rx_err;
4228*4882a593Smuzhiyun 	u32 num_rx_discard;
4229*4882a593Smuzhiyun 	u32 num_tx_not_acked;
4230*4882a593Smuzhiyun 	u32 tx_rate_history[MAX_TX_RATE_VALUES];
4231*4882a593Smuzhiyun 	u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4232*4882a593Smuzhiyun } __packed;
4233*4882a593Smuzhiyun 
4234*4882a593Smuzhiyun struct wmi_bcn_stats {
4235*4882a593Smuzhiyun 	u32 vdev_id;
4236*4882a593Smuzhiyun 	u32 tx_bcn_succ_cnt;
4237*4882a593Smuzhiyun 	u32 tx_bcn_outage_cnt;
4238*4882a593Smuzhiyun } __packed;
4239*4882a593Smuzhiyun 
4240*4882a593Smuzhiyun struct wmi_stats_event {
4241*4882a593Smuzhiyun 	u32 stats_id;
4242*4882a593Smuzhiyun 	u32 num_pdev_stats;
4243*4882a593Smuzhiyun 	u32 num_vdev_stats;
4244*4882a593Smuzhiyun 	u32 num_peer_stats;
4245*4882a593Smuzhiyun 	u32 num_bcnflt_stats;
4246*4882a593Smuzhiyun 	u32 num_chan_stats;
4247*4882a593Smuzhiyun 	u32 num_mib_stats;
4248*4882a593Smuzhiyun 	u32 pdev_id;
4249*4882a593Smuzhiyun 	u32 num_bcn_stats;
4250*4882a593Smuzhiyun 	u32 num_peer_extd_stats;
4251*4882a593Smuzhiyun 	u32 num_peer_extd2_stats;
4252*4882a593Smuzhiyun } __packed;
4253*4882a593Smuzhiyun 
4254*4882a593Smuzhiyun struct wmi_pdev_ctl_failsafe_chk_event {
4255*4882a593Smuzhiyun 	u32 pdev_id;
4256*4882a593Smuzhiyun 	u32 ctl_failsafe_status;
4257*4882a593Smuzhiyun } __packed;
4258*4882a593Smuzhiyun 
4259*4882a593Smuzhiyun struct wmi_pdev_csa_switch_ev {
4260*4882a593Smuzhiyun 	u32 pdev_id;
4261*4882a593Smuzhiyun 	u32 current_switch_count;
4262*4882a593Smuzhiyun 	u32 num_vdevs;
4263*4882a593Smuzhiyun } __packed;
4264*4882a593Smuzhiyun 
4265*4882a593Smuzhiyun struct wmi_pdev_radar_ev {
4266*4882a593Smuzhiyun 	u32 pdev_id;
4267*4882a593Smuzhiyun 	u32 detection_mode;
4268*4882a593Smuzhiyun 	u32 chan_freq;
4269*4882a593Smuzhiyun 	u32 chan_width;
4270*4882a593Smuzhiyun 	u32 detector_id;
4271*4882a593Smuzhiyun 	u32 segment_id;
4272*4882a593Smuzhiyun 	u32 timestamp;
4273*4882a593Smuzhiyun 	u32 is_chirp;
4274*4882a593Smuzhiyun 	s32 freq_offset;
4275*4882a593Smuzhiyun 	s32 sidx;
4276*4882a593Smuzhiyun } __packed;
4277*4882a593Smuzhiyun 
4278*4882a593Smuzhiyun struct wmi_pdev_temperature_event {
4279*4882a593Smuzhiyun 	/* temperature value in Celcius degree */
4280*4882a593Smuzhiyun 	s32 temp;
4281*4882a593Smuzhiyun 	u32 pdev_id;
4282*4882a593Smuzhiyun } __packed;
4283*4882a593Smuzhiyun 
4284*4882a593Smuzhiyun #define WMI_RX_STATUS_OK			0x00
4285*4882a593Smuzhiyun #define WMI_RX_STATUS_ERR_CRC			0x01
4286*4882a593Smuzhiyun #define WMI_RX_STATUS_ERR_DECRYPT		0x08
4287*4882a593Smuzhiyun #define WMI_RX_STATUS_ERR_MIC			0x10
4288*4882a593Smuzhiyun #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS	0x20
4289*4882a593Smuzhiyun 
4290*4882a593Smuzhiyun #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4
4291*4882a593Smuzhiyun 
4292*4882a593Smuzhiyun struct mgmt_rx_event_params {
4293*4882a593Smuzhiyun 	u32 chan_freq;
4294*4882a593Smuzhiyun 	u32 channel;
4295*4882a593Smuzhiyun 	u32 snr;
4296*4882a593Smuzhiyun 	u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA];
4297*4882a593Smuzhiyun 	u32 rate;
4298*4882a593Smuzhiyun 	enum wmi_phy_mode phy_mode;
4299*4882a593Smuzhiyun 	u32 buf_len;
4300*4882a593Smuzhiyun 	int status;
4301*4882a593Smuzhiyun 	u32 flags;
4302*4882a593Smuzhiyun 	int rssi;
4303*4882a593Smuzhiyun 	u32 tsf_delta;
4304*4882a593Smuzhiyun 	u8 pdev_id;
4305*4882a593Smuzhiyun };
4306*4882a593Smuzhiyun 
4307*4882a593Smuzhiyun #define ATH_MAX_ANTENNA 4
4308*4882a593Smuzhiyun 
4309*4882a593Smuzhiyun struct wmi_mgmt_rx_hdr {
4310*4882a593Smuzhiyun 	u32 channel;
4311*4882a593Smuzhiyun 	u32 snr;
4312*4882a593Smuzhiyun 	u32 rate;
4313*4882a593Smuzhiyun 	u32 phy_mode;
4314*4882a593Smuzhiyun 	u32 buf_len;
4315*4882a593Smuzhiyun 	u32 status;
4316*4882a593Smuzhiyun 	u32 rssi_ctl[ATH_MAX_ANTENNA];
4317*4882a593Smuzhiyun 	u32 flags;
4318*4882a593Smuzhiyun 	int rssi;
4319*4882a593Smuzhiyun 	u32 tsf_delta;
4320*4882a593Smuzhiyun 	u32 rx_tsf_l32;
4321*4882a593Smuzhiyun 	u32 rx_tsf_u32;
4322*4882a593Smuzhiyun 	u32 pdev_id;
4323*4882a593Smuzhiyun 	u32 chan_freq;
4324*4882a593Smuzhiyun } __packed;
4325*4882a593Smuzhiyun 
4326*4882a593Smuzhiyun #define MAX_ANTENNA_EIGHT 8
4327*4882a593Smuzhiyun 
4328*4882a593Smuzhiyun struct wmi_rssi_ctl_ext {
4329*4882a593Smuzhiyun 	u32 tlv_header;
4330*4882a593Smuzhiyun 	u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4331*4882a593Smuzhiyun };
4332*4882a593Smuzhiyun 
4333*4882a593Smuzhiyun struct wmi_mgmt_tx_compl_event {
4334*4882a593Smuzhiyun 	u32 desc_id;
4335*4882a593Smuzhiyun 	u32 status;
4336*4882a593Smuzhiyun 	u32 pdev_id;
4337*4882a593Smuzhiyun } __packed;
4338*4882a593Smuzhiyun 
4339*4882a593Smuzhiyun struct wmi_scan_event {
4340*4882a593Smuzhiyun 	u32 event_type; /* %WMI_SCAN_EVENT_ */
4341*4882a593Smuzhiyun 	u32 reason; /* %WMI_SCAN_REASON_ */
4342*4882a593Smuzhiyun 	u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4343*4882a593Smuzhiyun 	u32 scan_req_id;
4344*4882a593Smuzhiyun 	u32 scan_id;
4345*4882a593Smuzhiyun 	u32 vdev_id;
4346*4882a593Smuzhiyun 	/* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed
4347*4882a593Smuzhiyun 	 * In case of AP it is TSF of the AP vdev
4348*4882a593Smuzhiyun 	 * In case of STA connected state, this is the TSF of the AP
4349*4882a593Smuzhiyun 	 * In case of STA not connected, it will be the free running HW timer
4350*4882a593Smuzhiyun 	 */
4351*4882a593Smuzhiyun 	u32 tsf_timestamp;
4352*4882a593Smuzhiyun } __packed;
4353*4882a593Smuzhiyun 
4354*4882a593Smuzhiyun struct wmi_peer_sta_kickout_arg {
4355*4882a593Smuzhiyun 	const u8 *mac_addr;
4356*4882a593Smuzhiyun };
4357*4882a593Smuzhiyun 
4358*4882a593Smuzhiyun struct wmi_peer_sta_kickout_event {
4359*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
4360*4882a593Smuzhiyun } __packed;
4361*4882a593Smuzhiyun 
4362*4882a593Smuzhiyun enum wmi_roam_reason {
4363*4882a593Smuzhiyun 	WMI_ROAM_REASON_BETTER_AP = 1,
4364*4882a593Smuzhiyun 	WMI_ROAM_REASON_BEACON_MISS = 2,
4365*4882a593Smuzhiyun 	WMI_ROAM_REASON_LOW_RSSI = 3,
4366*4882a593Smuzhiyun 	WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4,
4367*4882a593Smuzhiyun 	WMI_ROAM_REASON_HO_FAILED = 5,
4368*4882a593Smuzhiyun 
4369*4882a593Smuzhiyun 	/* keep last */
4370*4882a593Smuzhiyun 	WMI_ROAM_REASON_MAX,
4371*4882a593Smuzhiyun };
4372*4882a593Smuzhiyun 
4373*4882a593Smuzhiyun struct wmi_roam_event {
4374*4882a593Smuzhiyun 	u32 vdev_id;
4375*4882a593Smuzhiyun 	u32 reason;
4376*4882a593Smuzhiyun 	u32 rssi;
4377*4882a593Smuzhiyun } __packed;
4378*4882a593Smuzhiyun 
4379*4882a593Smuzhiyun #define WMI_CHAN_INFO_START_RESP 0
4380*4882a593Smuzhiyun #define WMI_CHAN_INFO_END_RESP 1
4381*4882a593Smuzhiyun 
4382*4882a593Smuzhiyun struct wmi_chan_info_event {
4383*4882a593Smuzhiyun 	u32 err_code;
4384*4882a593Smuzhiyun 	u32 freq;
4385*4882a593Smuzhiyun 	u32 cmd_flags;
4386*4882a593Smuzhiyun 	u32 noise_floor;
4387*4882a593Smuzhiyun 	u32 rx_clear_count;
4388*4882a593Smuzhiyun 	u32 cycle_count;
4389*4882a593Smuzhiyun 	u32 chan_tx_pwr_range;
4390*4882a593Smuzhiyun 	u32 chan_tx_pwr_tp;
4391*4882a593Smuzhiyun 	u32 rx_frame_count;
4392*4882a593Smuzhiyun 	u32 my_bss_rx_cycle_count;
4393*4882a593Smuzhiyun 	u32 rx_11b_mode_data_duration;
4394*4882a593Smuzhiyun 	u32 tx_frame_cnt;
4395*4882a593Smuzhiyun 	u32 mac_clk_mhz;
4396*4882a593Smuzhiyun 	u32 vdev_id;
4397*4882a593Smuzhiyun } __packed;
4398*4882a593Smuzhiyun 
4399*4882a593Smuzhiyun struct ath11k_targ_cap {
4400*4882a593Smuzhiyun 	u32 phy_capability;
4401*4882a593Smuzhiyun 	u32 max_frag_entry;
4402*4882a593Smuzhiyun 	u32 num_rf_chains;
4403*4882a593Smuzhiyun 	u32 ht_cap_info;
4404*4882a593Smuzhiyun 	u32 vht_cap_info;
4405*4882a593Smuzhiyun 	u32 vht_supp_mcs;
4406*4882a593Smuzhiyun 	u32 hw_min_tx_power;
4407*4882a593Smuzhiyun 	u32 hw_max_tx_power;
4408*4882a593Smuzhiyun 	u32 sys_cap_info;
4409*4882a593Smuzhiyun 	u32 min_pkt_size_enable;
4410*4882a593Smuzhiyun 	u32 max_bcn_ie_size;
4411*4882a593Smuzhiyun 	u32 max_num_scan_channels;
4412*4882a593Smuzhiyun 	u32 max_supported_macs;
4413*4882a593Smuzhiyun 	u32 wmi_fw_sub_feat_caps;
4414*4882a593Smuzhiyun 	u32 txrx_chainmask;
4415*4882a593Smuzhiyun 	u32 default_dbs_hw_mode_index;
4416*4882a593Smuzhiyun 	u32 num_msdu_desc;
4417*4882a593Smuzhiyun };
4418*4882a593Smuzhiyun 
4419*4882a593Smuzhiyun enum wmi_vdev_type {
4420*4882a593Smuzhiyun 	WMI_VDEV_TYPE_AP      = 1,
4421*4882a593Smuzhiyun 	WMI_VDEV_TYPE_STA     = 2,
4422*4882a593Smuzhiyun 	WMI_VDEV_TYPE_IBSS    = 3,
4423*4882a593Smuzhiyun 	WMI_VDEV_TYPE_MONITOR = 4,
4424*4882a593Smuzhiyun };
4425*4882a593Smuzhiyun 
4426*4882a593Smuzhiyun enum wmi_vdev_subtype {
4427*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_NONE,
4428*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_P2P_DEVICE,
4429*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_P2P_CLIENT,
4430*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_P2P_GO,
4431*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_PROXY_STA,
4432*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_MESH_NON_11S,
4433*4882a593Smuzhiyun 	WMI_VDEV_SUBTYPE_MESH_11S,
4434*4882a593Smuzhiyun };
4435*4882a593Smuzhiyun 
4436*4882a593Smuzhiyun enum wmi_sta_powersave_param {
4437*4882a593Smuzhiyun 	WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
4438*4882a593Smuzhiyun 	WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
4439*4882a593Smuzhiyun 	WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
4440*4882a593Smuzhiyun 	WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
4441*4882a593Smuzhiyun 	WMI_STA_PS_PARAM_UAPSD = 4,
4442*4882a593Smuzhiyun };
4443*4882a593Smuzhiyun 
4444*4882a593Smuzhiyun #define WMI_UAPSD_AC_TYPE_DELI 0
4445*4882a593Smuzhiyun #define WMI_UAPSD_AC_TYPE_TRIG 1
4446*4882a593Smuzhiyun 
4447*4882a593Smuzhiyun #define WMI_UAPSD_AC_BIT_MASK(ac, type) \
4448*4882a593Smuzhiyun 	((type ==  WMI_UAPSD_AC_TYPE_DELI) ? \
4449*4882a593Smuzhiyun 	 (1 << (ac << 1)) : (1 << ((ac << 1) + 1)))
4450*4882a593Smuzhiyun 
4451*4882a593Smuzhiyun enum wmi_sta_ps_param_uapsd {
4452*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
4453*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC0_TRIGGER_EN  = (1 << 1),
4454*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
4455*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC1_TRIGGER_EN  = (1 << 3),
4456*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
4457*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC2_TRIGGER_EN  = (1 << 5),
4458*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
4459*4882a593Smuzhiyun 	WMI_STA_PS_UAPSD_AC3_TRIGGER_EN  = (1 << 7),
4460*4882a593Smuzhiyun };
4461*4882a593Smuzhiyun 
4462*4882a593Smuzhiyun #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX
4463*4882a593Smuzhiyun 
4464*4882a593Smuzhiyun struct wmi_sta_uapsd_auto_trig_param {
4465*4882a593Smuzhiyun 	u32 wmm_ac;
4466*4882a593Smuzhiyun 	u32 user_priority;
4467*4882a593Smuzhiyun 	u32 service_interval;
4468*4882a593Smuzhiyun 	u32 suspend_interval;
4469*4882a593Smuzhiyun 	u32 delay_interval;
4470*4882a593Smuzhiyun };
4471*4882a593Smuzhiyun 
4472*4882a593Smuzhiyun struct wmi_sta_uapsd_auto_trig_cmd_fixed_param {
4473*4882a593Smuzhiyun 	u32 vdev_id;
4474*4882a593Smuzhiyun 	struct wmi_mac_addr peer_macaddr;
4475*4882a593Smuzhiyun 	u32 num_ac;
4476*4882a593Smuzhiyun };
4477*4882a593Smuzhiyun 
4478*4882a593Smuzhiyun struct wmi_sta_uapsd_auto_trig_arg {
4479*4882a593Smuzhiyun 	u32 wmm_ac;
4480*4882a593Smuzhiyun 	u32 user_priority;
4481*4882a593Smuzhiyun 	u32 service_interval;
4482*4882a593Smuzhiyun 	u32 suspend_interval;
4483*4882a593Smuzhiyun 	u32 delay_interval;
4484*4882a593Smuzhiyun };
4485*4882a593Smuzhiyun 
4486*4882a593Smuzhiyun enum wmi_sta_ps_param_tx_wake_threshold {
4487*4882a593Smuzhiyun 	WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
4488*4882a593Smuzhiyun 	WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
4489*4882a593Smuzhiyun 
4490*4882a593Smuzhiyun 	/* Values greater than one indicate that many TX attempts per beacon
4491*4882a593Smuzhiyun 	 * interval before the STA will wake up
4492*4882a593Smuzhiyun 	 */
4493*4882a593Smuzhiyun };
4494*4882a593Smuzhiyun 
4495*4882a593Smuzhiyun /* The maximum number of PS-Poll frames the FW will send in response to
4496*4882a593Smuzhiyun  * traffic advertised in TIM before waking up (by sending a null frame with PS
4497*4882a593Smuzhiyun  * = 0). Value 0 has a special meaning: there is no maximum count and the FW
4498*4882a593Smuzhiyun  * will send as many PS-Poll as are necessary to retrieve buffered BU. This
4499*4882a593Smuzhiyun  * parameter is used when the RX wake policy is
4500*4882a593Smuzhiyun  * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake
4501*4882a593Smuzhiyun  * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE.
4502*4882a593Smuzhiyun  */
4503*4882a593Smuzhiyun enum wmi_sta_ps_param_pspoll_count {
4504*4882a593Smuzhiyun 	WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
4505*4882a593Smuzhiyun 	/* Values greater than 0 indicate the maximum numer of PS-Poll frames
4506*4882a593Smuzhiyun 	 * FW will send before waking up.
4507*4882a593Smuzhiyun 	 */
4508*4882a593Smuzhiyun };
4509*4882a593Smuzhiyun 
4510*4882a593Smuzhiyun /* U-APSD configuration of peer station from (re)assoc request and TSPECs */
4511*4882a593Smuzhiyun enum wmi_ap_ps_param_uapsd {
4512*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
4513*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC0_TRIGGER_EN  = (1 << 1),
4514*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
4515*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC1_TRIGGER_EN  = (1 << 3),
4516*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
4517*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC2_TRIGGER_EN  = (1 << 5),
4518*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
4519*4882a593Smuzhiyun 	WMI_AP_PS_UAPSD_AC3_TRIGGER_EN  = (1 << 7),
4520*4882a593Smuzhiyun };
4521*4882a593Smuzhiyun 
4522*4882a593Smuzhiyun /* U-APSD maximum service period of peer station */
4523*4882a593Smuzhiyun enum wmi_ap_ps_peer_param_max_sp {
4524*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
4525*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
4526*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
4527*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
4528*4882a593Smuzhiyun 	MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
4529*4882a593Smuzhiyun };
4530*4882a593Smuzhiyun 
4531*4882a593Smuzhiyun enum wmi_ap_ps_peer_param {
4532*4882a593Smuzhiyun 	/** Set uapsd configuration for a given peer.
4533*4882a593Smuzhiyun 	 *
4534*4882a593Smuzhiyun 	 * This include the delivery and trigger enabled state for each AC.
4535*4882a593Smuzhiyun 	 * The host MLME needs to set this based on AP capability and stations
4536*4882a593Smuzhiyun 	 * request Set in the association request  received from the station.
4537*4882a593Smuzhiyun 	 *
4538*4882a593Smuzhiyun 	 * Lower 8 bits of the value specify the UAPSD configuration.
4539*4882a593Smuzhiyun 	 *
4540*4882a593Smuzhiyun 	 * (see enum wmi_ap_ps_param_uapsd)
4541*4882a593Smuzhiyun 	 * The default value is 0.
4542*4882a593Smuzhiyun 	 */
4543*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_UAPSD = 0,
4544*4882a593Smuzhiyun 
4545*4882a593Smuzhiyun 	/**
4546*4882a593Smuzhiyun 	 * Set the service period for a UAPSD capable station
4547*4882a593Smuzhiyun 	 *
4548*4882a593Smuzhiyun 	 * The service period from wme ie in the (re)assoc request frame.
4549*4882a593Smuzhiyun 	 *
4550*4882a593Smuzhiyun 	 * (see enum wmi_ap_ps_peer_param_max_sp)
4551*4882a593Smuzhiyun 	 */
4552*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
4553*4882a593Smuzhiyun 
4554*4882a593Smuzhiyun 	/** Time in seconds for aging out buffered frames
4555*4882a593Smuzhiyun 	 * for STA in power save
4556*4882a593Smuzhiyun 	 */
4557*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
4558*4882a593Smuzhiyun 
4559*4882a593Smuzhiyun 	/** Specify frame types that are considered SIFS
4560*4882a593Smuzhiyun 	 * RESP trigger frame
4561*4882a593Smuzhiyun 	 */
4562*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3,
4563*4882a593Smuzhiyun 
4564*4882a593Smuzhiyun 	/** Specifies the trigger state of TID.
4565*4882a593Smuzhiyun 	 * Valid only for UAPSD frame type
4566*4882a593Smuzhiyun 	 */
4567*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4,
4568*4882a593Smuzhiyun 
4569*4882a593Smuzhiyun 	/* Specifies the WNM sleep state of a STA */
4570*4882a593Smuzhiyun 	WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5,
4571*4882a593Smuzhiyun };
4572*4882a593Smuzhiyun 
4573*4882a593Smuzhiyun #define DISABLE_SIFS_RESPONSE_TRIGGER 0
4574*4882a593Smuzhiyun 
4575*4882a593Smuzhiyun #define WMI_MAX_KEY_INDEX   3
4576*4882a593Smuzhiyun #define WMI_MAX_KEY_LEN     32
4577*4882a593Smuzhiyun 
4578*4882a593Smuzhiyun #define WMI_KEY_PAIRWISE 0x00
4579*4882a593Smuzhiyun #define WMI_KEY_GROUP    0x01
4580*4882a593Smuzhiyun 
4581*4882a593Smuzhiyun #define WMI_CIPHER_NONE     0x0 /* clear key */
4582*4882a593Smuzhiyun #define WMI_CIPHER_WEP      0x1
4583*4882a593Smuzhiyun #define WMI_CIPHER_TKIP     0x2
4584*4882a593Smuzhiyun #define WMI_CIPHER_AES_OCB  0x3
4585*4882a593Smuzhiyun #define WMI_CIPHER_AES_CCM  0x4
4586*4882a593Smuzhiyun #define WMI_CIPHER_WAPI     0x5
4587*4882a593Smuzhiyun #define WMI_CIPHER_CKIP     0x6
4588*4882a593Smuzhiyun #define WMI_CIPHER_AES_CMAC 0x7
4589*4882a593Smuzhiyun #define WMI_CIPHER_ANY      0x8
4590*4882a593Smuzhiyun #define WMI_CIPHER_AES_GCM  0x9
4591*4882a593Smuzhiyun #define WMI_CIPHER_AES_GMAC 0xa
4592*4882a593Smuzhiyun 
4593*4882a593Smuzhiyun /* Value to disable fixed rate setting */
4594*4882a593Smuzhiyun #define WMI_FIXED_RATE_NONE	(0xffff)
4595*4882a593Smuzhiyun 
4596*4882a593Smuzhiyun #define ATH11K_RC_VERSION_OFFSET	28
4597*4882a593Smuzhiyun #define ATH11K_RC_PREAMBLE_OFFSET	8
4598*4882a593Smuzhiyun #define ATH11K_RC_NSS_OFFSET		5
4599*4882a593Smuzhiyun 
4600*4882a593Smuzhiyun #define ATH11K_HW_RATE_CODE(rate, nss, preamble)	\
4601*4882a593Smuzhiyun 	((1 << ATH11K_RC_VERSION_OFFSET) |		\
4602*4882a593Smuzhiyun 	 ((nss) << ATH11K_RC_NSS_OFFSET) |		\
4603*4882a593Smuzhiyun 	 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) |	\
4604*4882a593Smuzhiyun 	 (rate))
4605*4882a593Smuzhiyun 
4606*4882a593Smuzhiyun /* Preamble types to be used with VDEV fixed rate configuration */
4607*4882a593Smuzhiyun enum wmi_rate_preamble {
4608*4882a593Smuzhiyun 	WMI_RATE_PREAMBLE_OFDM,
4609*4882a593Smuzhiyun 	WMI_RATE_PREAMBLE_CCK,
4610*4882a593Smuzhiyun 	WMI_RATE_PREAMBLE_HT,
4611*4882a593Smuzhiyun 	WMI_RATE_PREAMBLE_VHT,
4612*4882a593Smuzhiyun 	WMI_RATE_PREAMBLE_HE,
4613*4882a593Smuzhiyun };
4614*4882a593Smuzhiyun 
4615*4882a593Smuzhiyun /**
4616*4882a593Smuzhiyun  * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection.
4617*4882a593Smuzhiyun  * @WMI_RTS_CTS_DISABLED : RTS/CTS protection is disabled.
4618*4882a593Smuzhiyun  * @WMI_USE_RTS_CTS : RTS/CTS Enabled.
4619*4882a593Smuzhiyun  * @WMI_USE_CTS2SELF : CTS to self protection Enabled.
4620*4882a593Smuzhiyun  */
4621*4882a593Smuzhiyun enum wmi_rtscts_prot_mode {
4622*4882a593Smuzhiyun 	WMI_RTS_CTS_DISABLED = 0,
4623*4882a593Smuzhiyun 	WMI_USE_RTS_CTS = 1,
4624*4882a593Smuzhiyun 	WMI_USE_CTS2SELF = 2,
4625*4882a593Smuzhiyun };
4626*4882a593Smuzhiyun 
4627*4882a593Smuzhiyun /**
4628*4882a593Smuzhiyun  * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling
4629*4882a593Smuzhiyun  *                           protection mode.
4630*4882a593Smuzhiyun  * @WMI_RTSCTS_FOR_NO_RATESERIES - Neither of rate-series should use RTS-CTS
4631*4882a593Smuzhiyun  * @WMI_RTSCTS_FOR_SECOND_RATESERIES - Only second rate-series will use RTS-CTS
4632*4882a593Smuzhiyun  * @WMI_RTSCTS_ACROSS_SW_RETRIES - Only the second rate-series will use RTS-CTS,
4633*4882a593Smuzhiyun  *                                 but if there's a sw retry, both the rate
4634*4882a593Smuzhiyun  *                                 series will use RTS-CTS.
4635*4882a593Smuzhiyun  * @WMI_RTSCTS_ERP - RTS/CTS used for ERP protection for every PPDU.
4636*4882a593Smuzhiyun  * @WMI_RTSCTS_FOR_ALL_RATESERIES - Enable RTS-CTS for all rate series.
4637*4882a593Smuzhiyun  */
4638*4882a593Smuzhiyun enum wmi_rtscts_profile {
4639*4882a593Smuzhiyun 	WMI_RTSCTS_FOR_NO_RATESERIES = 0,
4640*4882a593Smuzhiyun 	WMI_RTSCTS_FOR_SECOND_RATESERIES = 1,
4641*4882a593Smuzhiyun 	WMI_RTSCTS_ACROSS_SW_RETRIES = 2,
4642*4882a593Smuzhiyun 	WMI_RTSCTS_ERP = 3,
4643*4882a593Smuzhiyun 	WMI_RTSCTS_FOR_ALL_RATESERIES = 4,
4644*4882a593Smuzhiyun };
4645*4882a593Smuzhiyun 
4646*4882a593Smuzhiyun struct ath11k_hal_reg_cap {
4647*4882a593Smuzhiyun 	u32 eeprom_rd;
4648*4882a593Smuzhiyun 	u32 eeprom_rd_ext;
4649*4882a593Smuzhiyun 	u32 regcap1;
4650*4882a593Smuzhiyun 	u32 regcap2;
4651*4882a593Smuzhiyun 	u32 wireless_modes;
4652*4882a593Smuzhiyun 	u32 low_2ghz_chan;
4653*4882a593Smuzhiyun 	u32 high_2ghz_chan;
4654*4882a593Smuzhiyun 	u32 low_5ghz_chan;
4655*4882a593Smuzhiyun 	u32 high_5ghz_chan;
4656*4882a593Smuzhiyun };
4657*4882a593Smuzhiyun 
4658*4882a593Smuzhiyun struct ath11k_mem_chunk {
4659*4882a593Smuzhiyun 	void *vaddr;
4660*4882a593Smuzhiyun 	dma_addr_t paddr;
4661*4882a593Smuzhiyun 	u32 len;
4662*4882a593Smuzhiyun 	u32 req_id;
4663*4882a593Smuzhiyun };
4664*4882a593Smuzhiyun 
4665*4882a593Smuzhiyun #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr)
4666*4882a593Smuzhiyun 
4667*4882a593Smuzhiyun enum wmi_sta_ps_param_rx_wake_policy {
4668*4882a593Smuzhiyun 	WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
4669*4882a593Smuzhiyun 	WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
4670*4882a593Smuzhiyun };
4671*4882a593Smuzhiyun 
4672*4882a593Smuzhiyun /* Do not change existing values! Used by ath11k_frame_mode parameter
4673*4882a593Smuzhiyun  * module parameter.
4674*4882a593Smuzhiyun  */
4675*4882a593Smuzhiyun enum ath11k_hw_txrx_mode {
4676*4882a593Smuzhiyun 	ATH11K_HW_TXRX_RAW = 0,
4677*4882a593Smuzhiyun 	ATH11K_HW_TXRX_NATIVE_WIFI = 1,
4678*4882a593Smuzhiyun 	ATH11K_HW_TXRX_ETHERNET = 2,
4679*4882a593Smuzhiyun };
4680*4882a593Smuzhiyun 
4681*4882a593Smuzhiyun struct wmi_wmm_params {
4682*4882a593Smuzhiyun 	u32 tlv_header;
4683*4882a593Smuzhiyun 	u32 cwmin;
4684*4882a593Smuzhiyun 	u32 cwmax;
4685*4882a593Smuzhiyun 	u32 aifs;
4686*4882a593Smuzhiyun 	u32 txoplimit;
4687*4882a593Smuzhiyun 	u32 acm;
4688*4882a593Smuzhiyun 	u32 no_ack;
4689*4882a593Smuzhiyun } __packed;
4690*4882a593Smuzhiyun 
4691*4882a593Smuzhiyun struct wmi_wmm_params_arg {
4692*4882a593Smuzhiyun 	u8 acm;
4693*4882a593Smuzhiyun 	u8 aifs;
4694*4882a593Smuzhiyun 	u16 cwmin;
4695*4882a593Smuzhiyun 	u16 cwmax;
4696*4882a593Smuzhiyun 	u16 txop;
4697*4882a593Smuzhiyun 	u8 no_ack;
4698*4882a593Smuzhiyun };
4699*4882a593Smuzhiyun 
4700*4882a593Smuzhiyun struct wmi_vdev_set_wmm_params_cmd {
4701*4882a593Smuzhiyun 	u32 tlv_header;
4702*4882a593Smuzhiyun 	u32 vdev_id;
4703*4882a593Smuzhiyun 	struct wmi_wmm_params wmm_params[4];
4704*4882a593Smuzhiyun 	u32 wmm_param_type;
4705*4882a593Smuzhiyun } __packed;
4706*4882a593Smuzhiyun 
4707*4882a593Smuzhiyun struct wmi_wmm_params_all_arg {
4708*4882a593Smuzhiyun 	struct wmi_wmm_params_arg ac_be;
4709*4882a593Smuzhiyun 	struct wmi_wmm_params_arg ac_bk;
4710*4882a593Smuzhiyun 	struct wmi_wmm_params_arg ac_vi;
4711*4882a593Smuzhiyun 	struct wmi_wmm_params_arg ac_vo;
4712*4882a593Smuzhiyun };
4713*4882a593Smuzhiyun 
4714*4882a593Smuzhiyun #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS		5000
4715*4882a593Smuzhiyun #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE		10
4716*4882a593Smuzhiyun #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP		50
4717*4882a593Smuzhiyun #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN	20
4718*4882a593Smuzhiyun #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL	100
4719*4882a593Smuzhiyun #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN	80
4720*4882a593Smuzhiyun #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP	50
4721*4882a593Smuzhiyun #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP			10
4722*4882a593Smuzhiyun #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN		2
4723*4882a593Smuzhiyun #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS		2
4724*4882a593Smuzhiyun #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS			2
4725*4882a593Smuzhiyun #define ATH11K_TWT_DEF_MAX_NO_STA_TWT			500
4726*4882a593Smuzhiyun #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL		10000
4727*4882a593Smuzhiyun #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL		1000
4728*4882a593Smuzhiyun #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL		5000
4729*4882a593Smuzhiyun 
4730*4882a593Smuzhiyun struct wmi_twt_enable_params_cmd {
4731*4882a593Smuzhiyun 	u32 tlv_header;
4732*4882a593Smuzhiyun 	u32 pdev_id;
4733*4882a593Smuzhiyun 	u32 sta_cong_timer_ms;
4734*4882a593Smuzhiyun 	u32 mbss_support;
4735*4882a593Smuzhiyun 	u32 default_slot_size;
4736*4882a593Smuzhiyun 	u32 congestion_thresh_setup;
4737*4882a593Smuzhiyun 	u32 congestion_thresh_teardown;
4738*4882a593Smuzhiyun 	u32 congestion_thresh_critical;
4739*4882a593Smuzhiyun 	u32 interference_thresh_teardown;
4740*4882a593Smuzhiyun 	u32 interference_thresh_setup;
4741*4882a593Smuzhiyun 	u32 min_no_sta_setup;
4742*4882a593Smuzhiyun 	u32 min_no_sta_teardown;
4743*4882a593Smuzhiyun 	u32 no_of_bcast_mcast_slots;
4744*4882a593Smuzhiyun 	u32 min_no_twt_slots;
4745*4882a593Smuzhiyun 	u32 max_no_sta_twt;
4746*4882a593Smuzhiyun 	u32 mode_check_interval;
4747*4882a593Smuzhiyun 	u32 add_sta_slot_interval;
4748*4882a593Smuzhiyun 	u32 remove_sta_slot_interval;
4749*4882a593Smuzhiyun } __packed;
4750*4882a593Smuzhiyun 
4751*4882a593Smuzhiyun struct wmi_twt_disable_params_cmd {
4752*4882a593Smuzhiyun 	u32 tlv_header;
4753*4882a593Smuzhiyun 	u32 pdev_id;
4754*4882a593Smuzhiyun } __packed;
4755*4882a593Smuzhiyun 
4756*4882a593Smuzhiyun struct wmi_obss_spatial_reuse_params_cmd {
4757*4882a593Smuzhiyun 	u32 tlv_header;
4758*4882a593Smuzhiyun 	u32 pdev_id;
4759*4882a593Smuzhiyun 	u32 enable;
4760*4882a593Smuzhiyun 	s32 obss_min;
4761*4882a593Smuzhiyun 	s32 obss_max;
4762*4882a593Smuzhiyun 	u32 vdev_id;
4763*4882a593Smuzhiyun } __packed;
4764*4882a593Smuzhiyun 
4765*4882a593Smuzhiyun #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS		200
4766*4882a593Smuzhiyun #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE		0
4767*4882a593Smuzhiyun #define ATH11K_OBSS_COLOR_COLLISION_DETECTION			1
4768*4882a593Smuzhiyun 
4769*4882a593Smuzhiyun #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS	10000
4770*4882a593Smuzhiyun #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS	5000
4771*4882a593Smuzhiyun 
4772*4882a593Smuzhiyun struct wmi_obss_color_collision_cfg_params_cmd {
4773*4882a593Smuzhiyun 	u32 tlv_header;
4774*4882a593Smuzhiyun 	u32 vdev_id;
4775*4882a593Smuzhiyun 	u32 flags;
4776*4882a593Smuzhiyun 	u32 evt_type;
4777*4882a593Smuzhiyun 	u32 current_bss_color;
4778*4882a593Smuzhiyun 	u32 detection_period_ms;
4779*4882a593Smuzhiyun 	u32 scan_period_ms;
4780*4882a593Smuzhiyun 	u32 free_slot_expiry_time_ms;
4781*4882a593Smuzhiyun } __packed;
4782*4882a593Smuzhiyun 
4783*4882a593Smuzhiyun struct wmi_bss_color_change_enable_params_cmd {
4784*4882a593Smuzhiyun 	u32 tlv_header;
4785*4882a593Smuzhiyun 	u32 vdev_id;
4786*4882a593Smuzhiyun 	u32 enable;
4787*4882a593Smuzhiyun } __packed;
4788*4882a593Smuzhiyun 
4789*4882a593Smuzhiyun #define ATH11K_IPV4_TH_SEED_SIZE 5
4790*4882a593Smuzhiyun #define ATH11K_IPV6_TH_SEED_SIZE 11
4791*4882a593Smuzhiyun 
4792*4882a593Smuzhiyun struct ath11k_wmi_pdev_lro_config_cmd {
4793*4882a593Smuzhiyun 	u32 tlv_header;
4794*4882a593Smuzhiyun 	u32 lro_enable;
4795*4882a593Smuzhiyun 	u32 res;
4796*4882a593Smuzhiyun 	u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
4797*4882a593Smuzhiyun 	u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
4798*4882a593Smuzhiyun 	u32 pdev_id;
4799*4882a593Smuzhiyun } __packed;
4800*4882a593Smuzhiyun 
4801*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT                 0
4802*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT              224
4803*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT              1
4804*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT              7
4805*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT                1
4806*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT           0
4807*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT     -96
4808*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT           80
4809*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT          12
4810*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT           8
4811*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT           0
4812*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT         0
4813*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT           0xf0
4814*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT            0
4815*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT              2
4816*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT             1
4817*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT               1
4818*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT              1
4819*4882a593Smuzhiyun 
4820*4882a593Smuzhiyun struct ath11k_wmi_vdev_spectral_conf_param {
4821*4882a593Smuzhiyun 	u32 vdev_id;
4822*4882a593Smuzhiyun 	u32 scan_count;
4823*4882a593Smuzhiyun 	u32 scan_period;
4824*4882a593Smuzhiyun 	u32 scan_priority;
4825*4882a593Smuzhiyun 	u32 scan_fft_size;
4826*4882a593Smuzhiyun 	u32 scan_gc_ena;
4827*4882a593Smuzhiyun 	u32 scan_restart_ena;
4828*4882a593Smuzhiyun 	u32 scan_noise_floor_ref;
4829*4882a593Smuzhiyun 	u32 scan_init_delay;
4830*4882a593Smuzhiyun 	u32 scan_nb_tone_thr;
4831*4882a593Smuzhiyun 	u32 scan_str_bin_thr;
4832*4882a593Smuzhiyun 	u32 scan_wb_rpt_mode;
4833*4882a593Smuzhiyun 	u32 scan_rssi_rpt_mode;
4834*4882a593Smuzhiyun 	u32 scan_rssi_thr;
4835*4882a593Smuzhiyun 	u32 scan_pwr_format;
4836*4882a593Smuzhiyun 	u32 scan_rpt_mode;
4837*4882a593Smuzhiyun 	u32 scan_bin_scale;
4838*4882a593Smuzhiyun 	u32 scan_dbm_adj;
4839*4882a593Smuzhiyun 	u32 scan_chn_mask;
4840*4882a593Smuzhiyun } __packed;
4841*4882a593Smuzhiyun 
4842*4882a593Smuzhiyun struct ath11k_wmi_vdev_spectral_conf_cmd {
4843*4882a593Smuzhiyun 	u32 tlv_header;
4844*4882a593Smuzhiyun 	struct ath11k_wmi_vdev_spectral_conf_param param;
4845*4882a593Smuzhiyun } __packed;
4846*4882a593Smuzhiyun 
4847*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER  1
4848*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR    2
4849*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE    1
4850*4882a593Smuzhiyun #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE   2
4851*4882a593Smuzhiyun 
4852*4882a593Smuzhiyun struct ath11k_wmi_vdev_spectral_enable_cmd {
4853*4882a593Smuzhiyun 	u32 tlv_header;
4854*4882a593Smuzhiyun 	u32 vdev_id;
4855*4882a593Smuzhiyun 	u32 trigger_cmd;
4856*4882a593Smuzhiyun 	u32 enable_cmd;
4857*4882a593Smuzhiyun } __packed;
4858*4882a593Smuzhiyun 
4859*4882a593Smuzhiyun struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd {
4860*4882a593Smuzhiyun 	u32 tlv_header;
4861*4882a593Smuzhiyun 	u32 pdev_id;
4862*4882a593Smuzhiyun 	u32 module_id;		/* see enum wmi_direct_buffer_module */
4863*4882a593Smuzhiyun 	u32 base_paddr_lo;
4864*4882a593Smuzhiyun 	u32 base_paddr_hi;
4865*4882a593Smuzhiyun 	u32 head_idx_paddr_lo;
4866*4882a593Smuzhiyun 	u32 head_idx_paddr_hi;
4867*4882a593Smuzhiyun 	u32 tail_idx_paddr_lo;
4868*4882a593Smuzhiyun 	u32 tail_idx_paddr_hi;
4869*4882a593Smuzhiyun 	u32 num_elems;		/* Number of elems in the ring */
4870*4882a593Smuzhiyun 	u32 buf_size;		/* size of allocated buffer in bytes */
4871*4882a593Smuzhiyun 
4872*4882a593Smuzhiyun 	/* Number of wmi_dma_buf_release_entry packed together */
4873*4882a593Smuzhiyun 	u32 num_resp_per_event;
4874*4882a593Smuzhiyun 
4875*4882a593Smuzhiyun 	/* Target should timeout and send whatever resp
4876*4882a593Smuzhiyun 	 * it has if this time expires, units in milliseconds
4877*4882a593Smuzhiyun 	 */
4878*4882a593Smuzhiyun 	u32 event_timeout_ms;
4879*4882a593Smuzhiyun } __packed;
4880*4882a593Smuzhiyun 
4881*4882a593Smuzhiyun struct ath11k_wmi_dma_buf_release_fixed_param {
4882*4882a593Smuzhiyun 	u32 pdev_id;
4883*4882a593Smuzhiyun 	u32 module_id;
4884*4882a593Smuzhiyun 	u32 num_buf_release_entry;
4885*4882a593Smuzhiyun 	u32 num_meta_data_entry;
4886*4882a593Smuzhiyun } __packed;
4887*4882a593Smuzhiyun 
4888*4882a593Smuzhiyun struct wmi_dma_buf_release_entry {
4889*4882a593Smuzhiyun 	u32 tlv_header;
4890*4882a593Smuzhiyun 	u32 paddr_lo;
4891*4882a593Smuzhiyun 
4892*4882a593Smuzhiyun 	/* Bits 11:0:   address of data
4893*4882a593Smuzhiyun 	 * Bits 31:12:  host context data
4894*4882a593Smuzhiyun 	 */
4895*4882a593Smuzhiyun 	u32 paddr_hi;
4896*4882a593Smuzhiyun } __packed;
4897*4882a593Smuzhiyun 
4898*4882a593Smuzhiyun #define WMI_SPECTRAL_META_INFO1_FREQ1		GENMASK(15, 0)
4899*4882a593Smuzhiyun #define WMI_SPECTRAL_META_INFO1_FREQ2		GENMASK(31, 16)
4900*4882a593Smuzhiyun 
4901*4882a593Smuzhiyun #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH	GENMASK(7, 0)
4902*4882a593Smuzhiyun 
4903*4882a593Smuzhiyun struct wmi_dma_buf_release_meta_data {
4904*4882a593Smuzhiyun 	u32 tlv_header;
4905*4882a593Smuzhiyun 	s32 noise_floor[WMI_MAX_CHAINS];
4906*4882a593Smuzhiyun 	u32 reset_delay;
4907*4882a593Smuzhiyun 	u32 freq1;
4908*4882a593Smuzhiyun 	u32 freq2;
4909*4882a593Smuzhiyun 	u32 ch_width;
4910*4882a593Smuzhiyun } __packed;
4911*4882a593Smuzhiyun 
4912*4882a593Smuzhiyun struct target_resource_config {
4913*4882a593Smuzhiyun 	u32 num_vdevs;
4914*4882a593Smuzhiyun 	u32 num_peers;
4915*4882a593Smuzhiyun 	u32 num_active_peers;
4916*4882a593Smuzhiyun 	u32 num_offload_peers;
4917*4882a593Smuzhiyun 	u32 num_offload_reorder_buffs;
4918*4882a593Smuzhiyun 	u32 num_peer_keys;
4919*4882a593Smuzhiyun 	u32 num_tids;
4920*4882a593Smuzhiyun 	u32 ast_skid_limit;
4921*4882a593Smuzhiyun 	u32 tx_chain_mask;
4922*4882a593Smuzhiyun 	u32 rx_chain_mask;
4923*4882a593Smuzhiyun 	u32 rx_timeout_pri[4];
4924*4882a593Smuzhiyun 	u32 rx_decap_mode;
4925*4882a593Smuzhiyun 	u32 scan_max_pending_req;
4926*4882a593Smuzhiyun 	u32 bmiss_offload_max_vdev;
4927*4882a593Smuzhiyun 	u32 roam_offload_max_vdev;
4928*4882a593Smuzhiyun 	u32 roam_offload_max_ap_profiles;
4929*4882a593Smuzhiyun 	u32 num_mcast_groups;
4930*4882a593Smuzhiyun 	u32 num_mcast_table_elems;
4931*4882a593Smuzhiyun 	u32 mcast2ucast_mode;
4932*4882a593Smuzhiyun 	u32 tx_dbg_log_size;
4933*4882a593Smuzhiyun 	u32 num_wds_entries;
4934*4882a593Smuzhiyun 	u32 dma_burst_size;
4935*4882a593Smuzhiyun 	u32 mac_aggr_delim;
4936*4882a593Smuzhiyun 	u32 rx_skip_defrag_timeout_dup_detection_check;
4937*4882a593Smuzhiyun 	u32 vow_config;
4938*4882a593Smuzhiyun 	u32 gtk_offload_max_vdev;
4939*4882a593Smuzhiyun 	u32 num_msdu_desc;
4940*4882a593Smuzhiyun 	u32 max_frag_entries;
4941*4882a593Smuzhiyun 	u32 max_peer_ext_stats;
4942*4882a593Smuzhiyun 	u32 smart_ant_cap;
4943*4882a593Smuzhiyun 	u32 bk_minfree;
4944*4882a593Smuzhiyun 	u32 be_minfree;
4945*4882a593Smuzhiyun 	u32 vi_minfree;
4946*4882a593Smuzhiyun 	u32 vo_minfree;
4947*4882a593Smuzhiyun 	u32 rx_batchmode;
4948*4882a593Smuzhiyun 	u32 tt_support;
4949*4882a593Smuzhiyun 	u32 atf_config;
4950*4882a593Smuzhiyun 	u32 iphdr_pad_config;
4951*4882a593Smuzhiyun 	u32 qwrap_config:16,
4952*4882a593Smuzhiyun 	    alloc_frag_desc_for_data_pkt:16;
4953*4882a593Smuzhiyun 	u32 num_tdls_vdevs;
4954*4882a593Smuzhiyun 	u32 num_tdls_conn_table_entries;
4955*4882a593Smuzhiyun 	u32 beacon_tx_offload_max_vdev;
4956*4882a593Smuzhiyun 	u32 num_multicast_filter_entries;
4957*4882a593Smuzhiyun 	u32 num_wow_filters;
4958*4882a593Smuzhiyun 	u32 num_keep_alive_pattern;
4959*4882a593Smuzhiyun 	u32 keep_alive_pattern_size;
4960*4882a593Smuzhiyun 	u32 max_tdls_concurrent_sleep_sta;
4961*4882a593Smuzhiyun 	u32 max_tdls_concurrent_buffer_sta;
4962*4882a593Smuzhiyun 	u32 wmi_send_separate;
4963*4882a593Smuzhiyun 	u32 num_ocb_vdevs;
4964*4882a593Smuzhiyun 	u32 num_ocb_channels;
4965*4882a593Smuzhiyun 	u32 num_ocb_schedules;
4966*4882a593Smuzhiyun 	u32 num_ns_ext_tuples_cfg;
4967*4882a593Smuzhiyun 	u32 bpf_instruction_size;
4968*4882a593Smuzhiyun 	u32 max_bssid_rx_filters;
4969*4882a593Smuzhiyun 	u32 use_pdev_id;
4970*4882a593Smuzhiyun 	u32 peer_map_unmap_v2_support;
4971*4882a593Smuzhiyun 	u32 sched_params;
4972*4882a593Smuzhiyun 	u32 twt_ap_pdev_count;
4973*4882a593Smuzhiyun 	u32 twt_ap_sta_count;
4974*4882a593Smuzhiyun };
4975*4882a593Smuzhiyun 
4976*4882a593Smuzhiyun #define WMI_MAX_MEM_REQS 32
4977*4882a593Smuzhiyun 
4978*4882a593Smuzhiyun #define MAX_RADIOS 3
4979*4882a593Smuzhiyun 
4980*4882a593Smuzhiyun #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
4981*4882a593Smuzhiyun #define WMI_SEND_TIMEOUT_HZ (3 * HZ)
4982*4882a593Smuzhiyun 
4983*4882a593Smuzhiyun struct ath11k_wmi_base {
4984*4882a593Smuzhiyun 	struct ath11k_base *ab;
4985*4882a593Smuzhiyun 	struct ath11k_pdev_wmi wmi[MAX_RADIOS];
4986*4882a593Smuzhiyun 	enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS];
4987*4882a593Smuzhiyun 	u32 max_msg_len[MAX_RADIOS];
4988*4882a593Smuzhiyun 
4989*4882a593Smuzhiyun 	struct completion service_ready;
4990*4882a593Smuzhiyun 	struct completion unified_ready;
4991*4882a593Smuzhiyun 	DECLARE_BITMAP(svc_map, WMI_MAX_EXT_SERVICE);
4992*4882a593Smuzhiyun 	wait_queue_head_t tx_credits_wq;
4993*4882a593Smuzhiyun 	const struct wmi_peer_flags_map *peer_flags;
4994*4882a593Smuzhiyun 	u32 num_mem_chunks;
4995*4882a593Smuzhiyun 	u32 rx_decap_mode;
4996*4882a593Smuzhiyun 	struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
4997*4882a593Smuzhiyun 
4998*4882a593Smuzhiyun 	enum wmi_host_hw_mode_config_type preferred_hw_mode;
4999*4882a593Smuzhiyun 	struct target_resource_config  wlan_resource_config;
5000*4882a593Smuzhiyun 
5001*4882a593Smuzhiyun 	struct ath11k_targ_cap *targ_cap;
5002*4882a593Smuzhiyun };
5003*4882a593Smuzhiyun 
5004*4882a593Smuzhiyun int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb,
5005*4882a593Smuzhiyun 			u32 cmd_id);
5006*4882a593Smuzhiyun struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
5007*4882a593Smuzhiyun int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
5008*4882a593Smuzhiyun 			 struct sk_buff *frame);
5009*4882a593Smuzhiyun int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
5010*4882a593Smuzhiyun 			struct ieee80211_mutable_offsets *offs,
5011*4882a593Smuzhiyun 			struct sk_buff *bcn);
5012*4882a593Smuzhiyun int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id);
5013*4882a593Smuzhiyun int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
5014*4882a593Smuzhiyun 		       const u8 *bssid);
5015*4882a593Smuzhiyun int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id);
5016*4882a593Smuzhiyun int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
5017*4882a593Smuzhiyun 			  bool restart);
5018*4882a593Smuzhiyun int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr,
5019*4882a593Smuzhiyun 			      u32 vdev_id, u32 param_id, u32 param_val);
5020*4882a593Smuzhiyun int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
5021*4882a593Smuzhiyun 			      u32 param_value, u8 pdev_id);
5022*4882a593Smuzhiyun int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id, u32 enable);
5023*4882a593Smuzhiyun int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab);
5024*4882a593Smuzhiyun int ath11k_wmi_cmd_init(struct ath11k_base *ab);
5025*4882a593Smuzhiyun int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab);
5026*4882a593Smuzhiyun int ath11k_wmi_connect(struct ath11k_base *ab);
5027*4882a593Smuzhiyun int ath11k_wmi_pdev_attach(struct ath11k_base *ab,
5028*4882a593Smuzhiyun 			   u8 pdev_id);
5029*4882a593Smuzhiyun int ath11k_wmi_attach(struct ath11k_base *ab);
5030*4882a593Smuzhiyun void ath11k_wmi_detach(struct ath11k_base *ab);
5031*4882a593Smuzhiyun int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr,
5032*4882a593Smuzhiyun 			   struct vdev_create_params *param);
5033*4882a593Smuzhiyun int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id,
5034*4882a593Smuzhiyun 					   const u8 *addr, dma_addr_t paddr,
5035*4882a593Smuzhiyun 					   u8 tid, u8 ba_window_size_valid,
5036*4882a593Smuzhiyun 					   u32 ba_window_size);
5037*4882a593Smuzhiyun int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar,
5038*4882a593Smuzhiyun 				    struct peer_create_params *param);
5039*4882a593Smuzhiyun int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
5040*4882a593Smuzhiyun 				  u32 param_id, u32 param_value);
5041*4882a593Smuzhiyun 
5042*4882a593Smuzhiyun int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
5043*4882a593Smuzhiyun 				u32 param, u32 param_value);
5044*4882a593Smuzhiyun int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
5045*4882a593Smuzhiyun int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar,
5046*4882a593Smuzhiyun 				    const u8 *peer_addr, u8 vdev_id);
5047*4882a593Smuzhiyun int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id);
5048*4882a593Smuzhiyun void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg);
5049*4882a593Smuzhiyun int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar,
5050*4882a593Smuzhiyun 				   struct scan_req_params *params);
5051*4882a593Smuzhiyun int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar,
5052*4882a593Smuzhiyun 				  struct scan_cancel_param *param);
5053*4882a593Smuzhiyun int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
5054*4882a593Smuzhiyun 				       struct wmi_wmm_params_all_arg *param);
5055*4882a593Smuzhiyun int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
5056*4882a593Smuzhiyun 			    u32 pdev_id);
5057*4882a593Smuzhiyun int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
5058*4882a593Smuzhiyun 
5059*4882a593Smuzhiyun int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar,
5060*4882a593Smuzhiyun 				   struct peer_assoc_params *param);
5061*4882a593Smuzhiyun int ath11k_wmi_vdev_install_key(struct ath11k *ar,
5062*4882a593Smuzhiyun 				struct wmi_vdev_install_key_arg *arg);
5063*4882a593Smuzhiyun int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar,
5064*4882a593Smuzhiyun 					  enum wmi_bss_chan_info_req_type type);
5065*4882a593Smuzhiyun int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar,
5066*4882a593Smuzhiyun 				      struct stats_request_params *param);
5067*4882a593Smuzhiyun int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar);
5068*4882a593Smuzhiyun int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar,
5069*4882a593Smuzhiyun 					u8 peer_addr[ETH_ALEN],
5070*4882a593Smuzhiyun 					struct peer_flush_params *param);
5071*4882a593Smuzhiyun int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr,
5072*4882a593Smuzhiyun 					struct ap_ps_params *param);
5073*4882a593Smuzhiyun int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
5074*4882a593Smuzhiyun 				       struct scan_chan_list_params *chan_list);
5075*4882a593Smuzhiyun int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar,
5076*4882a593Smuzhiyun 						  u32 pdev_id);
5077*4882a593Smuzhiyun int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
5078*4882a593Smuzhiyun int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5079*4882a593Smuzhiyun 			  u32 tid, u32 buf_size);
5080*4882a593Smuzhiyun int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5081*4882a593Smuzhiyun 			      u32 tid, u32 status);
5082*4882a593Smuzhiyun int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5083*4882a593Smuzhiyun 			  u32 tid, u32 initiator, u32 reason);
5084*4882a593Smuzhiyun int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar,
5085*4882a593Smuzhiyun 					    u32 vdev_id, u32 bcn_ctrl_op);
5086*4882a593Smuzhiyun int
5087*4882a593Smuzhiyun ath11k_wmi_send_init_country_cmd(struct ath11k *ar,
5088*4882a593Smuzhiyun 				 struct wmi_init_country_params init_cc_param);
5089*4882a593Smuzhiyun int
5090*4882a593Smuzhiyun ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar,
5091*4882a593Smuzhiyun 					     struct thermal_mitigation_params *param);
5092*4882a593Smuzhiyun int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
5093*4882a593Smuzhiyun int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar);
5094*4882a593Smuzhiyun int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable);
5095*4882a593Smuzhiyun int
5096*4882a593Smuzhiyun ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar,
5097*4882a593Smuzhiyun 				 struct rx_reorder_queue_remove_params *param);
5098*4882a593Smuzhiyun int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
5099*4882a593Smuzhiyun 				       struct pdev_set_regdomain_params *param);
5100*4882a593Smuzhiyun int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
5101*4882a593Smuzhiyun 			     struct ath11k_fw_stats *stats);
5102*4882a593Smuzhiyun size_t ath11k_wmi_fw_stats_num_peers(struct list_head *head);
5103*4882a593Smuzhiyun size_t ath11k_wmi_fw_stats_num_peers_extd(struct list_head *head);
5104*4882a593Smuzhiyun size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head);
5105*4882a593Smuzhiyun void ath11k_wmi_fw_stats_fill(struct ath11k *ar,
5106*4882a593Smuzhiyun 			      struct ath11k_fw_stats *fw_stats, u32 stats_id,
5107*4882a593Smuzhiyun 			      char *buf);
5108*4882a593Smuzhiyun int ath11k_wmi_simulate_radar(struct ath11k *ar);
5109*4882a593Smuzhiyun int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id);
5110*4882a593Smuzhiyun int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
5111*4882a593Smuzhiyun int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
5112*4882a593Smuzhiyun 				 struct ieee80211_he_obss_pd *he_obss_pd);
5113*4882a593Smuzhiyun int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
5114*4882a593Smuzhiyun 						 u8 bss_color, u32 period,
5115*4882a593Smuzhiyun 						 bool enable);
5116*4882a593Smuzhiyun int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
5117*4882a593Smuzhiyun 						bool enable);
5118*4882a593Smuzhiyun int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id);
5119*4882a593Smuzhiyun int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar,
5120*4882a593Smuzhiyun 				 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param);
5121*4882a593Smuzhiyun int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
5122*4882a593Smuzhiyun 				    u32 trigger, u32 enable);
5123*4882a593Smuzhiyun int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar,
5124*4882a593Smuzhiyun 				  struct ath11k_wmi_vdev_spectral_conf_param *param);
5125*4882a593Smuzhiyun #endif
5126