1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef ATH11K_RX_DESC_H 6*4882a593Smuzhiyun #define ATH11K_RX_DESC_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun enum rx_desc_rxpcu_filter { 9*4882a593Smuzhiyun RX_DESC_RXPCU_FILTER_PASS, 10*4882a593Smuzhiyun RX_DESC_RXPCU_FILTER_MONITOR_CLIENT, 11*4882a593Smuzhiyun RX_DESC_RXPCU_FILTER_MONITOR_OTHER, 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* rxpcu_filter_pass 15*4882a593Smuzhiyun * This MPDU passed the normal frame filter programming of rxpcu. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * rxpcu_filter_monitor_client 18*4882a593Smuzhiyun * This MPDU did not pass the regular frame filter and would 19*4882a593Smuzhiyun * have been dropped, were it not for the frame fitting into the 20*4882a593Smuzhiyun * 'monitor_client' category. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * rxpcu_filter_monitor_other 23*4882a593Smuzhiyun * This MPDU did not pass the regular frame filter and also did 24*4882a593Smuzhiyun * not pass the rxpcu_monitor_client filter. It would have been 25*4882a593Smuzhiyun * dropped accept that it did pass the 'monitor_other' category. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 29*4882a593Smuzhiyun #define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum rx_desc_sw_frame_grp_id { 32*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME, 33*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA, 34*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA, 35*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_NULL_DATA, 36*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0000, 37*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0001, 38*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0010, 39*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0011, 40*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0100, 41*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0101, 42*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0110, 43*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_0111, 44*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1000, 45*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1001, 46*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1010, 47*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1011, 48*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1100, 49*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1101, 50*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1110, 51*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_MGMT_1111, 52*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0000, 53*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0001, 54*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0010, 55*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0011, 56*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0100, 57*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0101, 58*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0110, 59*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_0111, 60*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1000, 61*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1001, 62*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1010, 63*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1011, 64*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1100, 65*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1101, 66*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1110, 67*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_CTRL_1111, 68*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED, 69*4882a593Smuzhiyun RX_DESC_SW_FRAME_GRP_ID_PHY_ERR, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun enum rx_desc_decap_type { 73*4882a593Smuzhiyun RX_DESC_DECAP_TYPE_RAW, 74*4882a593Smuzhiyun RX_DESC_DECAP_TYPE_NATIVE_WIFI, 75*4882a593Smuzhiyun RX_DESC_DECAP_TYPE_ETHERNET2_DIX, 76*4882a593Smuzhiyun RX_DESC_DECAP_TYPE_8023, 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun enum rx_desc_decrypt_status_code { 80*4882a593Smuzhiyun RX_DESC_DECRYPT_STATUS_CODE_OK, 81*4882a593Smuzhiyun RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME, 82*4882a593Smuzhiyun RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR, 83*4882a593Smuzhiyun RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID, 84*4882a593Smuzhiyun RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID, 85*4882a593Smuzhiyun RX_DESC_DECRYPT_STATUS_CODE_OTHER, 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0) 89*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_RSVD_1A BIT(1) 90*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2) 91*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3) 92*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4) 93*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5) 94*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_NON_QOS BIT(6) 95*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_NULL_DATA BIT(7) 96*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_MGMT_TYPE BIT(8) 97*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_CTRL_TYPE BIT(9) 98*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_MORE_DATA BIT(10) 99*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_EOSP BIT(11) 100*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_A_MSDU_ERROR BIT(12) 101*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_FRAGMENT BIT(13) 102*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_ORDER BIT(14) 103*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_CCE_MATCH BIT(15) 104*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_OVERFLOW_ERR BIT(16) 105*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_MSDU_LEN_ERR BIT(17) 106*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL BIT(18) 107*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_IP_CKSUM_FAIL BIT(19) 108*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_SA_IDX_INVALID BIT(20) 109*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_DA_IDX_INVALID BIT(21) 110*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_RSVD_1B BIT(22) 111*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP BIT(23) 112*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED BIT(24) 113*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_DIRECTED BIT(25) 114*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_BUFFER_FRAGMENT BIT(26) 115*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_MPDU_LEN_ERR BIT(27) 116*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_TKIP_MIC_ERR BIT(28) 117*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_DECRYPT_ERR BIT(29) 118*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR BIT(30) 119*4882a593Smuzhiyun #define RX_ATTENTION_INFO1_FCS_ERR BIT(31) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT BIT(0) 122*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_FLOW_IDX_INVALID BIT(1) 123*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_WIFI_PARSER_ERR BIT(2) 124*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR BIT(3) 125*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT BIT(4) 126*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT BIT(5) 127*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR BIT(6) 128*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_DA_IS_VALID BIT(7) 129*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_DA_IS_MCBC BIT(8) 130*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_SA_IS_VALID BIT(9) 131*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10) 132*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED BIT(13) 133*4882a593Smuzhiyun #define RX_ATTENTION_INFO2_MSDU_DONE BIT(31) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct rx_attention { 136*4882a593Smuzhiyun __le16 info0; 137*4882a593Smuzhiyun __le16 phy_ppdu_id; 138*4882a593Smuzhiyun __le32 info1; 139*4882a593Smuzhiyun __le32 info2; 140*4882a593Smuzhiyun } __packed; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* rx_attention 143*4882a593Smuzhiyun * 144*4882a593Smuzhiyun * rxpcu_mpdu_filter_in_category 145*4882a593Smuzhiyun * Field indicates what the reason was that this mpdu frame 146*4882a593Smuzhiyun * was allowed to come into the receive path by rxpcu. Values 147*4882a593Smuzhiyun * are defined in enum %RX_DESC_RXPCU_FILTER_*. 148*4882a593Smuzhiyun * 149*4882a593Smuzhiyun * sw_frame_group_id 150*4882a593Smuzhiyun * SW processes frames based on certain classifications. Values 151*4882a593Smuzhiyun * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 152*4882a593Smuzhiyun * 153*4882a593Smuzhiyun * phy_ppdu_id 154*4882a593Smuzhiyun * A ppdu counter value that PHY increments for every PPDU 155*4882a593Smuzhiyun * received. The counter value wraps around. 156*4882a593Smuzhiyun * 157*4882a593Smuzhiyun * first_mpdu 158*4882a593Smuzhiyun * Indicates the first MSDU of the PPDU. If both first_mpdu 159*4882a593Smuzhiyun * and last_mpdu are set in the MSDU then this is a not an 160*4882a593Smuzhiyun * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 161*4882a593Smuzhiyun * A-MPDU shall have both first_mpdu and last_mpdu bits set to 162*4882a593Smuzhiyun * 0. The PPDU start status will only be valid when this bit 163*4882a593Smuzhiyun * is set. 164*4882a593Smuzhiyun * 165*4882a593Smuzhiyun * mcast_bcast 166*4882a593Smuzhiyun * Multicast / broadcast indicator. Only set when the MAC 167*4882a593Smuzhiyun * address 1 bit 0 is set indicating mcast/bcast and the BSSID 168*4882a593Smuzhiyun * matches one of the 4 BSSID registers. Only set when 169*4882a593Smuzhiyun * first_msdu is set. 170*4882a593Smuzhiyun * 171*4882a593Smuzhiyun * ast_index_not_found 172*4882a593Smuzhiyun * Only valid when first_msdu is set. Indicates no AST matching 173*4882a593Smuzhiyun * entries within the the max search count. 174*4882a593Smuzhiyun * 175*4882a593Smuzhiyun * ast_index_timeout 176*4882a593Smuzhiyun * Only valid when first_msdu is set. Indicates an unsuccessful 177*4882a593Smuzhiyun * search in the address search table due to timeout. 178*4882a593Smuzhiyun * 179*4882a593Smuzhiyun * power_mgmt 180*4882a593Smuzhiyun * Power management bit set in the 802.11 header. Only set 181*4882a593Smuzhiyun * when first_msdu is set. 182*4882a593Smuzhiyun * 183*4882a593Smuzhiyun * non_qos 184*4882a593Smuzhiyun * Set if packet is not a non-QoS data frame. Only set when 185*4882a593Smuzhiyun * first_msdu is set. 186*4882a593Smuzhiyun * 187*4882a593Smuzhiyun * null_data 188*4882a593Smuzhiyun * Set if frame type indicates either null data or QoS null 189*4882a593Smuzhiyun * data format. Only set when first_msdu is set. 190*4882a593Smuzhiyun * 191*4882a593Smuzhiyun * mgmt_type 192*4882a593Smuzhiyun * Set if packet is a management packet. Only set when 193*4882a593Smuzhiyun * first_msdu is set. 194*4882a593Smuzhiyun * 195*4882a593Smuzhiyun * ctrl_type 196*4882a593Smuzhiyun * Set if packet is a control packet. Only set when first_msdu 197*4882a593Smuzhiyun * is set. 198*4882a593Smuzhiyun * 199*4882a593Smuzhiyun * more_data 200*4882a593Smuzhiyun * Set if more bit in frame control is set. Only set when 201*4882a593Smuzhiyun * first_msdu is set. 202*4882a593Smuzhiyun * 203*4882a593Smuzhiyun * eosp 204*4882a593Smuzhiyun * Set if the EOSP (end of service period) bit in the QoS 205*4882a593Smuzhiyun * control field is set. Only set when first_msdu is set. 206*4882a593Smuzhiyun * 207*4882a593Smuzhiyun * a_msdu_error 208*4882a593Smuzhiyun * Set if number of MSDUs in A-MSDU is above a threshold or if the 209*4882a593Smuzhiyun * size of the MSDU is invalid. This receive buffer will contain 210*4882a593Smuzhiyun * all of the remainder of MSDUs in this MPDU w/o decapsulation. 211*4882a593Smuzhiyun * 212*4882a593Smuzhiyun * fragment 213*4882a593Smuzhiyun * Indicates that this is an 802.11 fragment frame. This is 214*4882a593Smuzhiyun * set when either the more_frag bit is set in the frame 215*4882a593Smuzhiyun * control or the fragment number is not zero. Only set when 216*4882a593Smuzhiyun * first_msdu is set. 217*4882a593Smuzhiyun * 218*4882a593Smuzhiyun * order 219*4882a593Smuzhiyun * Set if the order bit in the frame control is set. Only set 220*4882a593Smuzhiyun * when first_msdu is set. 221*4882a593Smuzhiyun * 222*4882a593Smuzhiyun * cce_match 223*4882a593Smuzhiyun * Indicates that this status has a corresponding MSDU that 224*4882a593Smuzhiyun * requires FW processing. The OLE will have classification 225*4882a593Smuzhiyun * ring mask registers which will indicate the ring(s) for 226*4882a593Smuzhiyun * packets and descriptors which need FW attention. 227*4882a593Smuzhiyun * 228*4882a593Smuzhiyun * overflow_err 229*4882a593Smuzhiyun * PCU Receive FIFO does not have enough space to store the 230*4882a593Smuzhiyun * full receive packet. Enough space is reserved in the 231*4882a593Smuzhiyun * receive FIFO for the status is written. This MPDU remaining 232*4882a593Smuzhiyun * packets in the PPDU will be filtered and no Ack response 233*4882a593Smuzhiyun * will be transmitted. 234*4882a593Smuzhiyun * 235*4882a593Smuzhiyun * msdu_length_err 236*4882a593Smuzhiyun * Indicates that the MSDU length from the 802.3 encapsulated 237*4882a593Smuzhiyun * length field extends beyond the MPDU boundary. 238*4882a593Smuzhiyun * 239*4882a593Smuzhiyun * tcp_udp_chksum_fail 240*4882a593Smuzhiyun * Indicates that the computed checksum (tcp_udp_chksum) did 241*4882a593Smuzhiyun * not match the checksum in the TCP/UDP header. 242*4882a593Smuzhiyun * 243*4882a593Smuzhiyun * ip_chksum_fail 244*4882a593Smuzhiyun * Indicates that the computed checksum did not match the 245*4882a593Smuzhiyun * checksum in the IP header. 246*4882a593Smuzhiyun * 247*4882a593Smuzhiyun * sa_idx_invalid 248*4882a593Smuzhiyun * Indicates no matching entry was found in the address search 249*4882a593Smuzhiyun * table for the source MAC address. 250*4882a593Smuzhiyun * 251*4882a593Smuzhiyun * da_idx_invalid 252*4882a593Smuzhiyun * Indicates no matching entry was found in the address search 253*4882a593Smuzhiyun * table for the destination MAC address. 254*4882a593Smuzhiyun * 255*4882a593Smuzhiyun * rx_in_tx_decrypt_byp 256*4882a593Smuzhiyun * Indicates that RX packet is not decrypted as Crypto is busy 257*4882a593Smuzhiyun * with TX packet processing. 258*4882a593Smuzhiyun * 259*4882a593Smuzhiyun * encrypt_required 260*4882a593Smuzhiyun * Indicates that this data type frame is not encrypted even if 261*4882a593Smuzhiyun * the policy for this MPDU requires encryption as indicated in 262*4882a593Smuzhiyun * the peer table key type. 263*4882a593Smuzhiyun * 264*4882a593Smuzhiyun * directed 265*4882a593Smuzhiyun * MPDU is a directed packet which means that the RA matched 266*4882a593Smuzhiyun * our STA addresses. In proxySTA it means that the TA matched 267*4882a593Smuzhiyun * an entry in our address search table with the corresponding 268*4882a593Smuzhiyun * 'no_ack' bit is the address search entry cleared. 269*4882a593Smuzhiyun * 270*4882a593Smuzhiyun * buffer_fragment 271*4882a593Smuzhiyun * Indicates that at least one of the rx buffers has been 272*4882a593Smuzhiyun * fragmented. If set the FW should look at the rx_frag_info 273*4882a593Smuzhiyun * descriptor described below. 274*4882a593Smuzhiyun * 275*4882a593Smuzhiyun * mpdu_length_err 276*4882a593Smuzhiyun * Indicates that the MPDU was pre-maturely terminated 277*4882a593Smuzhiyun * resulting in a truncated MPDU. Don't trust the MPDU length 278*4882a593Smuzhiyun * field. 279*4882a593Smuzhiyun * 280*4882a593Smuzhiyun * tkip_mic_err 281*4882a593Smuzhiyun * Indicates that the MPDU Michael integrity check failed 282*4882a593Smuzhiyun * 283*4882a593Smuzhiyun * decrypt_err 284*4882a593Smuzhiyun * Indicates that the MPDU decrypt integrity check failed 285*4882a593Smuzhiyun * 286*4882a593Smuzhiyun * fcs_err 287*4882a593Smuzhiyun * Indicates that the MPDU FCS check failed 288*4882a593Smuzhiyun * 289*4882a593Smuzhiyun * flow_idx_timeout 290*4882a593Smuzhiyun * Indicates an unsuccessful flow search due to the expiring of 291*4882a593Smuzhiyun * the search timer. 292*4882a593Smuzhiyun * 293*4882a593Smuzhiyun * flow_idx_invalid 294*4882a593Smuzhiyun * flow id is not valid. 295*4882a593Smuzhiyun * 296*4882a593Smuzhiyun * amsdu_parser_error 297*4882a593Smuzhiyun * A-MSDU could not be properly de-agregated. 298*4882a593Smuzhiyun * 299*4882a593Smuzhiyun * sa_idx_timeout 300*4882a593Smuzhiyun * Indicates an unsuccessful search for the source MAC address 301*4882a593Smuzhiyun * due to the expiring of the search timer. 302*4882a593Smuzhiyun * 303*4882a593Smuzhiyun * da_idx_timeout 304*4882a593Smuzhiyun * Indicates an unsuccessful search for the destination MAC 305*4882a593Smuzhiyun * address due to the expiring of the search timer. 306*4882a593Smuzhiyun * 307*4882a593Smuzhiyun * msdu_limit_error 308*4882a593Smuzhiyun * Indicates that the MSDU threshold was exceeded and thus 309*4882a593Smuzhiyun * all the rest of the MSDUs will not be scattered and will not 310*4882a593Smuzhiyun * be decasulated but will be DMA'ed in RAW format as a single 311*4882a593Smuzhiyun * MSDU buffer. 312*4882a593Smuzhiyun * 313*4882a593Smuzhiyun * da_is_valid 314*4882a593Smuzhiyun * Indicates that OLE found a valid DA entry. 315*4882a593Smuzhiyun * 316*4882a593Smuzhiyun * da_is_mcbc 317*4882a593Smuzhiyun * Field Only valid if da_is_valid is set. Indicates the DA address 318*4882a593Smuzhiyun * was a Multicast or Broadcast address. 319*4882a593Smuzhiyun * 320*4882a593Smuzhiyun * sa_is_valid 321*4882a593Smuzhiyun * Indicates that OLE found a valid SA entry. 322*4882a593Smuzhiyun * 323*4882a593Smuzhiyun * decrypt_status_code 324*4882a593Smuzhiyun * Field provides insight into the decryption performed. Values are 325*4882a593Smuzhiyun * defined in enum %RX_DESC_DECRYPT_STATUS_CODE*. 326*4882a593Smuzhiyun * 327*4882a593Smuzhiyun * rx_bitmap_not_updated 328*4882a593Smuzhiyun * Frame is received, but RXPCU could not update the receive bitmap 329*4882a593Smuzhiyun * due to (temporary) fifo constraints. 330*4882a593Smuzhiyun * 331*4882a593Smuzhiyun * msdu_done 332*4882a593Smuzhiyun * If set indicates that the RX packet data, RX header data, RX 333*4882a593Smuzhiyun * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 334*4882a593Smuzhiyun * start/end descriptors and RX Attention descriptor are all 335*4882a593Smuzhiyun * valid. This bit must be in the last octet of the 336*4882a593Smuzhiyun * descriptor. 337*4882a593Smuzhiyun */ 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun #define RX_MPDU_START_INFO0_NDP_FRAME BIT(9) 340*4882a593Smuzhiyun #define RX_MPDU_START_INFO0_PHY_ERR BIT(10) 341*4882a593Smuzhiyun #define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR BIT(11) 342*4882a593Smuzhiyun #define RX_MPDU_START_INFO0_PROTO_VER_ERR BIT(12) 343*4882a593Smuzhiyun #define RX_MPDU_START_INFO0_AST_LOOKUP_VALID BIT(13) 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID BIT(0) 346*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_DUR_VALID BIT(1) 347*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MAC_ADDR1_VALID BIT(2) 348*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MAC_ADDR2_VALID BIT(3) 349*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MAC_ADDR3_VALID BIT(4) 350*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MAC_ADDR4_VALID BIT(5) 351*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID BIT(6) 352*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID BIT(7) 353*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID BIT(8) 354*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID BIT(9) 355*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10) 356*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MORE_FRAG_FLAG BIT(14) 357*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_FROM_DS BIT(16) 358*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_TO_DS BIT(17) 359*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_ENCRYPTED BIT(18) 360*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_RETRY BIT(19) 361*4882a593Smuzhiyun #define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20) 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_EPD_EN BIT(0) 364*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1) 365*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2) 366*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 367*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_MESH_STA BIT(8) 368*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_BSSID_HIT BIT(9) 369*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10) 370*4882a593Smuzhiyun #define RX_MPDU_START_INFO2_TID GENMASK(17, 14) 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0) 373*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7) 374*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA BIT(8) 375*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA BIT(9) 376*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR BIT(10) 377*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL GENMASK(12, 11) 378*4882a593Smuzhiyun #define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL GENMASK(14, 13) 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI GENMASK(7, 0) 381*4882a593Smuzhiyun #define RX_MPDU_START_INFO4_RECV_QUEUE_NUM GENMASK(23, 8) 382*4882a593Smuzhiyun #define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN BIT(24) 383*4882a593Smuzhiyun #define RX_MPDU_START_INFO4_FIRST_DELIM_ERR BIT(25) 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0) 386*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8) 387*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9) 388*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10) 389*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12) 390*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13) 391*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14) 392*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15) 393*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16) 394*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28) 395*4882a593Smuzhiyun #define RX_MPDU_START_INFO5_BAR_FRAME BIT(29) 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0) 398*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14) 399*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15) 400*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16) 401*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17) 402*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_POWER_MGMT BIT(18) 403*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_NON_QOS BIT(19) 404*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_NULL_DATA BIT(20) 405*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21) 406*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22) 407*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_MORE_DATA BIT(23) 408*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_EOSP BIT(24) 409*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_FRAGMENT BIT(25) 410*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_ORDER BIT(26) 411*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27) 412*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28) 413*4882a593Smuzhiyun #define RX_MPDU_START_INFO6_DIRECTED BIT(29) 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define RX_MPDU_START_RAW_MPDU BIT(0) 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun struct rx_mpdu_start { 418*4882a593Smuzhiyun __le16 info0; 419*4882a593Smuzhiyun __le16 phy_ppdu_id; 420*4882a593Smuzhiyun __le16 ast_index; 421*4882a593Smuzhiyun __le16 sw_peer_id; 422*4882a593Smuzhiyun __le32 info1; 423*4882a593Smuzhiyun __le32 info2; 424*4882a593Smuzhiyun __le32 pn[4]; 425*4882a593Smuzhiyun __le32 peer_meta_data; 426*4882a593Smuzhiyun __le32 info3; 427*4882a593Smuzhiyun __le32 reo_queue_desc_lo; 428*4882a593Smuzhiyun __le32 info4; 429*4882a593Smuzhiyun __le32 info5; 430*4882a593Smuzhiyun __le32 info6; 431*4882a593Smuzhiyun __le16 frame_ctrl; 432*4882a593Smuzhiyun __le16 duration; 433*4882a593Smuzhiyun u8 addr1[ETH_ALEN]; 434*4882a593Smuzhiyun u8 addr2[ETH_ALEN]; 435*4882a593Smuzhiyun u8 addr3[ETH_ALEN]; 436*4882a593Smuzhiyun __le16 seq_ctrl; 437*4882a593Smuzhiyun u8 addr4[ETH_ALEN]; 438*4882a593Smuzhiyun __le16 qos_ctrl; 439*4882a593Smuzhiyun __le32 ht_ctrl; 440*4882a593Smuzhiyun __le32 raw; 441*4882a593Smuzhiyun } __packed; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun /* rx_mpdu_start 444*4882a593Smuzhiyun * 445*4882a593Smuzhiyun * rxpcu_mpdu_filter_in_category 446*4882a593Smuzhiyun * Field indicates what the reason was that this mpdu frame 447*4882a593Smuzhiyun * was allowed to come into the receive path by rxpcu. Values 448*4882a593Smuzhiyun * are defined in enum %RX_DESC_RXPCU_FILTER_*. 449*4882a593Smuzhiyun * Note: for ndp frame, if it was expected because the preceding 450*4882a593Smuzhiyun * NDPA was filter_pass, the setting rxpcu_filter_pass will be 451*4882a593Smuzhiyun * used. This setting will also be used for every ndp frame in 452*4882a593Smuzhiyun * case Promiscuous mode is enabled. 453*4882a593Smuzhiyun * 454*4882a593Smuzhiyun * sw_frame_group_id 455*4882a593Smuzhiyun * SW processes frames based on certain classifications. Values 456*4882a593Smuzhiyun * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 457*4882a593Smuzhiyun * 458*4882a593Smuzhiyun * ndp_frame 459*4882a593Smuzhiyun * Indicates that the received frame was an NDP frame. 460*4882a593Smuzhiyun * 461*4882a593Smuzhiyun * phy_err 462*4882a593Smuzhiyun * Indicates that PHY error was received before MAC received data. 463*4882a593Smuzhiyun * 464*4882a593Smuzhiyun * phy_err_during_mpdu_header 465*4882a593Smuzhiyun * PHY error was received before MAC received the complete MPDU 466*4882a593Smuzhiyun * header which was needed for proper decoding. 467*4882a593Smuzhiyun * 468*4882a593Smuzhiyun * protocol_version_err 469*4882a593Smuzhiyun * RXPCU detected a version error in the frame control field. 470*4882a593Smuzhiyun * 471*4882a593Smuzhiyun * ast_based_lookup_valid 472*4882a593Smuzhiyun * AST based lookup for this frame has found a valid result. 473*4882a593Smuzhiyun * 474*4882a593Smuzhiyun * phy_ppdu_id 475*4882a593Smuzhiyun * A ppdu counter value that PHY increments for every PPDU 476*4882a593Smuzhiyun * received. The counter value wraps around. 477*4882a593Smuzhiyun * 478*4882a593Smuzhiyun * ast_index 479*4882a593Smuzhiyun * This field indicates the index of the AST entry corresponding 480*4882a593Smuzhiyun * to this MPDU. It is provided by the GSE module instantiated in 481*4882a593Smuzhiyun * RXPCU. A value of 0xFFFF indicates an invalid AST index. 482*4882a593Smuzhiyun * 483*4882a593Smuzhiyun * sw_peer_id 484*4882a593Smuzhiyun * This field indicates a unique peer identifier. It is set equal 485*4882a593Smuzhiyun * to field 'sw_peer_id' from the AST entry. 486*4882a593Smuzhiyun * 487*4882a593Smuzhiyun * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid, 488*4882a593Smuzhiyun * mpdu_ht_control_valid, frame_encryption_info_valid 489*4882a593Smuzhiyun * Indicates that each fields have valid entries. 490*4882a593Smuzhiyun * 491*4882a593Smuzhiyun * mac_addr_adx_valid 492*4882a593Smuzhiyun * Corresponding mac_addr_adx_{lo/hi} has valid entries. 493*4882a593Smuzhiyun * 494*4882a593Smuzhiyun * from_ds, to_ds 495*4882a593Smuzhiyun * Valid only when mpdu_frame_control_valid is set. Indicates that 496*4882a593Smuzhiyun * frame is received from DS and sent to DS. 497*4882a593Smuzhiyun * 498*4882a593Smuzhiyun * encrypted 499*4882a593Smuzhiyun * Protected bit from the frame control. 500*4882a593Smuzhiyun * 501*4882a593Smuzhiyun * mpdu_retry 502*4882a593Smuzhiyun * Retry bit from frame control. Only valid when first_msdu is set. 503*4882a593Smuzhiyun * 504*4882a593Smuzhiyun * mpdu_sequence_number 505*4882a593Smuzhiyun * The sequence number from the 802.11 header. 506*4882a593Smuzhiyun * 507*4882a593Smuzhiyun * epd_en 508*4882a593Smuzhiyun * If set, use EPD instead of LPD. 509*4882a593Smuzhiyun * 510*4882a593Smuzhiyun * all_frames_shall_be_encrypted 511*4882a593Smuzhiyun * If set, all frames (data only?) shall be encrypted. If not, 512*4882a593Smuzhiyun * RX CRYPTO shall set an error flag. 513*4882a593Smuzhiyun * 514*4882a593Smuzhiyun * encrypt_type 515*4882a593Smuzhiyun * Values are defined in enum %HAL_ENCRYPT_TYPE_. 516*4882a593Smuzhiyun * 517*4882a593Smuzhiyun * mesh_sta 518*4882a593Smuzhiyun * Indicates a Mesh (11s) STA. 519*4882a593Smuzhiyun * 520*4882a593Smuzhiyun * bssid_hit 521*4882a593Smuzhiyun * BSSID of the incoming frame matched one of the 8 BSSID 522*4882a593Smuzhiyun * register values. 523*4882a593Smuzhiyun * 524*4882a593Smuzhiyun * bssid_number 525*4882a593Smuzhiyun * This number indicates which one out of the 8 BSSID register 526*4882a593Smuzhiyun * values matched the incoming frame. 527*4882a593Smuzhiyun * 528*4882a593Smuzhiyun * tid 529*4882a593Smuzhiyun * TID field in the QoS control field 530*4882a593Smuzhiyun * 531*4882a593Smuzhiyun * pn 532*4882a593Smuzhiyun * The PN number. 533*4882a593Smuzhiyun * 534*4882a593Smuzhiyun * peer_meta_data 535*4882a593Smuzhiyun * Meta data that SW has programmed in the Peer table entry 536*4882a593Smuzhiyun * of the transmitting STA. 537*4882a593Smuzhiyun * 538*4882a593Smuzhiyun * rx_reo_queue_desc_addr_lo 539*4882a593Smuzhiyun * Address (lower 32 bits) of the REO queue descriptor. 540*4882a593Smuzhiyun * 541*4882a593Smuzhiyun * rx_reo_queue_desc_addr_hi 542*4882a593Smuzhiyun * Address (upper 8 bits) of the REO queue descriptor. 543*4882a593Smuzhiyun * 544*4882a593Smuzhiyun * receive_queue_number 545*4882a593Smuzhiyun * Indicates the MPDU queue ID to which this MPDU link 546*4882a593Smuzhiyun * descriptor belongs. 547*4882a593Smuzhiyun * 548*4882a593Smuzhiyun * pre_delim_err_warning 549*4882a593Smuzhiyun * Indicates that a delimiter FCS error was found in between the 550*4882a593Smuzhiyun * previous MPDU and this MPDU. Note that this is just a warning, 551*4882a593Smuzhiyun * and does not mean that this MPDU is corrupted in any way. If 552*4882a593Smuzhiyun * it is, there will be other errors indicated such as FCS or 553*4882a593Smuzhiyun * decrypt errors. 554*4882a593Smuzhiyun * 555*4882a593Smuzhiyun * first_delim_err 556*4882a593Smuzhiyun * Indicates that the first delimiter had a FCS failure. 557*4882a593Smuzhiyun * 558*4882a593Smuzhiyun * key_id 559*4882a593Smuzhiyun * The key ID octet from the IV. 560*4882a593Smuzhiyun * 561*4882a593Smuzhiyun * new_peer_entry 562*4882a593Smuzhiyun * Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 563*4882a593Smuzhiyun * doesn't follow so RX DECRYPTION module either uses old peer 564*4882a593Smuzhiyun * entry or not decrypt. 565*4882a593Smuzhiyun * 566*4882a593Smuzhiyun * decrypt_needed 567*4882a593Smuzhiyun * When RXPCU sets bit 'ast_index_not_found or ast_index_timeout', 568*4882a593Smuzhiyun * RXPCU will also ensure that this bit is NOT set. CRYPTO for that 569*4882a593Smuzhiyun * reason only needs to evaluate this bit and non of the other ones 570*4882a593Smuzhiyun * 571*4882a593Smuzhiyun * decap_type 572*4882a593Smuzhiyun * Used by the OLE during decapsulation. Values are defined in 573*4882a593Smuzhiyun * enum %MPDU_START_DECAP_TYPE_*. 574*4882a593Smuzhiyun * 575*4882a593Smuzhiyun * rx_insert_vlan_c_tag_padding 576*4882a593Smuzhiyun * rx_insert_vlan_s_tag_padding 577*4882a593Smuzhiyun * Insert 4 byte of all zeros as VLAN tag or double VLAN tag if 578*4882a593Smuzhiyun * the rx payload does not have VLAN. 579*4882a593Smuzhiyun * 580*4882a593Smuzhiyun * strip_vlan_c_tag_decap 581*4882a593Smuzhiyun * strip_vlan_s_tag_decap 582*4882a593Smuzhiyun * Strip VLAN or double VLAN during decapsulation. 583*4882a593Smuzhiyun * 584*4882a593Smuzhiyun * pre_delim_count 585*4882a593Smuzhiyun * The number of delimiters before this MPDU. Note that this 586*4882a593Smuzhiyun * number is cleared at PPDU start. If this MPDU is the first 587*4882a593Smuzhiyun * received MPDU in the PPDU and this MPDU gets filtered-in, 588*4882a593Smuzhiyun * this field will indicate the number of delimiters located 589*4882a593Smuzhiyun * after the last MPDU in the previous PPDU. 590*4882a593Smuzhiyun * 591*4882a593Smuzhiyun * If this MPDU is located after the first received MPDU in 592*4882a593Smuzhiyun * an PPDU, this field will indicate the number of delimiters 593*4882a593Smuzhiyun * located between the previous MPDU and this MPDU. 594*4882a593Smuzhiyun * 595*4882a593Smuzhiyun * ampdu_flag 596*4882a593Smuzhiyun * Received frame was part of an A-MPDU. 597*4882a593Smuzhiyun * 598*4882a593Smuzhiyun * bar_frame 599*4882a593Smuzhiyun * Received frame is a BAR frame 600*4882a593Smuzhiyun * 601*4882a593Smuzhiyun * mpdu_length 602*4882a593Smuzhiyun * MPDU length before decapsulation. 603*4882a593Smuzhiyun * 604*4882a593Smuzhiyun * first_mpdu..directed 605*4882a593Smuzhiyun * See definition in RX attention descriptor 606*4882a593Smuzhiyun * 607*4882a593Smuzhiyun */ 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun enum rx_msdu_start_pkt_type { 610*4882a593Smuzhiyun RX_MSDU_START_PKT_TYPE_11A, 611*4882a593Smuzhiyun RX_MSDU_START_PKT_TYPE_11B, 612*4882a593Smuzhiyun RX_MSDU_START_PKT_TYPE_11N, 613*4882a593Smuzhiyun RX_MSDU_START_PKT_TYPE_11AC, 614*4882a593Smuzhiyun RX_MSDU_START_PKT_TYPE_11AX, 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun enum rx_msdu_start_sgi { 618*4882a593Smuzhiyun RX_MSDU_START_SGI_0_8_US, 619*4882a593Smuzhiyun RX_MSDU_START_SGI_0_4_US, 620*4882a593Smuzhiyun RX_MSDU_START_SGI_1_6_US, 621*4882a593Smuzhiyun RX_MSDU_START_SGI_3_2_US, 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun enum rx_msdu_start_recv_bw { 625*4882a593Smuzhiyun RX_MSDU_START_RECV_BW_20MHZ, 626*4882a593Smuzhiyun RX_MSDU_START_RECV_BW_40MHZ, 627*4882a593Smuzhiyun RX_MSDU_START_RECV_BW_80MHZ, 628*4882a593Smuzhiyun RX_MSDU_START_RECV_BW_160MHZ, 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun enum rx_msdu_start_reception_type { 632*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_SU, 633*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO, 634*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA, 635*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 636*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO, 637*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA, 638*4882a593Smuzhiyun RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, 639*4882a593Smuzhiyun }; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun #define RX_MSDU_START_INFO1_MSDU_LENGTH GENMASK(13, 0) 642*4882a593Smuzhiyun #define RX_MSDU_START_INFO1_RSVD_1A BIT(14) 643*4882a593Smuzhiyun #define RX_MSDU_START_INFO1_IPSEC_ESP BIT(15) 644*4882a593Smuzhiyun #define RX_MSDU_START_INFO1_L3_OFFSET GENMASK(22, 16) 645*4882a593Smuzhiyun #define RX_MSDU_START_INFO1_IPSEC_AH BIT(23) 646*4882a593Smuzhiyun #define RX_MSDU_START_INFO1_L4_OFFSET GENMASK(31, 24) 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_MSDU_NUMBER GENMASK(7, 0) 649*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_DECAP_TYPE GENMASK(9, 8) 650*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IPV4 BIT(10) 651*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IPV6 BIT(11) 652*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_TCP BIT(12) 653*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_UDP BIT(13) 654*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IP_FRAG BIT(14) 655*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_TCP_ONLY_ACK BIT(15) 656*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST BIT(16) 657*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH GENMASK(18, 17) 658*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID BIT(19) 659*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID BIT(20) 660*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID BIT(21) 661*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT BIT(22) 662*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_LDPC BIT(23) 663*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR GENMASK(31, 24) 664*4882a593Smuzhiyun #define RX_MSDU_START_INFO2_DECAP_FORMAT GENMASK(9, 8) 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_USER_RSSI GENMASK(7, 0) 667*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_PKT_TYPE GENMASK(11, 8) 668*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_STBC BIT(12) 669*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_SGI GENMASK(14, 13) 670*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_RATE_MCS GENMASK(18, 15) 671*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_RECV_BW GENMASK(20, 19) 672*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21) 673*4882a593Smuzhiyun #define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24) 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun struct rx_msdu_start { 676*4882a593Smuzhiyun __le16 info0; 677*4882a593Smuzhiyun __le16 phy_ppdu_id; 678*4882a593Smuzhiyun __le32 info1; 679*4882a593Smuzhiyun __le32 info2; 680*4882a593Smuzhiyun __le32 toeplitz_hash; 681*4882a593Smuzhiyun __le32 flow_id_toeplitz; 682*4882a593Smuzhiyun __le32 info3; 683*4882a593Smuzhiyun __le32 ppdu_start_timestamp; 684*4882a593Smuzhiyun __le32 phy_meta_data; 685*4882a593Smuzhiyun } __packed; 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun /* rx_msdu_start 688*4882a593Smuzhiyun * 689*4882a593Smuzhiyun * rxpcu_mpdu_filter_in_category 690*4882a593Smuzhiyun * Field indicates what the reason was that this mpdu frame 691*4882a593Smuzhiyun * was allowed to come into the receive path by rxpcu. Values 692*4882a593Smuzhiyun * are defined in enum %RX_DESC_RXPCU_FILTER_*. 693*4882a593Smuzhiyun * 694*4882a593Smuzhiyun * sw_frame_group_id 695*4882a593Smuzhiyun * SW processes frames based on certain classifications. Values 696*4882a593Smuzhiyun * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 697*4882a593Smuzhiyun * 698*4882a593Smuzhiyun * phy_ppdu_id 699*4882a593Smuzhiyun * A ppdu counter value that PHY increments for every PPDU 700*4882a593Smuzhiyun * received. The counter value wraps around. 701*4882a593Smuzhiyun * 702*4882a593Smuzhiyun * msdu_length 703*4882a593Smuzhiyun * MSDU length in bytes after decapsulation. 704*4882a593Smuzhiyun * 705*4882a593Smuzhiyun * ipsec_esp 706*4882a593Smuzhiyun * Set if IPv4/v6 packet is using IPsec ESP. 707*4882a593Smuzhiyun * 708*4882a593Smuzhiyun * l3_offset 709*4882a593Smuzhiyun * Depending upon mode bit, this field either indicates the 710*4882a593Smuzhiyun * L3 offset in bytes from the start of the RX_HEADER or the IP 711*4882a593Smuzhiyun * offset in bytes from the start of the packet after 712*4882a593Smuzhiyun * decapsulation. The latter is only valid if ipv4_proto or 713*4882a593Smuzhiyun * ipv6_proto is set. 714*4882a593Smuzhiyun * 715*4882a593Smuzhiyun * ipsec_ah 716*4882a593Smuzhiyun * Set if IPv4/v6 packet is using IPsec AH 717*4882a593Smuzhiyun * 718*4882a593Smuzhiyun * l4_offset 719*4882a593Smuzhiyun * Depending upon mode bit, this field either indicates the 720*4882a593Smuzhiyun * L4 offset nin bytes from the start of RX_HEADER (only valid 721*4882a593Smuzhiyun * if either ipv4_proto or ipv6_proto is set to 1) or indicates 722*4882a593Smuzhiyun * the offset in bytes to the start of TCP or UDP header from 723*4882a593Smuzhiyun * the start of the IP header after decapsulation (Only valid if 724*4882a593Smuzhiyun * tcp_proto or udp_proto is set). The value 0 indicates that 725*4882a593Smuzhiyun * the offset is longer than 127 bytes. 726*4882a593Smuzhiyun * 727*4882a593Smuzhiyun * msdu_number 728*4882a593Smuzhiyun * Indicates the MSDU number within a MPDU. This value is 729*4882a593Smuzhiyun * reset to zero at the start of each MPDU. If the number of 730*4882a593Smuzhiyun * MSDU exceeds 255 this number will wrap using modulo 256. 731*4882a593Smuzhiyun * 732*4882a593Smuzhiyun * decap_type 733*4882a593Smuzhiyun * Indicates the format after decapsulation. Values are defined in 734*4882a593Smuzhiyun * enum %MPDU_START_DECAP_TYPE_*. 735*4882a593Smuzhiyun * 736*4882a593Smuzhiyun * ipv4_proto 737*4882a593Smuzhiyun * Set if L2 layer indicates IPv4 protocol. 738*4882a593Smuzhiyun * 739*4882a593Smuzhiyun * ipv6_proto 740*4882a593Smuzhiyun * Set if L2 layer indicates IPv6 protocol. 741*4882a593Smuzhiyun * 742*4882a593Smuzhiyun * tcp_proto 743*4882a593Smuzhiyun * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 744*4882a593Smuzhiyun * indicates TCP. 745*4882a593Smuzhiyun * 746*4882a593Smuzhiyun * udp_proto 747*4882a593Smuzhiyun * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 748*4882a593Smuzhiyun * indicates UDP. 749*4882a593Smuzhiyun * 750*4882a593Smuzhiyun * ip_frag 751*4882a593Smuzhiyun * Indicates that either the IP More frag bit is set or IP frag 752*4882a593Smuzhiyun * number is non-zero. If set indicates that this is a fragmented 753*4882a593Smuzhiyun * IP packet. 754*4882a593Smuzhiyun * 755*4882a593Smuzhiyun * tcp_only_ack 756*4882a593Smuzhiyun * Set if only the TCP Ack bit is set in the TCP flags and if 757*4882a593Smuzhiyun * the TCP payload is 0. 758*4882a593Smuzhiyun * 759*4882a593Smuzhiyun * da_is_bcast_mcast 760*4882a593Smuzhiyun * The destination address is broadcast or multicast. 761*4882a593Smuzhiyun * 762*4882a593Smuzhiyun * toeplitz_hash 763*4882a593Smuzhiyun * Actual chosen Hash. 764*4882a593Smuzhiyun * 0 - Toeplitz hash of 2-tuple (IP source address, IP 765*4882a593Smuzhiyun * destination address) 766*4882a593Smuzhiyun * 1 - Toeplitz hash of 4-tuple (IP source address, 767*4882a593Smuzhiyun * IP destination address, L4 (TCP/UDP) source port, 768*4882a593Smuzhiyun * L4 (TCP/UDP) destination port) 769*4882a593Smuzhiyun * 2 - Toeplitz of flow_id 770*4882a593Smuzhiyun * 3 - Zero is used 771*4882a593Smuzhiyun * 772*4882a593Smuzhiyun * ip_fixed_header_valid 773*4882a593Smuzhiyun * Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 774*4882a593Smuzhiyun * fully within first 256 bytes of the packet 775*4882a593Smuzhiyun * 776*4882a593Smuzhiyun * ip_extn_header_valid 777*4882a593Smuzhiyun * IPv6/IPv6 header, including IPv4 options and 778*4882a593Smuzhiyun * recognizable extension headers parsed fully within first 256 779*4882a593Smuzhiyun * bytes of the packet 780*4882a593Smuzhiyun * 781*4882a593Smuzhiyun * tcp_udp_header_valid 782*4882a593Smuzhiyun * Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 783*4882a593Smuzhiyun * header parsed fully within first 256 bytes of the packet 784*4882a593Smuzhiyun * 785*4882a593Smuzhiyun * mesh_control_present 786*4882a593Smuzhiyun * When set, this MSDU includes the 'Mesh Control' field 787*4882a593Smuzhiyun * 788*4882a593Smuzhiyun * ldpc 789*4882a593Smuzhiyun * 790*4882a593Smuzhiyun * ip4_protocol_ip6_next_header 791*4882a593Smuzhiyun * For IPv4, this is the 8 bit protocol field set). For IPv6 this 792*4882a593Smuzhiyun * is the 8 bit next_header field. 793*4882a593Smuzhiyun * 794*4882a593Smuzhiyun * toeplitz_hash_2_or_4 795*4882a593Smuzhiyun * Controlled by RxOLE register - If register bit set to 0, 796*4882a593Smuzhiyun * Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest 797*4882a593Smuzhiyun * addresses; otherwise, toeplitz hash is computed over 4-tuple 798*4882a593Smuzhiyun * IPv4 or IPv6 src/dest addresses and src/dest ports. 799*4882a593Smuzhiyun * 800*4882a593Smuzhiyun * flow_id_toeplitz 801*4882a593Smuzhiyun * Toeplitz hash of 5-tuple 802*4882a593Smuzhiyun * {IP source address, IP destination address, IP source port, IP 803*4882a593Smuzhiyun * destination port, L4 protocol} in case of non-IPSec. 804*4882a593Smuzhiyun * 805*4882a593Smuzhiyun * In case of IPSec - Toeplitz hash of 4-tuple 806*4882a593Smuzhiyun * {IP source address, IP destination address, SPI, L4 protocol} 807*4882a593Smuzhiyun * 808*4882a593Smuzhiyun * The relevant Toeplitz key registers are provided in RxOLE's 809*4882a593Smuzhiyun * instance of common parser module. These registers are separate 810*4882a593Smuzhiyun * from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 811*4882a593Smuzhiyun * The actual value will be passed on from common parser module 812*4882a593Smuzhiyun * to RxOLE in one of the WHO_* TLVs. 813*4882a593Smuzhiyun * 814*4882a593Smuzhiyun * user_rssi 815*4882a593Smuzhiyun * RSSI for this user 816*4882a593Smuzhiyun * 817*4882a593Smuzhiyun * pkt_type 818*4882a593Smuzhiyun * Values are defined in enum %RX_MSDU_START_PKT_TYPE_*. 819*4882a593Smuzhiyun * 820*4882a593Smuzhiyun * stbc 821*4882a593Smuzhiyun * When set, use STBC transmission rates. 822*4882a593Smuzhiyun * 823*4882a593Smuzhiyun * sgi 824*4882a593Smuzhiyun * Field only valid when pkt type is HT, VHT or HE. Values are 825*4882a593Smuzhiyun * defined in enum %RX_MSDU_START_SGI_*. 826*4882a593Smuzhiyun * 827*4882a593Smuzhiyun * rate_mcs 828*4882a593Smuzhiyun * MCS Rate used. 829*4882a593Smuzhiyun * 830*4882a593Smuzhiyun * receive_bandwidth 831*4882a593Smuzhiyun * Full receive Bandwidth. Values are defined in enum 832*4882a593Smuzhiyun * %RX_MSDU_START_RECV_*. 833*4882a593Smuzhiyun * 834*4882a593Smuzhiyun * reception_type 835*4882a593Smuzhiyun * Indicates what type of reception this is and defined in enum 836*4882a593Smuzhiyun * %RX_MSDU_START_RECEPTION_TYPE_*. 837*4882a593Smuzhiyun * 838*4882a593Smuzhiyun * mimo_ss_bitmap 839*4882a593Smuzhiyun * Field only valid when 840*4882a593Smuzhiyun * Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or 841*4882a593Smuzhiyun * RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO. 842*4882a593Smuzhiyun * 843*4882a593Smuzhiyun * Bitmap, with each bit indicating if the related spatial 844*4882a593Smuzhiyun * stream is used for this STA 845*4882a593Smuzhiyun * 846*4882a593Smuzhiyun * LSB related to SS 0 847*4882a593Smuzhiyun * 848*4882a593Smuzhiyun * 0 - spatial stream not used for this reception 849*4882a593Smuzhiyun * 1 - spatial stream used for this reception 850*4882a593Smuzhiyun * 851*4882a593Smuzhiyun * ppdu_start_timestamp 852*4882a593Smuzhiyun * Timestamp that indicates when the PPDU that contained this MPDU 853*4882a593Smuzhiyun * started on the medium. 854*4882a593Smuzhiyun * 855*4882a593Smuzhiyun * phy_meta_data 856*4882a593Smuzhiyun * SW programmed Meta data provided by the PHY. Can be used for SW 857*4882a593Smuzhiyun * to indicate the channel the device is on. 858*4882a593Smuzhiyun */ 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 861*4882a593Smuzhiyun #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun #define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0) 864*4882a593Smuzhiyun #define RX_MSDU_END_INFO1_CCE_SUPER_RULE GENMASK(13, 8) 865*4882a593Smuzhiyun #define RX_MSDU_END_INFO1_CCND_TRUNCATE BIT(14) 866*4882a593Smuzhiyun #define RX_MSDU_END_INFO1_CCND_CCE_DIS BIT(15) 867*4882a593Smuzhiyun #define RX_MSDU_END_INFO1_EXT_WAPI_PN GENMASK(31, 16) 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0) 870*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14) 871*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_LAST_MSDU BIT(15) 872*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16) 873*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17) 874*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18) 875*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT BIT(19) 876*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_FLOW_IDX_INVALID BIT(20) 877*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_WIFI_PARSER_ERR BIT(21) 878*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR BIT(22) 879*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_SA_IS_VALID BIT(23) 880*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_DA_IS_VALID BIT(24) 881*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_DA_IS_MCBC BIT(25) 882*4882a593Smuzhiyun #define RX_MSDU_END_INFO2_L3_HDR_PADDING GENMASK(27, 26) 883*4882a593Smuzhiyun 884*4882a593Smuzhiyun #define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0) 885*4882a593Smuzhiyun #define RX_MSDU_END_INFO3_LRO_ELIGIBLE BIT(9) 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun #define RX_MSDU_END_INFO4_DA_OFFSET GENMASK(5, 0) 888*4882a593Smuzhiyun #define RX_MSDU_END_INFO4_SA_OFFSET GENMASK(11, 6) 889*4882a593Smuzhiyun #define RX_MSDU_END_INFO4_DA_OFFSET_VALID BIT(12) 890*4882a593Smuzhiyun #define RX_MSDU_END_INFO4_SA_OFFSET_VALID BIT(13) 891*4882a593Smuzhiyun #define RX_MSDU_END_INFO4_L3_TYPE GENMASK(31, 16) 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun #define RX_MSDU_END_INFO5_MSDU_DROP BIT(0) 894*4882a593Smuzhiyun #define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1) 895*4882a593Smuzhiyun #define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6) 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun struct rx_msdu_end { 898*4882a593Smuzhiyun __le16 info0; 899*4882a593Smuzhiyun __le16 phy_ppdu_id; 900*4882a593Smuzhiyun __le16 ip_hdr_cksum; 901*4882a593Smuzhiyun __le16 tcp_udp_cksum; 902*4882a593Smuzhiyun __le32 info1; 903*4882a593Smuzhiyun __le32 ext_wapi_pn[2]; 904*4882a593Smuzhiyun __le32 info2; 905*4882a593Smuzhiyun __le32 ipv6_options_crc; 906*4882a593Smuzhiyun __le32 tcp_seq_num; 907*4882a593Smuzhiyun __le32 tcp_ack_num; 908*4882a593Smuzhiyun __le16 info3; 909*4882a593Smuzhiyun __le16 window_size; 910*4882a593Smuzhiyun __le32 info4; 911*4882a593Smuzhiyun __le32 rule_indication[2]; 912*4882a593Smuzhiyun __le16 sa_idx; 913*4882a593Smuzhiyun __le16 da_idx; 914*4882a593Smuzhiyun __le32 info5; 915*4882a593Smuzhiyun __le32 fse_metadata; 916*4882a593Smuzhiyun __le16 cce_metadata; 917*4882a593Smuzhiyun __le16 sa_sw_peer_id; 918*4882a593Smuzhiyun } __packed; 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun /* rx_msdu_end 921*4882a593Smuzhiyun * 922*4882a593Smuzhiyun * rxpcu_mpdu_filter_in_category 923*4882a593Smuzhiyun * Field indicates what the reason was that this mpdu frame 924*4882a593Smuzhiyun * was allowed to come into the receive path by rxpcu. Values 925*4882a593Smuzhiyun * are defined in enum %RX_DESC_RXPCU_FILTER_*. 926*4882a593Smuzhiyun * 927*4882a593Smuzhiyun * sw_frame_group_id 928*4882a593Smuzhiyun * SW processes frames based on certain classifications. Values 929*4882a593Smuzhiyun * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 930*4882a593Smuzhiyun * 931*4882a593Smuzhiyun * phy_ppdu_id 932*4882a593Smuzhiyun * A ppdu counter value that PHY increments for every PPDU 933*4882a593Smuzhiyun * received. The counter value wraps around. 934*4882a593Smuzhiyun * 935*4882a593Smuzhiyun * ip_hdr_cksum 936*4882a593Smuzhiyun * This can include the IP header checksum or the pseudo 937*4882a593Smuzhiyun * header checksum used by TCP/UDP checksum. 938*4882a593Smuzhiyun * 939*4882a593Smuzhiyun * tcp_udp_chksum 940*4882a593Smuzhiyun * The value of the computed TCP/UDP checksum. A mode bit 941*4882a593Smuzhiyun * selects whether this checksum is the full checksum or the 942*4882a593Smuzhiyun * partial checksum which does not include the pseudo header. 943*4882a593Smuzhiyun * 944*4882a593Smuzhiyun * key_id 945*4882a593Smuzhiyun * The key ID octet from the IV. Only valid when first_msdu is set. 946*4882a593Smuzhiyun * 947*4882a593Smuzhiyun * cce_super_rule 948*4882a593Smuzhiyun * Indicates the super filter rule. 949*4882a593Smuzhiyun * 950*4882a593Smuzhiyun * cce_classify_not_done_truncate 951*4882a593Smuzhiyun * Classification failed due to truncated frame. 952*4882a593Smuzhiyun * 953*4882a593Smuzhiyun * cce_classify_not_done_cce_dis 954*4882a593Smuzhiyun * Classification failed due to CCE global disable 955*4882a593Smuzhiyun * 956*4882a593Smuzhiyun * ext_wapi_pn* 957*4882a593Smuzhiyun * Extension PN (packet number) which is only used by WAPI. 958*4882a593Smuzhiyun * 959*4882a593Smuzhiyun * reported_mpdu_length 960*4882a593Smuzhiyun * MPDU length before decapsulation. Only valid when first_msdu is 961*4882a593Smuzhiyun * set. This field is taken directly from the length field of the 962*4882a593Smuzhiyun * A-MPDU delimiter or the preamble length field for non-A-MPDU 963*4882a593Smuzhiyun * frames. 964*4882a593Smuzhiyun * 965*4882a593Smuzhiyun * first_msdu 966*4882a593Smuzhiyun * Indicates the first MSDU of A-MSDU. If both first_msdu and 967*4882a593Smuzhiyun * last_msdu are set in the MSDU then this is a non-aggregated MSDU 968*4882a593Smuzhiyun * frame: normal MPDU. Interior MSDU in an A-MSDU shall have both 969*4882a593Smuzhiyun * first_mpdu and last_mpdu bits set to 0. 970*4882a593Smuzhiyun * 971*4882a593Smuzhiyun * last_msdu 972*4882a593Smuzhiyun * Indicates the last MSDU of the A-MSDU. MPDU end status is only 973*4882a593Smuzhiyun * valid when last_msdu is set. 974*4882a593Smuzhiyun * 975*4882a593Smuzhiyun * sa_idx_timeout 976*4882a593Smuzhiyun * Indicates an unsuccessful MAC source address search due to the 977*4882a593Smuzhiyun * expiring of the search timer. 978*4882a593Smuzhiyun * 979*4882a593Smuzhiyun * da_idx_timeout 980*4882a593Smuzhiyun * Indicates an unsuccessful MAC destination address search due to 981*4882a593Smuzhiyun * the expiring of the search timer. 982*4882a593Smuzhiyun * 983*4882a593Smuzhiyun * msdu_limit_error 984*4882a593Smuzhiyun * Indicates that the MSDU threshold was exceeded and thus all the 985*4882a593Smuzhiyun * rest of the MSDUs will not be scattered and will not be 986*4882a593Smuzhiyun * decapsulated but will be DMA'ed in RAW format as a single MSDU. 987*4882a593Smuzhiyun * 988*4882a593Smuzhiyun * flow_idx_timeout 989*4882a593Smuzhiyun * Indicates an unsuccessful flow search due to the expiring of 990*4882a593Smuzhiyun * the search timer. 991*4882a593Smuzhiyun * 992*4882a593Smuzhiyun * flow_idx_invalid 993*4882a593Smuzhiyun * flow id is not valid. 994*4882a593Smuzhiyun * 995*4882a593Smuzhiyun * amsdu_parser_error 996*4882a593Smuzhiyun * A-MSDU could not be properly de-agregated. 997*4882a593Smuzhiyun * 998*4882a593Smuzhiyun * sa_is_valid 999*4882a593Smuzhiyun * Indicates that OLE found a valid SA entry. 1000*4882a593Smuzhiyun * 1001*4882a593Smuzhiyun * da_is_valid 1002*4882a593Smuzhiyun * Indicates that OLE found a valid DA entry. 1003*4882a593Smuzhiyun * 1004*4882a593Smuzhiyun * da_is_mcbc 1005*4882a593Smuzhiyun * Field Only valid if da_is_valid is set. Indicates the DA address 1006*4882a593Smuzhiyun * was a Multicast of Broadcast address. 1007*4882a593Smuzhiyun * 1008*4882a593Smuzhiyun * l3_header_padding 1009*4882a593Smuzhiyun * Number of bytes padded to make sure that the L3 header will 1010*4882a593Smuzhiyun * always start of a Dword boundary. 1011*4882a593Smuzhiyun * 1012*4882a593Smuzhiyun * ipv6_options_crc 1013*4882a593Smuzhiyun * 32 bit CRC computed out of IP v6 extension headers. 1014*4882a593Smuzhiyun * 1015*4882a593Smuzhiyun * tcp_seq_number 1016*4882a593Smuzhiyun * TCP sequence number. 1017*4882a593Smuzhiyun * 1018*4882a593Smuzhiyun * tcp_ack_number 1019*4882a593Smuzhiyun * TCP acknowledge number. 1020*4882a593Smuzhiyun * 1021*4882a593Smuzhiyun * tcp_flag 1022*4882a593Smuzhiyun * TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}. 1023*4882a593Smuzhiyun * 1024*4882a593Smuzhiyun * lro_eligible 1025*4882a593Smuzhiyun * Computed out of TCP and IP fields to indicate that this 1026*4882a593Smuzhiyun * MSDU is eligible for LRO. 1027*4882a593Smuzhiyun * 1028*4882a593Smuzhiyun * window_size 1029*4882a593Smuzhiyun * TCP receive window size. 1030*4882a593Smuzhiyun * 1031*4882a593Smuzhiyun * da_offset 1032*4882a593Smuzhiyun * Offset into MSDU buffer for DA. 1033*4882a593Smuzhiyun * 1034*4882a593Smuzhiyun * sa_offset 1035*4882a593Smuzhiyun * Offset into MSDU buffer for SA. 1036*4882a593Smuzhiyun * 1037*4882a593Smuzhiyun * da_offset_valid 1038*4882a593Smuzhiyun * da_offset field is valid. This will be set to 0 in case 1039*4882a593Smuzhiyun * of a dynamic A-MSDU when DA is compressed. 1040*4882a593Smuzhiyun * 1041*4882a593Smuzhiyun * sa_offset_valid 1042*4882a593Smuzhiyun * sa_offset field is valid. This will be set to 0 in case 1043*4882a593Smuzhiyun * of a dynamic A-MSDU when SA is compressed. 1044*4882a593Smuzhiyun * 1045*4882a593Smuzhiyun * l3_type 1046*4882a593Smuzhiyun * The 16-bit type value indicating the type of L3 later 1047*4882a593Smuzhiyun * extracted from LLC/SNAP, set to zero if SNAP is not 1048*4882a593Smuzhiyun * available. 1049*4882a593Smuzhiyun * 1050*4882a593Smuzhiyun * rule_indication 1051*4882a593Smuzhiyun * Bitmap indicating which of rules have matched. 1052*4882a593Smuzhiyun * 1053*4882a593Smuzhiyun * sa_idx 1054*4882a593Smuzhiyun * The offset in the address table which matches MAC source address 1055*4882a593Smuzhiyun * 1056*4882a593Smuzhiyun * da_idx 1057*4882a593Smuzhiyun * The offset in the address table which matches MAC destination 1058*4882a593Smuzhiyun * address. 1059*4882a593Smuzhiyun * 1060*4882a593Smuzhiyun * msdu_drop 1061*4882a593Smuzhiyun * REO shall drop this MSDU and not forward it to any other ring. 1062*4882a593Smuzhiyun * 1063*4882a593Smuzhiyun * reo_destination_indication 1064*4882a593Smuzhiyun * The id of the reo exit ring where the msdu frame shall push 1065*4882a593Smuzhiyun * after (MPDU level) reordering has finished. Values are defined 1066*4882a593Smuzhiyun * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 1067*4882a593Smuzhiyun * 1068*4882a593Smuzhiyun * flow_idx 1069*4882a593Smuzhiyun * Flow table index. 1070*4882a593Smuzhiyun * 1071*4882a593Smuzhiyun * fse_metadata 1072*4882a593Smuzhiyun * FSE related meta data. 1073*4882a593Smuzhiyun * 1074*4882a593Smuzhiyun * cce_metadata 1075*4882a593Smuzhiyun * CCE related meta data. 1076*4882a593Smuzhiyun * 1077*4882a593Smuzhiyun * sa_sw_peer_id 1078*4882a593Smuzhiyun * sw_peer_id from the address search entry corresponding to the 1079*4882a593Smuzhiyun * source address of the MSDU. 1080*4882a593Smuzhiyun */ 1081*4882a593Smuzhiyun 1082*4882a593Smuzhiyun enum rx_mpdu_end_rxdma_dest_ring { 1083*4882a593Smuzhiyun RX_MPDU_END_RXDMA_DEST_RING_RELEASE, 1084*4882a593Smuzhiyun RX_MPDU_END_RXDMA_DEST_RING_FW, 1085*4882a593Smuzhiyun RX_MPDU_END_RXDMA_DEST_RING_SW, 1086*4882a593Smuzhiyun RX_MPDU_END_RXDMA_DEST_RING_REO, 1087*4882a593Smuzhiyun }; 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME BIT(11) 1090*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT BIT(12) 1091*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_OVERFLOW_ERR BIT(13) 1092*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_MPDU_LEN_ERR BIT(14) 1093*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_TKIP_MIC_ERR BIT(15) 1094*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_DECRYPT_ERR BIT(16) 1095*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR BIT(17) 1096*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_PN_FIELDS_VALID BIT(18) 1097*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_FCS_ERR BIT(19) 1098*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_MSDU_LEN_ERR BIT(20) 1099*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_RXDMA0_DEST_RING GENMASK(22, 21) 1100*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_RXDMA1_DEST_RING GENMASK(24, 23) 1101*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE GENMASK(27, 25) 1102*4882a593Smuzhiyun #define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD BIT(28) 1103*4882a593Smuzhiyun 1104*4882a593Smuzhiyun struct rx_mpdu_end { 1105*4882a593Smuzhiyun __le16 info0; 1106*4882a593Smuzhiyun __le16 phy_ppdu_id; 1107*4882a593Smuzhiyun __le32 info1; 1108*4882a593Smuzhiyun } __packed; 1109*4882a593Smuzhiyun 1110*4882a593Smuzhiyun /* rx_mpdu_end 1111*4882a593Smuzhiyun * 1112*4882a593Smuzhiyun * rxpcu_mpdu_filter_in_category 1113*4882a593Smuzhiyun * Field indicates what the reason was that this mpdu frame 1114*4882a593Smuzhiyun * was allowed to come into the receive path by rxpcu. Values 1115*4882a593Smuzhiyun * are defined in enum %RX_DESC_RXPCU_FILTER_*. 1116*4882a593Smuzhiyun * 1117*4882a593Smuzhiyun * sw_frame_group_id 1118*4882a593Smuzhiyun * SW processes frames based on certain classifications. Values 1119*4882a593Smuzhiyun * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 1120*4882a593Smuzhiyun * 1121*4882a593Smuzhiyun * phy_ppdu_id 1122*4882a593Smuzhiyun * A ppdu counter value that PHY increments for every PPDU 1123*4882a593Smuzhiyun * received. The counter value wraps around. 1124*4882a593Smuzhiyun * 1125*4882a593Smuzhiyun * unsup_ktype_short_frame 1126*4882a593Smuzhiyun * This bit will be '1' when WEP or TKIP or WAPI key type is 1127*4882a593Smuzhiyun * received for 11ah short frame. Crypto will bypass the received 1128*4882a593Smuzhiyun * packet without decryption to RxOLE after setting this bit. 1129*4882a593Smuzhiyun * 1130*4882a593Smuzhiyun * rx_in_tx_decrypt_byp 1131*4882a593Smuzhiyun * Indicates that RX packet is not decrypted as Crypto is 1132*4882a593Smuzhiyun * busy with TX packet processing. 1133*4882a593Smuzhiyun * 1134*4882a593Smuzhiyun * overflow_err 1135*4882a593Smuzhiyun * RXPCU Receive FIFO ran out of space to receive the full MPDU. 1136*4882a593Smuzhiyun * Therefore this MPDU is terminated early and is thus corrupted. 1137*4882a593Smuzhiyun * 1138*4882a593Smuzhiyun * This MPDU will not be ACKed. 1139*4882a593Smuzhiyun * 1140*4882a593Smuzhiyun * RXPCU might still be able to correctly receive the following 1141*4882a593Smuzhiyun * MPDUs in the PPDU if enough fifo space became available in time. 1142*4882a593Smuzhiyun * 1143*4882a593Smuzhiyun * mpdu_length_err 1144*4882a593Smuzhiyun * Set by RXPCU if the expected MPDU length does not correspond 1145*4882a593Smuzhiyun * with the actually received number of bytes in the MPDU. 1146*4882a593Smuzhiyun * 1147*4882a593Smuzhiyun * tkip_mic_err 1148*4882a593Smuzhiyun * Set by Rx crypto when crypto detected a TKIP MIC error for 1149*4882a593Smuzhiyun * this MPDU. 1150*4882a593Smuzhiyun * 1151*4882a593Smuzhiyun * decrypt_err 1152*4882a593Smuzhiyun * Set by RX CRYPTO when CRYPTO detected a decrypt error for this 1153*4882a593Smuzhiyun * MPDU or CRYPTO received an encrypted frame, but did not get a 1154*4882a593Smuzhiyun * valid corresponding key id in the peer entry. 1155*4882a593Smuzhiyun * 1156*4882a593Smuzhiyun * unencrypted_frame_err 1157*4882a593Smuzhiyun * Set by RX CRYPTO when CRYPTO detected an unencrypted frame while 1158*4882a593Smuzhiyun * in the peer entry field 'All_frames_shall_be_encrypted' is set. 1159*4882a593Smuzhiyun * 1160*4882a593Smuzhiyun * pn_fields_contain_valid_info 1161*4882a593Smuzhiyun * Set by RX CRYPTO to indicate that there is a valid PN field 1162*4882a593Smuzhiyun * present in this MPDU. 1163*4882a593Smuzhiyun * 1164*4882a593Smuzhiyun * fcs_err 1165*4882a593Smuzhiyun * Set by RXPCU when there is an FCS error detected for this MPDU. 1166*4882a593Smuzhiyun * 1167*4882a593Smuzhiyun * msdu_length_err 1168*4882a593Smuzhiyun * Set by RXOLE when there is an msdu length error detected 1169*4882a593Smuzhiyun * in at least 1 of the MSDUs embedded within the MPDU. 1170*4882a593Smuzhiyun * 1171*4882a593Smuzhiyun * rxdma0_destination_ring 1172*4882a593Smuzhiyun * rxdma1_destination_ring 1173*4882a593Smuzhiyun * The ring to which RXDMA0/1 shall push the frame, assuming 1174*4882a593Smuzhiyun * no MPDU level errors are detected. In case of MPDU level 1175*4882a593Smuzhiyun * errors, RXDMA0/1 might change the RXDMA0/1 destination. Values 1176*4882a593Smuzhiyun * are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*. 1177*4882a593Smuzhiyun * 1178*4882a593Smuzhiyun * decrypt_status_code 1179*4882a593Smuzhiyun * Field provides insight into the decryption performed. Values 1180*4882a593Smuzhiyun * are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*. 1181*4882a593Smuzhiyun * 1182*4882a593Smuzhiyun * rx_bitmap_not_updated 1183*4882a593Smuzhiyun * Frame is received, but RXPCU could not update the receive bitmap 1184*4882a593Smuzhiyun * due to (temporary) fifo constraints. 1185*4882a593Smuzhiyun */ 1186*4882a593Smuzhiyun 1187*4882a593Smuzhiyun /* Padding bytes to avoid TLV's spanning across 128 byte boundary */ 1188*4882a593Smuzhiyun #define HAL_RX_DESC_PADDING0_BYTES 4 1189*4882a593Smuzhiyun #define HAL_RX_DESC_PADDING1_BYTES 16 1190*4882a593Smuzhiyun 1191*4882a593Smuzhiyun #define HAL_RX_DESC_HDR_STATUS_LEN 120 1192*4882a593Smuzhiyun 1193*4882a593Smuzhiyun struct hal_rx_desc { 1194*4882a593Smuzhiyun __le32 msdu_end_tag; 1195*4882a593Smuzhiyun struct rx_msdu_end msdu_end; 1196*4882a593Smuzhiyun __le32 rx_attn_tag; 1197*4882a593Smuzhiyun struct rx_attention attention; 1198*4882a593Smuzhiyun __le32 msdu_start_tag; 1199*4882a593Smuzhiyun struct rx_msdu_start msdu_start; 1200*4882a593Smuzhiyun u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 1201*4882a593Smuzhiyun __le32 mpdu_start_tag; 1202*4882a593Smuzhiyun struct rx_mpdu_start mpdu_start; 1203*4882a593Smuzhiyun __le32 mpdu_end_tag; 1204*4882a593Smuzhiyun struct rx_mpdu_end mpdu_end; 1205*4882a593Smuzhiyun u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 1206*4882a593Smuzhiyun __le32 hdr_status_tag; 1207*4882a593Smuzhiyun __le32 phy_ppdu_id; 1208*4882a593Smuzhiyun u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 1209*4882a593Smuzhiyun u8 msdu_payload[0]; 1210*4882a593Smuzhiyun } __packed; 1211*4882a593Smuzhiyun 1212*4882a593Smuzhiyun #define HAL_RX_RU_ALLOC_TYPE_MAX 6 1213*4882a593Smuzhiyun #define RU_26 1 1214*4882a593Smuzhiyun #define RU_52 2 1215*4882a593Smuzhiyun #define RU_106 4 1216*4882a593Smuzhiyun #define RU_242 9 1217*4882a593Smuzhiyun #define RU_484 18 1218*4882a593Smuzhiyun #define RU_996 37 1219*4882a593Smuzhiyun 1220*4882a593Smuzhiyun #endif /* ATH11K_RX_DESC_H */ 1221