1*4882a593Smuzhiyun // SPDX-License-Identifier: BSD-3-Clause-Clear
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include "core.h"
6*4882a593Smuzhiyun #include "debug.h"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /* World regdom to be used in case default regd from fw is unavailable */
9*4882a593Smuzhiyun #define ATH11K_2GHZ_CH01_11 REG_RULE(2412 - 10, 2462 + 10, 40, 0, 20, 0)
10*4882a593Smuzhiyun #define ATH11K_5GHZ_5150_5350 REG_RULE(5150 - 10, 5350 + 10, 80, 0, 30,\
11*4882a593Smuzhiyun NL80211_RRF_NO_IR)
12*4882a593Smuzhiyun #define ATH11K_5GHZ_5725_5850 REG_RULE(5725 - 10, 5850 + 10, 80, 0, 30,\
13*4882a593Smuzhiyun NL80211_RRF_NO_IR)
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define ETSI_WEATHER_RADAR_BAND_LOW 5590
16*4882a593Smuzhiyun #define ETSI_WEATHER_RADAR_BAND_HIGH 5650
17*4882a593Smuzhiyun #define ETSI_WEATHER_RADAR_BAND_CAC_TIMEOUT 600000
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static const struct ieee80211_regdomain ath11k_world_regd = {
20*4882a593Smuzhiyun .n_reg_rules = 3,
21*4882a593Smuzhiyun .alpha2 = "00",
22*4882a593Smuzhiyun .reg_rules = {
23*4882a593Smuzhiyun ATH11K_2GHZ_CH01_11,
24*4882a593Smuzhiyun ATH11K_5GHZ_5150_5350,
25*4882a593Smuzhiyun ATH11K_5GHZ_5725_5850,
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
ath11k_regdom_changes(struct ath11k * ar,char * alpha2)29*4882a593Smuzhiyun static bool ath11k_regdom_changes(struct ath11k *ar, char *alpha2)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun const struct ieee80211_regdomain *regd;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun regd = rcu_dereference_rtnl(ar->hw->wiphy->regd);
34*4882a593Smuzhiyun /* This can happen during wiphy registration where the previous
35*4882a593Smuzhiyun * user request is received before we update the regd received
36*4882a593Smuzhiyun * from firmware.
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun if (!regd)
39*4882a593Smuzhiyun return true;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return memcmp(regd->alpha2, alpha2, 2) != 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static void
ath11k_reg_notifier(struct wiphy * wiphy,struct regulatory_request * request)45*4882a593Smuzhiyun ath11k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
48*4882a593Smuzhiyun struct wmi_init_country_params init_country_param;
49*4882a593Smuzhiyun struct ath11k *ar = hw->priv;
50*4882a593Smuzhiyun int ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun ath11k_dbg(ar->ab, ATH11K_DBG_REG,
53*4882a593Smuzhiyun "Regulatory Notification received for %s\n", wiphy_name(wiphy));
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Currently supporting only General User Hints. Cell base user
56*4882a593Smuzhiyun * hints to be handled later.
57*4882a593Smuzhiyun * Hints from other sources like Core, Beacons are not expected for
58*4882a593Smuzhiyun * self managed wiphy's
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun if (!(request->initiator == NL80211_REGDOM_SET_BY_USER &&
61*4882a593Smuzhiyun request->user_reg_hint_type == NL80211_USER_REG_HINT_USER)) {
62*4882a593Smuzhiyun ath11k_warn(ar->ab, "Unexpected Regulatory event for this wiphy\n");
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS)) {
67*4882a593Smuzhiyun ath11k_dbg(ar->ab, ATH11K_DBG_REG,
68*4882a593Smuzhiyun "Country Setting is not allowed\n");
69*4882a593Smuzhiyun return;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (!ath11k_regdom_changes(ar, request->alpha2)) {
73*4882a593Smuzhiyun ath11k_dbg(ar->ab, ATH11K_DBG_REG, "Country is already set\n");
74*4882a593Smuzhiyun return;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Set the country code to the firmware and wait for
78*4882a593Smuzhiyun * the WMI_REG_CHAN_LIST_CC EVENT for updating the
79*4882a593Smuzhiyun * reg info
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun init_country_param.flags = ALPHA_IS_SET;
82*4882a593Smuzhiyun memcpy(&init_country_param.cc_info.alpha2, request->alpha2, 2);
83*4882a593Smuzhiyun init_country_param.cc_info.alpha2[2] = 0;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun ret = ath11k_wmi_send_init_country_cmd(ar, init_country_param);
86*4882a593Smuzhiyun if (ret)
87*4882a593Smuzhiyun ath11k_warn(ar->ab,
88*4882a593Smuzhiyun "INIT Country code set to fw failed : %d\n", ret);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
ath11k_reg_update_chan_list(struct ath11k * ar)91*4882a593Smuzhiyun int ath11k_reg_update_chan_list(struct ath11k *ar)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct ieee80211_supported_band **bands;
94*4882a593Smuzhiyun struct scan_chan_list_params *params;
95*4882a593Smuzhiyun struct ieee80211_channel *channel;
96*4882a593Smuzhiyun struct ieee80211_hw *hw = ar->hw;
97*4882a593Smuzhiyun struct channel_param *ch;
98*4882a593Smuzhiyun enum nl80211_band band;
99*4882a593Smuzhiyun int num_channels = 0;
100*4882a593Smuzhiyun int params_len;
101*4882a593Smuzhiyun int i, ret;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun bands = hw->wiphy->bands;
104*4882a593Smuzhiyun for (band = 0; band < NUM_NL80211_BANDS; band++) {
105*4882a593Smuzhiyun if (!bands[band])
106*4882a593Smuzhiyun continue;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun for (i = 0; i < bands[band]->n_channels; i++) {
109*4882a593Smuzhiyun if (bands[band]->channels[i].flags &
110*4882a593Smuzhiyun IEEE80211_CHAN_DISABLED)
111*4882a593Smuzhiyun continue;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun num_channels++;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun if (WARN_ON(!num_channels))
118*4882a593Smuzhiyun return -EINVAL;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun params_len = sizeof(struct scan_chan_list_params) +
121*4882a593Smuzhiyun num_channels * sizeof(struct channel_param);
122*4882a593Smuzhiyun params = kzalloc(params_len, GFP_KERNEL);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (!params)
125*4882a593Smuzhiyun return -ENOMEM;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun params->pdev_id = ar->pdev->pdev_id;
128*4882a593Smuzhiyun params->nallchans = num_channels;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun ch = params->ch_param;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun for (band = 0; band < NUM_NL80211_BANDS; band++) {
133*4882a593Smuzhiyun if (!bands[band])
134*4882a593Smuzhiyun continue;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun for (i = 0; i < bands[band]->n_channels; i++) {
137*4882a593Smuzhiyun channel = &bands[band]->channels[i];
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (channel->flags & IEEE80211_CHAN_DISABLED)
140*4882a593Smuzhiyun continue;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* TODO: Set to true/false based on some condition? */
143*4882a593Smuzhiyun ch->allow_ht = true;
144*4882a593Smuzhiyun ch->allow_vht = true;
145*4882a593Smuzhiyun ch->allow_he = true;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun ch->dfs_set =
148*4882a593Smuzhiyun !!(channel->flags & IEEE80211_CHAN_RADAR);
149*4882a593Smuzhiyun ch->is_chan_passive = !!(channel->flags &
150*4882a593Smuzhiyun IEEE80211_CHAN_NO_IR);
151*4882a593Smuzhiyun ch->is_chan_passive |= ch->dfs_set;
152*4882a593Smuzhiyun ch->mhz = channel->center_freq;
153*4882a593Smuzhiyun ch->cfreq1 = channel->center_freq;
154*4882a593Smuzhiyun ch->minpower = 0;
155*4882a593Smuzhiyun ch->maxpower = channel->max_power * 2;
156*4882a593Smuzhiyun ch->maxregpower = channel->max_reg_power * 2;
157*4882a593Smuzhiyun ch->antennamax = channel->max_antenna_gain * 2;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* TODO: Use appropriate phymodes */
160*4882a593Smuzhiyun if (channel->band == NL80211_BAND_2GHZ)
161*4882a593Smuzhiyun ch->phy_mode = MODE_11G;
162*4882a593Smuzhiyun else
163*4882a593Smuzhiyun ch->phy_mode = MODE_11A;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun if (channel->band == NL80211_BAND_6GHZ &&
166*4882a593Smuzhiyun cfg80211_channel_is_psc(channel))
167*4882a593Smuzhiyun ch->psc_channel = true;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
170*4882a593Smuzhiyun "mac channel [%d/%d] freq %d maxpower %d regpower %d antenna %d mode %d\n",
171*4882a593Smuzhiyun i, params->nallchans,
172*4882a593Smuzhiyun ch->mhz, ch->maxpower, ch->maxregpower,
173*4882a593Smuzhiyun ch->antennamax, ch->phy_mode);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ch++;
176*4882a593Smuzhiyun /* TODO: use quarrter/half rate, cfreq12, dfs_cfreq2
177*4882a593Smuzhiyun * set_agile, reg_class_idx
178*4882a593Smuzhiyun */
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun ret = ath11k_wmi_send_scan_chan_list_cmd(ar, params);
183*4882a593Smuzhiyun kfree(params);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return ret;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
ath11k_copy_regd(struct ieee80211_regdomain * regd_orig,struct ieee80211_regdomain * regd_copy)188*4882a593Smuzhiyun static void ath11k_copy_regd(struct ieee80211_regdomain *regd_orig,
189*4882a593Smuzhiyun struct ieee80211_regdomain *regd_copy)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun u8 i;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* The caller should have checked error conditions */
194*4882a593Smuzhiyun memcpy(regd_copy, regd_orig, sizeof(*regd_orig));
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun for (i = 0; i < regd_orig->n_reg_rules; i++)
197*4882a593Smuzhiyun memcpy(®d_copy->reg_rules[i], ®d_orig->reg_rules[i],
198*4882a593Smuzhiyun sizeof(struct ieee80211_reg_rule));
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
ath11k_regd_update(struct ath11k * ar)201*4882a593Smuzhiyun int ath11k_regd_update(struct ath11k *ar)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun struct ieee80211_regdomain *regd, *regd_copy = NULL;
204*4882a593Smuzhiyun int ret, regd_len, pdev_id;
205*4882a593Smuzhiyun struct ath11k_base *ab;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun ab = ar->ab;
208*4882a593Smuzhiyun pdev_id = ar->pdev_idx;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun spin_lock_bh(&ab->base_lock);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* Prefer the latest regd update over default if it's available */
213*4882a593Smuzhiyun if (ab->new_regd[pdev_id]) {
214*4882a593Smuzhiyun regd = ab->new_regd[pdev_id];
215*4882a593Smuzhiyun } else {
216*4882a593Smuzhiyun /* Apply the regd received during init through
217*4882a593Smuzhiyun * WMI_REG_CHAN_LIST_CC event. In case of failure to
218*4882a593Smuzhiyun * receive the regd, initialize with a default world
219*4882a593Smuzhiyun * regulatory.
220*4882a593Smuzhiyun */
221*4882a593Smuzhiyun if (ab->default_regd[pdev_id]) {
222*4882a593Smuzhiyun regd = ab->default_regd[pdev_id];
223*4882a593Smuzhiyun } else {
224*4882a593Smuzhiyun ath11k_warn(ab,
225*4882a593Smuzhiyun "failed to receive default regd during init\n");
226*4882a593Smuzhiyun regd = (struct ieee80211_regdomain *)&ath11k_world_regd;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (!regd) {
231*4882a593Smuzhiyun ret = -EINVAL;
232*4882a593Smuzhiyun spin_unlock_bh(&ab->base_lock);
233*4882a593Smuzhiyun goto err;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun regd_len = sizeof(*regd) + (regd->n_reg_rules *
237*4882a593Smuzhiyun sizeof(struct ieee80211_reg_rule));
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun regd_copy = kzalloc(regd_len, GFP_ATOMIC);
240*4882a593Smuzhiyun if (regd_copy)
241*4882a593Smuzhiyun ath11k_copy_regd(regd, regd_copy);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun spin_unlock_bh(&ab->base_lock);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (!regd_copy) {
246*4882a593Smuzhiyun ret = -ENOMEM;
247*4882a593Smuzhiyun goto err;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun rtnl_lock();
251*4882a593Smuzhiyun ret = regulatory_set_wiphy_regd_sync_rtnl(ar->hw->wiphy, regd_copy);
252*4882a593Smuzhiyun rtnl_unlock();
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun kfree(regd_copy);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun if (ret)
257*4882a593Smuzhiyun goto err;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (ar->state == ATH11K_STATE_ON) {
260*4882a593Smuzhiyun ret = ath11k_reg_update_chan_list(ar);
261*4882a593Smuzhiyun if (ret)
262*4882a593Smuzhiyun goto err;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return 0;
266*4882a593Smuzhiyun err:
267*4882a593Smuzhiyun ath11k_warn(ab, "failed to perform regd update : %d\n", ret);
268*4882a593Smuzhiyun return ret;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static enum nl80211_dfs_regions
ath11k_map_fw_dfs_region(enum ath11k_dfs_region dfs_region)272*4882a593Smuzhiyun ath11k_map_fw_dfs_region(enum ath11k_dfs_region dfs_region)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun switch (dfs_region) {
275*4882a593Smuzhiyun case ATH11K_DFS_REG_FCC:
276*4882a593Smuzhiyun case ATH11K_DFS_REG_CN:
277*4882a593Smuzhiyun return NL80211_DFS_FCC;
278*4882a593Smuzhiyun case ATH11K_DFS_REG_ETSI:
279*4882a593Smuzhiyun case ATH11K_DFS_REG_KR:
280*4882a593Smuzhiyun return NL80211_DFS_ETSI;
281*4882a593Smuzhiyun case ATH11K_DFS_REG_MKK:
282*4882a593Smuzhiyun return NL80211_DFS_JP;
283*4882a593Smuzhiyun default:
284*4882a593Smuzhiyun return NL80211_DFS_UNSET;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
ath11k_map_fw_reg_flags(u16 reg_flags)288*4882a593Smuzhiyun static u32 ath11k_map_fw_reg_flags(u16 reg_flags)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun u32 flags = 0;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_NO_IR)
293*4882a593Smuzhiyun flags = NL80211_RRF_NO_IR;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_RADAR)
296*4882a593Smuzhiyun flags |= NL80211_RRF_DFS;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_NO_OFDM)
299*4882a593Smuzhiyun flags |= NL80211_RRF_NO_OFDM;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_INDOOR_ONLY)
302*4882a593Smuzhiyun flags |= NL80211_RRF_NO_OUTDOOR;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_NO_HT40)
305*4882a593Smuzhiyun flags |= NL80211_RRF_NO_HT40;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_NO_80MHZ)
308*4882a593Smuzhiyun flags |= NL80211_RRF_NO_80MHZ;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (reg_flags & REGULATORY_CHAN_NO_160MHZ)
311*4882a593Smuzhiyun flags |= NL80211_RRF_NO_160MHZ;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun return flags;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun static bool
ath11k_reg_can_intersect(struct ieee80211_reg_rule * rule1,struct ieee80211_reg_rule * rule2)317*4882a593Smuzhiyun ath11k_reg_can_intersect(struct ieee80211_reg_rule *rule1,
318*4882a593Smuzhiyun struct ieee80211_reg_rule *rule2)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun u32 start_freq1, end_freq1;
321*4882a593Smuzhiyun u32 start_freq2, end_freq2;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun start_freq1 = rule1->freq_range.start_freq_khz;
324*4882a593Smuzhiyun start_freq2 = rule2->freq_range.start_freq_khz;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun end_freq1 = rule1->freq_range.end_freq_khz;
327*4882a593Smuzhiyun end_freq2 = rule2->freq_range.end_freq_khz;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if ((start_freq1 >= start_freq2 &&
330*4882a593Smuzhiyun start_freq1 < end_freq2) ||
331*4882a593Smuzhiyun (start_freq2 > start_freq1 &&
332*4882a593Smuzhiyun start_freq2 < end_freq1))
333*4882a593Smuzhiyun return true;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /* TODO: Should we restrict intersection feasibility
336*4882a593Smuzhiyun * based on min bandwidth of the intersected region also,
337*4882a593Smuzhiyun * say the intersected rule should have a min bandwidth
338*4882a593Smuzhiyun * of 20MHz?
339*4882a593Smuzhiyun */
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return false;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
ath11k_reg_intersect_rules(struct ieee80211_reg_rule * rule1,struct ieee80211_reg_rule * rule2,struct ieee80211_reg_rule * new_rule)344*4882a593Smuzhiyun static void ath11k_reg_intersect_rules(struct ieee80211_reg_rule *rule1,
345*4882a593Smuzhiyun struct ieee80211_reg_rule *rule2,
346*4882a593Smuzhiyun struct ieee80211_reg_rule *new_rule)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun u32 start_freq1, end_freq1;
349*4882a593Smuzhiyun u32 start_freq2, end_freq2;
350*4882a593Smuzhiyun u32 freq_diff, max_bw;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun start_freq1 = rule1->freq_range.start_freq_khz;
353*4882a593Smuzhiyun start_freq2 = rule2->freq_range.start_freq_khz;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun end_freq1 = rule1->freq_range.end_freq_khz;
356*4882a593Smuzhiyun end_freq2 = rule2->freq_range.end_freq_khz;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun new_rule->freq_range.start_freq_khz = max_t(u32, start_freq1,
359*4882a593Smuzhiyun start_freq2);
360*4882a593Smuzhiyun new_rule->freq_range.end_freq_khz = min_t(u32, end_freq1, end_freq2);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun freq_diff = new_rule->freq_range.end_freq_khz -
363*4882a593Smuzhiyun new_rule->freq_range.start_freq_khz;
364*4882a593Smuzhiyun max_bw = min_t(u32, rule1->freq_range.max_bandwidth_khz,
365*4882a593Smuzhiyun rule2->freq_range.max_bandwidth_khz);
366*4882a593Smuzhiyun new_rule->freq_range.max_bandwidth_khz = min_t(u32, max_bw, freq_diff);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun new_rule->power_rule.max_antenna_gain =
369*4882a593Smuzhiyun min_t(u32, rule1->power_rule.max_antenna_gain,
370*4882a593Smuzhiyun rule2->power_rule.max_antenna_gain);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun new_rule->power_rule.max_eirp = min_t(u32, rule1->power_rule.max_eirp,
373*4882a593Smuzhiyun rule2->power_rule.max_eirp);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun /* Use the flags of both the rules */
376*4882a593Smuzhiyun new_rule->flags = rule1->flags | rule2->flags;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* To be safe, lts use the max cac timeout of both rules */
379*4882a593Smuzhiyun new_rule->dfs_cac_ms = max_t(u32, rule1->dfs_cac_ms,
380*4882a593Smuzhiyun rule2->dfs_cac_ms);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun static struct ieee80211_regdomain *
ath11k_regd_intersect(struct ieee80211_regdomain * default_regd,struct ieee80211_regdomain * curr_regd)384*4882a593Smuzhiyun ath11k_regd_intersect(struct ieee80211_regdomain *default_regd,
385*4882a593Smuzhiyun struct ieee80211_regdomain *curr_regd)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun u8 num_old_regd_rules, num_curr_regd_rules, num_new_regd_rules;
388*4882a593Smuzhiyun struct ieee80211_reg_rule *old_rule, *curr_rule, *new_rule;
389*4882a593Smuzhiyun struct ieee80211_regdomain *new_regd = NULL;
390*4882a593Smuzhiyun u8 i, j, k;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun num_old_regd_rules = default_regd->n_reg_rules;
393*4882a593Smuzhiyun num_curr_regd_rules = curr_regd->n_reg_rules;
394*4882a593Smuzhiyun num_new_regd_rules = 0;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun /* Find the number of intersecting rules to allocate new regd memory */
397*4882a593Smuzhiyun for (i = 0; i < num_old_regd_rules; i++) {
398*4882a593Smuzhiyun old_rule = default_regd->reg_rules + i;
399*4882a593Smuzhiyun for (j = 0; j < num_curr_regd_rules; j++) {
400*4882a593Smuzhiyun curr_rule = curr_regd->reg_rules + j;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (ath11k_reg_can_intersect(old_rule, curr_rule))
403*4882a593Smuzhiyun num_new_regd_rules++;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (!num_new_regd_rules)
408*4882a593Smuzhiyun return NULL;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun new_regd = kzalloc(sizeof(*new_regd) + (num_new_regd_rules *
411*4882a593Smuzhiyun sizeof(struct ieee80211_reg_rule)),
412*4882a593Smuzhiyun GFP_ATOMIC);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun if (!new_regd)
415*4882a593Smuzhiyun return NULL;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* We set the new country and dfs region directly and only trim
418*4882a593Smuzhiyun * the freq, power, antenna gain by intersecting with the
419*4882a593Smuzhiyun * default regdomain. Also MAX of the dfs cac timeout is selected.
420*4882a593Smuzhiyun */
421*4882a593Smuzhiyun new_regd->n_reg_rules = num_new_regd_rules;
422*4882a593Smuzhiyun memcpy(new_regd->alpha2, curr_regd->alpha2, sizeof(new_regd->alpha2));
423*4882a593Smuzhiyun new_regd->dfs_region = curr_regd->dfs_region;
424*4882a593Smuzhiyun new_rule = new_regd->reg_rules;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun for (i = 0, k = 0; i < num_old_regd_rules; i++) {
427*4882a593Smuzhiyun old_rule = default_regd->reg_rules + i;
428*4882a593Smuzhiyun for (j = 0; j < num_curr_regd_rules; j++) {
429*4882a593Smuzhiyun curr_rule = curr_regd->reg_rules + j;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun if (ath11k_reg_can_intersect(old_rule, curr_rule))
432*4882a593Smuzhiyun ath11k_reg_intersect_rules(old_rule, curr_rule,
433*4882a593Smuzhiyun (new_rule + k++));
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun return new_regd;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun static const char *
ath11k_reg_get_regdom_str(enum nl80211_dfs_regions dfs_region)440*4882a593Smuzhiyun ath11k_reg_get_regdom_str(enum nl80211_dfs_regions dfs_region)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun switch (dfs_region) {
443*4882a593Smuzhiyun case NL80211_DFS_FCC:
444*4882a593Smuzhiyun return "FCC";
445*4882a593Smuzhiyun case NL80211_DFS_ETSI:
446*4882a593Smuzhiyun return "ETSI";
447*4882a593Smuzhiyun case NL80211_DFS_JP:
448*4882a593Smuzhiyun return "JP";
449*4882a593Smuzhiyun default:
450*4882a593Smuzhiyun return "UNSET";
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun static u16
ath11k_reg_adjust_bw(u16 start_freq,u16 end_freq,u16 max_bw)455*4882a593Smuzhiyun ath11k_reg_adjust_bw(u16 start_freq, u16 end_freq, u16 max_bw)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun u16 bw;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun if (end_freq <= start_freq)
460*4882a593Smuzhiyun return 0;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun bw = end_freq - start_freq;
463*4882a593Smuzhiyun bw = min_t(u16, bw, max_bw);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun if (bw >= 80 && bw < 160)
466*4882a593Smuzhiyun bw = 80;
467*4882a593Smuzhiyun else if (bw >= 40 && bw < 80)
468*4882a593Smuzhiyun bw = 40;
469*4882a593Smuzhiyun else if (bw >= 20 && bw < 40)
470*4882a593Smuzhiyun bw = 20;
471*4882a593Smuzhiyun else
472*4882a593Smuzhiyun bw = 0;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun return bw;
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun static void
ath11k_reg_update_rule(struct ieee80211_reg_rule * reg_rule,u32 start_freq,u32 end_freq,u32 bw,u32 ant_gain,u32 reg_pwr,u32 reg_flags)478*4882a593Smuzhiyun ath11k_reg_update_rule(struct ieee80211_reg_rule *reg_rule, u32 start_freq,
479*4882a593Smuzhiyun u32 end_freq, u32 bw, u32 ant_gain, u32 reg_pwr,
480*4882a593Smuzhiyun u32 reg_flags)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun reg_rule->freq_range.start_freq_khz = MHZ_TO_KHZ(start_freq);
483*4882a593Smuzhiyun reg_rule->freq_range.end_freq_khz = MHZ_TO_KHZ(end_freq);
484*4882a593Smuzhiyun reg_rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw);
485*4882a593Smuzhiyun reg_rule->power_rule.max_antenna_gain = DBI_TO_MBI(ant_gain);
486*4882a593Smuzhiyun reg_rule->power_rule.max_eirp = DBM_TO_MBM(reg_pwr);
487*4882a593Smuzhiyun reg_rule->flags = reg_flags;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun static void
ath11k_reg_update_weather_radar_band(struct ath11k_base * ab,struct ieee80211_regdomain * regd,struct cur_reg_rule * reg_rule,u8 * rule_idx,u32 flags,u16 max_bw)491*4882a593Smuzhiyun ath11k_reg_update_weather_radar_band(struct ath11k_base *ab,
492*4882a593Smuzhiyun struct ieee80211_regdomain *regd,
493*4882a593Smuzhiyun struct cur_reg_rule *reg_rule,
494*4882a593Smuzhiyun u8 *rule_idx, u32 flags, u16 max_bw)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun u32 start_freq;
497*4882a593Smuzhiyun u32 end_freq;
498*4882a593Smuzhiyun u16 bw;
499*4882a593Smuzhiyun u8 i;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun i = *rule_idx;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /* there might be situations when even the input rule must be dropped */
504*4882a593Smuzhiyun i--;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* frequencies below weather radar */
507*4882a593Smuzhiyun bw = ath11k_reg_adjust_bw(reg_rule->start_freq,
508*4882a593Smuzhiyun ETSI_WEATHER_RADAR_BAND_LOW, max_bw);
509*4882a593Smuzhiyun if (bw > 0) {
510*4882a593Smuzhiyun i++;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun ath11k_reg_update_rule(regd->reg_rules + i,
513*4882a593Smuzhiyun reg_rule->start_freq,
514*4882a593Smuzhiyun ETSI_WEATHER_RADAR_BAND_LOW, bw,
515*4882a593Smuzhiyun reg_rule->ant_gain, reg_rule->reg_power,
516*4882a593Smuzhiyun flags);
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun ath11k_dbg(ab, ATH11K_DBG_REG,
519*4882a593Smuzhiyun "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
520*4882a593Smuzhiyun i + 1, reg_rule->start_freq,
521*4882a593Smuzhiyun ETSI_WEATHER_RADAR_BAND_LOW, bw, reg_rule->ant_gain,
522*4882a593Smuzhiyun reg_rule->reg_power, regd->reg_rules[i].dfs_cac_ms,
523*4882a593Smuzhiyun flags);
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /* weather radar frequencies */
527*4882a593Smuzhiyun start_freq = max_t(u32, reg_rule->start_freq,
528*4882a593Smuzhiyun ETSI_WEATHER_RADAR_BAND_LOW);
529*4882a593Smuzhiyun end_freq = min_t(u32, reg_rule->end_freq, ETSI_WEATHER_RADAR_BAND_HIGH);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun bw = ath11k_reg_adjust_bw(start_freq, end_freq, max_bw);
532*4882a593Smuzhiyun if (bw > 0) {
533*4882a593Smuzhiyun i++;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun ath11k_reg_update_rule(regd->reg_rules + i, start_freq,
536*4882a593Smuzhiyun end_freq, bw, reg_rule->ant_gain,
537*4882a593Smuzhiyun reg_rule->reg_power, flags);
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun regd->reg_rules[i].dfs_cac_ms = ETSI_WEATHER_RADAR_BAND_CAC_TIMEOUT;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun ath11k_dbg(ab, ATH11K_DBG_REG,
542*4882a593Smuzhiyun "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
543*4882a593Smuzhiyun i + 1, start_freq, end_freq, bw,
544*4882a593Smuzhiyun reg_rule->ant_gain, reg_rule->reg_power,
545*4882a593Smuzhiyun regd->reg_rules[i].dfs_cac_ms, flags);
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun /* frequencies above weather radar */
549*4882a593Smuzhiyun bw = ath11k_reg_adjust_bw(ETSI_WEATHER_RADAR_BAND_HIGH,
550*4882a593Smuzhiyun reg_rule->end_freq, max_bw);
551*4882a593Smuzhiyun if (bw > 0) {
552*4882a593Smuzhiyun i++;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun ath11k_reg_update_rule(regd->reg_rules + i,
555*4882a593Smuzhiyun ETSI_WEATHER_RADAR_BAND_HIGH,
556*4882a593Smuzhiyun reg_rule->end_freq, bw,
557*4882a593Smuzhiyun reg_rule->ant_gain, reg_rule->reg_power,
558*4882a593Smuzhiyun flags);
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun ath11k_dbg(ab, ATH11K_DBG_REG,
561*4882a593Smuzhiyun "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
562*4882a593Smuzhiyun i + 1, ETSI_WEATHER_RADAR_BAND_HIGH,
563*4882a593Smuzhiyun reg_rule->end_freq, bw, reg_rule->ant_gain,
564*4882a593Smuzhiyun reg_rule->reg_power, regd->reg_rules[i].dfs_cac_ms,
565*4882a593Smuzhiyun flags);
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun *rule_idx = i;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun struct ieee80211_regdomain *
ath11k_reg_build_regd(struct ath11k_base * ab,struct cur_regulatory_info * reg_info,bool intersect)572*4882a593Smuzhiyun ath11k_reg_build_regd(struct ath11k_base *ab,
573*4882a593Smuzhiyun struct cur_regulatory_info *reg_info, bool intersect)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun struct ieee80211_regdomain *tmp_regd, *default_regd, *new_regd = NULL;
576*4882a593Smuzhiyun struct cur_reg_rule *reg_rule;
577*4882a593Smuzhiyun u8 i = 0, j = 0;
578*4882a593Smuzhiyun u8 num_rules;
579*4882a593Smuzhiyun u16 max_bw;
580*4882a593Smuzhiyun u32 flags;
581*4882a593Smuzhiyun char alpha2[3];
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun num_rules = reg_info->num_5g_reg_rules + reg_info->num_2g_reg_rules;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun if (!num_rules)
586*4882a593Smuzhiyun goto ret;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun /* Add max additional rules to accommodate weather radar band */
589*4882a593Smuzhiyun if (reg_info->dfs_region == ATH11K_DFS_REG_ETSI)
590*4882a593Smuzhiyun num_rules += 2;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun tmp_regd = kzalloc(sizeof(*tmp_regd) +
593*4882a593Smuzhiyun (num_rules * sizeof(struct ieee80211_reg_rule)),
594*4882a593Smuzhiyun GFP_ATOMIC);
595*4882a593Smuzhiyun if (!tmp_regd)
596*4882a593Smuzhiyun goto ret;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun memcpy(tmp_regd->alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1);
599*4882a593Smuzhiyun memcpy(alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1);
600*4882a593Smuzhiyun alpha2[2] = '\0';
601*4882a593Smuzhiyun tmp_regd->dfs_region = ath11k_map_fw_dfs_region(reg_info->dfs_region);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun ath11k_dbg(ab, ATH11K_DBG_REG,
604*4882a593Smuzhiyun "\r\nCountry %s, CFG Regdomain %s FW Regdomain %d, num_reg_rules %d\n",
605*4882a593Smuzhiyun alpha2, ath11k_reg_get_regdom_str(tmp_regd->dfs_region),
606*4882a593Smuzhiyun reg_info->dfs_region, num_rules);
607*4882a593Smuzhiyun /* Update reg_rules[] below. Firmware is expected to
608*4882a593Smuzhiyun * send these rules in order(2G rules first and then 5G)
609*4882a593Smuzhiyun */
610*4882a593Smuzhiyun for (; i < num_rules; i++) {
611*4882a593Smuzhiyun if (reg_info->num_2g_reg_rules &&
612*4882a593Smuzhiyun (i < reg_info->num_2g_reg_rules)) {
613*4882a593Smuzhiyun reg_rule = reg_info->reg_rules_2g_ptr + i;
614*4882a593Smuzhiyun max_bw = min_t(u16, reg_rule->max_bw,
615*4882a593Smuzhiyun reg_info->max_bw_2g);
616*4882a593Smuzhiyun flags = 0;
617*4882a593Smuzhiyun } else if (reg_info->num_5g_reg_rules &&
618*4882a593Smuzhiyun (j < reg_info->num_5g_reg_rules)) {
619*4882a593Smuzhiyun reg_rule = reg_info->reg_rules_5g_ptr + j++;
620*4882a593Smuzhiyun max_bw = min_t(u16, reg_rule->max_bw,
621*4882a593Smuzhiyun reg_info->max_bw_5g);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun /* FW doesn't pass NL80211_RRF_AUTO_BW flag for
624*4882a593Smuzhiyun * BW Auto correction, we can enable this by default
625*4882a593Smuzhiyun * for all 5G rules here. The regulatory core performs
626*4882a593Smuzhiyun * BW correction if required and applies flags as
627*4882a593Smuzhiyun * per other BW rule flags we pass from here
628*4882a593Smuzhiyun */
629*4882a593Smuzhiyun flags = NL80211_RRF_AUTO_BW;
630*4882a593Smuzhiyun } else {
631*4882a593Smuzhiyun break;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun flags |= ath11k_map_fw_reg_flags(reg_rule->flags);
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun ath11k_reg_update_rule(tmp_regd->reg_rules + i,
637*4882a593Smuzhiyun reg_rule->start_freq,
638*4882a593Smuzhiyun reg_rule->end_freq, max_bw,
639*4882a593Smuzhiyun reg_rule->ant_gain, reg_rule->reg_power,
640*4882a593Smuzhiyun flags);
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /* Update dfs cac timeout if the dfs domain is ETSI and the
643*4882a593Smuzhiyun * new rule covers weather radar band.
644*4882a593Smuzhiyun * Default value of '0' corresponds to 60s timeout, so no
645*4882a593Smuzhiyun * need to update that for other rules.
646*4882a593Smuzhiyun */
647*4882a593Smuzhiyun if (flags & NL80211_RRF_DFS &&
648*4882a593Smuzhiyun reg_info->dfs_region == ATH11K_DFS_REG_ETSI &&
649*4882a593Smuzhiyun (reg_rule->end_freq > ETSI_WEATHER_RADAR_BAND_LOW &&
650*4882a593Smuzhiyun reg_rule->start_freq < ETSI_WEATHER_RADAR_BAND_HIGH)){
651*4882a593Smuzhiyun ath11k_reg_update_weather_radar_band(ab, tmp_regd,
652*4882a593Smuzhiyun reg_rule, &i,
653*4882a593Smuzhiyun flags, max_bw);
654*4882a593Smuzhiyun continue;
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun ath11k_dbg(ab, ATH11K_DBG_REG,
658*4882a593Smuzhiyun "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
659*4882a593Smuzhiyun i + 1, reg_rule->start_freq, reg_rule->end_freq,
660*4882a593Smuzhiyun max_bw, reg_rule->ant_gain, reg_rule->reg_power,
661*4882a593Smuzhiyun tmp_regd->reg_rules[i].dfs_cac_ms,
662*4882a593Smuzhiyun flags);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun tmp_regd->n_reg_rules = i;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun if (intersect) {
668*4882a593Smuzhiyun default_regd = ab->default_regd[reg_info->phy_id];
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun /* Get a new regd by intersecting the received regd with
671*4882a593Smuzhiyun * our default regd.
672*4882a593Smuzhiyun */
673*4882a593Smuzhiyun new_regd = ath11k_regd_intersect(default_regd, tmp_regd);
674*4882a593Smuzhiyun kfree(tmp_regd);
675*4882a593Smuzhiyun if (!new_regd) {
676*4882a593Smuzhiyun ath11k_warn(ab, "Unable to create intersected regdomain\n");
677*4882a593Smuzhiyun goto ret;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun } else {
680*4882a593Smuzhiyun new_regd = tmp_regd;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun ret:
684*4882a593Smuzhiyun return new_regd;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun
ath11k_regd_update_work(struct work_struct * work)687*4882a593Smuzhiyun void ath11k_regd_update_work(struct work_struct *work)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun struct ath11k *ar = container_of(work, struct ath11k,
690*4882a593Smuzhiyun regd_update_work);
691*4882a593Smuzhiyun int ret;
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun ret = ath11k_regd_update(ar);
694*4882a593Smuzhiyun if (ret) {
695*4882a593Smuzhiyun /* Firmware has already moved to the new regd. We need
696*4882a593Smuzhiyun * to maintain channel consistency across FW, Host driver
697*4882a593Smuzhiyun * and userspace. Hence as a fallback mechanism we can set
698*4882a593Smuzhiyun * the prev or default country code to the firmware.
699*4882a593Smuzhiyun */
700*4882a593Smuzhiyun /* TODO: Implement Fallback Mechanism */
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
ath11k_reg_init(struct ath11k * ar)704*4882a593Smuzhiyun void ath11k_reg_init(struct ath11k *ar)
705*4882a593Smuzhiyun {
706*4882a593Smuzhiyun ar->hw->wiphy->regulatory_flags = REGULATORY_WIPHY_SELF_MANAGED;
707*4882a593Smuzhiyun ar->hw->wiphy->reg_notifier = ath11k_reg_notifier;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
ath11k_reg_free(struct ath11k_base * ab)710*4882a593Smuzhiyun void ath11k_reg_free(struct ath11k_base *ab)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun int i;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun for (i = 0; i < ab->hw_params.max_radios; i++) {
715*4882a593Smuzhiyun kfree(ab->default_regd[i]);
716*4882a593Smuzhiyun kfree(ab->new_regd[i]);
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun }
719