1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _ATH11K_PCI_H 6*4882a593Smuzhiyun #define _ATH11K_PCI_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/mhi.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "core.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define PCIE_SOC_GLOBAL_RESET 0x3008 13*4882a593Smuzhiyun #define PCIE_SOC_GLOBAL_RESET_V 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define WLAON_WARM_SW_ENTRY 0x1f80504 16*4882a593Smuzhiyun #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define PCIE_Q6_COOKIE_ADDR 0x01f80500 19*4882a593Smuzhiyun #define PCIE_Q6_COOKIE_DATA 0xc0000000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* register to wake the UMAC from power collapse */ 22*4882a593Smuzhiyun #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* register used for handshake mechanism to validate UMAC is awake */ 25*4882a593Smuzhiyun #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct ath11k_msi_user { 28*4882a593Smuzhiyun char *name; 29*4882a593Smuzhiyun int num_vectors; 30*4882a593Smuzhiyun u32 base_vector; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct ath11k_msi_config { 34*4882a593Smuzhiyun int total_vectors; 35*4882a593Smuzhiyun int total_users; 36*4882a593Smuzhiyun struct ath11k_msi_user *users; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun enum ath11k_pci_flags { 40*4882a593Smuzhiyun ATH11K_PCI_FLAG_INIT_DONE, 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct ath11k_pci { 44*4882a593Smuzhiyun struct pci_dev *pdev; 45*4882a593Smuzhiyun struct ath11k_base *ab; 46*4882a593Smuzhiyun u16 dev_id; 47*4882a593Smuzhiyun char amss_path[100]; 48*4882a593Smuzhiyun u32 msi_ep_base_data; 49*4882a593Smuzhiyun struct mhi_controller *mhi_ctrl; 50*4882a593Smuzhiyun unsigned long mhi_state; 51*4882a593Smuzhiyun u32 register_window; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* protects register_window above */ 54*4882a593Smuzhiyun spinlock_t window_lock; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* enum ath11k_pci_flags */ 57*4882a593Smuzhiyun unsigned long flags; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun ath11k_pci_priv(struct ath11k_base * ab)60*4882a593Smuzhiyunstatic inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun return (struct ath11k_pci *)ab->drv_priv; 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name, 66*4882a593Smuzhiyun int *num_vectors, u32 *user_base_data, 67*4882a593Smuzhiyun u32 *base_vector); 68*4882a593Smuzhiyun int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector); 69*4882a593Smuzhiyun void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value); 70*4882a593Smuzhiyun u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif 73