1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef ATH11K_MAC_H 7*4882a593Smuzhiyun #define ATH11K_MAC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <net/mac80211.h> 10*4882a593Smuzhiyun #include <net/cfg80211.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct ath11k; 13*4882a593Smuzhiyun struct ath11k_base; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct ath11k_generic_iter { 16*4882a593Smuzhiyun struct ath11k *ar; 17*4882a593Smuzhiyun int ret; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* number of failed packets (20 packets with 16 sw reties each) */ 21*4882a593Smuzhiyun #define ATH11K_KICKOUT_THRESHOLD (20 * 16) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Use insanely high numbers to make sure that the firmware implementation 24*4882a593Smuzhiyun * won't start, we have the same functionality already in hostapd. Unit 25*4882a593Smuzhiyun * is seconds. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define ATH11K_KEEPALIVE_MIN_IDLE 3747 28*4882a593Smuzhiyun #define ATH11K_KEEPALIVE_MAX_IDLE 3895 29*4882a593Smuzhiyun #define ATH11K_KEEPALIVE_MAX_UNRESPONSIVE 3900 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define WMI_HOST_RC_DS_FLAG 0x01 32*4882a593Smuzhiyun #define WMI_HOST_RC_CW40_FLAG 0x02 33*4882a593Smuzhiyun #define WMI_HOST_RC_SGI_FLAG 0x04 34*4882a593Smuzhiyun #define WMI_HOST_RC_HT_FLAG 0x08 35*4882a593Smuzhiyun #define WMI_HOST_RC_RTSCTS_FLAG 0x10 36*4882a593Smuzhiyun #define WMI_HOST_RC_TX_STBC_FLAG 0x20 37*4882a593Smuzhiyun #define WMI_HOST_RC_RX_STBC_FLAG 0xC0 38*4882a593Smuzhiyun #define WMI_HOST_RC_RX_STBC_FLAG_S 6 39*4882a593Smuzhiyun #define WMI_HOST_RC_WEP_TKIP_FLAG 0x100 40*4882a593Smuzhiyun #define WMI_HOST_RC_TS_FLAG 0x200 41*4882a593Smuzhiyun #define WMI_HOST_RC_UAPSD_FLAG 0x400 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define WMI_HT_CAP_ENABLED 0x0001 44*4882a593Smuzhiyun #define WMI_HT_CAP_HT20_SGI 0x0002 45*4882a593Smuzhiyun #define WMI_HT_CAP_DYNAMIC_SMPS 0x0004 46*4882a593Smuzhiyun #define WMI_HT_CAP_TX_STBC 0x0008 47*4882a593Smuzhiyun #define WMI_HT_CAP_TX_STBC_MASK_SHIFT 3 48*4882a593Smuzhiyun #define WMI_HT_CAP_RX_STBC 0x0030 49*4882a593Smuzhiyun #define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4 50*4882a593Smuzhiyun #define WMI_HT_CAP_LDPC 0x0040 51*4882a593Smuzhiyun #define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080 52*4882a593Smuzhiyun #define WMI_HT_CAP_MPDU_DENSITY 0x0700 53*4882a593Smuzhiyun #define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT 8 54*4882a593Smuzhiyun #define WMI_HT_CAP_HT40_SGI 0x0800 55*4882a593Smuzhiyun #define WMI_HT_CAP_RX_LDPC 0x1000 56*4882a593Smuzhiyun #define WMI_HT_CAP_TX_LDPC 0x2000 57*4882a593Smuzhiyun #define WMI_HT_CAP_IBF_BFER 0x4000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* These macros should be used when we wish to advertise STBC support for 60*4882a593Smuzhiyun * only 1SS or 2SS or 3SS. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define WMI_HT_CAP_RX_STBC_1SS 0x0010 63*4882a593Smuzhiyun #define WMI_HT_CAP_RX_STBC_2SS 0x0020 64*4882a593Smuzhiyun #define WMI_HT_CAP_RX_STBC_3SS 0x0030 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED | \ 67*4882a593Smuzhiyun WMI_HT_CAP_HT20_SGI | \ 68*4882a593Smuzhiyun WMI_HT_CAP_HT40_SGI | \ 69*4882a593Smuzhiyun WMI_HT_CAP_TX_STBC | \ 70*4882a593Smuzhiyun WMI_HT_CAP_RX_STBC | \ 71*4882a593Smuzhiyun WMI_HT_CAP_LDPC) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003 74*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_LDPC 0x00000010 75*4882a593Smuzhiyun #define WMI_VHT_CAP_SGI_80MHZ 0x00000020 76*4882a593Smuzhiyun #define WMI_VHT_CAP_SGI_160MHZ 0x00000040 77*4882a593Smuzhiyun #define WMI_VHT_CAP_TX_STBC 0x00000080 78*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_STBC_MASK 0x00000300 79*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_STBC_MASK_SHIFT 8 80*4882a593Smuzhiyun #define WMI_VHT_CAP_SU_BFER 0x00000800 81*4882a593Smuzhiyun #define WMI_VHT_CAP_SU_BFEE 0x00001000 82*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_CS_ANT_MASK 0x0000E000 83*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_CS_ANT_MASK_SHIFT 13 84*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_SND_DIM_MASK 0x00070000 85*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_SND_DIM_MASK_SHIFT 16 86*4882a593Smuzhiyun #define WMI_VHT_CAP_MU_BFER 0x00080000 87*4882a593Smuzhiyun #define WMI_VHT_CAP_MU_BFEE 0x00100000 88*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000 89*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIT 23 90*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000 91*4882a593Smuzhiyun #define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* These macros should be used when we wish to advertise STBC support for 96*4882a593Smuzhiyun * only 1SS or 2SS or 3SS. 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_STBC_1SS 0x00000100 99*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_STBC_2SS 0x00000200 100*4882a593Smuzhiyun #define WMI_VHT_CAP_RX_STBC_3SS 0x00000300 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \ 103*4882a593Smuzhiyun WMI_VHT_CAP_SGI_80MHZ | \ 104*4882a593Smuzhiyun WMI_VHT_CAP_TX_STBC | \ 105*4882a593Smuzhiyun WMI_VHT_CAP_RX_STBC_MASK | \ 106*4882a593Smuzhiyun WMI_VHT_CAP_RX_LDPC | \ 107*4882a593Smuzhiyun WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \ 108*4882a593Smuzhiyun WMI_VHT_CAP_RX_FIXED_ANT | \ 109*4882a593Smuzhiyun WMI_VHT_CAP_TX_FIXED_ANT) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* FIXME: should these be in ieee80211.h? */ 112*4882a593Smuzhiyun #define IEEE80211_VHT_MCS_SUPPORT_0_11_MASK GENMASK(23, 16) 113*4882a593Smuzhiyun #define IEEE80211_DISABLE_VHT_MCS_SUPPORT_0_11 BIT(24) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define WMI_MAX_SPATIAL_STREAM 3 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define ATH11K_CHAN_WIDTH_NUM 8 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun extern const struct htt_rx_ring_tlv_filter ath11k_mac_mon_status_filter_default; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun void ath11k_mac_destroy(struct ath11k_base *ab); 122*4882a593Smuzhiyun void ath11k_mac_unregister(struct ath11k_base *ab); 123*4882a593Smuzhiyun int ath11k_mac_register(struct ath11k_base *ab); 124*4882a593Smuzhiyun int ath11k_mac_allocate(struct ath11k_base *ab); 125*4882a593Smuzhiyun int ath11k_mac_hw_ratecode_to_legacy_rate(u8 hw_rc, u8 preamble, u8 *rateidx, 126*4882a593Smuzhiyun u16 *rate); 127*4882a593Smuzhiyun u8 ath11k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband, 128*4882a593Smuzhiyun u32 bitrate); 129*4882a593Smuzhiyun u8 ath11k_mac_hw_rate_to_idx(const struct ieee80211_supported_band *sband, 130*4882a593Smuzhiyun u8 hw_rate, bool cck); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun void __ath11k_mac_scan_finish(struct ath11k *ar); 133*4882a593Smuzhiyun void ath11k_mac_scan_finish(struct ath11k *ar); 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct ath11k_vif *ath11k_mac_get_arvif(struct ath11k *ar, u32 vdev_id); 136*4882a593Smuzhiyun struct ath11k_vif *ath11k_mac_get_arvif_by_vdev_id(struct ath11k_base *ab, 137*4882a593Smuzhiyun u32 vdev_id); 138*4882a593Smuzhiyun struct ath11k *ath11k_mac_get_ar_by_vdev_id(struct ath11k_base *ab, u32 vdev_id); 139*4882a593Smuzhiyun struct ath11k *ath11k_mac_get_ar_by_pdev_id(struct ath11k_base *ab, u32 pdev_id); 140*4882a593Smuzhiyun struct ath11k *ath11k_mac_get_ar_vdev_stop_status(struct ath11k_base *ab, 141*4882a593Smuzhiyun u32 vdev_id); 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun void ath11k_mac_drain_tx(struct ath11k *ar); 144*4882a593Smuzhiyun void ath11k_mac_peer_cleanup_all(struct ath11k *ar); 145*4882a593Smuzhiyun int ath11k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx); 146*4882a593Smuzhiyun u8 ath11k_mac_bw_to_mac80211_bw(u8 bw); 147*4882a593Smuzhiyun enum ath11k_supported_bw ath11k_mac_mac80211_bw_to_ath11k_bw(enum rate_info_bw bw); 148*4882a593Smuzhiyun enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher); 149*4882a593Smuzhiyun #endif 150