1*4882a593Smuzhiyun // SPDX-License-Identifier: BSD-3-Clause-Clear
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include "core.h"
7*4882a593Smuzhiyun #include "dp_tx.h"
8*4882a593Smuzhiyun #include "debug.h"
9*4882a593Smuzhiyun #include "debugfs_sta.h"
10*4882a593Smuzhiyun #include "hw.h"
11*4882a593Smuzhiyun #include "peer.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static enum hal_tcl_encap_type
ath11k_dp_tx_get_encap_type(struct ath11k_vif * arvif,struct sk_buff * skb)14*4882a593Smuzhiyun ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
17*4882a593Smuzhiyun struct ath11k_base *ab = arvif->ar->ab;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
20*4882a593Smuzhiyun return HAL_TCL_ENCAP_TYPE_RAW;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
23*4882a593Smuzhiyun return HAL_TCL_ENCAP_TYPE_ETHERNET;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
ath11k_dp_tx_encap_nwifi(struct sk_buff * skb)28*4882a593Smuzhiyun static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (void *)skb->data;
31*4882a593Smuzhiyun u8 *qos_ctl;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun if (!ieee80211_is_data_qos(hdr->frame_control))
34*4882a593Smuzhiyun return;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun qos_ctl = ieee80211_get_qos_ctl(hdr);
37*4882a593Smuzhiyun memmove(skb->data + IEEE80211_QOS_CTL_LEN,
38*4882a593Smuzhiyun skb->data, (void *)qos_ctl - (void *)skb->data);
39*4882a593Smuzhiyun skb_pull(skb, IEEE80211_QOS_CTL_LEN);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun hdr = (void *)skb->data;
42*4882a593Smuzhiyun hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
ath11k_dp_tx_get_tid(struct sk_buff * skb)45*4882a593Smuzhiyun static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (void *)skb->data;
48*4882a593Smuzhiyun struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (cb->flags & ATH11K_SKB_HW_80211_ENCAP)
51*4882a593Smuzhiyun return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
52*4882a593Smuzhiyun else if (!ieee80211_is_data_qos(hdr->frame_control))
53*4882a593Smuzhiyun return HAL_DESC_REO_NON_QOS_TID;
54*4882a593Smuzhiyun else
55*4882a593Smuzhiyun return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
ath11k_dp_tx_get_encrypt_type(u32 cipher)58*4882a593Smuzhiyun enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun switch (cipher) {
61*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP40:
62*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_WEP_40;
63*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_WEP104:
64*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_WEP_104;
65*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_TKIP:
66*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_TKIP_MIC;
67*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP:
68*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_CCMP_128;
69*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_CCMP_256:
70*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_CCMP_256;
71*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_GCMP:
72*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_GCMP_128;
73*4882a593Smuzhiyun case WLAN_CIPHER_SUITE_GCMP_256:
74*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_AES_GCMP_256;
75*4882a593Smuzhiyun default:
76*4882a593Smuzhiyun return HAL_ENCRYPT_TYPE_OPEN;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
ath11k_dp_tx(struct ath11k * ar,struct ath11k_vif * arvif,struct sk_buff * skb)80*4882a593Smuzhiyun int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
81*4882a593Smuzhiyun struct sk_buff *skb)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
84*4882a593Smuzhiyun struct ath11k_dp *dp = &ab->dp;
85*4882a593Smuzhiyun struct hal_tx_info ti = {0};
86*4882a593Smuzhiyun struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87*4882a593Smuzhiyun struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
88*4882a593Smuzhiyun struct hal_srng *tcl_ring;
89*4882a593Smuzhiyun struct ieee80211_hdr *hdr = (void *)skb->data;
90*4882a593Smuzhiyun struct dp_tx_ring *tx_ring;
91*4882a593Smuzhiyun void *hal_tcl_desc;
92*4882a593Smuzhiyun u8 pool_id;
93*4882a593Smuzhiyun u8 hal_ring_id;
94*4882a593Smuzhiyun int ret;
95*4882a593Smuzhiyun u8 ring_selector = 0, ring_map = 0;
96*4882a593Smuzhiyun bool tcl_ring_retry;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
99*4882a593Smuzhiyun return -ESHUTDOWN;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
102*4882a593Smuzhiyun !ieee80211_is_data(hdr->frame_control))
103*4882a593Smuzhiyun return -ENOTSUPP;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Let the default ring selection be based on a round robin
108*4882a593Smuzhiyun * fashion where one of the 3 tcl rings are selected based on
109*4882a593Smuzhiyun * the tcl_ring_selector counter. In case that ring
110*4882a593Smuzhiyun * is full/busy, we resort to other available rings.
111*4882a593Smuzhiyun * If all rings are full, we drop the packet.
112*4882a593Smuzhiyun * //TODO Add throttling logic when all rings are full
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun ring_selector = atomic_inc_return(&ab->tcl_ring_selector);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun tcl_ring_sel:
117*4882a593Smuzhiyun tcl_ring_retry = false;
118*4882a593Smuzhiyun /* For some chip, it can only use tcl0 to tx */
119*4882a593Smuzhiyun if (ar->ab->hw_params.tcl_0_only)
120*4882a593Smuzhiyun ti.ring_id = 0;
121*4882a593Smuzhiyun else
122*4882a593Smuzhiyun ti.ring_id = ring_selector % DP_TCL_NUM_RING_MAX;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ring_map |= BIT(ti.ring_id);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun tx_ring = &dp->tx_ring[ti.ring_id];
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun spin_lock_bh(&tx_ring->tx_idr_lock);
129*4882a593Smuzhiyun ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
130*4882a593Smuzhiyun DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
131*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (ret < 0) {
134*4882a593Smuzhiyun if (ring_map == (BIT(DP_TCL_NUM_RING_MAX) - 1)) {
135*4882a593Smuzhiyun atomic_inc(&ab->soc_stats.tx_err.misc_fail);
136*4882a593Smuzhiyun return -ENOSPC;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* Check if the next ring is available */
140*4882a593Smuzhiyun ring_selector++;
141*4882a593Smuzhiyun goto tcl_ring_sel;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
145*4882a593Smuzhiyun FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
146*4882a593Smuzhiyun FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
147*4882a593Smuzhiyun ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
148*4882a593Smuzhiyun ti.meta_data_flags = arvif->tcl_metadata;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW) {
151*4882a593Smuzhiyun if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) {
152*4882a593Smuzhiyun ti.encrypt_type =
153*4882a593Smuzhiyun ath11k_dp_tx_get_encrypt_type(skb_cb->cipher);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (ieee80211_has_protected(hdr->frame_control))
156*4882a593Smuzhiyun skb_put(skb, IEEE80211_CCMP_MIC_LEN);
157*4882a593Smuzhiyun } else {
158*4882a593Smuzhiyun ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ti.addr_search_flags = arvif->hal_addr_search_flags;
163*4882a593Smuzhiyun ti.search_type = arvif->search_type;
164*4882a593Smuzhiyun ti.type = HAL_TCL_DESC_TYPE_BUFFER;
165*4882a593Smuzhiyun ti.pkt_offset = 0;
166*4882a593Smuzhiyun ti.lmac_id = ar->lmac_id;
167*4882a593Smuzhiyun ti.bss_ast_hash = arvif->ast_hash;
168*4882a593Smuzhiyun ti.dscp_tid_tbl_idx = 0;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun if (skb->ip_summed == CHECKSUM_PARTIAL &&
171*4882a593Smuzhiyun ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) {
172*4882a593Smuzhiyun ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
173*4882a593Smuzhiyun FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
174*4882a593Smuzhiyun FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
175*4882a593Smuzhiyun FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
176*4882a593Smuzhiyun FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (ieee80211_vif_is_mesh(arvif->vif))
180*4882a593Smuzhiyun ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun ti.tid = ath11k_dp_tx_get_tid(skb);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun switch (ti.encap_type) {
187*4882a593Smuzhiyun case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
188*4882a593Smuzhiyun ath11k_dp_tx_encap_nwifi(skb);
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun case HAL_TCL_ENCAP_TYPE_RAW:
191*4882a593Smuzhiyun if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) {
192*4882a593Smuzhiyun ret = -EINVAL;
193*4882a593Smuzhiyun goto fail_remove_idr;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun break;
196*4882a593Smuzhiyun case HAL_TCL_ENCAP_TYPE_ETHERNET:
197*4882a593Smuzhiyun /* no need to encap */
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun case HAL_TCL_ENCAP_TYPE_802_3:
200*4882a593Smuzhiyun default:
201*4882a593Smuzhiyun /* TODO: Take care of other encap modes as well */
202*4882a593Smuzhiyun ret = -EINVAL;
203*4882a593Smuzhiyun atomic_inc(&ab->soc_stats.tx_err.misc_fail);
204*4882a593Smuzhiyun goto fail_remove_idr;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
208*4882a593Smuzhiyun if (dma_mapping_error(ab->dev, ti.paddr)) {
209*4882a593Smuzhiyun atomic_inc(&ab->soc_stats.tx_err.misc_fail);
210*4882a593Smuzhiyun ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
211*4882a593Smuzhiyun ret = -ENOMEM;
212*4882a593Smuzhiyun goto fail_remove_idr;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun ti.data_len = skb->len;
216*4882a593Smuzhiyun skb_cb->paddr = ti.paddr;
217*4882a593Smuzhiyun skb_cb->vif = arvif->vif;
218*4882a593Smuzhiyun skb_cb->ar = ar;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun hal_ring_id = tx_ring->tcl_data_ring.ring_id;
221*4882a593Smuzhiyun tcl_ring = &ab->hal.srng_list[hal_ring_id];
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun spin_lock_bh(&tcl_ring->lock);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun ath11k_hal_srng_access_begin(ab, tcl_ring);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
228*4882a593Smuzhiyun if (!hal_tcl_desc) {
229*4882a593Smuzhiyun /* NOTE: It is highly unlikely we'll be running out of tcl_ring
230*4882a593Smuzhiyun * desc because the desc is directly enqueued onto hw queue.
231*4882a593Smuzhiyun */
232*4882a593Smuzhiyun ath11k_hal_srng_access_end(ab, tcl_ring);
233*4882a593Smuzhiyun ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
234*4882a593Smuzhiyun spin_unlock_bh(&tcl_ring->lock);
235*4882a593Smuzhiyun ret = -ENOMEM;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* Checking for available tcl descritors in another ring in
238*4882a593Smuzhiyun * case of failure due to full tcl ring now, is better than
239*4882a593Smuzhiyun * checking this ring earlier for each pkt tx.
240*4882a593Smuzhiyun * Restart ring selection if some rings are not checked yet.
241*4882a593Smuzhiyun */
242*4882a593Smuzhiyun if (ring_map != (BIT(DP_TCL_NUM_RING_MAX) - 1) &&
243*4882a593Smuzhiyun !ar->ab->hw_params.tcl_0_only) {
244*4882a593Smuzhiyun tcl_ring_retry = true;
245*4882a593Smuzhiyun ring_selector++;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun goto fail_unmap_dma;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
252*4882a593Smuzhiyun sizeof(struct hal_tlv_hdr), &ti);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun ath11k_hal_srng_access_end(ab, tcl_ring);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun spin_unlock_bh(&tcl_ring->lock);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ",
261*4882a593Smuzhiyun skb->data, skb->len);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun atomic_inc(&ar->dp.num_tx_pending);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return 0;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun fail_unmap_dma:
268*4882a593Smuzhiyun dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun fail_remove_idr:
271*4882a593Smuzhiyun spin_lock_bh(&tx_ring->tx_idr_lock);
272*4882a593Smuzhiyun idr_remove(&tx_ring->txbuf_idr,
273*4882a593Smuzhiyun FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
274*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (tcl_ring_retry)
277*4882a593Smuzhiyun goto tcl_ring_sel;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return ret;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
ath11k_dp_tx_free_txbuf(struct ath11k_base * ab,u8 mac_id,int msdu_id,struct dp_tx_ring * tx_ring)282*4882a593Smuzhiyun static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
283*4882a593Smuzhiyun int msdu_id,
284*4882a593Smuzhiyun struct dp_tx_ring *tx_ring)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun struct ath11k *ar;
287*4882a593Smuzhiyun struct sk_buff *msdu;
288*4882a593Smuzhiyun struct ath11k_skb_cb *skb_cb;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun spin_lock_bh(&tx_ring->tx_idr_lock);
291*4882a593Smuzhiyun msdu = idr_find(&tx_ring->txbuf_idr, msdu_id);
292*4882a593Smuzhiyun if (!msdu) {
293*4882a593Smuzhiyun ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
294*4882a593Smuzhiyun msdu_id);
295*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
296*4882a593Smuzhiyun return;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun skb_cb = ATH11K_SKB_CB(msdu);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun idr_remove(&tx_ring->txbuf_idr, msdu_id);
302*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
305*4882a593Smuzhiyun dev_kfree_skb_any(msdu);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun ar = ab->pdevs[mac_id].ar;
308*4882a593Smuzhiyun if (atomic_dec_and_test(&ar->dp.num_tx_pending))
309*4882a593Smuzhiyun wake_up(&ar->dp.tx_empty_waitq);
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun static void
ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base * ab,struct dp_tx_ring * tx_ring,struct ath11k_dp_htt_wbm_tx_status * ts)313*4882a593Smuzhiyun ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
314*4882a593Smuzhiyun struct dp_tx_ring *tx_ring,
315*4882a593Smuzhiyun struct ath11k_dp_htt_wbm_tx_status *ts)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct sk_buff *msdu;
318*4882a593Smuzhiyun struct ieee80211_tx_info *info;
319*4882a593Smuzhiyun struct ath11k_skb_cb *skb_cb;
320*4882a593Smuzhiyun struct ath11k *ar;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun spin_lock_bh(&tx_ring->tx_idr_lock);
323*4882a593Smuzhiyun msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id);
324*4882a593Smuzhiyun if (!msdu) {
325*4882a593Smuzhiyun ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
326*4882a593Smuzhiyun ts->msdu_id);
327*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
328*4882a593Smuzhiyun return;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun skb_cb = ATH11K_SKB_CB(msdu);
332*4882a593Smuzhiyun info = IEEE80211_SKB_CB(msdu);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun ar = skb_cb->ar;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
337*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun if (atomic_dec_and_test(&ar->dp.num_tx_pending))
340*4882a593Smuzhiyun wake_up(&ar->dp.tx_empty_waitq);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun memset(&info->status, 0, sizeof(info->status));
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun if (ts->acked) {
347*4882a593Smuzhiyun if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
348*4882a593Smuzhiyun info->flags |= IEEE80211_TX_STAT_ACK;
349*4882a593Smuzhiyun info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
350*4882a593Smuzhiyun ts->ack_rssi;
351*4882a593Smuzhiyun info->status.is_valid_ack_signal = true;
352*4882a593Smuzhiyun } else {
353*4882a593Smuzhiyun info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun ieee80211_tx_status(ar->hw, msdu);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun static void
ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base * ab,void * desc,u8 mac_id,u32 msdu_id,struct dp_tx_ring * tx_ring)361*4882a593Smuzhiyun ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
362*4882a593Smuzhiyun void *desc, u8 mac_id,
363*4882a593Smuzhiyun u32 msdu_id, struct dp_tx_ring *tx_ring)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun struct htt_tx_wbm_completion *status_desc;
366*4882a593Smuzhiyun struct ath11k_dp_htt_wbm_tx_status ts = {0};
367*4882a593Smuzhiyun enum hal_wbm_htt_tx_comp_status wbm_status;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
372*4882a593Smuzhiyun status_desc->info0);
373*4882a593Smuzhiyun switch (wbm_status) {
374*4882a593Smuzhiyun case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
375*4882a593Smuzhiyun case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
376*4882a593Smuzhiyun case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
377*4882a593Smuzhiyun ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
378*4882a593Smuzhiyun ts.msdu_id = msdu_id;
379*4882a593Smuzhiyun ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
380*4882a593Smuzhiyun status_desc->info1);
381*4882a593Smuzhiyun ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
382*4882a593Smuzhiyun break;
383*4882a593Smuzhiyun case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
384*4882a593Smuzhiyun case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
385*4882a593Smuzhiyun ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
386*4882a593Smuzhiyun break;
387*4882a593Smuzhiyun case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
388*4882a593Smuzhiyun /* This event is to be handled only when the driver decides to
389*4882a593Smuzhiyun * use WDS offload functionality.
390*4882a593Smuzhiyun */
391*4882a593Smuzhiyun break;
392*4882a593Smuzhiyun default:
393*4882a593Smuzhiyun ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
394*4882a593Smuzhiyun break;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
ath11k_dp_tx_cache_peer_stats(struct ath11k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)398*4882a593Smuzhiyun static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
399*4882a593Smuzhiyun struct sk_buff *msdu,
400*4882a593Smuzhiyun struct hal_tx_status *ts)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun if (ts->try_cnt > 1) {
405*4882a593Smuzhiyun peer_stats->retry_pkts += ts->try_cnt - 1;
406*4882a593Smuzhiyun peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
409*4882a593Smuzhiyun peer_stats->failed_pkts += 1;
410*4882a593Smuzhiyun peer_stats->failed_bytes += msdu->len;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
ath11k_dp_tx_complete_msdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)415*4882a593Smuzhiyun static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
416*4882a593Smuzhiyun struct sk_buff *msdu,
417*4882a593Smuzhiyun struct hal_tx_status *ts)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
420*4882a593Smuzhiyun struct ieee80211_tx_info *info;
421*4882a593Smuzhiyun struct ath11k_skb_cb *skb_cb;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
424*4882a593Smuzhiyun /* Must not happen */
425*4882a593Smuzhiyun return;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun skb_cb = ATH11K_SKB_CB(msdu);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun rcu_read_lock();
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {
435*4882a593Smuzhiyun dev_kfree_skb_any(msdu);
436*4882a593Smuzhiyun goto exit;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun if (!skb_cb->vif) {
440*4882a593Smuzhiyun dev_kfree_skb_any(msdu);
441*4882a593Smuzhiyun goto exit;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun info = IEEE80211_SKB_CB(msdu);
445*4882a593Smuzhiyun memset(&info->status, 0, sizeof(info->status));
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun /* skip tx rate update from ieee80211_status*/
448*4882a593Smuzhiyun info->status.rates[0].idx = -1;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
451*4882a593Smuzhiyun !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
452*4882a593Smuzhiyun info->flags |= IEEE80211_TX_STAT_ACK;
453*4882a593Smuzhiyun info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
454*4882a593Smuzhiyun ts->ack_rssi;
455*4882a593Smuzhiyun info->status.is_valid_ack_signal = true;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
459*4882a593Smuzhiyun (info->flags & IEEE80211_TX_CTL_NO_ACK))
460*4882a593Smuzhiyun info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) {
463*4882a593Smuzhiyun if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
464*4882a593Smuzhiyun if (ar->last_ppdu_id == 0) {
465*4882a593Smuzhiyun ar->last_ppdu_id = ts->ppdu_id;
466*4882a593Smuzhiyun } else if (ar->last_ppdu_id == ts->ppdu_id ||
467*4882a593Smuzhiyun ar->cached_ppdu_id == ar->last_ppdu_id) {
468*4882a593Smuzhiyun ar->cached_ppdu_id = ar->last_ppdu_id;
469*4882a593Smuzhiyun ar->cached_stats.is_ampdu = true;
470*4882a593Smuzhiyun ath11k_debugfs_sta_update_txcompl(ar, msdu, ts);
471*4882a593Smuzhiyun memset(&ar->cached_stats, 0,
472*4882a593Smuzhiyun sizeof(struct ath11k_per_peer_tx_stats));
473*4882a593Smuzhiyun } else {
474*4882a593Smuzhiyun ar->cached_stats.is_ampdu = false;
475*4882a593Smuzhiyun ath11k_debugfs_sta_update_txcompl(ar, msdu, ts);
476*4882a593Smuzhiyun memset(&ar->cached_stats, 0,
477*4882a593Smuzhiyun sizeof(struct ath11k_per_peer_tx_stats));
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun ar->last_ppdu_id = ts->ppdu_id;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* NOTE: Tx rate status reporting. Tx completion status does not have
486*4882a593Smuzhiyun * necessary information (for example nss) to build the tx rate.
487*4882a593Smuzhiyun * Might end up reporting it out-of-band from HTT stats.
488*4882a593Smuzhiyun */
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun ieee80211_tx_status(ar->hw, msdu);
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun exit:
493*4882a593Smuzhiyun rcu_read_unlock();
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
ath11k_dp_tx_status_parse(struct ath11k_base * ab,struct hal_wbm_release_ring * desc,struct hal_tx_status * ts)496*4882a593Smuzhiyun static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
497*4882a593Smuzhiyun struct hal_wbm_release_ring *desc,
498*4882a593Smuzhiyun struct hal_tx_status *ts)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun ts->buf_rel_source =
501*4882a593Smuzhiyun FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
502*4882a593Smuzhiyun if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
503*4882a593Smuzhiyun ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)
504*4882a593Smuzhiyun return;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)
507*4882a593Smuzhiyun return;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
510*4882a593Smuzhiyun desc->info0);
511*4882a593Smuzhiyun ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
512*4882a593Smuzhiyun desc->info1);
513*4882a593Smuzhiyun ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
514*4882a593Smuzhiyun desc->info1);
515*4882a593Smuzhiyun ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
516*4882a593Smuzhiyun desc->info2);
517*4882a593Smuzhiyun if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
518*4882a593Smuzhiyun ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
519*4882a593Smuzhiyun ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
520*4882a593Smuzhiyun ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
521*4882a593Smuzhiyun if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
522*4882a593Smuzhiyun ts->rate_stats = desc->rate_stats.info0;
523*4882a593Smuzhiyun else
524*4882a593Smuzhiyun ts->rate_stats = 0;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
ath11k_dp_tx_completion_handler(struct ath11k_base * ab,int ring_id)527*4882a593Smuzhiyun void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun struct ath11k *ar;
530*4882a593Smuzhiyun struct ath11k_dp *dp = &ab->dp;
531*4882a593Smuzhiyun int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
532*4882a593Smuzhiyun struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
533*4882a593Smuzhiyun struct sk_buff *msdu;
534*4882a593Smuzhiyun struct hal_tx_status ts = { 0 };
535*4882a593Smuzhiyun struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
536*4882a593Smuzhiyun u32 *desc;
537*4882a593Smuzhiyun u32 msdu_id;
538*4882a593Smuzhiyun u8 mac_id;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun spin_lock_bh(&status_ring->lock);
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun ath11k_hal_srng_access_begin(ab, status_ring);
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
545*4882a593Smuzhiyun tx_ring->tx_status_tail) &&
546*4882a593Smuzhiyun (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
547*4882a593Smuzhiyun memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
548*4882a593Smuzhiyun desc, sizeof(struct hal_wbm_release_ring));
549*4882a593Smuzhiyun tx_ring->tx_status_head =
550*4882a593Smuzhiyun ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
554*4882a593Smuzhiyun (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {
555*4882a593Smuzhiyun /* TODO: Process pending tx_status messages when kfifo_is_full() */
556*4882a593Smuzhiyun ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun ath11k_hal_srng_access_end(ab, status_ring);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun spin_unlock_bh(&status_ring->lock);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
564*4882a593Smuzhiyun struct hal_wbm_release_ring *tx_status;
565*4882a593Smuzhiyun u32 desc_id;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun tx_ring->tx_status_tail =
568*4882a593Smuzhiyun ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
569*4882a593Smuzhiyun tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
570*4882a593Smuzhiyun ath11k_dp_tx_status_parse(ab, tx_status, &ts);
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
573*4882a593Smuzhiyun tx_status->buf_addr_info.info1);
574*4882a593Smuzhiyun mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
575*4882a593Smuzhiyun msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {
578*4882a593Smuzhiyun ath11k_dp_tx_process_htt_tx_complete(ab,
579*4882a593Smuzhiyun (void *)tx_status,
580*4882a593Smuzhiyun mac_id, msdu_id,
581*4882a593Smuzhiyun tx_ring);
582*4882a593Smuzhiyun continue;
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun spin_lock_bh(&tx_ring->tx_idr_lock);
586*4882a593Smuzhiyun msdu = idr_find(&tx_ring->txbuf_idr, msdu_id);
587*4882a593Smuzhiyun if (!msdu) {
588*4882a593Smuzhiyun ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
589*4882a593Smuzhiyun msdu_id);
590*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
591*4882a593Smuzhiyun continue;
592*4882a593Smuzhiyun }
593*4882a593Smuzhiyun idr_remove(&tx_ring->txbuf_idr, msdu_id);
594*4882a593Smuzhiyun spin_unlock_bh(&tx_ring->tx_idr_lock);
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun ar = ab->pdevs[mac_id].ar;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun if (atomic_dec_and_test(&ar->dp.num_tx_pending))
599*4882a593Smuzhiyun wake_up(&ar->dp.tx_empty_waitq);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
ath11k_dp_tx_send_reo_cmd(struct ath11k_base * ab,struct dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd,void (* cb)(struct ath11k_dp *,void *,enum hal_reo_cmd_status))605*4882a593Smuzhiyun int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
606*4882a593Smuzhiyun enum hal_reo_cmd_type type,
607*4882a593Smuzhiyun struct ath11k_hal_reo_cmd *cmd,
608*4882a593Smuzhiyun void (*cb)(struct ath11k_dp *, void *,
609*4882a593Smuzhiyun enum hal_reo_cmd_status))
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun struct ath11k_dp *dp = &ab->dp;
612*4882a593Smuzhiyun struct dp_reo_cmd *dp_cmd;
613*4882a593Smuzhiyun struct hal_srng *cmd_ring;
614*4882a593Smuzhiyun int cmd_num;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
617*4882a593Smuzhiyun cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun /* cmd_num should start from 1, during failure return the error code */
620*4882a593Smuzhiyun if (cmd_num < 0)
621*4882a593Smuzhiyun return cmd_num;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun /* reo cmd ring descriptors has cmd_num starting from 1 */
624*4882a593Smuzhiyun if (cmd_num == 0)
625*4882a593Smuzhiyun return -EINVAL;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun if (!cb)
628*4882a593Smuzhiyun return 0;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /* Can this be optimized so that we keep the pending command list only
631*4882a593Smuzhiyun * for tid delete command to free up the resoruce on the command status
632*4882a593Smuzhiyun * indication?
633*4882a593Smuzhiyun */
634*4882a593Smuzhiyun dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun if (!dp_cmd)
637*4882a593Smuzhiyun return -ENOMEM;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
640*4882a593Smuzhiyun dp_cmd->cmd_num = cmd_num;
641*4882a593Smuzhiyun dp_cmd->handler = cb;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun spin_lock_bh(&dp->reo_cmd_lock);
644*4882a593Smuzhiyun list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
645*4882a593Smuzhiyun spin_unlock_bh(&dp->reo_cmd_lock);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun return 0;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun static int
ath11k_dp_tx_get_ring_id_type(struct ath11k_base * ab,int mac_id,u32 ring_id,enum hal_ring_type ring_type,enum htt_srng_ring_type * htt_ring_type,enum htt_srng_ring_id * htt_ring_id)651*4882a593Smuzhiyun ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
652*4882a593Smuzhiyun int mac_id, u32 ring_id,
653*4882a593Smuzhiyun enum hal_ring_type ring_type,
654*4882a593Smuzhiyun enum htt_srng_ring_type *htt_ring_type,
655*4882a593Smuzhiyun enum htt_srng_ring_id *htt_ring_id)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun int lmac_ring_id_offset = 0;
658*4882a593Smuzhiyun int ret = 0;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun switch (ring_type) {
661*4882a593Smuzhiyun case HAL_RXDMA_BUF:
662*4882a593Smuzhiyun lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun /* for QCA6390, host fills rx buffer to fw and fw fills to
665*4882a593Smuzhiyun * rxbuf ring for each rxdma
666*4882a593Smuzhiyun */
667*4882a593Smuzhiyun if (!ab->hw_params.rx_mac_buf_ring) {
668*4882a593Smuzhiyun if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
669*4882a593Smuzhiyun lmac_ring_id_offset) ||
670*4882a593Smuzhiyun ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
671*4882a593Smuzhiyun lmac_ring_id_offset))) {
672*4882a593Smuzhiyun ret = -EINVAL;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
675*4882a593Smuzhiyun *htt_ring_type = HTT_SW_TO_HW_RING;
676*4882a593Smuzhiyun } else {
677*4882a593Smuzhiyun if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) {
678*4882a593Smuzhiyun *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
679*4882a593Smuzhiyun *htt_ring_type = HTT_SW_TO_SW_RING;
680*4882a593Smuzhiyun } else {
681*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
682*4882a593Smuzhiyun *htt_ring_type = HTT_SW_TO_HW_RING;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun break;
686*4882a593Smuzhiyun case HAL_RXDMA_DST:
687*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
688*4882a593Smuzhiyun *htt_ring_type = HTT_HW_TO_SW_RING;
689*4882a593Smuzhiyun break;
690*4882a593Smuzhiyun case HAL_RXDMA_MONITOR_BUF:
691*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
692*4882a593Smuzhiyun *htt_ring_type = HTT_SW_TO_HW_RING;
693*4882a593Smuzhiyun break;
694*4882a593Smuzhiyun case HAL_RXDMA_MONITOR_STATUS:
695*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
696*4882a593Smuzhiyun *htt_ring_type = HTT_SW_TO_HW_RING;
697*4882a593Smuzhiyun break;
698*4882a593Smuzhiyun case HAL_RXDMA_MONITOR_DST:
699*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
700*4882a593Smuzhiyun *htt_ring_type = HTT_HW_TO_SW_RING;
701*4882a593Smuzhiyun break;
702*4882a593Smuzhiyun case HAL_RXDMA_MONITOR_DESC:
703*4882a593Smuzhiyun *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
704*4882a593Smuzhiyun *htt_ring_type = HTT_SW_TO_HW_RING;
705*4882a593Smuzhiyun break;
706*4882a593Smuzhiyun default:
707*4882a593Smuzhiyun ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
708*4882a593Smuzhiyun ret = -EINVAL;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun return ret;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
ath11k_dp_tx_htt_srng_setup(struct ath11k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type)713*4882a593Smuzhiyun int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
714*4882a593Smuzhiyun int mac_id, enum hal_ring_type ring_type)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun struct htt_srng_setup_cmd *cmd;
717*4882a593Smuzhiyun struct hal_srng *srng = &ab->hal.srng_list[ring_id];
718*4882a593Smuzhiyun struct hal_srng_params params;
719*4882a593Smuzhiyun struct sk_buff *skb;
720*4882a593Smuzhiyun u32 ring_entry_sz;
721*4882a593Smuzhiyun int len = sizeof(*cmd);
722*4882a593Smuzhiyun dma_addr_t hp_addr, tp_addr;
723*4882a593Smuzhiyun enum htt_srng_ring_type htt_ring_type;
724*4882a593Smuzhiyun enum htt_srng_ring_id htt_ring_id;
725*4882a593Smuzhiyun int ret;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun skb = ath11k_htc_alloc_skb(ab, len);
728*4882a593Smuzhiyun if (!skb)
729*4882a593Smuzhiyun return -ENOMEM;
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun memset(¶ms, 0, sizeof(params));
732*4882a593Smuzhiyun ath11k_hal_srng_get_params(ab, srng, ¶ms);
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
735*4882a593Smuzhiyun tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
738*4882a593Smuzhiyun ring_type, &htt_ring_type,
739*4882a593Smuzhiyun &htt_ring_id);
740*4882a593Smuzhiyun if (ret)
741*4882a593Smuzhiyun goto err_free;
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun skb_put(skb, len);
744*4882a593Smuzhiyun cmd = (struct htt_srng_setup_cmd *)skb->data;
745*4882a593Smuzhiyun cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
746*4882a593Smuzhiyun HTT_H2T_MSG_TYPE_SRING_SETUP);
747*4882a593Smuzhiyun if (htt_ring_type == HTT_SW_TO_HW_RING ||
748*4882a593Smuzhiyun htt_ring_type == HTT_HW_TO_SW_RING)
749*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
750*4882a593Smuzhiyun DP_SW2HW_MACID(mac_id));
751*4882a593Smuzhiyun else
752*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
753*4882a593Smuzhiyun mac_id);
754*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
755*4882a593Smuzhiyun htt_ring_type);
756*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun cmd->ring_base_addr_lo = params.ring_base_paddr &
759*4882a593Smuzhiyun HAL_ADDR_LSB_REG_MASK;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
762*4882a593Smuzhiyun HAL_ADDR_MSB_REG_SHIFT;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun ret = ath11k_hal_srng_get_entrysize(ab, ring_type);
765*4882a593Smuzhiyun if (ret < 0)
766*4882a593Smuzhiyun goto err_free;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun ring_entry_sz = ret;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun ring_entry_sz >>= 2;
771*4882a593Smuzhiyun cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
772*4882a593Smuzhiyun ring_entry_sz);
773*4882a593Smuzhiyun cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
774*4882a593Smuzhiyun params.num_entries * ring_entry_sz);
775*4882a593Smuzhiyun cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
776*4882a593Smuzhiyun !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
777*4882a593Smuzhiyun cmd->info1 |= FIELD_PREP(
778*4882a593Smuzhiyun HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
779*4882a593Smuzhiyun !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
780*4882a593Smuzhiyun cmd->info1 |= FIELD_PREP(
781*4882a593Smuzhiyun HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
782*4882a593Smuzhiyun !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
783*4882a593Smuzhiyun if (htt_ring_type == HTT_SW_TO_HW_RING)
784*4882a593Smuzhiyun cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
787*4882a593Smuzhiyun cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
788*4882a593Smuzhiyun HAL_ADDR_MSB_REG_SHIFT;
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
791*4882a593Smuzhiyun cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
792*4882a593Smuzhiyun HAL_ADDR_MSB_REG_SHIFT;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun cmd->ring_msi_addr_lo = params.msi_addr & 0xffffffff;
795*4882a593Smuzhiyun cmd->ring_msi_addr_hi = ((uint64_t)(params.msi_addr) >> 32) & 0xffffffff;
796*4882a593Smuzhiyun cmd->msi_data = params.msi_data;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun cmd->intr_info = FIELD_PREP(
799*4882a593Smuzhiyun HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
800*4882a593Smuzhiyun params.intr_batch_cntr_thres_entries * ring_entry_sz);
801*4882a593Smuzhiyun cmd->intr_info |= FIELD_PREP(
802*4882a593Smuzhiyun HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
803*4882a593Smuzhiyun params.intr_timer_thres_us >> 3);
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun cmd->info2 = 0;
806*4882a593Smuzhiyun if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
807*4882a593Smuzhiyun cmd->info2 = FIELD_PREP(
808*4882a593Smuzhiyun HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
809*4882a593Smuzhiyun params.low_threshold);
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun ath11k_dbg(ab, ATH11k_DBG_HAL,
813*4882a593Smuzhiyun "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
814*4882a593Smuzhiyun __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
815*4882a593Smuzhiyun cmd->msi_data);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun ath11k_dbg(ab, ATH11k_DBG_HAL,
818*4882a593Smuzhiyun "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
819*4882a593Smuzhiyun ring_id, ring_type, cmd->intr_info, cmd->info2);
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
822*4882a593Smuzhiyun if (ret)
823*4882a593Smuzhiyun goto err_free;
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun return 0;
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun err_free:
828*4882a593Smuzhiyun dev_kfree_skb_any(skb);
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun return ret;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
834*4882a593Smuzhiyun
ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base * ab)835*4882a593Smuzhiyun int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun struct ath11k_dp *dp = &ab->dp;
838*4882a593Smuzhiyun struct sk_buff *skb;
839*4882a593Smuzhiyun struct htt_ver_req_cmd *cmd;
840*4882a593Smuzhiyun int len = sizeof(*cmd);
841*4882a593Smuzhiyun int ret;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun init_completion(&dp->htt_tgt_version_received);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun skb = ath11k_htc_alloc_skb(ab, len);
846*4882a593Smuzhiyun if (!skb)
847*4882a593Smuzhiyun return -ENOMEM;
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun skb_put(skb, len);
850*4882a593Smuzhiyun cmd = (struct htt_ver_req_cmd *)skb->data;
851*4882a593Smuzhiyun cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
852*4882a593Smuzhiyun HTT_H2T_MSG_TYPE_VERSION_REQ);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
855*4882a593Smuzhiyun if (ret) {
856*4882a593Smuzhiyun dev_kfree_skb_any(skb);
857*4882a593Smuzhiyun return ret;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
861*4882a593Smuzhiyun HTT_TARGET_VERSION_TIMEOUT_HZ);
862*4882a593Smuzhiyun if (ret == 0) {
863*4882a593Smuzhiyun ath11k_warn(ab, "htt target version request timed out\n");
864*4882a593Smuzhiyun return -ETIMEDOUT;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
868*4882a593Smuzhiyun ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
869*4882a593Smuzhiyun dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
870*4882a593Smuzhiyun return -ENOTSUPP;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun return 0;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k * ar,u32 mask)876*4882a593Smuzhiyun int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
879*4882a593Smuzhiyun struct ath11k_dp *dp = &ab->dp;
880*4882a593Smuzhiyun struct sk_buff *skb;
881*4882a593Smuzhiyun struct htt_ppdu_stats_cfg_cmd *cmd;
882*4882a593Smuzhiyun int len = sizeof(*cmd);
883*4882a593Smuzhiyun u8 pdev_mask;
884*4882a593Smuzhiyun int ret;
885*4882a593Smuzhiyun int i;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
888*4882a593Smuzhiyun skb = ath11k_htc_alloc_skb(ab, len);
889*4882a593Smuzhiyun if (!skb)
890*4882a593Smuzhiyun return -ENOMEM;
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun skb_put(skb, len);
893*4882a593Smuzhiyun cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
894*4882a593Smuzhiyun cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
895*4882a593Smuzhiyun HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun pdev_mask = 1 << (ar->pdev_idx + i);
898*4882a593Smuzhiyun cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
899*4882a593Smuzhiyun cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
902*4882a593Smuzhiyun if (ret) {
903*4882a593Smuzhiyun dev_kfree_skb_any(skb);
904*4882a593Smuzhiyun return ret;
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun return 0;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun
ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int rx_buf_size,struct htt_rx_ring_tlv_filter * tlv_filter)911*4882a593Smuzhiyun int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
912*4882a593Smuzhiyun int mac_id, enum hal_ring_type ring_type,
913*4882a593Smuzhiyun int rx_buf_size,
914*4882a593Smuzhiyun struct htt_rx_ring_tlv_filter *tlv_filter)
915*4882a593Smuzhiyun {
916*4882a593Smuzhiyun struct htt_rx_ring_selection_cfg_cmd *cmd;
917*4882a593Smuzhiyun struct hal_srng *srng = &ab->hal.srng_list[ring_id];
918*4882a593Smuzhiyun struct hal_srng_params params;
919*4882a593Smuzhiyun struct sk_buff *skb;
920*4882a593Smuzhiyun int len = sizeof(*cmd);
921*4882a593Smuzhiyun enum htt_srng_ring_type htt_ring_type;
922*4882a593Smuzhiyun enum htt_srng_ring_id htt_ring_id;
923*4882a593Smuzhiyun int ret;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun skb = ath11k_htc_alloc_skb(ab, len);
926*4882a593Smuzhiyun if (!skb)
927*4882a593Smuzhiyun return -ENOMEM;
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun memset(¶ms, 0, sizeof(params));
930*4882a593Smuzhiyun ath11k_hal_srng_get_params(ab, srng, ¶ms);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
933*4882a593Smuzhiyun ring_type, &htt_ring_type,
934*4882a593Smuzhiyun &htt_ring_id);
935*4882a593Smuzhiyun if (ret)
936*4882a593Smuzhiyun goto err_free;
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun skb_put(skb, len);
939*4882a593Smuzhiyun cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
940*4882a593Smuzhiyun cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
941*4882a593Smuzhiyun HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
942*4882a593Smuzhiyun if (htt_ring_type == HTT_SW_TO_HW_RING ||
943*4882a593Smuzhiyun htt_ring_type == HTT_HW_TO_SW_RING)
944*4882a593Smuzhiyun cmd->info0 |=
945*4882a593Smuzhiyun FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
946*4882a593Smuzhiyun DP_SW2HW_MACID(mac_id));
947*4882a593Smuzhiyun else
948*4882a593Smuzhiyun cmd->info0 |=
949*4882a593Smuzhiyun FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
950*4882a593Smuzhiyun mac_id);
951*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
952*4882a593Smuzhiyun htt_ring_id);
953*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
954*4882a593Smuzhiyun !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
955*4882a593Smuzhiyun cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
956*4882a593Smuzhiyun !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
959*4882a593Smuzhiyun rx_buf_size);
960*4882a593Smuzhiyun cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
961*4882a593Smuzhiyun cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
962*4882a593Smuzhiyun cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
963*4882a593Smuzhiyun cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
964*4882a593Smuzhiyun cmd->rx_filter_tlv = tlv_filter->rx_filter;
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
967*4882a593Smuzhiyun if (ret)
968*4882a593Smuzhiyun goto err_free;
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun return 0;
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun err_free:
973*4882a593Smuzhiyun dev_kfree_skb_any(skb);
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun return ret;
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun int
ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k * ar,u8 type,struct htt_ext_stats_cfg_params * cfg_params,u64 cookie)979*4882a593Smuzhiyun ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
980*4882a593Smuzhiyun struct htt_ext_stats_cfg_params *cfg_params,
981*4882a593Smuzhiyun u64 cookie)
982*4882a593Smuzhiyun {
983*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
984*4882a593Smuzhiyun struct ath11k_dp *dp = &ab->dp;
985*4882a593Smuzhiyun struct sk_buff *skb;
986*4882a593Smuzhiyun struct htt_ext_stats_cfg_cmd *cmd;
987*4882a593Smuzhiyun int len = sizeof(*cmd);
988*4882a593Smuzhiyun int ret;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun skb = ath11k_htc_alloc_skb(ab, len);
991*4882a593Smuzhiyun if (!skb)
992*4882a593Smuzhiyun return -ENOMEM;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun skb_put(skb, len);
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
997*4882a593Smuzhiyun memset(cmd, 0, sizeof(*cmd));
998*4882a593Smuzhiyun cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id;
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun cmd->hdr.stats_type = type;
1003*4882a593Smuzhiyun cmd->cfg_param0 = cfg_params->cfg0;
1004*4882a593Smuzhiyun cmd->cfg_param1 = cfg_params->cfg1;
1005*4882a593Smuzhiyun cmd->cfg_param2 = cfg_params->cfg2;
1006*4882a593Smuzhiyun cmd->cfg_param3 = cfg_params->cfg3;
1007*4882a593Smuzhiyun cmd->cookie_lsb = lower_32_bits(cookie);
1008*4882a593Smuzhiyun cmd->cookie_msb = upper_32_bits(cookie);
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1011*4882a593Smuzhiyun if (ret) {
1012*4882a593Smuzhiyun ath11k_warn(ab, "failed to send htt type stats request: %d",
1013*4882a593Smuzhiyun ret);
1014*4882a593Smuzhiyun dev_kfree_skb_any(skb);
1015*4882a593Smuzhiyun return ret;
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun return 0;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun
ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k * ar,bool reset)1021*4882a593Smuzhiyun int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun struct ath11k_pdev_dp *dp = &ar->dp;
1024*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
1025*4882a593Smuzhiyun struct htt_rx_ring_tlv_filter tlv_filter = {0};
1026*4882a593Smuzhiyun int ret = 0, ring_id = 0, i;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun if (!reset) {
1031*4882a593Smuzhiyun tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
1032*4882a593Smuzhiyun tlv_filter.pkt_filter_flags0 =
1033*4882a593Smuzhiyun HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1034*4882a593Smuzhiyun HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1035*4882a593Smuzhiyun tlv_filter.pkt_filter_flags1 =
1036*4882a593Smuzhiyun HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1037*4882a593Smuzhiyun HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1038*4882a593Smuzhiyun tlv_filter.pkt_filter_flags2 =
1039*4882a593Smuzhiyun HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1040*4882a593Smuzhiyun HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1041*4882a593Smuzhiyun tlv_filter.pkt_filter_flags3 =
1042*4882a593Smuzhiyun HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1043*4882a593Smuzhiyun HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1044*4882a593Smuzhiyun HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1045*4882a593Smuzhiyun HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun if (ab->hw_params.rxdma1_enable) {
1049*4882a593Smuzhiyun ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
1050*4882a593Smuzhiyun HAL_RXDMA_MONITOR_BUF,
1051*4882a593Smuzhiyun DP_RXDMA_REFILL_RING_SIZE,
1052*4882a593Smuzhiyun &tlv_filter);
1053*4882a593Smuzhiyun } else if (!reset) {
1054*4882a593Smuzhiyun /* set in monitor mode only */
1055*4882a593Smuzhiyun for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1056*4882a593Smuzhiyun ring_id = dp->rx_mac_buf_ring[i].ring_id;
1057*4882a593Smuzhiyun ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
1058*4882a593Smuzhiyun dp->mac_id + i,
1059*4882a593Smuzhiyun HAL_RXDMA_BUF,
1060*4882a593Smuzhiyun 1024,
1061*4882a593Smuzhiyun &tlv_filter);
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun if (ret)
1066*4882a593Smuzhiyun return ret;
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1069*4882a593Smuzhiyun ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
1070*4882a593Smuzhiyun if (!reset)
1071*4882a593Smuzhiyun tlv_filter.rx_filter =
1072*4882a593Smuzhiyun HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
1073*4882a593Smuzhiyun else
1074*4882a593Smuzhiyun tlv_filter = ath11k_mac_mon_status_filter_default;
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id,
1077*4882a593Smuzhiyun dp->mac_id + i,
1078*4882a593Smuzhiyun HAL_RXDMA_MONITOR_STATUS,
1079*4882a593Smuzhiyun DP_RXDMA_REFILL_RING_SIZE,
1080*4882a593Smuzhiyun &tlv_filter);
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun if (!ar->ab->hw_params.rxdma1_enable)
1084*4882a593Smuzhiyun mod_timer(&ar->ab->mon_reap_timer, jiffies +
1085*4882a593Smuzhiyun msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun return ret;
1088*4882a593Smuzhiyun }
1089