xref: /OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath11k/dp_rx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: BSD-3-Clause-Clear
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/ieee80211.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/skbuff.h>
9*4882a593Smuzhiyun #include <crypto/hash.h>
10*4882a593Smuzhiyun #include "core.h"
11*4882a593Smuzhiyun #include "debug.h"
12*4882a593Smuzhiyun #include "debugfs_htt_stats.h"
13*4882a593Smuzhiyun #include "debugfs_sta.h"
14*4882a593Smuzhiyun #include "hal_desc.h"
15*4882a593Smuzhiyun #include "hw.h"
16*4882a593Smuzhiyun #include "dp_rx.h"
17*4882a593Smuzhiyun #include "hal_rx.h"
18*4882a593Smuzhiyun #include "dp_tx.h"
19*4882a593Smuzhiyun #include "peer.h"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22*4882a593Smuzhiyun 
ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc * desc)23*4882a593Smuzhiyun static u8 *ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc *desc)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun 	return desc->hdr_status;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc * desc)28*4882a593Smuzhiyun static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc *desc)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	if (!(__le32_to_cpu(desc->mpdu_start.info1) &
31*4882a593Smuzhiyun 	    RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID))
32*4882a593Smuzhiyun 		return HAL_ENCRYPT_TYPE_OPEN;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
35*4882a593Smuzhiyun 			 __le32_to_cpu(desc->mpdu_start.info2));
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc * desc)38*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc *desc)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
41*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info2));
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc * desc)44*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc *desc)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
47*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info2));
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc * desc)50*4882a593Smuzhiyun static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc *desc)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
53*4882a593Smuzhiyun 			   __le32_to_cpu(desc->mpdu_start.info1));
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc * desc)56*4882a593Smuzhiyun static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc *desc)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
59*4882a593Smuzhiyun 			   __le32_to_cpu(desc->mpdu_start.info1));
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff * skb)62*4882a593Smuzhiyun static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff *skb)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
67*4882a593Smuzhiyun 	return ieee80211_has_morefrags(hdr->frame_control);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff * skb)70*4882a593Smuzhiyun static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff *skb)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
75*4882a593Smuzhiyun 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc * desc)78*4882a593Smuzhiyun static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc *desc)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
81*4882a593Smuzhiyun 			 __le32_to_cpu(desc->mpdu_start.info1));
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc * desc)84*4882a593Smuzhiyun static bool ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc *desc)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
87*4882a593Smuzhiyun 			   __le32_to_cpu(desc->attention.info2));
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc * desc)90*4882a593Smuzhiyun static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc *desc)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
93*4882a593Smuzhiyun 			   __le32_to_cpu(desc->attention.info1));
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc * desc)96*4882a593Smuzhiyun static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc *desc)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
99*4882a593Smuzhiyun 			   __le32_to_cpu(desc->attention.info1));
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc * desc)102*4882a593Smuzhiyun static bool ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc *desc)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
105*4882a593Smuzhiyun 			  __le32_to_cpu(desc->attention.info2)) ==
106*4882a593Smuzhiyun 		RX_DESC_DECRYPT_STATUS_CODE_OK);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc * desc)109*4882a593Smuzhiyun static u32 ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc *desc)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	u32 info = __le32_to_cpu(desc->attention.info1);
112*4882a593Smuzhiyun 	u32 errmap = 0;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
115*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_FCS;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
118*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
121*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
124*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
127*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
130*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
133*4882a593Smuzhiyun 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	return errmap;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc * desc)138*4882a593Smuzhiyun static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc *desc)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
141*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info1));
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc * desc)144*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc *desc)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
147*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info3));
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc * desc)150*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc *desc)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
153*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info3));
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc * desc)156*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc *desc)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
159*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info3));
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc * desc)162*4882a593Smuzhiyun static u32 ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc *desc)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	return __le32_to_cpu(desc->msdu_start.phy_meta_data);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc * desc)167*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc *desc)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
170*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_start.info3));
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc * desc)173*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc *desc)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	u8 mimo_ss_bitmap = FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
176*4882a593Smuzhiyun 				      __le32_to_cpu(desc->msdu_start.info3));
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return hweight8(mimo_ss_bitmap);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc * desc)181*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc *desc)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	return FIELD_GET(RX_MPDU_START_INFO2_TID,
184*4882a593Smuzhiyun 			 __le32_to_cpu(desc->mpdu_start.info2));
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc * desc)187*4882a593Smuzhiyun static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc *desc)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	return __le16_to_cpu(desc->mpdu_start.sw_peer_id);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc * desc)192*4882a593Smuzhiyun static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc *desc)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
195*4882a593Smuzhiyun 			 __le32_to_cpu(desc->msdu_end.info2));
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc * desc)198*4882a593Smuzhiyun static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc *desc)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
201*4882a593Smuzhiyun 			   __le32_to_cpu(desc->msdu_end.info2));
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc * desc)204*4882a593Smuzhiyun static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc *desc)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
207*4882a593Smuzhiyun 			   __le32_to_cpu(desc->msdu_end.info2));
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)210*4882a593Smuzhiyun static void ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc *fdesc,
211*4882a593Smuzhiyun 					   struct hal_rx_desc *ldesc)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	memcpy((u8 *)&fdesc->msdu_end, (u8 *)&ldesc->msdu_end,
214*4882a593Smuzhiyun 	       sizeof(struct rx_msdu_end));
215*4882a593Smuzhiyun 	memcpy((u8 *)&fdesc->attention, (u8 *)&ldesc->attention,
216*4882a593Smuzhiyun 	       sizeof(struct rx_attention));
217*4882a593Smuzhiyun 	memcpy((u8 *)&fdesc->mpdu_end, (u8 *)&ldesc->mpdu_end,
218*4882a593Smuzhiyun 	       sizeof(struct rx_mpdu_end));
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc * rx_desc)221*4882a593Smuzhiyun static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc *rx_desc)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	struct rx_attention *rx_attn;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	rx_attn = &rx_desc->attention;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
228*4882a593Smuzhiyun 			 __le32_to_cpu(rx_attn->info1));
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun 
ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc * rx_desc)231*4882a593Smuzhiyun static u32 ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc *rx_desc)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	struct rx_msdu_start *rx_msdu_start;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	rx_msdu_start = &rx_desc->msdu_start;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
238*4882a593Smuzhiyun 			 __le32_to_cpu(rx_msdu_start->info2));
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc * rx_desc)241*4882a593Smuzhiyun static u8 *ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc *rx_desc)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	u8 *rx_pkt_hdr;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	rx_pkt_hdr = &rx_desc->msdu_payload[0];
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return rx_pkt_hdr;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc * rx_desc)250*4882a593Smuzhiyun static bool ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc *rx_desc)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	u32 tlv_tag;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG,
255*4882a593Smuzhiyun 			    __le32_to_cpu(rx_desc->mpdu_start_tag));
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	return tlv_tag == HAL_RX_MPDU_START;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc * rx_desc)260*4882a593Smuzhiyun static u32 ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc *rx_desc)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	return __le16_to_cpu(rx_desc->mpdu_start.phy_ppdu_id);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
ath11k_dp_service_mon_ring(struct timer_list * t)265*4882a593Smuzhiyun static void ath11k_dp_service_mon_ring(struct timer_list *t)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
268*4882a593Smuzhiyun 	int i;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
271*4882a593Smuzhiyun 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	mod_timer(&ab->mon_reap_timer, jiffies +
274*4882a593Smuzhiyun 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)278*4882a593Smuzhiyun int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
279*4882a593Smuzhiyun 			       struct dp_rxdma_ring *rx_ring,
280*4882a593Smuzhiyun 			       int req_entries,
281*4882a593Smuzhiyun 			       enum hal_rx_buf_return_buf_manager mgr)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun 	struct hal_srng *srng;
284*4882a593Smuzhiyun 	u32 *desc;
285*4882a593Smuzhiyun 	struct sk_buff *skb;
286*4882a593Smuzhiyun 	int num_free;
287*4882a593Smuzhiyun 	int num_remain;
288*4882a593Smuzhiyun 	int buf_id;
289*4882a593Smuzhiyun 	u32 cookie;
290*4882a593Smuzhiyun 	dma_addr_t paddr;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	req_entries = min(req_entries, rx_ring->bufs_max);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
301*4882a593Smuzhiyun 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
302*4882a593Smuzhiyun 		req_entries = num_free;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	req_entries = min(num_free, req_entries);
305*4882a593Smuzhiyun 	num_remain = req_entries;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	while (num_remain > 0) {
308*4882a593Smuzhiyun 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
309*4882a593Smuzhiyun 				    DP_RX_BUFFER_ALIGN_SIZE);
310*4882a593Smuzhiyun 		if (!skb)
311*4882a593Smuzhiyun 			break;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 		if (!IS_ALIGNED((unsigned long)skb->data,
314*4882a593Smuzhiyun 				DP_RX_BUFFER_ALIGN_SIZE)) {
315*4882a593Smuzhiyun 			skb_pull(skb,
316*4882a593Smuzhiyun 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
317*4882a593Smuzhiyun 				 skb->data);
318*4882a593Smuzhiyun 		}
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 		paddr = dma_map_single(ab->dev, skb->data,
321*4882a593Smuzhiyun 				       skb->len + skb_tailroom(skb),
322*4882a593Smuzhiyun 				       DMA_FROM_DEVICE);
323*4882a593Smuzhiyun 		if (dma_mapping_error(ab->dev, paddr))
324*4882a593Smuzhiyun 			goto fail_free_skb;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 		spin_lock_bh(&rx_ring->idr_lock);
327*4882a593Smuzhiyun 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
328*4882a593Smuzhiyun 				   rx_ring->bufs_max * 3, GFP_ATOMIC);
329*4882a593Smuzhiyun 		spin_unlock_bh(&rx_ring->idr_lock);
330*4882a593Smuzhiyun 		if (buf_id < 0)
331*4882a593Smuzhiyun 			goto fail_dma_unmap;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
334*4882a593Smuzhiyun 		if (!desc)
335*4882a593Smuzhiyun 			goto fail_idr_remove;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
340*4882a593Smuzhiyun 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 		num_remain--;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
345*4882a593Smuzhiyun 	}
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	return req_entries - num_remain;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun fail_idr_remove:
354*4882a593Smuzhiyun 	spin_lock_bh(&rx_ring->idr_lock);
355*4882a593Smuzhiyun 	idr_remove(&rx_ring->bufs_idr, buf_id);
356*4882a593Smuzhiyun 	spin_unlock_bh(&rx_ring->idr_lock);
357*4882a593Smuzhiyun fail_dma_unmap:
358*4882a593Smuzhiyun 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
359*4882a593Smuzhiyun 			 DMA_FROM_DEVICE);
360*4882a593Smuzhiyun fail_free_skb:
361*4882a593Smuzhiyun 	dev_kfree_skb_any(skb);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	return req_entries - num_remain;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)370*4882a593Smuzhiyun static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
371*4882a593Smuzhiyun 					 struct dp_rxdma_ring *rx_ring)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
374*4882a593Smuzhiyun 	struct sk_buff *skb;
375*4882a593Smuzhiyun 	int buf_id;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	spin_lock_bh(&rx_ring->idr_lock);
378*4882a593Smuzhiyun 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
379*4882a593Smuzhiyun 		idr_remove(&rx_ring->bufs_idr, buf_id);
380*4882a593Smuzhiyun 		/* TODO: Understand where internal driver does this dma_unmap of
381*4882a593Smuzhiyun 		 * of rxdma_buffer.
382*4882a593Smuzhiyun 		 */
383*4882a593Smuzhiyun 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
384*4882a593Smuzhiyun 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
385*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
386*4882a593Smuzhiyun 	}
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	idr_destroy(&rx_ring->bufs_idr);
389*4882a593Smuzhiyun 	spin_unlock_bh(&rx_ring->idr_lock);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	/* if rxdma1_enable is false, mon_status_refill_ring
392*4882a593Smuzhiyun 	 * isn't setup, so don't clean.
393*4882a593Smuzhiyun 	 */
394*4882a593Smuzhiyun 	if (!ar->ab->hw_params.rxdma1_enable)
395*4882a593Smuzhiyun 		return 0;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	rx_ring = &dp->rx_mon_status_refill_ring[0];
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	spin_lock_bh(&rx_ring->idr_lock);
400*4882a593Smuzhiyun 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
401*4882a593Smuzhiyun 		idr_remove(&rx_ring->bufs_idr, buf_id);
402*4882a593Smuzhiyun 		/* XXX: Understand where internal driver does this dma_unmap of
403*4882a593Smuzhiyun 		 * of rxdma_buffer.
404*4882a593Smuzhiyun 		 */
405*4882a593Smuzhiyun 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
406*4882a593Smuzhiyun 				 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
407*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
408*4882a593Smuzhiyun 	}
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	idr_destroy(&rx_ring->bufs_idr);
411*4882a593Smuzhiyun 	spin_unlock_bh(&rx_ring->idr_lock);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	return 0;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun 
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)416*4882a593Smuzhiyun static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
419*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
420*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
421*4882a593Smuzhiyun 	int i;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	rx_ring = &dp->rxdma_mon_buf_ring;
426*4882a593Smuzhiyun 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
429*4882a593Smuzhiyun 		rx_ring = &dp->rx_mon_status_refill_ring[i];
430*4882a593Smuzhiyun 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun 
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)436*4882a593Smuzhiyun static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
437*4882a593Smuzhiyun 					  struct dp_rxdma_ring *rx_ring,
438*4882a593Smuzhiyun 					  u32 ringtype)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
441*4882a593Smuzhiyun 	int num_entries;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	num_entries = rx_ring->refill_buf_ring.size /
444*4882a593Smuzhiyun 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	rx_ring->bufs_max = num_entries;
447*4882a593Smuzhiyun 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
448*4882a593Smuzhiyun 				   HAL_RX_BUF_RBM_SW3_BM);
449*4882a593Smuzhiyun 	return 0;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun 
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)452*4882a593Smuzhiyun static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
455*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
456*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
457*4882a593Smuzhiyun 	int i;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	if (ar->ab->hw_params.rxdma1_enable) {
462*4882a593Smuzhiyun 		rx_ring = &dp->rxdma_mon_buf_ring;
463*4882a593Smuzhiyun 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
464*4882a593Smuzhiyun 	}
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
467*4882a593Smuzhiyun 		rx_ring = &dp->rx_mon_status_refill_ring[i];
468*4882a593Smuzhiyun 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
469*4882a593Smuzhiyun 	}
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	return 0;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)474*4882a593Smuzhiyun static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
477*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
478*4882a593Smuzhiyun 	int i;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
483*4882a593Smuzhiyun 		if (ab->hw_params.rx_mac_buf_ring)
484*4882a593Smuzhiyun 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
487*4882a593Smuzhiyun 		ath11k_dp_srng_cleanup(ab,
488*4882a593Smuzhiyun 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
489*4882a593Smuzhiyun 	}
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun 
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)494*4882a593Smuzhiyun void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
497*4882a593Smuzhiyun 	int i;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
500*4882a593Smuzhiyun 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun 
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)503*4882a593Smuzhiyun int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
506*4882a593Smuzhiyun 	int ret;
507*4882a593Smuzhiyun 	int i;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
510*4882a593Smuzhiyun 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
511*4882a593Smuzhiyun 					   HAL_REO_DST, i, 0,
512*4882a593Smuzhiyun 					   DP_REO_DST_RING_SIZE);
513*4882a593Smuzhiyun 		if (ret) {
514*4882a593Smuzhiyun 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
515*4882a593Smuzhiyun 			goto err_reo_cleanup;
516*4882a593Smuzhiyun 		}
517*4882a593Smuzhiyun 	}
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	return 0;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun err_reo_cleanup:
522*4882a593Smuzhiyun 	ath11k_dp_pdev_reo_cleanup(ab);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)527*4882a593Smuzhiyun static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
530*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
531*4882a593Smuzhiyun 	struct dp_srng *srng = NULL;
532*4882a593Smuzhiyun 	int i;
533*4882a593Smuzhiyun 	int ret;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	ret = ath11k_dp_srng_setup(ar->ab,
536*4882a593Smuzhiyun 				   &dp->rx_refill_buf_ring.refill_buf_ring,
537*4882a593Smuzhiyun 				   HAL_RXDMA_BUF, 0,
538*4882a593Smuzhiyun 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
539*4882a593Smuzhiyun 	if (ret) {
540*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
541*4882a593Smuzhiyun 		return ret;
542*4882a593Smuzhiyun 	}
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	if (ar->ab->hw_params.rx_mac_buf_ring) {
545*4882a593Smuzhiyun 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
546*4882a593Smuzhiyun 			ret = ath11k_dp_srng_setup(ar->ab,
547*4882a593Smuzhiyun 						   &dp->rx_mac_buf_ring[i],
548*4882a593Smuzhiyun 						   HAL_RXDMA_BUF, 1,
549*4882a593Smuzhiyun 						   dp->mac_id + i, 1024);
550*4882a593Smuzhiyun 			if (ret) {
551*4882a593Smuzhiyun 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
552*4882a593Smuzhiyun 					    i);
553*4882a593Smuzhiyun 				return ret;
554*4882a593Smuzhiyun 			}
555*4882a593Smuzhiyun 		}
556*4882a593Smuzhiyun 	}
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
559*4882a593Smuzhiyun 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
560*4882a593Smuzhiyun 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
561*4882a593Smuzhiyun 					   DP_RXDMA_ERR_DST_RING_SIZE);
562*4882a593Smuzhiyun 		if (ret) {
563*4882a593Smuzhiyun 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
564*4882a593Smuzhiyun 			return ret;
565*4882a593Smuzhiyun 		}
566*4882a593Smuzhiyun 	}
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
569*4882a593Smuzhiyun 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
570*4882a593Smuzhiyun 		ret = ath11k_dp_srng_setup(ar->ab,
571*4882a593Smuzhiyun 					   srng,
572*4882a593Smuzhiyun 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
573*4882a593Smuzhiyun 					   DP_RXDMA_MON_STATUS_RING_SIZE);
574*4882a593Smuzhiyun 		if (ret) {
575*4882a593Smuzhiyun 			ath11k_warn(ar->ab,
576*4882a593Smuzhiyun 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
577*4882a593Smuzhiyun 			return ret;
578*4882a593Smuzhiyun 		}
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	/* if rxdma1_enable is false, then it doesn't need
582*4882a593Smuzhiyun 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
583*4882a593Smuzhiyun 	 * and rxdma_mon_desc_ring.
584*4882a593Smuzhiyun 	 * init reap timer for QCA6390.
585*4882a593Smuzhiyun 	 */
586*4882a593Smuzhiyun 	if (!ar->ab->hw_params.rxdma1_enable) {
587*4882a593Smuzhiyun 		//init mon status buffer reap timer
588*4882a593Smuzhiyun 		timer_setup(&ar->ab->mon_reap_timer,
589*4882a593Smuzhiyun 			    ath11k_dp_service_mon_ring, 0);
590*4882a593Smuzhiyun 		return 0;
591*4882a593Smuzhiyun 	}
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	ret = ath11k_dp_srng_setup(ar->ab,
594*4882a593Smuzhiyun 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
595*4882a593Smuzhiyun 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
596*4882a593Smuzhiyun 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
597*4882a593Smuzhiyun 	if (ret) {
598*4882a593Smuzhiyun 		ath11k_warn(ar->ab,
599*4882a593Smuzhiyun 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
600*4882a593Smuzhiyun 		return ret;
601*4882a593Smuzhiyun 	}
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
604*4882a593Smuzhiyun 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
605*4882a593Smuzhiyun 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
606*4882a593Smuzhiyun 	if (ret) {
607*4882a593Smuzhiyun 		ath11k_warn(ar->ab,
608*4882a593Smuzhiyun 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
609*4882a593Smuzhiyun 		return ret;
610*4882a593Smuzhiyun 	}
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
613*4882a593Smuzhiyun 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
614*4882a593Smuzhiyun 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
615*4882a593Smuzhiyun 	if (ret) {
616*4882a593Smuzhiyun 		ath11k_warn(ar->ab,
617*4882a593Smuzhiyun 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
618*4882a593Smuzhiyun 		return ret;
619*4882a593Smuzhiyun 	}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	return 0;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun 
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)624*4882a593Smuzhiyun void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
627*4882a593Smuzhiyun 	struct dp_reo_cmd *cmd, *tmp;
628*4882a593Smuzhiyun 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	spin_lock_bh(&dp->reo_cmd_lock);
631*4882a593Smuzhiyun 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
632*4882a593Smuzhiyun 		list_del(&cmd->list);
633*4882a593Smuzhiyun 		dma_unmap_single(ab->dev, cmd->data.paddr,
634*4882a593Smuzhiyun 				 cmd->data.size, DMA_BIDIRECTIONAL);
635*4882a593Smuzhiyun 		kfree(cmd->data.vaddr);
636*4882a593Smuzhiyun 		kfree(cmd);
637*4882a593Smuzhiyun 	}
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	list_for_each_entry_safe(cmd_cache, tmp_cache,
640*4882a593Smuzhiyun 				 &dp->reo_cmd_cache_flush_list, list) {
641*4882a593Smuzhiyun 		list_del(&cmd_cache->list);
642*4882a593Smuzhiyun 		dp->reo_cmd_cache_flush_count--;
643*4882a593Smuzhiyun 		dma_unmap_single(ab->dev, cmd_cache->data.paddr,
644*4882a593Smuzhiyun 				 cmd_cache->data.size, DMA_BIDIRECTIONAL);
645*4882a593Smuzhiyun 		kfree(cmd_cache->data.vaddr);
646*4882a593Smuzhiyun 		kfree(cmd_cache);
647*4882a593Smuzhiyun 	}
648*4882a593Smuzhiyun 	spin_unlock_bh(&dp->reo_cmd_lock);
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun 
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)651*4882a593Smuzhiyun static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
652*4882a593Smuzhiyun 				   enum hal_reo_cmd_status status)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid = ctx;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	if (status != HAL_REO_CMD_SUCCESS)
657*4882a593Smuzhiyun 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
658*4882a593Smuzhiyun 			    rx_tid->tid, status);
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
661*4882a593Smuzhiyun 			 DMA_BIDIRECTIONAL);
662*4882a593Smuzhiyun 	kfree(rx_tid->vaddr);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun 
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)665*4882a593Smuzhiyun static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
666*4882a593Smuzhiyun 				      struct dp_rx_tid *rx_tid)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	struct ath11k_hal_reo_cmd cmd = {0};
669*4882a593Smuzhiyun 	unsigned long tot_desc_sz, desc_sz;
670*4882a593Smuzhiyun 	int ret;
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	tot_desc_sz = rx_tid->size;
673*4882a593Smuzhiyun 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	while (tot_desc_sz > desc_sz) {
676*4882a593Smuzhiyun 		tot_desc_sz -= desc_sz;
677*4882a593Smuzhiyun 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
678*4882a593Smuzhiyun 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
679*4882a593Smuzhiyun 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
680*4882a593Smuzhiyun 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
681*4882a593Smuzhiyun 						NULL);
682*4882a593Smuzhiyun 		if (ret)
683*4882a593Smuzhiyun 			ath11k_warn(ab,
684*4882a593Smuzhiyun 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
685*4882a593Smuzhiyun 				    rx_tid->tid, ret);
686*4882a593Smuzhiyun 	}
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	memset(&cmd, 0, sizeof(cmd));
689*4882a593Smuzhiyun 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
690*4882a593Smuzhiyun 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
691*4882a593Smuzhiyun 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
692*4882a593Smuzhiyun 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
693*4882a593Smuzhiyun 					HAL_REO_CMD_FLUSH_CACHE,
694*4882a593Smuzhiyun 					&cmd, ath11k_dp_reo_cmd_free);
695*4882a593Smuzhiyun 	if (ret) {
696*4882a593Smuzhiyun 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
697*4882a593Smuzhiyun 			   rx_tid->tid, ret);
698*4882a593Smuzhiyun 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
699*4882a593Smuzhiyun 				 DMA_BIDIRECTIONAL);
700*4882a593Smuzhiyun 		kfree(rx_tid->vaddr);
701*4882a593Smuzhiyun 	}
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun 
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)704*4882a593Smuzhiyun static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
705*4882a593Smuzhiyun 				      enum hal_reo_cmd_status status)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun 	struct ath11k_base *ab = dp->ab;
708*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid = ctx;
709*4882a593Smuzhiyun 	struct dp_reo_cache_flush_elem *elem, *tmp;
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	if (status == HAL_REO_CMD_DRAIN) {
712*4882a593Smuzhiyun 		goto free_desc;
713*4882a593Smuzhiyun 	} else if (status != HAL_REO_CMD_SUCCESS) {
714*4882a593Smuzhiyun 		/* Shouldn't happen! Cleanup in case of other failure? */
715*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
716*4882a593Smuzhiyun 			    rx_tid->tid, status);
717*4882a593Smuzhiyun 		return;
718*4882a593Smuzhiyun 	}
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
721*4882a593Smuzhiyun 	if (!elem)
722*4882a593Smuzhiyun 		goto free_desc;
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	elem->ts = jiffies;
725*4882a593Smuzhiyun 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	spin_lock_bh(&dp->reo_cmd_lock);
728*4882a593Smuzhiyun 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
729*4882a593Smuzhiyun 	dp->reo_cmd_cache_flush_count++;
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	/* Flush and invalidate aged REO desc from HW cache */
732*4882a593Smuzhiyun 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
733*4882a593Smuzhiyun 				 list) {
734*4882a593Smuzhiyun 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
735*4882a593Smuzhiyun 		    time_after(jiffies, elem->ts +
736*4882a593Smuzhiyun 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
737*4882a593Smuzhiyun 			list_del(&elem->list);
738*4882a593Smuzhiyun 			dp->reo_cmd_cache_flush_count--;
739*4882a593Smuzhiyun 			spin_unlock_bh(&dp->reo_cmd_lock);
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun 			ath11k_dp_reo_cache_flush(ab, &elem->data);
742*4882a593Smuzhiyun 			kfree(elem);
743*4882a593Smuzhiyun 			spin_lock_bh(&dp->reo_cmd_lock);
744*4882a593Smuzhiyun 		}
745*4882a593Smuzhiyun 	}
746*4882a593Smuzhiyun 	spin_unlock_bh(&dp->reo_cmd_lock);
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	return;
749*4882a593Smuzhiyun free_desc:
750*4882a593Smuzhiyun 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
751*4882a593Smuzhiyun 			 DMA_BIDIRECTIONAL);
752*4882a593Smuzhiyun 	kfree(rx_tid->vaddr);
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun 
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)755*4882a593Smuzhiyun void ath11k_peer_rx_tid_delete(struct ath11k *ar,
756*4882a593Smuzhiyun 			       struct ath11k_peer *peer, u8 tid)
757*4882a593Smuzhiyun {
758*4882a593Smuzhiyun 	struct ath11k_hal_reo_cmd cmd = {0};
759*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
760*4882a593Smuzhiyun 	int ret;
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun 	if (!rx_tid->active)
763*4882a593Smuzhiyun 		return;
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
766*4882a593Smuzhiyun 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
767*4882a593Smuzhiyun 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
768*4882a593Smuzhiyun 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
769*4882a593Smuzhiyun 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
770*4882a593Smuzhiyun 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
771*4882a593Smuzhiyun 					ath11k_dp_rx_tid_del_func);
772*4882a593Smuzhiyun 	if (ret) {
773*4882a593Smuzhiyun 		ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
774*4882a593Smuzhiyun 			   tid, ret);
775*4882a593Smuzhiyun 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
776*4882a593Smuzhiyun 				 DMA_BIDIRECTIONAL);
777*4882a593Smuzhiyun 		kfree(rx_tid->vaddr);
778*4882a593Smuzhiyun 	}
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun 	rx_tid->active = false;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun 
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)783*4882a593Smuzhiyun static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
784*4882a593Smuzhiyun 					 u32 *link_desc,
785*4882a593Smuzhiyun 					 enum hal_wbm_rel_bm_act action)
786*4882a593Smuzhiyun {
787*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
788*4882a593Smuzhiyun 	struct hal_srng *srng;
789*4882a593Smuzhiyun 	u32 *desc;
790*4882a593Smuzhiyun 	int ret = 0;
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
799*4882a593Smuzhiyun 	if (!desc) {
800*4882a593Smuzhiyun 		ret = -ENOBUFS;
801*4882a593Smuzhiyun 		goto exit;
802*4882a593Smuzhiyun 	}
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
805*4882a593Smuzhiyun 					 action);
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun exit:
808*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 	return ret;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun 
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)815*4882a593Smuzhiyun static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun 	struct ath11k_base *ab = rx_tid->ab;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	lockdep_assert_held(&ab->base_lock);
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	if (rx_tid->dst_ring_desc) {
822*4882a593Smuzhiyun 		if (rel_link_desc)
823*4882a593Smuzhiyun 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
824*4882a593Smuzhiyun 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
825*4882a593Smuzhiyun 		kfree(rx_tid->dst_ring_desc);
826*4882a593Smuzhiyun 		rx_tid->dst_ring_desc = NULL;
827*4882a593Smuzhiyun 	}
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	rx_tid->cur_sn = 0;
830*4882a593Smuzhiyun 	rx_tid->last_frag_no = 0;
831*4882a593Smuzhiyun 	rx_tid->rx_frag_bitmap = 0;
832*4882a593Smuzhiyun 	__skb_queue_purge(&rx_tid->rx_frags);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun 
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)835*4882a593Smuzhiyun void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
838*4882a593Smuzhiyun 	int i;
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	lockdep_assert_held(&ar->ab->base_lock);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
843*4882a593Smuzhiyun 		rx_tid = &peer->rx_tid[i];
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 		spin_unlock_bh(&ar->ab->base_lock);
846*4882a593Smuzhiyun 		del_timer_sync(&rx_tid->frag_timer);
847*4882a593Smuzhiyun 		spin_lock_bh(&ar->ab->base_lock);
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
850*4882a593Smuzhiyun 	}
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun 
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)853*4882a593Smuzhiyun void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
854*4882a593Smuzhiyun {
855*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
856*4882a593Smuzhiyun 	int i;
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	lockdep_assert_held(&ar->ab->base_lock);
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
861*4882a593Smuzhiyun 		rx_tid = &peer->rx_tid[i];
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 		ath11k_peer_rx_tid_delete(ar, peer, i);
864*4882a593Smuzhiyun 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 		spin_unlock_bh(&ar->ab->base_lock);
867*4882a593Smuzhiyun 		del_timer_sync(&rx_tid->frag_timer);
868*4882a593Smuzhiyun 		spin_lock_bh(&ar->ab->base_lock);
869*4882a593Smuzhiyun 	}
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun 
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)872*4882a593Smuzhiyun static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
873*4882a593Smuzhiyun 					 struct ath11k_peer *peer,
874*4882a593Smuzhiyun 					 struct dp_rx_tid *rx_tid,
875*4882a593Smuzhiyun 					 u32 ba_win_sz, u16 ssn,
876*4882a593Smuzhiyun 					 bool update_ssn)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun 	struct ath11k_hal_reo_cmd cmd = {0};
879*4882a593Smuzhiyun 	int ret;
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
882*4882a593Smuzhiyun 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
883*4882a593Smuzhiyun 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
884*4882a593Smuzhiyun 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
885*4882a593Smuzhiyun 	cmd.ba_window_size = ba_win_sz;
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	if (update_ssn) {
888*4882a593Smuzhiyun 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
889*4882a593Smuzhiyun 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
890*4882a593Smuzhiyun 	}
891*4882a593Smuzhiyun 
892*4882a593Smuzhiyun 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
893*4882a593Smuzhiyun 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
894*4882a593Smuzhiyun 					NULL);
895*4882a593Smuzhiyun 	if (ret) {
896*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
897*4882a593Smuzhiyun 			    rx_tid->tid, ret);
898*4882a593Smuzhiyun 		return ret;
899*4882a593Smuzhiyun 	}
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	rx_tid->ba_win_sz = ba_win_sz;
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 	return 0;
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun 
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)906*4882a593Smuzhiyun static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
907*4882a593Smuzhiyun 				      const u8 *peer_mac, int vdev_id, u8 tid)
908*4882a593Smuzhiyun {
909*4882a593Smuzhiyun 	struct ath11k_peer *peer;
910*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
915*4882a593Smuzhiyun 	if (!peer) {
916*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
917*4882a593Smuzhiyun 		goto unlock_exit;
918*4882a593Smuzhiyun 	}
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	rx_tid = &peer->rx_tid[tid];
921*4882a593Smuzhiyun 	if (!rx_tid->active)
922*4882a593Smuzhiyun 		goto unlock_exit;
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
925*4882a593Smuzhiyun 			 DMA_BIDIRECTIONAL);
926*4882a593Smuzhiyun 	kfree(rx_tid->vaddr);
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun 	rx_tid->active = false;
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun unlock_exit:
931*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun 
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)934*4882a593Smuzhiyun int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
935*4882a593Smuzhiyun 			     u8 tid, u32 ba_win_sz, u16 ssn,
936*4882a593Smuzhiyun 			     enum hal_pn_type pn_type)
937*4882a593Smuzhiyun {
938*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
939*4882a593Smuzhiyun 	struct ath11k_peer *peer;
940*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
941*4882a593Smuzhiyun 	u32 hw_desc_sz;
942*4882a593Smuzhiyun 	u32 *addr_aligned;
943*4882a593Smuzhiyun 	void *vaddr;
944*4882a593Smuzhiyun 	dma_addr_t paddr;
945*4882a593Smuzhiyun 	int ret;
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
950*4882a593Smuzhiyun 	if (!peer) {
951*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
952*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
953*4882a593Smuzhiyun 		return -ENOENT;
954*4882a593Smuzhiyun 	}
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 	rx_tid = &peer->rx_tid[tid];
957*4882a593Smuzhiyun 	/* Update the tid queue if it is already setup */
958*4882a593Smuzhiyun 	if (rx_tid->active) {
959*4882a593Smuzhiyun 		paddr = rx_tid->paddr;
960*4882a593Smuzhiyun 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
961*4882a593Smuzhiyun 						    ba_win_sz, ssn, true);
962*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
963*4882a593Smuzhiyun 		if (ret) {
964*4882a593Smuzhiyun 			ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
965*4882a593Smuzhiyun 			return ret;
966*4882a593Smuzhiyun 		}
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
969*4882a593Smuzhiyun 							     peer_mac, paddr,
970*4882a593Smuzhiyun 							     tid, 1, ba_win_sz);
971*4882a593Smuzhiyun 		if (ret)
972*4882a593Smuzhiyun 			ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
973*4882a593Smuzhiyun 				    tid, ret);
974*4882a593Smuzhiyun 		return ret;
975*4882a593Smuzhiyun 	}
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	rx_tid->tid = tid;
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun 	rx_tid->ba_win_sz = ba_win_sz;
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 	/* TODO: Optimize the memory allocation for qos tid based on the
982*4882a593Smuzhiyun 	 * the actual BA window size in REO tid update path.
983*4882a593Smuzhiyun 	 */
984*4882a593Smuzhiyun 	if (tid == HAL_DESC_REO_NON_QOS_TID)
985*4882a593Smuzhiyun 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
986*4882a593Smuzhiyun 	else
987*4882a593Smuzhiyun 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
990*4882a593Smuzhiyun 	if (!vaddr) {
991*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
992*4882a593Smuzhiyun 		return -ENOMEM;
993*4882a593Smuzhiyun 	}
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
998*4882a593Smuzhiyun 				   ssn, pn_type);
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1001*4882a593Smuzhiyun 			       DMA_BIDIRECTIONAL);
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	ret = dma_mapping_error(ab->dev, paddr);
1004*4882a593Smuzhiyun 	if (ret) {
1005*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
1006*4882a593Smuzhiyun 		goto err_mem_free;
1007*4882a593Smuzhiyun 	}
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	rx_tid->vaddr = vaddr;
1010*4882a593Smuzhiyun 	rx_tid->paddr = paddr;
1011*4882a593Smuzhiyun 	rx_tid->size = hw_desc_sz;
1012*4882a593Smuzhiyun 	rx_tid->active = true;
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1017*4882a593Smuzhiyun 						     paddr, tid, 1, ba_win_sz);
1018*4882a593Smuzhiyun 	if (ret) {
1019*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1020*4882a593Smuzhiyun 			    tid, ret);
1021*4882a593Smuzhiyun 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1022*4882a593Smuzhiyun 	}
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	return ret;
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun err_mem_free:
1027*4882a593Smuzhiyun 	kfree(vaddr);
1028*4882a593Smuzhiyun 
1029*4882a593Smuzhiyun 	return ret;
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun 
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1032*4882a593Smuzhiyun int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1033*4882a593Smuzhiyun 			     struct ieee80211_ampdu_params *params)
1034*4882a593Smuzhiyun {
1035*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
1036*4882a593Smuzhiyun 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1037*4882a593Smuzhiyun 	int vdev_id = arsta->arvif->vdev_id;
1038*4882a593Smuzhiyun 	int ret;
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1041*4882a593Smuzhiyun 				       params->tid, params->buf_size,
1042*4882a593Smuzhiyun 				       params->ssn, arsta->pn_type);
1043*4882a593Smuzhiyun 	if (ret)
1044*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun 	return ret;
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun 
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1049*4882a593Smuzhiyun int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1050*4882a593Smuzhiyun 			    struct ieee80211_ampdu_params *params)
1051*4882a593Smuzhiyun {
1052*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
1053*4882a593Smuzhiyun 	struct ath11k_peer *peer;
1054*4882a593Smuzhiyun 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1055*4882a593Smuzhiyun 	int vdev_id = arsta->arvif->vdev_id;
1056*4882a593Smuzhiyun 	dma_addr_t paddr;
1057*4882a593Smuzhiyun 	bool active;
1058*4882a593Smuzhiyun 	int ret;
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1063*4882a593Smuzhiyun 	if (!peer) {
1064*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1065*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
1066*4882a593Smuzhiyun 		return -ENOENT;
1067*4882a593Smuzhiyun 	}
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	paddr = peer->rx_tid[params->tid].paddr;
1070*4882a593Smuzhiyun 	active = peer->rx_tid[params->tid].active;
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	if (!active) {
1073*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
1074*4882a593Smuzhiyun 		return 0;
1075*4882a593Smuzhiyun 	}
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1078*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
1079*4882a593Smuzhiyun 	if (ret) {
1080*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1081*4882a593Smuzhiyun 			    params->tid, ret);
1082*4882a593Smuzhiyun 		return ret;
1083*4882a593Smuzhiyun 	}
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1086*4882a593Smuzhiyun 						     params->sta->addr, paddr,
1087*4882a593Smuzhiyun 						     params->tid, 1, 1);
1088*4882a593Smuzhiyun 	if (ret)
1089*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1090*4882a593Smuzhiyun 			    ret);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	return ret;
1093*4882a593Smuzhiyun }
1094*4882a593Smuzhiyun 
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1095*4882a593Smuzhiyun int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1096*4882a593Smuzhiyun 				       const u8 *peer_addr,
1097*4882a593Smuzhiyun 				       enum set_key_cmd key_cmd,
1098*4882a593Smuzhiyun 				       struct ieee80211_key_conf *key)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun 	struct ath11k *ar = arvif->ar;
1101*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
1102*4882a593Smuzhiyun 	struct ath11k_hal_reo_cmd cmd = {0};
1103*4882a593Smuzhiyun 	struct ath11k_peer *peer;
1104*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
1105*4882a593Smuzhiyun 	u8 tid;
1106*4882a593Smuzhiyun 	int ret = 0;
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1109*4882a593Smuzhiyun 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1110*4882a593Smuzhiyun 	 * for now.
1111*4882a593Smuzhiyun 	 */
1112*4882a593Smuzhiyun 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1113*4882a593Smuzhiyun 		return 0;
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1116*4882a593Smuzhiyun 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1117*4882a593Smuzhiyun 		    HAL_REO_CMD_UPD0_PN_SIZE |
1118*4882a593Smuzhiyun 		    HAL_REO_CMD_UPD0_PN_VALID |
1119*4882a593Smuzhiyun 		    HAL_REO_CMD_UPD0_PN_CHECK |
1120*4882a593Smuzhiyun 		    HAL_REO_CMD_UPD0_SVLD;
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	switch (key->cipher) {
1123*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_TKIP:
1124*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_CCMP:
1125*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_CCMP_256:
1126*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_GCMP:
1127*4882a593Smuzhiyun 	case WLAN_CIPHER_SUITE_GCMP_256:
1128*4882a593Smuzhiyun 		if (key_cmd == SET_KEY) {
1129*4882a593Smuzhiyun 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1130*4882a593Smuzhiyun 			cmd.pn_size = 48;
1131*4882a593Smuzhiyun 		}
1132*4882a593Smuzhiyun 		break;
1133*4882a593Smuzhiyun 	default:
1134*4882a593Smuzhiyun 		break;
1135*4882a593Smuzhiyun 	}
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1140*4882a593Smuzhiyun 	if (!peer) {
1141*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1142*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
1143*4882a593Smuzhiyun 		return -ENOENT;
1144*4882a593Smuzhiyun 	}
1145*4882a593Smuzhiyun 
1146*4882a593Smuzhiyun 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1147*4882a593Smuzhiyun 		rx_tid = &peer->rx_tid[tid];
1148*4882a593Smuzhiyun 		if (!rx_tid->active)
1149*4882a593Smuzhiyun 			continue;
1150*4882a593Smuzhiyun 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1151*4882a593Smuzhiyun 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1152*4882a593Smuzhiyun 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1153*4882a593Smuzhiyun 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1154*4882a593Smuzhiyun 						&cmd, NULL);
1155*4882a593Smuzhiyun 		if (ret) {
1156*4882a593Smuzhiyun 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1157*4882a593Smuzhiyun 				    tid, ret);
1158*4882a593Smuzhiyun 			break;
1159*4882a593Smuzhiyun 		}
1160*4882a593Smuzhiyun 	}
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	spin_unlock_bh(&ar->ab->base_lock);
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun 	return ret;
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun 
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1167*4882a593Smuzhiyun static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1168*4882a593Smuzhiyun 					     u16 peer_id)
1169*4882a593Smuzhiyun {
1170*4882a593Smuzhiyun 	int i;
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1173*4882a593Smuzhiyun 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1174*4882a593Smuzhiyun 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1175*4882a593Smuzhiyun 				return i;
1176*4882a593Smuzhiyun 		} else {
1177*4882a593Smuzhiyun 			return i;
1178*4882a593Smuzhiyun 		}
1179*4882a593Smuzhiyun 	}
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	return -EINVAL;
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun 
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1184*4882a593Smuzhiyun static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1185*4882a593Smuzhiyun 					   u16 tag, u16 len, const void *ptr,
1186*4882a593Smuzhiyun 					   void *data)
1187*4882a593Smuzhiyun {
1188*4882a593Smuzhiyun 	struct htt_ppdu_stats_info *ppdu_info;
1189*4882a593Smuzhiyun 	struct htt_ppdu_user_stats *user_stats;
1190*4882a593Smuzhiyun 	int cur_user;
1191*4882a593Smuzhiyun 	u16 peer_id;
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun 	ppdu_info = (struct htt_ppdu_stats_info *)data;
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun 	switch (tag) {
1196*4882a593Smuzhiyun 	case HTT_PPDU_STATS_TAG_COMMON:
1197*4882a593Smuzhiyun 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1198*4882a593Smuzhiyun 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1199*4882a593Smuzhiyun 				    len, tag);
1200*4882a593Smuzhiyun 			return -EINVAL;
1201*4882a593Smuzhiyun 		}
1202*4882a593Smuzhiyun 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1203*4882a593Smuzhiyun 		       sizeof(struct htt_ppdu_stats_common));
1204*4882a593Smuzhiyun 		break;
1205*4882a593Smuzhiyun 	case HTT_PPDU_STATS_TAG_USR_RATE:
1206*4882a593Smuzhiyun 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1207*4882a593Smuzhiyun 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1208*4882a593Smuzhiyun 				    len, tag);
1209*4882a593Smuzhiyun 			return -EINVAL;
1210*4882a593Smuzhiyun 		}
1211*4882a593Smuzhiyun 
1212*4882a593Smuzhiyun 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1213*4882a593Smuzhiyun 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1214*4882a593Smuzhiyun 						      peer_id);
1215*4882a593Smuzhiyun 		if (cur_user < 0)
1216*4882a593Smuzhiyun 			return -EINVAL;
1217*4882a593Smuzhiyun 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1218*4882a593Smuzhiyun 		user_stats->peer_id = peer_id;
1219*4882a593Smuzhiyun 		user_stats->is_valid_peer_id = true;
1220*4882a593Smuzhiyun 		memcpy((void *)&user_stats->rate, ptr,
1221*4882a593Smuzhiyun 		       sizeof(struct htt_ppdu_stats_user_rate));
1222*4882a593Smuzhiyun 		user_stats->tlv_flags |= BIT(tag);
1223*4882a593Smuzhiyun 		break;
1224*4882a593Smuzhiyun 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1225*4882a593Smuzhiyun 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1226*4882a593Smuzhiyun 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1227*4882a593Smuzhiyun 				    len, tag);
1228*4882a593Smuzhiyun 			return -EINVAL;
1229*4882a593Smuzhiyun 		}
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1232*4882a593Smuzhiyun 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1233*4882a593Smuzhiyun 						      peer_id);
1234*4882a593Smuzhiyun 		if (cur_user < 0)
1235*4882a593Smuzhiyun 			return -EINVAL;
1236*4882a593Smuzhiyun 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1237*4882a593Smuzhiyun 		user_stats->peer_id = peer_id;
1238*4882a593Smuzhiyun 		user_stats->is_valid_peer_id = true;
1239*4882a593Smuzhiyun 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1240*4882a593Smuzhiyun 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1241*4882a593Smuzhiyun 		user_stats->tlv_flags |= BIT(tag);
1242*4882a593Smuzhiyun 		break;
1243*4882a593Smuzhiyun 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1244*4882a593Smuzhiyun 		if (len <
1245*4882a593Smuzhiyun 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1246*4882a593Smuzhiyun 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1247*4882a593Smuzhiyun 				    len, tag);
1248*4882a593Smuzhiyun 			return -EINVAL;
1249*4882a593Smuzhiyun 		}
1250*4882a593Smuzhiyun 
1251*4882a593Smuzhiyun 		peer_id =
1252*4882a593Smuzhiyun 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1253*4882a593Smuzhiyun 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1254*4882a593Smuzhiyun 						      peer_id);
1255*4882a593Smuzhiyun 		if (cur_user < 0)
1256*4882a593Smuzhiyun 			return -EINVAL;
1257*4882a593Smuzhiyun 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1258*4882a593Smuzhiyun 		user_stats->peer_id = peer_id;
1259*4882a593Smuzhiyun 		user_stats->is_valid_peer_id = true;
1260*4882a593Smuzhiyun 		memcpy((void *)&user_stats->ack_ba, ptr,
1261*4882a593Smuzhiyun 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1262*4882a593Smuzhiyun 		user_stats->tlv_flags |= BIT(tag);
1263*4882a593Smuzhiyun 		break;
1264*4882a593Smuzhiyun 	}
1265*4882a593Smuzhiyun 	return 0;
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun 
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1268*4882a593Smuzhiyun int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1269*4882a593Smuzhiyun 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1270*4882a593Smuzhiyun 				       const void *ptr, void *data),
1271*4882a593Smuzhiyun 			   void *data)
1272*4882a593Smuzhiyun {
1273*4882a593Smuzhiyun 	const struct htt_tlv *tlv;
1274*4882a593Smuzhiyun 	const void *begin = ptr;
1275*4882a593Smuzhiyun 	u16 tlv_tag, tlv_len;
1276*4882a593Smuzhiyun 	int ret = -EINVAL;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	while (len > 0) {
1279*4882a593Smuzhiyun 		if (len < sizeof(*tlv)) {
1280*4882a593Smuzhiyun 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1281*4882a593Smuzhiyun 				   ptr - begin, len, sizeof(*tlv));
1282*4882a593Smuzhiyun 			return -EINVAL;
1283*4882a593Smuzhiyun 		}
1284*4882a593Smuzhiyun 		tlv = (struct htt_tlv *)ptr;
1285*4882a593Smuzhiyun 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1286*4882a593Smuzhiyun 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1287*4882a593Smuzhiyun 		ptr += sizeof(*tlv);
1288*4882a593Smuzhiyun 		len -= sizeof(*tlv);
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 		if (tlv_len > len) {
1291*4882a593Smuzhiyun 			ath11k_err(ab, "htt tlv parse failure of tag %hhu at byte %zd (%zu bytes left, %hhu expected)\n",
1292*4882a593Smuzhiyun 				   tlv_tag, ptr - begin, len, tlv_len);
1293*4882a593Smuzhiyun 			return -EINVAL;
1294*4882a593Smuzhiyun 		}
1295*4882a593Smuzhiyun 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1296*4882a593Smuzhiyun 		if (ret == -ENOMEM)
1297*4882a593Smuzhiyun 			return ret;
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 		ptr += tlv_len;
1300*4882a593Smuzhiyun 		len -= tlv_len;
1301*4882a593Smuzhiyun 	}
1302*4882a593Smuzhiyun 	return 0;
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun 
ath11k_he_gi_to_nl80211_he_gi(u8 sgi)1305*4882a593Smuzhiyun static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi)
1306*4882a593Smuzhiyun {
1307*4882a593Smuzhiyun 	u32 ret = 0;
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	switch (sgi) {
1310*4882a593Smuzhiyun 	case RX_MSDU_START_SGI_0_8_US:
1311*4882a593Smuzhiyun 		ret = NL80211_RATE_INFO_HE_GI_0_8;
1312*4882a593Smuzhiyun 		break;
1313*4882a593Smuzhiyun 	case RX_MSDU_START_SGI_1_6_US:
1314*4882a593Smuzhiyun 		ret = NL80211_RATE_INFO_HE_GI_1_6;
1315*4882a593Smuzhiyun 		break;
1316*4882a593Smuzhiyun 	case RX_MSDU_START_SGI_3_2_US:
1317*4882a593Smuzhiyun 		ret = NL80211_RATE_INFO_HE_GI_3_2;
1318*4882a593Smuzhiyun 		break;
1319*4882a593Smuzhiyun 	}
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun 	return ret;
1322*4882a593Smuzhiyun }
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1325*4882a593Smuzhiyun ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1326*4882a593Smuzhiyun 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1327*4882a593Smuzhiyun {
1328*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
1329*4882a593Smuzhiyun 	struct ath11k_peer *peer;
1330*4882a593Smuzhiyun 	struct ieee80211_sta *sta;
1331*4882a593Smuzhiyun 	struct ath11k_sta *arsta;
1332*4882a593Smuzhiyun 	struct htt_ppdu_stats_user_rate *user_rate;
1333*4882a593Smuzhiyun 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1334*4882a593Smuzhiyun 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1335*4882a593Smuzhiyun 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1336*4882a593Smuzhiyun 	int ret;
1337*4882a593Smuzhiyun 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1338*4882a593Smuzhiyun 	u32 succ_bytes = 0;
1339*4882a593Smuzhiyun 	u16 rate = 0, succ_pkts = 0;
1340*4882a593Smuzhiyun 	u32 tx_duration = 0;
1341*4882a593Smuzhiyun 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1342*4882a593Smuzhiyun 	bool is_ampdu = false;
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	if (!usr_stats)
1345*4882a593Smuzhiyun 		return;
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1348*4882a593Smuzhiyun 		return;
1349*4882a593Smuzhiyun 
1350*4882a593Smuzhiyun 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1351*4882a593Smuzhiyun 		is_ampdu =
1352*4882a593Smuzhiyun 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun 	if (usr_stats->tlv_flags &
1355*4882a593Smuzhiyun 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1356*4882a593Smuzhiyun 		succ_bytes = usr_stats->ack_ba.success_bytes;
1357*4882a593Smuzhiyun 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1358*4882a593Smuzhiyun 				      usr_stats->ack_ba.info);
1359*4882a593Smuzhiyun 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1360*4882a593Smuzhiyun 				usr_stats->ack_ba.info);
1361*4882a593Smuzhiyun 	}
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	if (common->fes_duration_us)
1364*4882a593Smuzhiyun 		tx_duration = common->fes_duration_us;
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	user_rate = &usr_stats->rate;
1367*4882a593Smuzhiyun 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1368*4882a593Smuzhiyun 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1369*4882a593Smuzhiyun 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1370*4882a593Smuzhiyun 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1371*4882a593Smuzhiyun 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1372*4882a593Smuzhiyun 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun 	/* Note: If host configured fixed rates and in some other special
1375*4882a593Smuzhiyun 	 * cases, the broadcast/management frames are sent in different rates.
1376*4882a593Smuzhiyun 	 * Firmware rate's control to be skipped for this?
1377*4882a593Smuzhiyun 	 */
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) {
1380*4882a593Smuzhiyun 		ath11k_warn(ab, "Invalid HE mcs %hhd peer stats",  mcs);
1381*4882a593Smuzhiyun 		return;
1382*4882a593Smuzhiyun 	}
1383*4882a593Smuzhiyun 
1384*4882a593Smuzhiyun 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1385*4882a593Smuzhiyun 		ath11k_warn(ab, "Invalid HE mcs %hhd peer stats",  mcs);
1386*4882a593Smuzhiyun 		return;
1387*4882a593Smuzhiyun 	}
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1390*4882a593Smuzhiyun 		ath11k_warn(ab, "Invalid VHT mcs %hhd peer stats",  mcs);
1391*4882a593Smuzhiyun 		return;
1392*4882a593Smuzhiyun 	}
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1395*4882a593Smuzhiyun 		ath11k_warn(ab, "Invalid HT mcs %hhd nss %hhd peer stats",
1396*4882a593Smuzhiyun 			    mcs, nss);
1397*4882a593Smuzhiyun 		return;
1398*4882a593Smuzhiyun 	}
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1401*4882a593Smuzhiyun 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1402*4882a593Smuzhiyun 							    flags,
1403*4882a593Smuzhiyun 							    &rate_idx,
1404*4882a593Smuzhiyun 							    &rate);
1405*4882a593Smuzhiyun 		if (ret < 0)
1406*4882a593Smuzhiyun 			return;
1407*4882a593Smuzhiyun 	}
1408*4882a593Smuzhiyun 
1409*4882a593Smuzhiyun 	rcu_read_lock();
1410*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
1411*4882a593Smuzhiyun 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun 	if (!peer || !peer->sta) {
1414*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
1415*4882a593Smuzhiyun 		rcu_read_unlock();
1416*4882a593Smuzhiyun 		return;
1417*4882a593Smuzhiyun 	}
1418*4882a593Smuzhiyun 
1419*4882a593Smuzhiyun 	sta = peer->sta;
1420*4882a593Smuzhiyun 	arsta = (struct ath11k_sta *)sta->drv_priv;
1421*4882a593Smuzhiyun 
1422*4882a593Smuzhiyun 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun 	switch (flags) {
1425*4882a593Smuzhiyun 	case WMI_RATE_PREAMBLE_OFDM:
1426*4882a593Smuzhiyun 		arsta->txrate.legacy = rate;
1427*4882a593Smuzhiyun 		break;
1428*4882a593Smuzhiyun 	case WMI_RATE_PREAMBLE_CCK:
1429*4882a593Smuzhiyun 		arsta->txrate.legacy = rate;
1430*4882a593Smuzhiyun 		break;
1431*4882a593Smuzhiyun 	case WMI_RATE_PREAMBLE_HT:
1432*4882a593Smuzhiyun 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1433*4882a593Smuzhiyun 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1434*4882a593Smuzhiyun 		if (sgi)
1435*4882a593Smuzhiyun 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1436*4882a593Smuzhiyun 		break;
1437*4882a593Smuzhiyun 	case WMI_RATE_PREAMBLE_VHT:
1438*4882a593Smuzhiyun 		arsta->txrate.mcs = mcs;
1439*4882a593Smuzhiyun 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1440*4882a593Smuzhiyun 		if (sgi)
1441*4882a593Smuzhiyun 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1442*4882a593Smuzhiyun 		break;
1443*4882a593Smuzhiyun 	case WMI_RATE_PREAMBLE_HE:
1444*4882a593Smuzhiyun 		arsta->txrate.mcs = mcs;
1445*4882a593Smuzhiyun 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1446*4882a593Smuzhiyun 		arsta->txrate.he_dcm = dcm;
1447*4882a593Smuzhiyun 		arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
1448*4882a593Smuzhiyun 		arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc(
1449*4882a593Smuzhiyun 						(user_rate->ru_end -
1450*4882a593Smuzhiyun 						 user_rate->ru_start) + 1);
1451*4882a593Smuzhiyun 		break;
1452*4882a593Smuzhiyun 	}
1453*4882a593Smuzhiyun 
1454*4882a593Smuzhiyun 	arsta->txrate.nss = nss;
1455*4882a593Smuzhiyun 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1456*4882a593Smuzhiyun 	arsta->tx_duration += tx_duration;
1457*4882a593Smuzhiyun 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1458*4882a593Smuzhiyun 
1459*4882a593Smuzhiyun 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1460*4882a593Smuzhiyun 	 * So skip peer stats update for mgmt packets.
1461*4882a593Smuzhiyun 	 */
1462*4882a593Smuzhiyun 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1463*4882a593Smuzhiyun 		memset(peer_stats, 0, sizeof(*peer_stats));
1464*4882a593Smuzhiyun 		peer_stats->succ_pkts = succ_pkts;
1465*4882a593Smuzhiyun 		peer_stats->succ_bytes = succ_bytes;
1466*4882a593Smuzhiyun 		peer_stats->is_ampdu = is_ampdu;
1467*4882a593Smuzhiyun 		peer_stats->duration = tx_duration;
1468*4882a593Smuzhiyun 		peer_stats->ba_fails =
1469*4882a593Smuzhiyun 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1470*4882a593Smuzhiyun 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1473*4882a593Smuzhiyun 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1474*4882a593Smuzhiyun 	}
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
1477*4882a593Smuzhiyun 	rcu_read_unlock();
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun 
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1480*4882a593Smuzhiyun static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1481*4882a593Smuzhiyun 					 struct htt_ppdu_stats *ppdu_stats)
1482*4882a593Smuzhiyun {
1483*4882a593Smuzhiyun 	u8 user;
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1486*4882a593Smuzhiyun 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1487*4882a593Smuzhiyun }
1488*4882a593Smuzhiyun 
1489*4882a593Smuzhiyun static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1490*4882a593Smuzhiyun struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1491*4882a593Smuzhiyun 							u32 ppdu_id)
1492*4882a593Smuzhiyun {
1493*4882a593Smuzhiyun 	struct htt_ppdu_stats_info *ppdu_info;
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	spin_lock_bh(&ar->data_lock);
1496*4882a593Smuzhiyun 	if (!list_empty(&ar->ppdu_stats_info)) {
1497*4882a593Smuzhiyun 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1498*4882a593Smuzhiyun 			if (ppdu_info->ppdu_id == ppdu_id) {
1499*4882a593Smuzhiyun 				spin_unlock_bh(&ar->data_lock);
1500*4882a593Smuzhiyun 				return ppdu_info;
1501*4882a593Smuzhiyun 			}
1502*4882a593Smuzhiyun 		}
1503*4882a593Smuzhiyun 
1504*4882a593Smuzhiyun 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1505*4882a593Smuzhiyun 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1506*4882a593Smuzhiyun 						     typeof(*ppdu_info), list);
1507*4882a593Smuzhiyun 			list_del(&ppdu_info->list);
1508*4882a593Smuzhiyun 			ar->ppdu_stat_list_depth--;
1509*4882a593Smuzhiyun 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1510*4882a593Smuzhiyun 			kfree(ppdu_info);
1511*4882a593Smuzhiyun 		}
1512*4882a593Smuzhiyun 	}
1513*4882a593Smuzhiyun 	spin_unlock_bh(&ar->data_lock);
1514*4882a593Smuzhiyun 
1515*4882a593Smuzhiyun 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1516*4882a593Smuzhiyun 	if (!ppdu_info)
1517*4882a593Smuzhiyun 		return NULL;
1518*4882a593Smuzhiyun 
1519*4882a593Smuzhiyun 	spin_lock_bh(&ar->data_lock);
1520*4882a593Smuzhiyun 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1521*4882a593Smuzhiyun 	ar->ppdu_stat_list_depth++;
1522*4882a593Smuzhiyun 	spin_unlock_bh(&ar->data_lock);
1523*4882a593Smuzhiyun 
1524*4882a593Smuzhiyun 	return ppdu_info;
1525*4882a593Smuzhiyun }
1526*4882a593Smuzhiyun 
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1527*4882a593Smuzhiyun static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1528*4882a593Smuzhiyun 				      struct sk_buff *skb)
1529*4882a593Smuzhiyun {
1530*4882a593Smuzhiyun 	struct ath11k_htt_ppdu_stats_msg *msg;
1531*4882a593Smuzhiyun 	struct htt_ppdu_stats_info *ppdu_info;
1532*4882a593Smuzhiyun 	struct ath11k *ar;
1533*4882a593Smuzhiyun 	int ret;
1534*4882a593Smuzhiyun 	u8 pdev_id;
1535*4882a593Smuzhiyun 	u32 ppdu_id, len;
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1538*4882a593Smuzhiyun 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1539*4882a593Smuzhiyun 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1540*4882a593Smuzhiyun 	ppdu_id = msg->ppdu_id;
1541*4882a593Smuzhiyun 
1542*4882a593Smuzhiyun 	rcu_read_lock();
1543*4882a593Smuzhiyun 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1544*4882a593Smuzhiyun 	if (!ar) {
1545*4882a593Smuzhiyun 		ret = -EINVAL;
1546*4882a593Smuzhiyun 		goto exit;
1547*4882a593Smuzhiyun 	}
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1550*4882a593Smuzhiyun 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1553*4882a593Smuzhiyun 	if (!ppdu_info) {
1554*4882a593Smuzhiyun 		ret = -EINVAL;
1555*4882a593Smuzhiyun 		goto exit;
1556*4882a593Smuzhiyun 	}
1557*4882a593Smuzhiyun 
1558*4882a593Smuzhiyun 	ppdu_info->ppdu_id = ppdu_id;
1559*4882a593Smuzhiyun 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1560*4882a593Smuzhiyun 				     ath11k_htt_tlv_ppdu_stats_parse,
1561*4882a593Smuzhiyun 				     (void *)ppdu_info);
1562*4882a593Smuzhiyun 	if (ret) {
1563*4882a593Smuzhiyun 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1564*4882a593Smuzhiyun 		goto exit;
1565*4882a593Smuzhiyun 	}
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun exit:
1568*4882a593Smuzhiyun 	rcu_read_unlock();
1569*4882a593Smuzhiyun 
1570*4882a593Smuzhiyun 	return ret;
1571*4882a593Smuzhiyun }
1572*4882a593Smuzhiyun 
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1573*4882a593Smuzhiyun static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1574*4882a593Smuzhiyun {
1575*4882a593Smuzhiyun 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1576*4882a593Smuzhiyun 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1577*4882a593Smuzhiyun 	struct ath11k *ar;
1578*4882a593Smuzhiyun 	u8 pdev_id;
1579*4882a593Smuzhiyun 
1580*4882a593Smuzhiyun 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1581*4882a593Smuzhiyun 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1582*4882a593Smuzhiyun 	if (!ar) {
1583*4882a593Smuzhiyun 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1584*4882a593Smuzhiyun 		return;
1585*4882a593Smuzhiyun 	}
1586*4882a593Smuzhiyun 
1587*4882a593Smuzhiyun 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1588*4882a593Smuzhiyun 				ar->ab->pktlog_defs_checksum);
1589*4882a593Smuzhiyun }
1590*4882a593Smuzhiyun 
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1591*4882a593Smuzhiyun static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1592*4882a593Smuzhiyun 						  struct sk_buff *skb)
1593*4882a593Smuzhiyun {
1594*4882a593Smuzhiyun 	u32 *data = (u32 *)skb->data;
1595*4882a593Smuzhiyun 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1596*4882a593Smuzhiyun 	u16 hp, tp;
1597*4882a593Smuzhiyun 	u32 backpressure_time;
1598*4882a593Smuzhiyun 	struct ath11k_bp_stats *bp_stats;
1599*4882a593Smuzhiyun 
1600*4882a593Smuzhiyun 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1601*4882a593Smuzhiyun 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1602*4882a593Smuzhiyun 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1603*4882a593Smuzhiyun 	++data;
1604*4882a593Smuzhiyun 
1605*4882a593Smuzhiyun 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1606*4882a593Smuzhiyun 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1607*4882a593Smuzhiyun 	++data;
1608*4882a593Smuzhiyun 
1609*4882a593Smuzhiyun 	backpressure_time = *data;
1610*4882a593Smuzhiyun 
1611*4882a593Smuzhiyun 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1612*4882a593Smuzhiyun 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1613*4882a593Smuzhiyun 
1614*4882a593Smuzhiyun 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1615*4882a593Smuzhiyun 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1616*4882a593Smuzhiyun 			return;
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1619*4882a593Smuzhiyun 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1620*4882a593Smuzhiyun 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1621*4882a593Smuzhiyun 
1622*4882a593Smuzhiyun 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1623*4882a593Smuzhiyun 			return;
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1626*4882a593Smuzhiyun 	} else {
1627*4882a593Smuzhiyun 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1628*4882a593Smuzhiyun 			    ring_type);
1629*4882a593Smuzhiyun 		return;
1630*4882a593Smuzhiyun 	}
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
1633*4882a593Smuzhiyun 	bp_stats->hp = hp;
1634*4882a593Smuzhiyun 	bp_stats->tp = tp;
1635*4882a593Smuzhiyun 	bp_stats->count++;
1636*4882a593Smuzhiyun 	bp_stats->jiffies = jiffies;
1637*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun 
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1640*4882a593Smuzhiyun void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1641*4882a593Smuzhiyun 				       struct sk_buff *skb)
1642*4882a593Smuzhiyun {
1643*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
1644*4882a593Smuzhiyun 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1645*4882a593Smuzhiyun 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1646*4882a593Smuzhiyun 	u16 peer_id;
1647*4882a593Smuzhiyun 	u8 vdev_id;
1648*4882a593Smuzhiyun 	u8 mac_addr[ETH_ALEN];
1649*4882a593Smuzhiyun 	u16 peer_mac_h16;
1650*4882a593Smuzhiyun 	u16 ast_hash;
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1653*4882a593Smuzhiyun 
1654*4882a593Smuzhiyun 	switch (type) {
1655*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1656*4882a593Smuzhiyun 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1657*4882a593Smuzhiyun 						  resp->version_msg.version);
1658*4882a593Smuzhiyun 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1659*4882a593Smuzhiyun 						  resp->version_msg.version);
1660*4882a593Smuzhiyun 		complete(&dp->htt_tgt_version_received);
1661*4882a593Smuzhiyun 		break;
1662*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1663*4882a593Smuzhiyun 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1664*4882a593Smuzhiyun 				    resp->peer_map_ev.info);
1665*4882a593Smuzhiyun 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1666*4882a593Smuzhiyun 				    resp->peer_map_ev.info);
1667*4882a593Smuzhiyun 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1668*4882a593Smuzhiyun 					 resp->peer_map_ev.info1);
1669*4882a593Smuzhiyun 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1670*4882a593Smuzhiyun 				       peer_mac_h16, mac_addr);
1671*4882a593Smuzhiyun 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0);
1672*4882a593Smuzhiyun 		break;
1673*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1674*4882a593Smuzhiyun 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1675*4882a593Smuzhiyun 				    resp->peer_map_ev.info);
1676*4882a593Smuzhiyun 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1677*4882a593Smuzhiyun 				    resp->peer_map_ev.info);
1678*4882a593Smuzhiyun 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1679*4882a593Smuzhiyun 					 resp->peer_map_ev.info1);
1680*4882a593Smuzhiyun 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1681*4882a593Smuzhiyun 				       peer_mac_h16, mac_addr);
1682*4882a593Smuzhiyun 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1683*4882a593Smuzhiyun 				     resp->peer_map_ev.info2);
1684*4882a593Smuzhiyun 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash);
1685*4882a593Smuzhiyun 		break;
1686*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1687*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1688*4882a593Smuzhiyun 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1689*4882a593Smuzhiyun 				    resp->peer_unmap_ev.info);
1690*4882a593Smuzhiyun 		ath11k_peer_unmap_event(ab, peer_id);
1691*4882a593Smuzhiyun 		break;
1692*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1693*4882a593Smuzhiyun 		ath11k_htt_pull_ppdu_stats(ab, skb);
1694*4882a593Smuzhiyun 		break;
1695*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1696*4882a593Smuzhiyun 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1697*4882a593Smuzhiyun 		break;
1698*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_PKTLOG:
1699*4882a593Smuzhiyun 		ath11k_htt_pktlog(ab, skb);
1700*4882a593Smuzhiyun 		break;
1701*4882a593Smuzhiyun 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1702*4882a593Smuzhiyun 		ath11k_htt_backpressure_event_handler(ab, skb);
1703*4882a593Smuzhiyun 		break;
1704*4882a593Smuzhiyun 	default:
1705*4882a593Smuzhiyun 		ath11k_warn(ab, "htt event %d not handled\n", type);
1706*4882a593Smuzhiyun 		break;
1707*4882a593Smuzhiyun 	}
1708*4882a593Smuzhiyun 
1709*4882a593Smuzhiyun 	dev_kfree_skb_any(skb);
1710*4882a593Smuzhiyun }
1711*4882a593Smuzhiyun 
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1712*4882a593Smuzhiyun static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1713*4882a593Smuzhiyun 				      struct sk_buff_head *msdu_list,
1714*4882a593Smuzhiyun 				      struct sk_buff *first, struct sk_buff *last,
1715*4882a593Smuzhiyun 				      u8 l3pad_bytes, int msdu_len)
1716*4882a593Smuzhiyun {
1717*4882a593Smuzhiyun 	struct sk_buff *skb;
1718*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1719*4882a593Smuzhiyun 	int buf_first_hdr_len, buf_first_len;
1720*4882a593Smuzhiyun 	struct hal_rx_desc *ldesc;
1721*4882a593Smuzhiyun 	int space_extra;
1722*4882a593Smuzhiyun 	int rem_len;
1723*4882a593Smuzhiyun 	int buf_len;
1724*4882a593Smuzhiyun 
1725*4882a593Smuzhiyun 	/* As the msdu is spread across multiple rx buffers,
1726*4882a593Smuzhiyun 	 * find the offset to the start of msdu for computing
1727*4882a593Smuzhiyun 	 * the length of the msdu in the first buffer.
1728*4882a593Smuzhiyun 	 */
1729*4882a593Smuzhiyun 	buf_first_hdr_len = HAL_RX_DESC_SIZE + l3pad_bytes;
1730*4882a593Smuzhiyun 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1731*4882a593Smuzhiyun 
1732*4882a593Smuzhiyun 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1733*4882a593Smuzhiyun 		skb_put(first, buf_first_hdr_len + msdu_len);
1734*4882a593Smuzhiyun 		skb_pull(first, buf_first_hdr_len);
1735*4882a593Smuzhiyun 		return 0;
1736*4882a593Smuzhiyun 	}
1737*4882a593Smuzhiyun 
1738*4882a593Smuzhiyun 	ldesc = (struct hal_rx_desc *)last->data;
1739*4882a593Smuzhiyun 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ldesc);
1740*4882a593Smuzhiyun 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ldesc);
1741*4882a593Smuzhiyun 
1742*4882a593Smuzhiyun 	/* MSDU spans over multiple buffers because the length of the MSDU
1743*4882a593Smuzhiyun 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1744*4882a593Smuzhiyun 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1745*4882a593Smuzhiyun 	 */
1746*4882a593Smuzhiyun 	skb_put(first, DP_RX_BUFFER_SIZE);
1747*4882a593Smuzhiyun 	skb_pull(first, buf_first_hdr_len);
1748*4882a593Smuzhiyun 
1749*4882a593Smuzhiyun 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1750*4882a593Smuzhiyun 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1751*4882a593Smuzhiyun 	 */
1752*4882a593Smuzhiyun 	ath11k_dp_rx_desc_end_tlv_copy(rxcb->rx_desc, ldesc);
1753*4882a593Smuzhiyun 
1754*4882a593Smuzhiyun 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1755*4882a593Smuzhiyun 	if (space_extra > 0 &&
1756*4882a593Smuzhiyun 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1757*4882a593Smuzhiyun 		/* Free up all buffers of the MSDU */
1758*4882a593Smuzhiyun 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1759*4882a593Smuzhiyun 			rxcb = ATH11K_SKB_RXCB(skb);
1760*4882a593Smuzhiyun 			if (!rxcb->is_continuation) {
1761*4882a593Smuzhiyun 				dev_kfree_skb_any(skb);
1762*4882a593Smuzhiyun 				break;
1763*4882a593Smuzhiyun 			}
1764*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
1765*4882a593Smuzhiyun 		}
1766*4882a593Smuzhiyun 		return -ENOMEM;
1767*4882a593Smuzhiyun 	}
1768*4882a593Smuzhiyun 
1769*4882a593Smuzhiyun 	rem_len = msdu_len - buf_first_len;
1770*4882a593Smuzhiyun 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1771*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(skb);
1772*4882a593Smuzhiyun 		if (rxcb->is_continuation)
1773*4882a593Smuzhiyun 			buf_len = DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE;
1774*4882a593Smuzhiyun 		else
1775*4882a593Smuzhiyun 			buf_len = rem_len;
1776*4882a593Smuzhiyun 
1777*4882a593Smuzhiyun 		if (buf_len > (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)) {
1778*4882a593Smuzhiyun 			WARN_ON_ONCE(1);
1779*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
1780*4882a593Smuzhiyun 			return -EINVAL;
1781*4882a593Smuzhiyun 		}
1782*4882a593Smuzhiyun 
1783*4882a593Smuzhiyun 		skb_put(skb, buf_len + HAL_RX_DESC_SIZE);
1784*4882a593Smuzhiyun 		skb_pull(skb, HAL_RX_DESC_SIZE);
1785*4882a593Smuzhiyun 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1786*4882a593Smuzhiyun 					  buf_len);
1787*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
1788*4882a593Smuzhiyun 
1789*4882a593Smuzhiyun 		rem_len -= buf_len;
1790*4882a593Smuzhiyun 		if (!rxcb->is_continuation)
1791*4882a593Smuzhiyun 			break;
1792*4882a593Smuzhiyun 	}
1793*4882a593Smuzhiyun 
1794*4882a593Smuzhiyun 	return 0;
1795*4882a593Smuzhiyun }
1796*4882a593Smuzhiyun 
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1797*4882a593Smuzhiyun static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1798*4882a593Smuzhiyun 						      struct sk_buff *first)
1799*4882a593Smuzhiyun {
1800*4882a593Smuzhiyun 	struct sk_buff *skb;
1801*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1802*4882a593Smuzhiyun 
1803*4882a593Smuzhiyun 	if (!rxcb->is_continuation)
1804*4882a593Smuzhiyun 		return first;
1805*4882a593Smuzhiyun 
1806*4882a593Smuzhiyun 	skb_queue_walk(msdu_list, skb) {
1807*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(skb);
1808*4882a593Smuzhiyun 		if (!rxcb->is_continuation)
1809*4882a593Smuzhiyun 			return skb;
1810*4882a593Smuzhiyun 	}
1811*4882a593Smuzhiyun 
1812*4882a593Smuzhiyun 	return NULL;
1813*4882a593Smuzhiyun }
1814*4882a593Smuzhiyun 
ath11k_dp_rx_h_csum_offload(struct sk_buff * msdu)1815*4882a593Smuzhiyun static void ath11k_dp_rx_h_csum_offload(struct sk_buff *msdu)
1816*4882a593Smuzhiyun {
1817*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1818*4882a593Smuzhiyun 	bool ip_csum_fail, l4_csum_fail;
1819*4882a593Smuzhiyun 
1820*4882a593Smuzhiyun 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rxcb->rx_desc);
1821*4882a593Smuzhiyun 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rxcb->rx_desc);
1822*4882a593Smuzhiyun 
1823*4882a593Smuzhiyun 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1824*4882a593Smuzhiyun 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1825*4882a593Smuzhiyun }
1826*4882a593Smuzhiyun 
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1827*4882a593Smuzhiyun static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1828*4882a593Smuzhiyun 				       enum hal_encrypt_type enctype)
1829*4882a593Smuzhiyun {
1830*4882a593Smuzhiyun 	switch (enctype) {
1831*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_OPEN:
1832*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1833*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1834*4882a593Smuzhiyun 		return 0;
1835*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_CCMP_128:
1836*4882a593Smuzhiyun 		return IEEE80211_CCMP_MIC_LEN;
1837*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_CCMP_256:
1838*4882a593Smuzhiyun 		return IEEE80211_CCMP_256_MIC_LEN;
1839*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_GCMP_128:
1840*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1841*4882a593Smuzhiyun 		return IEEE80211_GCMP_MIC_LEN;
1842*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_40:
1843*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_104:
1844*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_128:
1845*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1846*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WAPI:
1847*4882a593Smuzhiyun 		break;
1848*4882a593Smuzhiyun 	}
1849*4882a593Smuzhiyun 
1850*4882a593Smuzhiyun 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1851*4882a593Smuzhiyun 	return 0;
1852*4882a593Smuzhiyun }
1853*4882a593Smuzhiyun 
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1854*4882a593Smuzhiyun static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1855*4882a593Smuzhiyun 					 enum hal_encrypt_type enctype)
1856*4882a593Smuzhiyun {
1857*4882a593Smuzhiyun 	switch (enctype) {
1858*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_OPEN:
1859*4882a593Smuzhiyun 		return 0;
1860*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1861*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1862*4882a593Smuzhiyun 		return IEEE80211_TKIP_IV_LEN;
1863*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_CCMP_128:
1864*4882a593Smuzhiyun 		return IEEE80211_CCMP_HDR_LEN;
1865*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_CCMP_256:
1866*4882a593Smuzhiyun 		return IEEE80211_CCMP_256_HDR_LEN;
1867*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_GCMP_128:
1868*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1869*4882a593Smuzhiyun 		return IEEE80211_GCMP_HDR_LEN;
1870*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_40:
1871*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_104:
1872*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_128:
1873*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1874*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WAPI:
1875*4882a593Smuzhiyun 		break;
1876*4882a593Smuzhiyun 	}
1877*4882a593Smuzhiyun 
1878*4882a593Smuzhiyun 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1879*4882a593Smuzhiyun 	return 0;
1880*4882a593Smuzhiyun }
1881*4882a593Smuzhiyun 
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1882*4882a593Smuzhiyun static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1883*4882a593Smuzhiyun 				       enum hal_encrypt_type enctype)
1884*4882a593Smuzhiyun {
1885*4882a593Smuzhiyun 	switch (enctype) {
1886*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_OPEN:
1887*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_CCMP_128:
1888*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_CCMP_256:
1889*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_GCMP_128:
1890*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1891*4882a593Smuzhiyun 		return 0;
1892*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1893*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1894*4882a593Smuzhiyun 		return IEEE80211_TKIP_ICV_LEN;
1895*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_40:
1896*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_104:
1897*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WEP_128:
1898*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1899*4882a593Smuzhiyun 	case HAL_ENCRYPT_TYPE_WAPI:
1900*4882a593Smuzhiyun 		break;
1901*4882a593Smuzhiyun 	}
1902*4882a593Smuzhiyun 
1903*4882a593Smuzhiyun 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1904*4882a593Smuzhiyun 	return 0;
1905*4882a593Smuzhiyun }
1906*4882a593Smuzhiyun 
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1907*4882a593Smuzhiyun static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1908*4882a593Smuzhiyun 					 struct sk_buff *msdu,
1909*4882a593Smuzhiyun 					 u8 *first_hdr,
1910*4882a593Smuzhiyun 					 enum hal_encrypt_type enctype,
1911*4882a593Smuzhiyun 					 struct ieee80211_rx_status *status)
1912*4882a593Smuzhiyun {
1913*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1914*4882a593Smuzhiyun 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1915*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
1916*4882a593Smuzhiyun 	size_t hdr_len;
1917*4882a593Smuzhiyun 	u8 da[ETH_ALEN];
1918*4882a593Smuzhiyun 	u8 sa[ETH_ALEN];
1919*4882a593Smuzhiyun 	u16 qos_ctl = 0;
1920*4882a593Smuzhiyun 	u8 *qos;
1921*4882a593Smuzhiyun 
1922*4882a593Smuzhiyun 	/* copy SA & DA and pull decapped header */
1923*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)msdu->data;
1924*4882a593Smuzhiyun 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1925*4882a593Smuzhiyun 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1926*4882a593Smuzhiyun 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1927*4882a593Smuzhiyun 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1928*4882a593Smuzhiyun 
1929*4882a593Smuzhiyun 	if (rxcb->is_first_msdu) {
1930*4882a593Smuzhiyun 		/* original 802.11 header is valid for the first msdu
1931*4882a593Smuzhiyun 		 * hence we can reuse the same header
1932*4882a593Smuzhiyun 		 */
1933*4882a593Smuzhiyun 		hdr = (struct ieee80211_hdr *)first_hdr;
1934*4882a593Smuzhiyun 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1935*4882a593Smuzhiyun 
1936*4882a593Smuzhiyun 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1937*4882a593Smuzhiyun 		 * so strip the A-MSDU bit from QoS Ctl.
1938*4882a593Smuzhiyun 		 */
1939*4882a593Smuzhiyun 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1940*4882a593Smuzhiyun 			qos = ieee80211_get_qos_ctl(hdr);
1941*4882a593Smuzhiyun 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1942*4882a593Smuzhiyun 		}
1943*4882a593Smuzhiyun 	} else {
1944*4882a593Smuzhiyun 		/*  Rebuild qos header if this is a middle/last msdu */
1945*4882a593Smuzhiyun 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1946*4882a593Smuzhiyun 
1947*4882a593Smuzhiyun 		/* Reset the order bit as the HT_Control header is stripped */
1948*4882a593Smuzhiyun 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1949*4882a593Smuzhiyun 
1950*4882a593Smuzhiyun 		qos_ctl = rxcb->tid;
1951*4882a593Smuzhiyun 
1952*4882a593Smuzhiyun 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(rxcb->rx_desc))
1953*4882a593Smuzhiyun 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1954*4882a593Smuzhiyun 
1955*4882a593Smuzhiyun 		/* TODO Add other QoS ctl fields when required */
1956*4882a593Smuzhiyun 
1957*4882a593Smuzhiyun 		/* copy decap header before overwriting for reuse below */
1958*4882a593Smuzhiyun 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
1959*4882a593Smuzhiyun 	}
1960*4882a593Smuzhiyun 
1961*4882a593Smuzhiyun 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
1962*4882a593Smuzhiyun 		memcpy(skb_push(msdu,
1963*4882a593Smuzhiyun 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
1964*4882a593Smuzhiyun 		       (void *)hdr + hdr_len,
1965*4882a593Smuzhiyun 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
1966*4882a593Smuzhiyun 	}
1967*4882a593Smuzhiyun 
1968*4882a593Smuzhiyun 	if (!rxcb->is_first_msdu) {
1969*4882a593Smuzhiyun 		memcpy(skb_push(msdu,
1970*4882a593Smuzhiyun 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
1971*4882a593Smuzhiyun 				IEEE80211_QOS_CTL_LEN);
1972*4882a593Smuzhiyun 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
1973*4882a593Smuzhiyun 		return;
1974*4882a593Smuzhiyun 	}
1975*4882a593Smuzhiyun 
1976*4882a593Smuzhiyun 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
1977*4882a593Smuzhiyun 
1978*4882a593Smuzhiyun 	/* original 802.11 header has a different DA and in
1979*4882a593Smuzhiyun 	 * case of 4addr it may also have different SA
1980*4882a593Smuzhiyun 	 */
1981*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)msdu->data;
1982*4882a593Smuzhiyun 	ether_addr_copy(ieee80211_get_DA(hdr), da);
1983*4882a593Smuzhiyun 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
1984*4882a593Smuzhiyun }
1985*4882a593Smuzhiyun 
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)1986*4882a593Smuzhiyun static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
1987*4882a593Smuzhiyun 				       enum hal_encrypt_type enctype,
1988*4882a593Smuzhiyun 				       struct ieee80211_rx_status *status,
1989*4882a593Smuzhiyun 				       bool decrypted)
1990*4882a593Smuzhiyun {
1991*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1992*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
1993*4882a593Smuzhiyun 	size_t hdr_len;
1994*4882a593Smuzhiyun 	size_t crypto_len;
1995*4882a593Smuzhiyun 
1996*4882a593Smuzhiyun 	if (!rxcb->is_first_msdu ||
1997*4882a593Smuzhiyun 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
1998*4882a593Smuzhiyun 		WARN_ON_ONCE(1);
1999*4882a593Smuzhiyun 		return;
2000*4882a593Smuzhiyun 	}
2001*4882a593Smuzhiyun 
2002*4882a593Smuzhiyun 	skb_trim(msdu, msdu->len - FCS_LEN);
2003*4882a593Smuzhiyun 
2004*4882a593Smuzhiyun 	if (!decrypted)
2005*4882a593Smuzhiyun 		return;
2006*4882a593Smuzhiyun 
2007*4882a593Smuzhiyun 	hdr = (void *)msdu->data;
2008*4882a593Smuzhiyun 
2009*4882a593Smuzhiyun 	/* Tail */
2010*4882a593Smuzhiyun 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2011*4882a593Smuzhiyun 		skb_trim(msdu, msdu->len -
2012*4882a593Smuzhiyun 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2013*4882a593Smuzhiyun 
2014*4882a593Smuzhiyun 		skb_trim(msdu, msdu->len -
2015*4882a593Smuzhiyun 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2016*4882a593Smuzhiyun 	} else {
2017*4882a593Smuzhiyun 		/* MIC */
2018*4882a593Smuzhiyun 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2019*4882a593Smuzhiyun 			skb_trim(msdu, msdu->len -
2020*4882a593Smuzhiyun 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2021*4882a593Smuzhiyun 
2022*4882a593Smuzhiyun 		/* ICV */
2023*4882a593Smuzhiyun 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2024*4882a593Smuzhiyun 			skb_trim(msdu, msdu->len -
2025*4882a593Smuzhiyun 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2026*4882a593Smuzhiyun 	}
2027*4882a593Smuzhiyun 
2028*4882a593Smuzhiyun 	/* MMIC */
2029*4882a593Smuzhiyun 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2030*4882a593Smuzhiyun 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2031*4882a593Smuzhiyun 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2032*4882a593Smuzhiyun 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2033*4882a593Smuzhiyun 
2034*4882a593Smuzhiyun 	/* Head */
2035*4882a593Smuzhiyun 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2036*4882a593Smuzhiyun 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2037*4882a593Smuzhiyun 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2038*4882a593Smuzhiyun 
2039*4882a593Smuzhiyun 		memmove((void *)msdu->data + crypto_len,
2040*4882a593Smuzhiyun 			(void *)msdu->data, hdr_len);
2041*4882a593Smuzhiyun 		skb_pull(msdu, crypto_len);
2042*4882a593Smuzhiyun 	}
2043*4882a593Smuzhiyun }
2044*4882a593Smuzhiyun 
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2045*4882a593Smuzhiyun static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2046*4882a593Smuzhiyun 					 struct sk_buff *msdu,
2047*4882a593Smuzhiyun 					 enum hal_encrypt_type enctype)
2048*4882a593Smuzhiyun {
2049*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2050*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
2051*4882a593Smuzhiyun 	size_t hdr_len, crypto_len;
2052*4882a593Smuzhiyun 	void *rfc1042;
2053*4882a593Smuzhiyun 	bool is_amsdu;
2054*4882a593Smuzhiyun 
2055*4882a593Smuzhiyun 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2056*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(rxcb->rx_desc);
2057*4882a593Smuzhiyun 	rfc1042 = hdr;
2058*4882a593Smuzhiyun 
2059*4882a593Smuzhiyun 	if (rxcb->is_first_msdu) {
2060*4882a593Smuzhiyun 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2061*4882a593Smuzhiyun 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2062*4882a593Smuzhiyun 
2063*4882a593Smuzhiyun 		rfc1042 += hdr_len + crypto_len;
2064*4882a593Smuzhiyun 	}
2065*4882a593Smuzhiyun 
2066*4882a593Smuzhiyun 	if (is_amsdu)
2067*4882a593Smuzhiyun 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2068*4882a593Smuzhiyun 
2069*4882a593Smuzhiyun 	return rfc1042;
2070*4882a593Smuzhiyun }
2071*4882a593Smuzhiyun 
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2072*4882a593Smuzhiyun static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2073*4882a593Smuzhiyun 				       struct sk_buff *msdu,
2074*4882a593Smuzhiyun 				       u8 *first_hdr,
2075*4882a593Smuzhiyun 				       enum hal_encrypt_type enctype,
2076*4882a593Smuzhiyun 				       struct ieee80211_rx_status *status)
2077*4882a593Smuzhiyun {
2078*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
2079*4882a593Smuzhiyun 	struct ethhdr *eth;
2080*4882a593Smuzhiyun 	size_t hdr_len;
2081*4882a593Smuzhiyun 	u8 da[ETH_ALEN];
2082*4882a593Smuzhiyun 	u8 sa[ETH_ALEN];
2083*4882a593Smuzhiyun 	void *rfc1042;
2084*4882a593Smuzhiyun 
2085*4882a593Smuzhiyun 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2086*4882a593Smuzhiyun 	if (WARN_ON_ONCE(!rfc1042))
2087*4882a593Smuzhiyun 		return;
2088*4882a593Smuzhiyun 
2089*4882a593Smuzhiyun 	/* pull decapped header and copy SA & DA */
2090*4882a593Smuzhiyun 	eth = (struct ethhdr *)msdu->data;
2091*4882a593Smuzhiyun 	ether_addr_copy(da, eth->h_dest);
2092*4882a593Smuzhiyun 	ether_addr_copy(sa, eth->h_source);
2093*4882a593Smuzhiyun 	skb_pull(msdu, sizeof(struct ethhdr));
2094*4882a593Smuzhiyun 
2095*4882a593Smuzhiyun 	/* push rfc1042/llc/snap */
2096*4882a593Smuzhiyun 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2097*4882a593Smuzhiyun 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2098*4882a593Smuzhiyun 
2099*4882a593Smuzhiyun 	/* push original 802.11 header */
2100*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)first_hdr;
2101*4882a593Smuzhiyun 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2102*4882a593Smuzhiyun 
2103*4882a593Smuzhiyun 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2104*4882a593Smuzhiyun 		memcpy(skb_push(msdu,
2105*4882a593Smuzhiyun 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2106*4882a593Smuzhiyun 		       (void *)hdr + hdr_len,
2107*4882a593Smuzhiyun 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2108*4882a593Smuzhiyun 	}
2109*4882a593Smuzhiyun 
2110*4882a593Smuzhiyun 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2111*4882a593Smuzhiyun 
2112*4882a593Smuzhiyun 	/* original 802.11 header has a different DA and in
2113*4882a593Smuzhiyun 	 * case of 4addr it may also have different SA
2114*4882a593Smuzhiyun 	 */
2115*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)msdu->data;
2116*4882a593Smuzhiyun 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2117*4882a593Smuzhiyun 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2118*4882a593Smuzhiyun }
2119*4882a593Smuzhiyun 
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2120*4882a593Smuzhiyun static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2121*4882a593Smuzhiyun 				   struct hal_rx_desc *rx_desc,
2122*4882a593Smuzhiyun 				   enum hal_encrypt_type enctype,
2123*4882a593Smuzhiyun 				   struct ieee80211_rx_status *status,
2124*4882a593Smuzhiyun 				   bool decrypted)
2125*4882a593Smuzhiyun {
2126*4882a593Smuzhiyun 	u8 *first_hdr;
2127*4882a593Smuzhiyun 	u8 decap;
2128*4882a593Smuzhiyun 
2129*4882a593Smuzhiyun 	first_hdr = ath11k_dp_rx_h_80211_hdr(rx_desc);
2130*4882a593Smuzhiyun 	decap = ath11k_dp_rx_h_msdu_start_decap_type(rx_desc);
2131*4882a593Smuzhiyun 
2132*4882a593Smuzhiyun 	switch (decap) {
2133*4882a593Smuzhiyun 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2134*4882a593Smuzhiyun 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2135*4882a593Smuzhiyun 					     enctype, status);
2136*4882a593Smuzhiyun 		break;
2137*4882a593Smuzhiyun 	case DP_RX_DECAP_TYPE_RAW:
2138*4882a593Smuzhiyun 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2139*4882a593Smuzhiyun 					   decrypted);
2140*4882a593Smuzhiyun 		break;
2141*4882a593Smuzhiyun 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2142*4882a593Smuzhiyun 		/* TODO undecap support for middle/last msdu's of amsdu */
2143*4882a593Smuzhiyun 		ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2144*4882a593Smuzhiyun 					   enctype, status);
2145*4882a593Smuzhiyun 		break;
2146*4882a593Smuzhiyun 	case DP_RX_DECAP_TYPE_8023:
2147*4882a593Smuzhiyun 		/* TODO: Handle undecap for these formats */
2148*4882a593Smuzhiyun 		break;
2149*4882a593Smuzhiyun 	}
2150*4882a593Smuzhiyun }
2151*4882a593Smuzhiyun 
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2152*4882a593Smuzhiyun static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2153*4882a593Smuzhiyun 				struct sk_buff *msdu,
2154*4882a593Smuzhiyun 				struct hal_rx_desc *rx_desc,
2155*4882a593Smuzhiyun 				struct ieee80211_rx_status *rx_status)
2156*4882a593Smuzhiyun {
2157*4882a593Smuzhiyun 	bool  fill_crypto_hdr, mcast;
2158*4882a593Smuzhiyun 	enum hal_encrypt_type enctype;
2159*4882a593Smuzhiyun 	bool is_decrypted = false;
2160*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
2161*4882a593Smuzhiyun 	struct ath11k_peer *peer;
2162*4882a593Smuzhiyun 	u32 err_bitmap;
2163*4882a593Smuzhiyun 
2164*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)msdu->data;
2165*4882a593Smuzhiyun 
2166*4882a593Smuzhiyun 	/* PN for multicast packets will be checked in mac80211 */
2167*4882a593Smuzhiyun 
2168*4882a593Smuzhiyun 	mcast = is_multicast_ether_addr(hdr->addr1);
2169*4882a593Smuzhiyun 	fill_crypto_hdr = mcast;
2170*4882a593Smuzhiyun 
2171*4882a593Smuzhiyun 	spin_lock_bh(&ar->ab->base_lock);
2172*4882a593Smuzhiyun 	peer = ath11k_peer_find_by_addr(ar->ab, hdr->addr2);
2173*4882a593Smuzhiyun 	if (peer) {
2174*4882a593Smuzhiyun 		if (mcast)
2175*4882a593Smuzhiyun 			enctype = peer->sec_type_grp;
2176*4882a593Smuzhiyun 		else
2177*4882a593Smuzhiyun 			enctype = peer->sec_type;
2178*4882a593Smuzhiyun 	} else {
2179*4882a593Smuzhiyun 		enctype = HAL_ENCRYPT_TYPE_OPEN;
2180*4882a593Smuzhiyun 	}
2181*4882a593Smuzhiyun 	spin_unlock_bh(&ar->ab->base_lock);
2182*4882a593Smuzhiyun 
2183*4882a593Smuzhiyun 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_desc);
2184*4882a593Smuzhiyun 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2185*4882a593Smuzhiyun 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc);
2186*4882a593Smuzhiyun 
2187*4882a593Smuzhiyun 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2188*4882a593Smuzhiyun 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2189*4882a593Smuzhiyun 			     RX_FLAG_MMIC_ERROR |
2190*4882a593Smuzhiyun 			     RX_FLAG_DECRYPTED |
2191*4882a593Smuzhiyun 			     RX_FLAG_IV_STRIPPED |
2192*4882a593Smuzhiyun 			     RX_FLAG_MMIC_STRIPPED);
2193*4882a593Smuzhiyun 
2194*4882a593Smuzhiyun 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2195*4882a593Smuzhiyun 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2196*4882a593Smuzhiyun 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2197*4882a593Smuzhiyun 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2198*4882a593Smuzhiyun 
2199*4882a593Smuzhiyun 	if (is_decrypted) {
2200*4882a593Smuzhiyun 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2201*4882a593Smuzhiyun 
2202*4882a593Smuzhiyun 		if (fill_crypto_hdr)
2203*4882a593Smuzhiyun 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2204*4882a593Smuzhiyun 					RX_FLAG_ICV_STRIPPED;
2205*4882a593Smuzhiyun 		else
2206*4882a593Smuzhiyun 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2207*4882a593Smuzhiyun 					   RX_FLAG_PN_VALIDATED;
2208*4882a593Smuzhiyun 	}
2209*4882a593Smuzhiyun 
2210*4882a593Smuzhiyun 	ath11k_dp_rx_h_csum_offload(msdu);
2211*4882a593Smuzhiyun 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2212*4882a593Smuzhiyun 			       enctype, rx_status, is_decrypted);
2213*4882a593Smuzhiyun 
2214*4882a593Smuzhiyun 	if (!is_decrypted || fill_crypto_hdr)
2215*4882a593Smuzhiyun 		return;
2216*4882a593Smuzhiyun 
2217*4882a593Smuzhiyun 	hdr = (void *)msdu->data;
2218*4882a593Smuzhiyun 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2219*4882a593Smuzhiyun }
2220*4882a593Smuzhiyun 
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2221*4882a593Smuzhiyun static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2222*4882a593Smuzhiyun 				struct ieee80211_rx_status *rx_status)
2223*4882a593Smuzhiyun {
2224*4882a593Smuzhiyun 	struct ieee80211_supported_band *sband;
2225*4882a593Smuzhiyun 	enum rx_msdu_start_pkt_type pkt_type;
2226*4882a593Smuzhiyun 	u8 bw;
2227*4882a593Smuzhiyun 	u8 rate_mcs, nss;
2228*4882a593Smuzhiyun 	u8 sgi;
2229*4882a593Smuzhiyun 	bool is_cck;
2230*4882a593Smuzhiyun 
2231*4882a593Smuzhiyun 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(rx_desc);
2232*4882a593Smuzhiyun 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(rx_desc);
2233*4882a593Smuzhiyun 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(rx_desc);
2234*4882a593Smuzhiyun 	nss = ath11k_dp_rx_h_msdu_start_nss(rx_desc);
2235*4882a593Smuzhiyun 	sgi = ath11k_dp_rx_h_msdu_start_sgi(rx_desc);
2236*4882a593Smuzhiyun 
2237*4882a593Smuzhiyun 	switch (pkt_type) {
2238*4882a593Smuzhiyun 	case RX_MSDU_START_PKT_TYPE_11A:
2239*4882a593Smuzhiyun 	case RX_MSDU_START_PKT_TYPE_11B:
2240*4882a593Smuzhiyun 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2241*4882a593Smuzhiyun 		sband = &ar->mac.sbands[rx_status->band];
2242*4882a593Smuzhiyun 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2243*4882a593Smuzhiyun 								is_cck);
2244*4882a593Smuzhiyun 		break;
2245*4882a593Smuzhiyun 	case RX_MSDU_START_PKT_TYPE_11N:
2246*4882a593Smuzhiyun 		rx_status->encoding = RX_ENC_HT;
2247*4882a593Smuzhiyun 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2248*4882a593Smuzhiyun 			ath11k_warn(ar->ab,
2249*4882a593Smuzhiyun 				    "Received with invalid mcs in HT mode %d\n",
2250*4882a593Smuzhiyun 				     rate_mcs);
2251*4882a593Smuzhiyun 			break;
2252*4882a593Smuzhiyun 		}
2253*4882a593Smuzhiyun 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2254*4882a593Smuzhiyun 		if (sgi)
2255*4882a593Smuzhiyun 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2256*4882a593Smuzhiyun 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2257*4882a593Smuzhiyun 		break;
2258*4882a593Smuzhiyun 	case RX_MSDU_START_PKT_TYPE_11AC:
2259*4882a593Smuzhiyun 		rx_status->encoding = RX_ENC_VHT;
2260*4882a593Smuzhiyun 		rx_status->rate_idx = rate_mcs;
2261*4882a593Smuzhiyun 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2262*4882a593Smuzhiyun 			ath11k_warn(ar->ab,
2263*4882a593Smuzhiyun 				    "Received with invalid mcs in VHT mode %d\n",
2264*4882a593Smuzhiyun 				     rate_mcs);
2265*4882a593Smuzhiyun 			break;
2266*4882a593Smuzhiyun 		}
2267*4882a593Smuzhiyun 		rx_status->nss = nss;
2268*4882a593Smuzhiyun 		if (sgi)
2269*4882a593Smuzhiyun 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2270*4882a593Smuzhiyun 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2271*4882a593Smuzhiyun 		break;
2272*4882a593Smuzhiyun 	case RX_MSDU_START_PKT_TYPE_11AX:
2273*4882a593Smuzhiyun 		rx_status->rate_idx = rate_mcs;
2274*4882a593Smuzhiyun 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2275*4882a593Smuzhiyun 			ath11k_warn(ar->ab,
2276*4882a593Smuzhiyun 				    "Received with invalid mcs in HE mode %d\n",
2277*4882a593Smuzhiyun 				    rate_mcs);
2278*4882a593Smuzhiyun 			break;
2279*4882a593Smuzhiyun 		}
2280*4882a593Smuzhiyun 		rx_status->encoding = RX_ENC_HE;
2281*4882a593Smuzhiyun 		rx_status->nss = nss;
2282*4882a593Smuzhiyun 		rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
2283*4882a593Smuzhiyun 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2284*4882a593Smuzhiyun 		break;
2285*4882a593Smuzhiyun 	}
2286*4882a593Smuzhiyun }
2287*4882a593Smuzhiyun 
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2288*4882a593Smuzhiyun static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2289*4882a593Smuzhiyun 				struct ieee80211_rx_status *rx_status)
2290*4882a593Smuzhiyun {
2291*4882a593Smuzhiyun 	u8 channel_num;
2292*4882a593Smuzhiyun 	u32 center_freq;
2293*4882a593Smuzhiyun 	struct ieee80211_channel *channel;
2294*4882a593Smuzhiyun 
2295*4882a593Smuzhiyun 	rx_status->freq = 0;
2296*4882a593Smuzhiyun 	rx_status->rate_idx = 0;
2297*4882a593Smuzhiyun 	rx_status->nss = 0;
2298*4882a593Smuzhiyun 	rx_status->encoding = RX_ENC_LEGACY;
2299*4882a593Smuzhiyun 	rx_status->bw = RATE_INFO_BW_20;
2300*4882a593Smuzhiyun 
2301*4882a593Smuzhiyun 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2302*4882a593Smuzhiyun 
2303*4882a593Smuzhiyun 	channel_num = ath11k_dp_rx_h_msdu_start_freq(rx_desc);
2304*4882a593Smuzhiyun 	center_freq = ath11k_dp_rx_h_msdu_start_freq(rx_desc) >> 16;
2305*4882a593Smuzhiyun 
2306*4882a593Smuzhiyun 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2307*4882a593Smuzhiyun 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2308*4882a593Smuzhiyun 		rx_status->band = NL80211_BAND_6GHZ;
2309*4882a593Smuzhiyun 		rx_status->freq = center_freq;
2310*4882a593Smuzhiyun 	} else if (channel_num >= 1 && channel_num <= 14) {
2311*4882a593Smuzhiyun 		rx_status->band = NL80211_BAND_2GHZ;
2312*4882a593Smuzhiyun 	} else if (channel_num >= 36 && channel_num <= 173) {
2313*4882a593Smuzhiyun 		rx_status->band = NL80211_BAND_5GHZ;
2314*4882a593Smuzhiyun 	} else {
2315*4882a593Smuzhiyun 		spin_lock_bh(&ar->data_lock);
2316*4882a593Smuzhiyun 		channel = ar->rx_channel;
2317*4882a593Smuzhiyun 		if (channel) {
2318*4882a593Smuzhiyun 			rx_status->band = channel->band;
2319*4882a593Smuzhiyun 			channel_num =
2320*4882a593Smuzhiyun 				ieee80211_frequency_to_channel(channel->center_freq);
2321*4882a593Smuzhiyun 		}
2322*4882a593Smuzhiyun 		spin_unlock_bh(&ar->data_lock);
2323*4882a593Smuzhiyun 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2324*4882a593Smuzhiyun 				rx_desc, sizeof(struct hal_rx_desc));
2325*4882a593Smuzhiyun 	}
2326*4882a593Smuzhiyun 
2327*4882a593Smuzhiyun 	if (rx_status->band != NL80211_BAND_6GHZ)
2328*4882a593Smuzhiyun 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2329*4882a593Smuzhiyun 								 rx_status->band);
2330*4882a593Smuzhiyun 
2331*4882a593Smuzhiyun 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2332*4882a593Smuzhiyun }
2333*4882a593Smuzhiyun 
ath11k_print_get_tid(struct ieee80211_hdr * hdr,char * out,size_t size)2334*4882a593Smuzhiyun static char *ath11k_print_get_tid(struct ieee80211_hdr *hdr, char *out,
2335*4882a593Smuzhiyun 				  size_t size)
2336*4882a593Smuzhiyun {
2337*4882a593Smuzhiyun 	u8 *qc;
2338*4882a593Smuzhiyun 	int tid;
2339*4882a593Smuzhiyun 
2340*4882a593Smuzhiyun 	if (!ieee80211_is_data_qos(hdr->frame_control))
2341*4882a593Smuzhiyun 		return "";
2342*4882a593Smuzhiyun 
2343*4882a593Smuzhiyun 	qc = ieee80211_get_qos_ctl(hdr);
2344*4882a593Smuzhiyun 	tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
2345*4882a593Smuzhiyun 	snprintf(out, size, "tid %d", tid);
2346*4882a593Smuzhiyun 
2347*4882a593Smuzhiyun 	return out;
2348*4882a593Smuzhiyun }
2349*4882a593Smuzhiyun 
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu)2350*4882a593Smuzhiyun static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2351*4882a593Smuzhiyun 				      struct sk_buff *msdu)
2352*4882a593Smuzhiyun {
2353*4882a593Smuzhiyun 	static const struct ieee80211_radiotap_he known = {
2354*4882a593Smuzhiyun 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2355*4882a593Smuzhiyun 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2356*4882a593Smuzhiyun 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2357*4882a593Smuzhiyun 	};
2358*4882a593Smuzhiyun 	struct ieee80211_rx_status *status;
2359*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
2360*4882a593Smuzhiyun 	struct ieee80211_radiotap_he *he = NULL;
2361*4882a593Smuzhiyun 	char tid[32];
2362*4882a593Smuzhiyun 
2363*4882a593Smuzhiyun 	status = IEEE80211_SKB_RXCB(msdu);
2364*4882a593Smuzhiyun 	if (status->encoding == RX_ENC_HE) {
2365*4882a593Smuzhiyun 		he = skb_push(msdu, sizeof(known));
2366*4882a593Smuzhiyun 		memcpy(he, &known, sizeof(known));
2367*4882a593Smuzhiyun 		status->flag |= RX_FLAG_RADIOTAP_HE;
2368*4882a593Smuzhiyun 	}
2369*4882a593Smuzhiyun 
2370*4882a593Smuzhiyun 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2371*4882a593Smuzhiyun 		   "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2372*4882a593Smuzhiyun 		   msdu,
2373*4882a593Smuzhiyun 		   msdu->len,
2374*4882a593Smuzhiyun 		   ieee80211_get_SA(hdr),
2375*4882a593Smuzhiyun 		   ath11k_print_get_tid(hdr, tid, sizeof(tid)),
2376*4882a593Smuzhiyun 		   is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
2377*4882a593Smuzhiyun 							"mcast" : "ucast",
2378*4882a593Smuzhiyun 		   (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
2379*4882a593Smuzhiyun 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2380*4882a593Smuzhiyun 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2381*4882a593Smuzhiyun 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2382*4882a593Smuzhiyun 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2383*4882a593Smuzhiyun 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2384*4882a593Smuzhiyun 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2385*4882a593Smuzhiyun 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2386*4882a593Smuzhiyun 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2387*4882a593Smuzhiyun 		   status->rate_idx,
2388*4882a593Smuzhiyun 		   status->nss,
2389*4882a593Smuzhiyun 		   status->freq,
2390*4882a593Smuzhiyun 		   status->band, status->flag,
2391*4882a593Smuzhiyun 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2392*4882a593Smuzhiyun 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2393*4882a593Smuzhiyun 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2394*4882a593Smuzhiyun 
2395*4882a593Smuzhiyun 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2396*4882a593Smuzhiyun 			msdu->data, msdu->len);
2397*4882a593Smuzhiyun 
2398*4882a593Smuzhiyun 	/* TODO: trace rx packet */
2399*4882a593Smuzhiyun 
2400*4882a593Smuzhiyun 	ieee80211_rx_napi(ar->hw, NULL, msdu, napi);
2401*4882a593Smuzhiyun }
2402*4882a593Smuzhiyun 
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list)2403*4882a593Smuzhiyun static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2404*4882a593Smuzhiyun 				     struct sk_buff *msdu,
2405*4882a593Smuzhiyun 				     struct sk_buff_head *msdu_list)
2406*4882a593Smuzhiyun {
2407*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc, *lrx_desc;
2408*4882a593Smuzhiyun 	struct ieee80211_rx_status rx_status = {0};
2409*4882a593Smuzhiyun 	struct ieee80211_rx_status *status;
2410*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
2411*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
2412*4882a593Smuzhiyun 	struct sk_buff *last_buf;
2413*4882a593Smuzhiyun 	u8 l3_pad_bytes;
2414*4882a593Smuzhiyun 	u8 *hdr_status;
2415*4882a593Smuzhiyun 	u16 msdu_len;
2416*4882a593Smuzhiyun 	int ret;
2417*4882a593Smuzhiyun 
2418*4882a593Smuzhiyun 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2419*4882a593Smuzhiyun 	if (!last_buf) {
2420*4882a593Smuzhiyun 		ath11k_warn(ar->ab,
2421*4882a593Smuzhiyun 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2422*4882a593Smuzhiyun 		ret = -EIO;
2423*4882a593Smuzhiyun 		goto free_out;
2424*4882a593Smuzhiyun 	}
2425*4882a593Smuzhiyun 
2426*4882a593Smuzhiyun 	rx_desc = (struct hal_rx_desc *)msdu->data;
2427*4882a593Smuzhiyun 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2428*4882a593Smuzhiyun 	if (!ath11k_dp_rx_h_attn_msdu_done(lrx_desc)) {
2429*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "msdu_done bit in attention is not set\n");
2430*4882a593Smuzhiyun 		ret = -EIO;
2431*4882a593Smuzhiyun 		goto free_out;
2432*4882a593Smuzhiyun 	}
2433*4882a593Smuzhiyun 
2434*4882a593Smuzhiyun 	rxcb = ATH11K_SKB_RXCB(msdu);
2435*4882a593Smuzhiyun 	rxcb->rx_desc = rx_desc;
2436*4882a593Smuzhiyun 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc);
2437*4882a593Smuzhiyun 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(lrx_desc);
2438*4882a593Smuzhiyun 
2439*4882a593Smuzhiyun 	if (rxcb->is_frag) {
2440*4882a593Smuzhiyun 		skb_pull(msdu, HAL_RX_DESC_SIZE);
2441*4882a593Smuzhiyun 	} else if (!rxcb->is_continuation) {
2442*4882a593Smuzhiyun 		if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) {
2443*4882a593Smuzhiyun 			hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc);
2444*4882a593Smuzhiyun 			ret = -EINVAL;
2445*4882a593Smuzhiyun 			ath11k_warn(ar->ab, "invalid msdu len %u\n", msdu_len);
2446*4882a593Smuzhiyun 			ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2447*4882a593Smuzhiyun 					sizeof(struct ieee80211_hdr));
2448*4882a593Smuzhiyun 			ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2449*4882a593Smuzhiyun 					sizeof(struct hal_rx_desc));
2450*4882a593Smuzhiyun 			goto free_out;
2451*4882a593Smuzhiyun 		}
2452*4882a593Smuzhiyun 		skb_put(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes + msdu_len);
2453*4882a593Smuzhiyun 		skb_pull(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes);
2454*4882a593Smuzhiyun 	} else {
2455*4882a593Smuzhiyun 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2456*4882a593Smuzhiyun 						 msdu, last_buf,
2457*4882a593Smuzhiyun 						 l3_pad_bytes, msdu_len);
2458*4882a593Smuzhiyun 		if (ret) {
2459*4882a593Smuzhiyun 			ath11k_warn(ar->ab,
2460*4882a593Smuzhiyun 				    "failed to coalesce msdu rx buffer%d\n", ret);
2461*4882a593Smuzhiyun 			goto free_out;
2462*4882a593Smuzhiyun 		}
2463*4882a593Smuzhiyun 	}
2464*4882a593Smuzhiyun 
2465*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)msdu->data;
2466*4882a593Smuzhiyun 
2467*4882a593Smuzhiyun 	/* Process only data frames */
2468*4882a593Smuzhiyun 	if (!ieee80211_is_data(hdr->frame_control))
2469*4882a593Smuzhiyun 		return -EINVAL;
2470*4882a593Smuzhiyun 
2471*4882a593Smuzhiyun 	ath11k_dp_rx_h_ppdu(ar, rx_desc, &rx_status);
2472*4882a593Smuzhiyun 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, &rx_status);
2473*4882a593Smuzhiyun 
2474*4882a593Smuzhiyun 	rx_status.flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2475*4882a593Smuzhiyun 
2476*4882a593Smuzhiyun 	status = IEEE80211_SKB_RXCB(msdu);
2477*4882a593Smuzhiyun 	*status = rx_status;
2478*4882a593Smuzhiyun 	return 0;
2479*4882a593Smuzhiyun 
2480*4882a593Smuzhiyun free_out:
2481*4882a593Smuzhiyun 	return ret;
2482*4882a593Smuzhiyun }
2483*4882a593Smuzhiyun 
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int * quota,int ring_id)2484*4882a593Smuzhiyun static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2485*4882a593Smuzhiyun 						  struct napi_struct *napi,
2486*4882a593Smuzhiyun 						  struct sk_buff_head *msdu_list,
2487*4882a593Smuzhiyun 						  int *quota, int ring_id)
2488*4882a593Smuzhiyun {
2489*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
2490*4882a593Smuzhiyun 	struct sk_buff *msdu;
2491*4882a593Smuzhiyun 	struct ath11k *ar;
2492*4882a593Smuzhiyun 	u8 mac_id;
2493*4882a593Smuzhiyun 	int ret;
2494*4882a593Smuzhiyun 
2495*4882a593Smuzhiyun 	if (skb_queue_empty(msdu_list))
2496*4882a593Smuzhiyun 		return;
2497*4882a593Smuzhiyun 
2498*4882a593Smuzhiyun 	rcu_read_lock();
2499*4882a593Smuzhiyun 
2500*4882a593Smuzhiyun 	while (*quota && (msdu = __skb_dequeue(msdu_list))) {
2501*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(msdu);
2502*4882a593Smuzhiyun 		mac_id = rxcb->mac_id;
2503*4882a593Smuzhiyun 		ar = ab->pdevs[mac_id].ar;
2504*4882a593Smuzhiyun 		if (!rcu_dereference(ab->pdevs_active[mac_id])) {
2505*4882a593Smuzhiyun 			dev_kfree_skb_any(msdu);
2506*4882a593Smuzhiyun 			continue;
2507*4882a593Smuzhiyun 		}
2508*4882a593Smuzhiyun 
2509*4882a593Smuzhiyun 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
2510*4882a593Smuzhiyun 			dev_kfree_skb_any(msdu);
2511*4882a593Smuzhiyun 			continue;
2512*4882a593Smuzhiyun 		}
2513*4882a593Smuzhiyun 
2514*4882a593Smuzhiyun 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list);
2515*4882a593Smuzhiyun 		if (ret) {
2516*4882a593Smuzhiyun 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2517*4882a593Smuzhiyun 				   "Unable to process msdu %d", ret);
2518*4882a593Smuzhiyun 			dev_kfree_skb_any(msdu);
2519*4882a593Smuzhiyun 			continue;
2520*4882a593Smuzhiyun 		}
2521*4882a593Smuzhiyun 
2522*4882a593Smuzhiyun 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
2523*4882a593Smuzhiyun 		(*quota)--;
2524*4882a593Smuzhiyun 	}
2525*4882a593Smuzhiyun 
2526*4882a593Smuzhiyun 	rcu_read_unlock();
2527*4882a593Smuzhiyun }
2528*4882a593Smuzhiyun 
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2529*4882a593Smuzhiyun int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2530*4882a593Smuzhiyun 			 struct napi_struct *napi, int budget)
2531*4882a593Smuzhiyun {
2532*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
2533*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring;
2534*4882a593Smuzhiyun 	int num_buffs_reaped[MAX_RADIOS] = {0};
2535*4882a593Smuzhiyun 	struct sk_buff_head msdu_list;
2536*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
2537*4882a593Smuzhiyun 	int total_msdu_reaped = 0;
2538*4882a593Smuzhiyun 	struct hal_srng *srng;
2539*4882a593Smuzhiyun 	struct sk_buff *msdu;
2540*4882a593Smuzhiyun 	int quota = budget;
2541*4882a593Smuzhiyun 	bool done = false;
2542*4882a593Smuzhiyun 	int buf_id, mac_id;
2543*4882a593Smuzhiyun 	struct ath11k *ar;
2544*4882a593Smuzhiyun 	u32 *rx_desc;
2545*4882a593Smuzhiyun 	int i;
2546*4882a593Smuzhiyun 
2547*4882a593Smuzhiyun 	__skb_queue_head_init(&msdu_list);
2548*4882a593Smuzhiyun 
2549*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2550*4882a593Smuzhiyun 
2551*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
2552*4882a593Smuzhiyun 
2553*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
2554*4882a593Smuzhiyun 
2555*4882a593Smuzhiyun try_again:
2556*4882a593Smuzhiyun 	while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
2557*4882a593Smuzhiyun 		struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc;
2558*4882a593Smuzhiyun 		enum hal_reo_dest_ring_push_reason push_reason;
2559*4882a593Smuzhiyun 		u32 cookie;
2560*4882a593Smuzhiyun 
2561*4882a593Smuzhiyun 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2562*4882a593Smuzhiyun 				   desc.buf_addr_info.info1);
2563*4882a593Smuzhiyun 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2564*4882a593Smuzhiyun 				   cookie);
2565*4882a593Smuzhiyun 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2566*4882a593Smuzhiyun 
2567*4882a593Smuzhiyun 		ar = ab->pdevs[mac_id].ar;
2568*4882a593Smuzhiyun 		rx_ring = &ar->dp.rx_refill_buf_ring;
2569*4882a593Smuzhiyun 		spin_lock_bh(&rx_ring->idr_lock);
2570*4882a593Smuzhiyun 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2571*4882a593Smuzhiyun 		if (!msdu) {
2572*4882a593Smuzhiyun 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2573*4882a593Smuzhiyun 				    buf_id);
2574*4882a593Smuzhiyun 			spin_unlock_bh(&rx_ring->idr_lock);
2575*4882a593Smuzhiyun 			continue;
2576*4882a593Smuzhiyun 		}
2577*4882a593Smuzhiyun 
2578*4882a593Smuzhiyun 		idr_remove(&rx_ring->bufs_idr, buf_id);
2579*4882a593Smuzhiyun 		spin_unlock_bh(&rx_ring->idr_lock);
2580*4882a593Smuzhiyun 
2581*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(msdu);
2582*4882a593Smuzhiyun 		dma_unmap_single(ab->dev, rxcb->paddr,
2583*4882a593Smuzhiyun 				 msdu->len + skb_tailroom(msdu),
2584*4882a593Smuzhiyun 				 DMA_FROM_DEVICE);
2585*4882a593Smuzhiyun 
2586*4882a593Smuzhiyun 		num_buffs_reaped[mac_id]++;
2587*4882a593Smuzhiyun 		total_msdu_reaped++;
2588*4882a593Smuzhiyun 
2589*4882a593Smuzhiyun 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2590*4882a593Smuzhiyun 					desc.info0);
2591*4882a593Smuzhiyun 		if (push_reason !=
2592*4882a593Smuzhiyun 		    HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2593*4882a593Smuzhiyun 			dev_kfree_skb_any(msdu);
2594*4882a593Smuzhiyun 			ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2595*4882a593Smuzhiyun 			continue;
2596*4882a593Smuzhiyun 		}
2597*4882a593Smuzhiyun 
2598*4882a593Smuzhiyun 		rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 &
2599*4882a593Smuzhiyun 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2600*4882a593Smuzhiyun 		rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 &
2601*4882a593Smuzhiyun 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2602*4882a593Smuzhiyun 		rxcb->is_continuation = !!(desc.rx_msdu_info.info0 &
2603*4882a593Smuzhiyun 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2604*4882a593Smuzhiyun 		rxcb->mac_id = mac_id;
2605*4882a593Smuzhiyun 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2606*4882a593Smuzhiyun 				      desc.info0);
2607*4882a593Smuzhiyun 
2608*4882a593Smuzhiyun 		__skb_queue_tail(&msdu_list, msdu);
2609*4882a593Smuzhiyun 
2610*4882a593Smuzhiyun 		if (total_msdu_reaped >= quota && !rxcb->is_continuation) {
2611*4882a593Smuzhiyun 			done = true;
2612*4882a593Smuzhiyun 			break;
2613*4882a593Smuzhiyun 		}
2614*4882a593Smuzhiyun 	}
2615*4882a593Smuzhiyun 
2616*4882a593Smuzhiyun 	/* Hw might have updated the head pointer after we cached it.
2617*4882a593Smuzhiyun 	 * In this case, even though there are entries in the ring we'll
2618*4882a593Smuzhiyun 	 * get rx_desc NULL. Give the read another try with updated cached
2619*4882a593Smuzhiyun 	 * head pointer so that we can reap complete MPDU in the current
2620*4882a593Smuzhiyun 	 * rx processing.
2621*4882a593Smuzhiyun 	 */
2622*4882a593Smuzhiyun 	if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) {
2623*4882a593Smuzhiyun 		ath11k_hal_srng_access_end(ab, srng);
2624*4882a593Smuzhiyun 		goto try_again;
2625*4882a593Smuzhiyun 	}
2626*4882a593Smuzhiyun 
2627*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
2628*4882a593Smuzhiyun 
2629*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
2630*4882a593Smuzhiyun 
2631*4882a593Smuzhiyun 	if (!total_msdu_reaped)
2632*4882a593Smuzhiyun 		goto exit;
2633*4882a593Smuzhiyun 
2634*4882a593Smuzhiyun 	for (i = 0; i < ab->num_radios; i++) {
2635*4882a593Smuzhiyun 		if (!num_buffs_reaped[i])
2636*4882a593Smuzhiyun 			continue;
2637*4882a593Smuzhiyun 
2638*4882a593Smuzhiyun 		ar = ab->pdevs[i].ar;
2639*4882a593Smuzhiyun 		rx_ring = &ar->dp.rx_refill_buf_ring;
2640*4882a593Smuzhiyun 
2641*4882a593Smuzhiyun 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2642*4882a593Smuzhiyun 					   HAL_RX_BUF_RBM_SW3_BM);
2643*4882a593Smuzhiyun 	}
2644*4882a593Smuzhiyun 
2645*4882a593Smuzhiyun 	ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2646*4882a593Smuzhiyun 					      &quota, ring_id);
2647*4882a593Smuzhiyun 
2648*4882a593Smuzhiyun exit:
2649*4882a593Smuzhiyun 	return budget - quota;
2650*4882a593Smuzhiyun }
2651*4882a593Smuzhiyun 
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2652*4882a593Smuzhiyun static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2653*4882a593Smuzhiyun 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2654*4882a593Smuzhiyun {
2655*4882a593Smuzhiyun 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2656*4882a593Smuzhiyun 	u32 num_msdu;
2657*4882a593Smuzhiyun 
2658*4882a593Smuzhiyun 	if (!rx_stats)
2659*4882a593Smuzhiyun 		return;
2660*4882a593Smuzhiyun 
2661*4882a593Smuzhiyun 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2662*4882a593Smuzhiyun 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2663*4882a593Smuzhiyun 
2664*4882a593Smuzhiyun 	rx_stats->num_msdu += num_msdu;
2665*4882a593Smuzhiyun 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2666*4882a593Smuzhiyun 				    ppdu_info->tcp_ack_msdu_count;
2667*4882a593Smuzhiyun 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2668*4882a593Smuzhiyun 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2669*4882a593Smuzhiyun 
2670*4882a593Smuzhiyun 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2671*4882a593Smuzhiyun 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2672*4882a593Smuzhiyun 		ppdu_info->nss = 1;
2673*4882a593Smuzhiyun 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2674*4882a593Smuzhiyun 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2675*4882a593Smuzhiyun 	}
2676*4882a593Smuzhiyun 
2677*4882a593Smuzhiyun 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2678*4882a593Smuzhiyun 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2679*4882a593Smuzhiyun 
2680*4882a593Smuzhiyun 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2681*4882a593Smuzhiyun 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2682*4882a593Smuzhiyun 
2683*4882a593Smuzhiyun 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2684*4882a593Smuzhiyun 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2685*4882a593Smuzhiyun 
2686*4882a593Smuzhiyun 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2687*4882a593Smuzhiyun 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2688*4882a593Smuzhiyun 
2689*4882a593Smuzhiyun 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2690*4882a593Smuzhiyun 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2691*4882a593Smuzhiyun 
2692*4882a593Smuzhiyun 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2693*4882a593Smuzhiyun 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2694*4882a593Smuzhiyun 
2695*4882a593Smuzhiyun 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2696*4882a593Smuzhiyun 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2697*4882a593Smuzhiyun 
2698*4882a593Smuzhiyun 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2699*4882a593Smuzhiyun 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2700*4882a593Smuzhiyun 
2701*4882a593Smuzhiyun 	if (ppdu_info->is_stbc)
2702*4882a593Smuzhiyun 		rx_stats->stbc_count += num_msdu;
2703*4882a593Smuzhiyun 
2704*4882a593Smuzhiyun 	if (ppdu_info->beamformed)
2705*4882a593Smuzhiyun 		rx_stats->beamformed_count += num_msdu;
2706*4882a593Smuzhiyun 
2707*4882a593Smuzhiyun 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2708*4882a593Smuzhiyun 		rx_stats->ampdu_msdu_count += num_msdu;
2709*4882a593Smuzhiyun 	else
2710*4882a593Smuzhiyun 		rx_stats->non_ampdu_msdu_count += num_msdu;
2711*4882a593Smuzhiyun 
2712*4882a593Smuzhiyun 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2713*4882a593Smuzhiyun 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2714*4882a593Smuzhiyun 	rx_stats->dcm_count += ppdu_info->dcm;
2715*4882a593Smuzhiyun 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2716*4882a593Smuzhiyun 
2717*4882a593Smuzhiyun 	arsta->rssi_comb = ppdu_info->rssi_comb;
2718*4882a593Smuzhiyun 	rx_stats->rx_duration += ppdu_info->rx_duration;
2719*4882a593Smuzhiyun 	arsta->rx_duration = rx_stats->rx_duration;
2720*4882a593Smuzhiyun }
2721*4882a593Smuzhiyun 
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2722*4882a593Smuzhiyun static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2723*4882a593Smuzhiyun 							 struct dp_rxdma_ring *rx_ring,
2724*4882a593Smuzhiyun 							 int *buf_id)
2725*4882a593Smuzhiyun {
2726*4882a593Smuzhiyun 	struct sk_buff *skb;
2727*4882a593Smuzhiyun 	dma_addr_t paddr;
2728*4882a593Smuzhiyun 
2729*4882a593Smuzhiyun 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2730*4882a593Smuzhiyun 			    DP_RX_BUFFER_ALIGN_SIZE);
2731*4882a593Smuzhiyun 
2732*4882a593Smuzhiyun 	if (!skb)
2733*4882a593Smuzhiyun 		goto fail_alloc_skb;
2734*4882a593Smuzhiyun 
2735*4882a593Smuzhiyun 	if (!IS_ALIGNED((unsigned long)skb->data,
2736*4882a593Smuzhiyun 			DP_RX_BUFFER_ALIGN_SIZE)) {
2737*4882a593Smuzhiyun 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2738*4882a593Smuzhiyun 			 skb->data);
2739*4882a593Smuzhiyun 	}
2740*4882a593Smuzhiyun 
2741*4882a593Smuzhiyun 	paddr = dma_map_single(ab->dev, skb->data,
2742*4882a593Smuzhiyun 			       skb->len + skb_tailroom(skb),
2743*4882a593Smuzhiyun 			       DMA_BIDIRECTIONAL);
2744*4882a593Smuzhiyun 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2745*4882a593Smuzhiyun 		goto fail_free_skb;
2746*4882a593Smuzhiyun 
2747*4882a593Smuzhiyun 	spin_lock_bh(&rx_ring->idr_lock);
2748*4882a593Smuzhiyun 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2749*4882a593Smuzhiyun 			    rx_ring->bufs_max, GFP_ATOMIC);
2750*4882a593Smuzhiyun 	spin_unlock_bh(&rx_ring->idr_lock);
2751*4882a593Smuzhiyun 	if (*buf_id < 0)
2752*4882a593Smuzhiyun 		goto fail_dma_unmap;
2753*4882a593Smuzhiyun 
2754*4882a593Smuzhiyun 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2755*4882a593Smuzhiyun 	return skb;
2756*4882a593Smuzhiyun 
2757*4882a593Smuzhiyun fail_dma_unmap:
2758*4882a593Smuzhiyun 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2759*4882a593Smuzhiyun 			 DMA_BIDIRECTIONAL);
2760*4882a593Smuzhiyun fail_free_skb:
2761*4882a593Smuzhiyun 	dev_kfree_skb_any(skb);
2762*4882a593Smuzhiyun fail_alloc_skb:
2763*4882a593Smuzhiyun 	return NULL;
2764*4882a593Smuzhiyun }
2765*4882a593Smuzhiyun 
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2766*4882a593Smuzhiyun int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2767*4882a593Smuzhiyun 					   struct dp_rxdma_ring *rx_ring,
2768*4882a593Smuzhiyun 					   int req_entries,
2769*4882a593Smuzhiyun 					   enum hal_rx_buf_return_buf_manager mgr)
2770*4882a593Smuzhiyun {
2771*4882a593Smuzhiyun 	struct hal_srng *srng;
2772*4882a593Smuzhiyun 	u32 *desc;
2773*4882a593Smuzhiyun 	struct sk_buff *skb;
2774*4882a593Smuzhiyun 	int num_free;
2775*4882a593Smuzhiyun 	int num_remain;
2776*4882a593Smuzhiyun 	int buf_id;
2777*4882a593Smuzhiyun 	u32 cookie;
2778*4882a593Smuzhiyun 	dma_addr_t paddr;
2779*4882a593Smuzhiyun 
2780*4882a593Smuzhiyun 	req_entries = min(req_entries, rx_ring->bufs_max);
2781*4882a593Smuzhiyun 
2782*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2783*4882a593Smuzhiyun 
2784*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
2785*4882a593Smuzhiyun 
2786*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
2787*4882a593Smuzhiyun 
2788*4882a593Smuzhiyun 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2789*4882a593Smuzhiyun 
2790*4882a593Smuzhiyun 	req_entries = min(num_free, req_entries);
2791*4882a593Smuzhiyun 	num_remain = req_entries;
2792*4882a593Smuzhiyun 
2793*4882a593Smuzhiyun 	while (num_remain > 0) {
2794*4882a593Smuzhiyun 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2795*4882a593Smuzhiyun 							&buf_id);
2796*4882a593Smuzhiyun 		if (!skb)
2797*4882a593Smuzhiyun 			break;
2798*4882a593Smuzhiyun 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2799*4882a593Smuzhiyun 
2800*4882a593Smuzhiyun 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2801*4882a593Smuzhiyun 		if (!desc)
2802*4882a593Smuzhiyun 			goto fail_desc_get;
2803*4882a593Smuzhiyun 
2804*4882a593Smuzhiyun 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2805*4882a593Smuzhiyun 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2806*4882a593Smuzhiyun 
2807*4882a593Smuzhiyun 		num_remain--;
2808*4882a593Smuzhiyun 
2809*4882a593Smuzhiyun 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2810*4882a593Smuzhiyun 	}
2811*4882a593Smuzhiyun 
2812*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
2813*4882a593Smuzhiyun 
2814*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
2815*4882a593Smuzhiyun 
2816*4882a593Smuzhiyun 	return req_entries - num_remain;
2817*4882a593Smuzhiyun 
2818*4882a593Smuzhiyun fail_desc_get:
2819*4882a593Smuzhiyun 	spin_lock_bh(&rx_ring->idr_lock);
2820*4882a593Smuzhiyun 	idr_remove(&rx_ring->bufs_idr, buf_id);
2821*4882a593Smuzhiyun 	spin_unlock_bh(&rx_ring->idr_lock);
2822*4882a593Smuzhiyun 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2823*4882a593Smuzhiyun 			 DMA_BIDIRECTIONAL);
2824*4882a593Smuzhiyun 	dev_kfree_skb_any(skb);
2825*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
2826*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
2827*4882a593Smuzhiyun 
2828*4882a593Smuzhiyun 	return req_entries - num_remain;
2829*4882a593Smuzhiyun }
2830*4882a593Smuzhiyun 
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)2831*4882a593Smuzhiyun static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2832*4882a593Smuzhiyun 					     int *budget, struct sk_buff_head *skb_list)
2833*4882a593Smuzhiyun {
2834*4882a593Smuzhiyun 	struct ath11k *ar;
2835*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp;
2836*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring;
2837*4882a593Smuzhiyun 	struct hal_srng *srng;
2838*4882a593Smuzhiyun 	void *rx_mon_status_desc;
2839*4882a593Smuzhiyun 	struct sk_buff *skb;
2840*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
2841*4882a593Smuzhiyun 	struct hal_tlv_hdr *tlv;
2842*4882a593Smuzhiyun 	u32 cookie;
2843*4882a593Smuzhiyun 	int buf_id, srng_id;
2844*4882a593Smuzhiyun 	dma_addr_t paddr;
2845*4882a593Smuzhiyun 	u8 rbm;
2846*4882a593Smuzhiyun 	int num_buffs_reaped = 0;
2847*4882a593Smuzhiyun 
2848*4882a593Smuzhiyun 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
2849*4882a593Smuzhiyun 	dp = &ar->dp;
2850*4882a593Smuzhiyun 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
2851*4882a593Smuzhiyun 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
2852*4882a593Smuzhiyun 
2853*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2854*4882a593Smuzhiyun 
2855*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
2856*4882a593Smuzhiyun 
2857*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
2858*4882a593Smuzhiyun 	while (*budget) {
2859*4882a593Smuzhiyun 		*budget -= 1;
2860*4882a593Smuzhiyun 		rx_mon_status_desc =
2861*4882a593Smuzhiyun 			ath11k_hal_srng_src_peek(ab, srng);
2862*4882a593Smuzhiyun 		if (!rx_mon_status_desc)
2863*4882a593Smuzhiyun 			break;
2864*4882a593Smuzhiyun 
2865*4882a593Smuzhiyun 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
2866*4882a593Smuzhiyun 						&cookie, &rbm);
2867*4882a593Smuzhiyun 		if (paddr) {
2868*4882a593Smuzhiyun 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
2869*4882a593Smuzhiyun 
2870*4882a593Smuzhiyun 			spin_lock_bh(&rx_ring->idr_lock);
2871*4882a593Smuzhiyun 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
2872*4882a593Smuzhiyun 			if (!skb) {
2873*4882a593Smuzhiyun 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
2874*4882a593Smuzhiyun 					    buf_id);
2875*4882a593Smuzhiyun 				spin_unlock_bh(&rx_ring->idr_lock);
2876*4882a593Smuzhiyun 				goto move_next;
2877*4882a593Smuzhiyun 			}
2878*4882a593Smuzhiyun 
2879*4882a593Smuzhiyun 			idr_remove(&rx_ring->bufs_idr, buf_id);
2880*4882a593Smuzhiyun 			spin_unlock_bh(&rx_ring->idr_lock);
2881*4882a593Smuzhiyun 
2882*4882a593Smuzhiyun 			rxcb = ATH11K_SKB_RXCB(skb);
2883*4882a593Smuzhiyun 
2884*4882a593Smuzhiyun 			dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
2885*4882a593Smuzhiyun 						skb->len + skb_tailroom(skb),
2886*4882a593Smuzhiyun 						DMA_FROM_DEVICE);
2887*4882a593Smuzhiyun 
2888*4882a593Smuzhiyun 			dma_unmap_single(ab->dev, rxcb->paddr,
2889*4882a593Smuzhiyun 					 skb->len + skb_tailroom(skb),
2890*4882a593Smuzhiyun 					 DMA_BIDIRECTIONAL);
2891*4882a593Smuzhiyun 
2892*4882a593Smuzhiyun 			tlv = (struct hal_tlv_hdr *)skb->data;
2893*4882a593Smuzhiyun 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
2894*4882a593Smuzhiyun 					HAL_RX_STATUS_BUFFER_DONE) {
2895*4882a593Smuzhiyun 				ath11k_warn(ab, "mon status DONE not set %lx\n",
2896*4882a593Smuzhiyun 					    FIELD_GET(HAL_TLV_HDR_TAG,
2897*4882a593Smuzhiyun 						      tlv->tl));
2898*4882a593Smuzhiyun 				dev_kfree_skb_any(skb);
2899*4882a593Smuzhiyun 				goto move_next;
2900*4882a593Smuzhiyun 			}
2901*4882a593Smuzhiyun 
2902*4882a593Smuzhiyun 			__skb_queue_tail(skb_list, skb);
2903*4882a593Smuzhiyun 		}
2904*4882a593Smuzhiyun move_next:
2905*4882a593Smuzhiyun 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2906*4882a593Smuzhiyun 							&buf_id);
2907*4882a593Smuzhiyun 
2908*4882a593Smuzhiyun 		if (!skb) {
2909*4882a593Smuzhiyun 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
2910*4882a593Smuzhiyun 							HAL_RX_BUF_RBM_SW3_BM);
2911*4882a593Smuzhiyun 			num_buffs_reaped++;
2912*4882a593Smuzhiyun 			break;
2913*4882a593Smuzhiyun 		}
2914*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(skb);
2915*4882a593Smuzhiyun 
2916*4882a593Smuzhiyun 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2917*4882a593Smuzhiyun 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2918*4882a593Smuzhiyun 
2919*4882a593Smuzhiyun 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
2920*4882a593Smuzhiyun 						cookie, HAL_RX_BUF_RBM_SW3_BM);
2921*4882a593Smuzhiyun 		ath11k_hal_srng_src_get_next_entry(ab, srng);
2922*4882a593Smuzhiyun 		num_buffs_reaped++;
2923*4882a593Smuzhiyun 	}
2924*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
2925*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
2926*4882a593Smuzhiyun 
2927*4882a593Smuzhiyun 	return num_buffs_reaped;
2928*4882a593Smuzhiyun }
2929*4882a593Smuzhiyun 
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)2930*4882a593Smuzhiyun int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
2931*4882a593Smuzhiyun 				    struct napi_struct *napi, int budget)
2932*4882a593Smuzhiyun {
2933*4882a593Smuzhiyun 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
2934*4882a593Smuzhiyun 	enum hal_rx_mon_status hal_status;
2935*4882a593Smuzhiyun 	struct sk_buff *skb;
2936*4882a593Smuzhiyun 	struct sk_buff_head skb_list;
2937*4882a593Smuzhiyun 	struct hal_rx_mon_ppdu_info ppdu_info;
2938*4882a593Smuzhiyun 	struct ath11k_peer *peer;
2939*4882a593Smuzhiyun 	struct ath11k_sta *arsta;
2940*4882a593Smuzhiyun 	int num_buffs_reaped = 0;
2941*4882a593Smuzhiyun 
2942*4882a593Smuzhiyun 	__skb_queue_head_init(&skb_list);
2943*4882a593Smuzhiyun 
2944*4882a593Smuzhiyun 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
2945*4882a593Smuzhiyun 							     &skb_list);
2946*4882a593Smuzhiyun 	if (!num_buffs_reaped)
2947*4882a593Smuzhiyun 		goto exit;
2948*4882a593Smuzhiyun 
2949*4882a593Smuzhiyun 	while ((skb = __skb_dequeue(&skb_list))) {
2950*4882a593Smuzhiyun 		memset(&ppdu_info, 0, sizeof(ppdu_info));
2951*4882a593Smuzhiyun 		ppdu_info.peer_id = HAL_INVALID_PEERID;
2952*4882a593Smuzhiyun 
2953*4882a593Smuzhiyun 		if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar))
2954*4882a593Smuzhiyun 			trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2955*4882a593Smuzhiyun 
2956*4882a593Smuzhiyun 		hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
2957*4882a593Smuzhiyun 
2958*4882a593Smuzhiyun 		if (ppdu_info.peer_id == HAL_INVALID_PEERID ||
2959*4882a593Smuzhiyun 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2960*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
2961*4882a593Smuzhiyun 			continue;
2962*4882a593Smuzhiyun 		}
2963*4882a593Smuzhiyun 
2964*4882a593Smuzhiyun 		rcu_read_lock();
2965*4882a593Smuzhiyun 		spin_lock_bh(&ab->base_lock);
2966*4882a593Smuzhiyun 		peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id);
2967*4882a593Smuzhiyun 
2968*4882a593Smuzhiyun 		if (!peer || !peer->sta) {
2969*4882a593Smuzhiyun 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2970*4882a593Smuzhiyun 				   "failed to find the peer with peer_id %d\n",
2971*4882a593Smuzhiyun 				   ppdu_info.peer_id);
2972*4882a593Smuzhiyun 			spin_unlock_bh(&ab->base_lock);
2973*4882a593Smuzhiyun 			rcu_read_unlock();
2974*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
2975*4882a593Smuzhiyun 			continue;
2976*4882a593Smuzhiyun 		}
2977*4882a593Smuzhiyun 
2978*4882a593Smuzhiyun 		arsta = (struct ath11k_sta *)peer->sta->drv_priv;
2979*4882a593Smuzhiyun 		ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
2980*4882a593Smuzhiyun 
2981*4882a593Smuzhiyun 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
2982*4882a593Smuzhiyun 			trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2983*4882a593Smuzhiyun 
2984*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
2985*4882a593Smuzhiyun 		rcu_read_unlock();
2986*4882a593Smuzhiyun 
2987*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
2988*4882a593Smuzhiyun 	}
2989*4882a593Smuzhiyun exit:
2990*4882a593Smuzhiyun 	return num_buffs_reaped;
2991*4882a593Smuzhiyun }
2992*4882a593Smuzhiyun 
ath11k_dp_rx_frag_timer(struct timer_list * timer)2993*4882a593Smuzhiyun static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
2994*4882a593Smuzhiyun {
2995*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2996*4882a593Smuzhiyun 
2997*4882a593Smuzhiyun 	spin_lock_bh(&rx_tid->ab->base_lock);
2998*4882a593Smuzhiyun 	if (rx_tid->last_frag_no &&
2999*4882a593Smuzhiyun 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3000*4882a593Smuzhiyun 		spin_unlock_bh(&rx_tid->ab->base_lock);
3001*4882a593Smuzhiyun 		return;
3002*4882a593Smuzhiyun 	}
3003*4882a593Smuzhiyun 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3004*4882a593Smuzhiyun 	spin_unlock_bh(&rx_tid->ab->base_lock);
3005*4882a593Smuzhiyun }
3006*4882a593Smuzhiyun 
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3007*4882a593Smuzhiyun int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3008*4882a593Smuzhiyun {
3009*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
3010*4882a593Smuzhiyun 	struct crypto_shash *tfm;
3011*4882a593Smuzhiyun 	struct ath11k_peer *peer;
3012*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
3013*4882a593Smuzhiyun 	int i;
3014*4882a593Smuzhiyun 
3015*4882a593Smuzhiyun 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3016*4882a593Smuzhiyun 	if (IS_ERR(tfm))
3017*4882a593Smuzhiyun 		return PTR_ERR(tfm);
3018*4882a593Smuzhiyun 
3019*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
3020*4882a593Smuzhiyun 
3021*4882a593Smuzhiyun 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3022*4882a593Smuzhiyun 	if (!peer) {
3023*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3024*4882a593Smuzhiyun 		spin_unlock_bh(&ab->base_lock);
3025*4882a593Smuzhiyun 		return -ENOENT;
3026*4882a593Smuzhiyun 	}
3027*4882a593Smuzhiyun 
3028*4882a593Smuzhiyun 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3029*4882a593Smuzhiyun 		rx_tid = &peer->rx_tid[i];
3030*4882a593Smuzhiyun 		rx_tid->ab = ab;
3031*4882a593Smuzhiyun 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3032*4882a593Smuzhiyun 		skb_queue_head_init(&rx_tid->rx_frags);
3033*4882a593Smuzhiyun 	}
3034*4882a593Smuzhiyun 
3035*4882a593Smuzhiyun 	peer->tfm_mmic = tfm;
3036*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
3037*4882a593Smuzhiyun 
3038*4882a593Smuzhiyun 	return 0;
3039*4882a593Smuzhiyun }
3040*4882a593Smuzhiyun 
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3041*4882a593Smuzhiyun static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3042*4882a593Smuzhiyun 				      struct ieee80211_hdr *hdr, u8 *data,
3043*4882a593Smuzhiyun 				      size_t data_len, u8 *mic)
3044*4882a593Smuzhiyun {
3045*4882a593Smuzhiyun 	SHASH_DESC_ON_STACK(desc, tfm);
3046*4882a593Smuzhiyun 	u8 mic_hdr[16] = {0};
3047*4882a593Smuzhiyun 	u8 tid = 0;
3048*4882a593Smuzhiyun 	int ret;
3049*4882a593Smuzhiyun 
3050*4882a593Smuzhiyun 	if (!tfm)
3051*4882a593Smuzhiyun 		return -EINVAL;
3052*4882a593Smuzhiyun 
3053*4882a593Smuzhiyun 	desc->tfm = tfm;
3054*4882a593Smuzhiyun 
3055*4882a593Smuzhiyun 	ret = crypto_shash_setkey(tfm, key, 8);
3056*4882a593Smuzhiyun 	if (ret)
3057*4882a593Smuzhiyun 		goto out;
3058*4882a593Smuzhiyun 
3059*4882a593Smuzhiyun 	ret = crypto_shash_init(desc);
3060*4882a593Smuzhiyun 	if (ret)
3061*4882a593Smuzhiyun 		goto out;
3062*4882a593Smuzhiyun 
3063*4882a593Smuzhiyun 	/* TKIP MIC header */
3064*4882a593Smuzhiyun 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3065*4882a593Smuzhiyun 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3066*4882a593Smuzhiyun 	if (ieee80211_is_data_qos(hdr->frame_control))
3067*4882a593Smuzhiyun 		tid = ieee80211_get_tid(hdr);
3068*4882a593Smuzhiyun 	mic_hdr[12] = tid;
3069*4882a593Smuzhiyun 
3070*4882a593Smuzhiyun 	ret = crypto_shash_update(desc, mic_hdr, 16);
3071*4882a593Smuzhiyun 	if (ret)
3072*4882a593Smuzhiyun 		goto out;
3073*4882a593Smuzhiyun 	ret = crypto_shash_update(desc, data, data_len);
3074*4882a593Smuzhiyun 	if (ret)
3075*4882a593Smuzhiyun 		goto out;
3076*4882a593Smuzhiyun 	ret = crypto_shash_final(desc, mic);
3077*4882a593Smuzhiyun out:
3078*4882a593Smuzhiyun 	shash_desc_zero(desc);
3079*4882a593Smuzhiyun 	return ret;
3080*4882a593Smuzhiyun }
3081*4882a593Smuzhiyun 
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3082*4882a593Smuzhiyun static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3083*4882a593Smuzhiyun 					  struct sk_buff *msdu)
3084*4882a593Smuzhiyun {
3085*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3086*4882a593Smuzhiyun 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3087*4882a593Smuzhiyun 	struct ieee80211_key_conf *key_conf;
3088*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
3089*4882a593Smuzhiyun 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3090*4882a593Smuzhiyun 	int head_len, tail_len, ret;
3091*4882a593Smuzhiyun 	size_t data_len;
3092*4882a593Smuzhiyun 	u32 hdr_len;
3093*4882a593Smuzhiyun 	u8 *key, *data;
3094*4882a593Smuzhiyun 	u8 key_idx;
3095*4882a593Smuzhiyun 
3096*4882a593Smuzhiyun 	if (ath11k_dp_rx_h_mpdu_start_enctype(rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
3097*4882a593Smuzhiyun 		return 0;
3098*4882a593Smuzhiyun 
3099*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE);
3100*4882a593Smuzhiyun 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3101*4882a593Smuzhiyun 	head_len = hdr_len + HAL_RX_DESC_SIZE + IEEE80211_TKIP_IV_LEN;
3102*4882a593Smuzhiyun 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3103*4882a593Smuzhiyun 
3104*4882a593Smuzhiyun 	if (!is_multicast_ether_addr(hdr->addr1))
3105*4882a593Smuzhiyun 		key_idx = peer->ucast_keyidx;
3106*4882a593Smuzhiyun 	else
3107*4882a593Smuzhiyun 		key_idx = peer->mcast_keyidx;
3108*4882a593Smuzhiyun 
3109*4882a593Smuzhiyun 	key_conf = peer->keys[key_idx];
3110*4882a593Smuzhiyun 
3111*4882a593Smuzhiyun 	data = msdu->data + head_len;
3112*4882a593Smuzhiyun 	data_len = msdu->len - head_len - tail_len;
3113*4882a593Smuzhiyun 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3114*4882a593Smuzhiyun 
3115*4882a593Smuzhiyun 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3116*4882a593Smuzhiyun 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3117*4882a593Smuzhiyun 		goto mic_fail;
3118*4882a593Smuzhiyun 
3119*4882a593Smuzhiyun 	return 0;
3120*4882a593Smuzhiyun 
3121*4882a593Smuzhiyun mic_fail:
3122*4882a593Smuzhiyun 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3123*4882a593Smuzhiyun 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3124*4882a593Smuzhiyun 
3125*4882a593Smuzhiyun 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3126*4882a593Smuzhiyun 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3127*4882a593Smuzhiyun 	skb_pull(msdu, HAL_RX_DESC_SIZE);
3128*4882a593Smuzhiyun 
3129*4882a593Smuzhiyun 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3130*4882a593Smuzhiyun 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3131*4882a593Smuzhiyun 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3132*4882a593Smuzhiyun 	ieee80211_rx(ar->hw, msdu);
3133*4882a593Smuzhiyun 	return -EINVAL;
3134*4882a593Smuzhiyun }
3135*4882a593Smuzhiyun 
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3136*4882a593Smuzhiyun static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3137*4882a593Smuzhiyun 					enum hal_encrypt_type enctype, u32 flags)
3138*4882a593Smuzhiyun {
3139*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
3140*4882a593Smuzhiyun 	size_t hdr_len;
3141*4882a593Smuzhiyun 	size_t crypto_len;
3142*4882a593Smuzhiyun 
3143*4882a593Smuzhiyun 	if (!flags)
3144*4882a593Smuzhiyun 		return;
3145*4882a593Smuzhiyun 
3146*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE);
3147*4882a593Smuzhiyun 
3148*4882a593Smuzhiyun 	if (flags & RX_FLAG_MIC_STRIPPED)
3149*4882a593Smuzhiyun 		skb_trim(msdu, msdu->len -
3150*4882a593Smuzhiyun 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3151*4882a593Smuzhiyun 
3152*4882a593Smuzhiyun 	if (flags & RX_FLAG_ICV_STRIPPED)
3153*4882a593Smuzhiyun 		skb_trim(msdu, msdu->len -
3154*4882a593Smuzhiyun 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3155*4882a593Smuzhiyun 
3156*4882a593Smuzhiyun 	if (flags & RX_FLAG_IV_STRIPPED) {
3157*4882a593Smuzhiyun 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3158*4882a593Smuzhiyun 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3159*4882a593Smuzhiyun 
3160*4882a593Smuzhiyun 		memmove((void *)msdu->data + HAL_RX_DESC_SIZE + crypto_len,
3161*4882a593Smuzhiyun 			(void *)msdu->data + HAL_RX_DESC_SIZE, hdr_len);
3162*4882a593Smuzhiyun 		skb_pull(msdu, crypto_len);
3163*4882a593Smuzhiyun 	}
3164*4882a593Smuzhiyun }
3165*4882a593Smuzhiyun 
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3166*4882a593Smuzhiyun static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3167*4882a593Smuzhiyun 				 struct ath11k_peer *peer,
3168*4882a593Smuzhiyun 				 struct dp_rx_tid *rx_tid,
3169*4882a593Smuzhiyun 				 struct sk_buff **defrag_skb)
3170*4882a593Smuzhiyun {
3171*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc;
3172*4882a593Smuzhiyun 	struct sk_buff *skb, *first_frag, *last_frag;
3173*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
3174*4882a593Smuzhiyun 	enum hal_encrypt_type enctype;
3175*4882a593Smuzhiyun 	bool is_decrypted = false;
3176*4882a593Smuzhiyun 	int msdu_len = 0;
3177*4882a593Smuzhiyun 	int extra_space;
3178*4882a593Smuzhiyun 	u32 flags;
3179*4882a593Smuzhiyun 
3180*4882a593Smuzhiyun 	first_frag = skb_peek(&rx_tid->rx_frags);
3181*4882a593Smuzhiyun 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3182*4882a593Smuzhiyun 
3183*4882a593Smuzhiyun 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3184*4882a593Smuzhiyun 		flags = 0;
3185*4882a593Smuzhiyun 		rx_desc = (struct hal_rx_desc *)skb->data;
3186*4882a593Smuzhiyun 		hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
3187*4882a593Smuzhiyun 
3188*4882a593Smuzhiyun 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(rx_desc);
3189*4882a593Smuzhiyun 		if (enctype != HAL_ENCRYPT_TYPE_OPEN)
3190*4882a593Smuzhiyun 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc);
3191*4882a593Smuzhiyun 
3192*4882a593Smuzhiyun 		if (is_decrypted) {
3193*4882a593Smuzhiyun 			if (skb != first_frag)
3194*4882a593Smuzhiyun 				flags |=  RX_FLAG_IV_STRIPPED;
3195*4882a593Smuzhiyun 			if (skb != last_frag)
3196*4882a593Smuzhiyun 				flags |= RX_FLAG_ICV_STRIPPED |
3197*4882a593Smuzhiyun 					 RX_FLAG_MIC_STRIPPED;
3198*4882a593Smuzhiyun 		}
3199*4882a593Smuzhiyun 
3200*4882a593Smuzhiyun 		/* RX fragments are always raw packets */
3201*4882a593Smuzhiyun 		if (skb != last_frag)
3202*4882a593Smuzhiyun 			skb_trim(skb, skb->len - FCS_LEN);
3203*4882a593Smuzhiyun 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3204*4882a593Smuzhiyun 
3205*4882a593Smuzhiyun 		if (skb != first_frag)
3206*4882a593Smuzhiyun 			skb_pull(skb, HAL_RX_DESC_SIZE +
3207*4882a593Smuzhiyun 				      ieee80211_hdrlen(hdr->frame_control));
3208*4882a593Smuzhiyun 		msdu_len += skb->len;
3209*4882a593Smuzhiyun 	}
3210*4882a593Smuzhiyun 
3211*4882a593Smuzhiyun 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3212*4882a593Smuzhiyun 	if (extra_space > 0 &&
3213*4882a593Smuzhiyun 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3214*4882a593Smuzhiyun 		return -ENOMEM;
3215*4882a593Smuzhiyun 
3216*4882a593Smuzhiyun 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3217*4882a593Smuzhiyun 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3218*4882a593Smuzhiyun 		skb_put_data(first_frag, skb->data, skb->len);
3219*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
3220*4882a593Smuzhiyun 	}
3221*4882a593Smuzhiyun 
3222*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)(first_frag->data + HAL_RX_DESC_SIZE);
3223*4882a593Smuzhiyun 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3224*4882a593Smuzhiyun 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3225*4882a593Smuzhiyun 
3226*4882a593Smuzhiyun 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3227*4882a593Smuzhiyun 		first_frag = NULL;
3228*4882a593Smuzhiyun 
3229*4882a593Smuzhiyun 	*defrag_skb = first_frag;
3230*4882a593Smuzhiyun 	return 0;
3231*4882a593Smuzhiyun }
3232*4882a593Smuzhiyun 
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3233*4882a593Smuzhiyun static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3234*4882a593Smuzhiyun 					      struct sk_buff *defrag_skb)
3235*4882a593Smuzhiyun {
3236*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
3237*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
3238*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3239*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3240*4882a593Smuzhiyun 	struct hal_reo_entrance_ring *reo_ent_ring;
3241*4882a593Smuzhiyun 	struct hal_reo_dest_ring *reo_dest_ring;
3242*4882a593Smuzhiyun 	struct dp_link_desc_bank *link_desc_banks;
3243*4882a593Smuzhiyun 	struct hal_rx_msdu_link *msdu_link;
3244*4882a593Smuzhiyun 	struct hal_rx_msdu_details *msdu0;
3245*4882a593Smuzhiyun 	struct hal_srng *srng;
3246*4882a593Smuzhiyun 	dma_addr_t paddr;
3247*4882a593Smuzhiyun 	u32 desc_bank, msdu_info, mpdu_info;
3248*4882a593Smuzhiyun 	u32 dst_idx, cookie;
3249*4882a593Smuzhiyun 	u32 *msdu_len_offset;
3250*4882a593Smuzhiyun 	int ret, buf_id;
3251*4882a593Smuzhiyun 
3252*4882a593Smuzhiyun 	link_desc_banks = ab->dp.link_desc_banks;
3253*4882a593Smuzhiyun 	reo_dest_ring = rx_tid->dst_ring_desc;
3254*4882a593Smuzhiyun 
3255*4882a593Smuzhiyun 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3256*4882a593Smuzhiyun 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3257*4882a593Smuzhiyun 			(paddr - link_desc_banks[desc_bank].paddr));
3258*4882a593Smuzhiyun 	msdu0 = &msdu_link->msdu_link[0];
3259*4882a593Smuzhiyun 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3260*4882a593Smuzhiyun 	memset(msdu0, 0, sizeof(*msdu0));
3261*4882a593Smuzhiyun 
3262*4882a593Smuzhiyun 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3263*4882a593Smuzhiyun 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3264*4882a593Smuzhiyun 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3265*4882a593Smuzhiyun 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3266*4882a593Smuzhiyun 			       defrag_skb->len - HAL_RX_DESC_SIZE) |
3267*4882a593Smuzhiyun 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3268*4882a593Smuzhiyun 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3269*4882a593Smuzhiyun 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3270*4882a593Smuzhiyun 	msdu0->rx_msdu_info.info0 = msdu_info;
3271*4882a593Smuzhiyun 
3272*4882a593Smuzhiyun 	/* change msdu len in hal rx desc */
3273*4882a593Smuzhiyun 	msdu_len_offset = (u32 *)&rx_desc->msdu_start;
3274*4882a593Smuzhiyun 	*msdu_len_offset &= ~(RX_MSDU_START_INFO1_MSDU_LENGTH);
3275*4882a593Smuzhiyun 	*msdu_len_offset |= defrag_skb->len - HAL_RX_DESC_SIZE;
3276*4882a593Smuzhiyun 
3277*4882a593Smuzhiyun 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3278*4882a593Smuzhiyun 			       defrag_skb->len + skb_tailroom(defrag_skb),
3279*4882a593Smuzhiyun 			       DMA_TO_DEVICE);
3280*4882a593Smuzhiyun 	if (dma_mapping_error(ab->dev, paddr))
3281*4882a593Smuzhiyun 		return -ENOMEM;
3282*4882a593Smuzhiyun 
3283*4882a593Smuzhiyun 	spin_lock_bh(&rx_refill_ring->idr_lock);
3284*4882a593Smuzhiyun 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3285*4882a593Smuzhiyun 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3286*4882a593Smuzhiyun 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3287*4882a593Smuzhiyun 	if (buf_id < 0) {
3288*4882a593Smuzhiyun 		ret = -ENOMEM;
3289*4882a593Smuzhiyun 		goto err_unmap_dma;
3290*4882a593Smuzhiyun 	}
3291*4882a593Smuzhiyun 
3292*4882a593Smuzhiyun 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3293*4882a593Smuzhiyun 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3294*4882a593Smuzhiyun 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3295*4882a593Smuzhiyun 
3296*4882a593Smuzhiyun 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM);
3297*4882a593Smuzhiyun 
3298*4882a593Smuzhiyun 	/* Fill mpdu details into reo entrace ring */
3299*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3300*4882a593Smuzhiyun 
3301*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
3302*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
3303*4882a593Smuzhiyun 
3304*4882a593Smuzhiyun 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3305*4882a593Smuzhiyun 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3306*4882a593Smuzhiyun 	if (!reo_ent_ring) {
3307*4882a593Smuzhiyun 		ath11k_hal_srng_access_end(ab, srng);
3308*4882a593Smuzhiyun 		spin_unlock_bh(&srng->lock);
3309*4882a593Smuzhiyun 		ret = -ENOSPC;
3310*4882a593Smuzhiyun 		goto err_free_idr;
3311*4882a593Smuzhiyun 	}
3312*4882a593Smuzhiyun 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3313*4882a593Smuzhiyun 
3314*4882a593Smuzhiyun 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3315*4882a593Smuzhiyun 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3316*4882a593Smuzhiyun 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3317*4882a593Smuzhiyun 
3318*4882a593Smuzhiyun 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3319*4882a593Smuzhiyun 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3320*4882a593Smuzhiyun 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3321*4882a593Smuzhiyun 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3322*4882a593Smuzhiyun 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3323*4882a593Smuzhiyun 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3324*4882a593Smuzhiyun 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3325*4882a593Smuzhiyun 
3326*4882a593Smuzhiyun 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3327*4882a593Smuzhiyun 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3328*4882a593Smuzhiyun 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3329*4882a593Smuzhiyun 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3330*4882a593Smuzhiyun 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3331*4882a593Smuzhiyun 						   reo_dest_ring->info0)) |
3332*4882a593Smuzhiyun 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3333*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
3334*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
3335*4882a593Smuzhiyun 
3336*4882a593Smuzhiyun 	return 0;
3337*4882a593Smuzhiyun 
3338*4882a593Smuzhiyun err_free_idr:
3339*4882a593Smuzhiyun 	spin_lock_bh(&rx_refill_ring->idr_lock);
3340*4882a593Smuzhiyun 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3341*4882a593Smuzhiyun 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3342*4882a593Smuzhiyun err_unmap_dma:
3343*4882a593Smuzhiyun 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3344*4882a593Smuzhiyun 			 DMA_TO_DEVICE);
3345*4882a593Smuzhiyun 	return ret;
3346*4882a593Smuzhiyun }
3347*4882a593Smuzhiyun 
ath11k_dp_rx_h_cmp_frags(struct sk_buff * a,struct sk_buff * b)3348*4882a593Smuzhiyun static int ath11k_dp_rx_h_cmp_frags(struct sk_buff *a, struct sk_buff *b)
3349*4882a593Smuzhiyun {
3350*4882a593Smuzhiyun 	int frag1, frag2;
3351*4882a593Smuzhiyun 
3352*4882a593Smuzhiyun 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(a);
3353*4882a593Smuzhiyun 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(b);
3354*4882a593Smuzhiyun 
3355*4882a593Smuzhiyun 	return frag1 - frag2;
3356*4882a593Smuzhiyun }
3357*4882a593Smuzhiyun 
ath11k_dp_rx_h_sort_frags(struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3358*4882a593Smuzhiyun static void ath11k_dp_rx_h_sort_frags(struct sk_buff_head *frag_list,
3359*4882a593Smuzhiyun 				      struct sk_buff *cur_frag)
3360*4882a593Smuzhiyun {
3361*4882a593Smuzhiyun 	struct sk_buff *skb;
3362*4882a593Smuzhiyun 	int cmp;
3363*4882a593Smuzhiyun 
3364*4882a593Smuzhiyun 	skb_queue_walk(frag_list, skb) {
3365*4882a593Smuzhiyun 		cmp = ath11k_dp_rx_h_cmp_frags(skb, cur_frag);
3366*4882a593Smuzhiyun 		if (cmp < 0)
3367*4882a593Smuzhiyun 			continue;
3368*4882a593Smuzhiyun 		__skb_queue_before(frag_list, skb, cur_frag);
3369*4882a593Smuzhiyun 		return;
3370*4882a593Smuzhiyun 	}
3371*4882a593Smuzhiyun 	__skb_queue_tail(frag_list, cur_frag);
3372*4882a593Smuzhiyun }
3373*4882a593Smuzhiyun 
ath11k_dp_rx_h_get_pn(struct sk_buff * skb)3374*4882a593Smuzhiyun static u64 ath11k_dp_rx_h_get_pn(struct sk_buff *skb)
3375*4882a593Smuzhiyun {
3376*4882a593Smuzhiyun 	struct ieee80211_hdr *hdr;
3377*4882a593Smuzhiyun 	u64 pn = 0;
3378*4882a593Smuzhiyun 	u8 *ehdr;
3379*4882a593Smuzhiyun 
3380*4882a593Smuzhiyun 	hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
3381*4882a593Smuzhiyun 	ehdr = skb->data + HAL_RX_DESC_SIZE + ieee80211_hdrlen(hdr->frame_control);
3382*4882a593Smuzhiyun 
3383*4882a593Smuzhiyun 	pn = ehdr[0];
3384*4882a593Smuzhiyun 	pn |= (u64)ehdr[1] << 8;
3385*4882a593Smuzhiyun 	pn |= (u64)ehdr[4] << 16;
3386*4882a593Smuzhiyun 	pn |= (u64)ehdr[5] << 24;
3387*4882a593Smuzhiyun 	pn |= (u64)ehdr[6] << 32;
3388*4882a593Smuzhiyun 	pn |= (u64)ehdr[7] << 40;
3389*4882a593Smuzhiyun 
3390*4882a593Smuzhiyun 	return pn;
3391*4882a593Smuzhiyun }
3392*4882a593Smuzhiyun 
3393*4882a593Smuzhiyun static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3394*4882a593Smuzhiyun ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3395*4882a593Smuzhiyun {
3396*4882a593Smuzhiyun 	enum hal_encrypt_type encrypt_type;
3397*4882a593Smuzhiyun 	struct sk_buff *first_frag, *skb;
3398*4882a593Smuzhiyun 	struct hal_rx_desc *desc;
3399*4882a593Smuzhiyun 	u64 last_pn;
3400*4882a593Smuzhiyun 	u64 cur_pn;
3401*4882a593Smuzhiyun 
3402*4882a593Smuzhiyun 	first_frag = skb_peek(&rx_tid->rx_frags);
3403*4882a593Smuzhiyun 	desc = (struct hal_rx_desc *)first_frag->data;
3404*4882a593Smuzhiyun 
3405*4882a593Smuzhiyun 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(desc);
3406*4882a593Smuzhiyun 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3407*4882a593Smuzhiyun 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3408*4882a593Smuzhiyun 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3409*4882a593Smuzhiyun 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3410*4882a593Smuzhiyun 		return true;
3411*4882a593Smuzhiyun 
3412*4882a593Smuzhiyun 	last_pn = ath11k_dp_rx_h_get_pn(first_frag);
3413*4882a593Smuzhiyun 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3414*4882a593Smuzhiyun 		if (skb == first_frag)
3415*4882a593Smuzhiyun 			continue;
3416*4882a593Smuzhiyun 
3417*4882a593Smuzhiyun 		cur_pn = ath11k_dp_rx_h_get_pn(skb);
3418*4882a593Smuzhiyun 		if (cur_pn != last_pn + 1)
3419*4882a593Smuzhiyun 			return false;
3420*4882a593Smuzhiyun 		last_pn = cur_pn;
3421*4882a593Smuzhiyun 	}
3422*4882a593Smuzhiyun 	return true;
3423*4882a593Smuzhiyun }
3424*4882a593Smuzhiyun 
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3425*4882a593Smuzhiyun static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3426*4882a593Smuzhiyun 				    struct sk_buff *msdu,
3427*4882a593Smuzhiyun 				    u32 *ring_desc)
3428*4882a593Smuzhiyun {
3429*4882a593Smuzhiyun 	struct ath11k_base *ab = ar->ab;
3430*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc;
3431*4882a593Smuzhiyun 	struct ath11k_peer *peer;
3432*4882a593Smuzhiyun 	struct dp_rx_tid *rx_tid;
3433*4882a593Smuzhiyun 	struct sk_buff *defrag_skb = NULL;
3434*4882a593Smuzhiyun 	u32 peer_id;
3435*4882a593Smuzhiyun 	u16 seqno, frag_no;
3436*4882a593Smuzhiyun 	u8 tid;
3437*4882a593Smuzhiyun 	int ret = 0;
3438*4882a593Smuzhiyun 	bool more_frags;
3439*4882a593Smuzhiyun 
3440*4882a593Smuzhiyun 	rx_desc = (struct hal_rx_desc *)msdu->data;
3441*4882a593Smuzhiyun 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(rx_desc);
3442*4882a593Smuzhiyun 	tid = ath11k_dp_rx_h_mpdu_start_tid(rx_desc);
3443*4882a593Smuzhiyun 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(rx_desc);
3444*4882a593Smuzhiyun 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(msdu);
3445*4882a593Smuzhiyun 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(msdu);
3446*4882a593Smuzhiyun 
3447*4882a593Smuzhiyun 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(rx_desc) ||
3448*4882a593Smuzhiyun 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(rx_desc) ||
3449*4882a593Smuzhiyun 	    tid > IEEE80211_NUM_TIDS)
3450*4882a593Smuzhiyun 		return -EINVAL;
3451*4882a593Smuzhiyun 
3452*4882a593Smuzhiyun 	/* received unfragmented packet in reo
3453*4882a593Smuzhiyun 	 * exception ring, this shouldn't happen
3454*4882a593Smuzhiyun 	 * as these packets typically come from
3455*4882a593Smuzhiyun 	 * reo2sw srngs.
3456*4882a593Smuzhiyun 	 */
3457*4882a593Smuzhiyun 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3458*4882a593Smuzhiyun 		return -EINVAL;
3459*4882a593Smuzhiyun 
3460*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
3461*4882a593Smuzhiyun 	peer = ath11k_peer_find_by_id(ab, peer_id);
3462*4882a593Smuzhiyun 	if (!peer) {
3463*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3464*4882a593Smuzhiyun 			    peer_id);
3465*4882a593Smuzhiyun 		ret = -ENOENT;
3466*4882a593Smuzhiyun 		goto out_unlock;
3467*4882a593Smuzhiyun 	}
3468*4882a593Smuzhiyun 	rx_tid = &peer->rx_tid[tid];
3469*4882a593Smuzhiyun 
3470*4882a593Smuzhiyun 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3471*4882a593Smuzhiyun 	    skb_queue_empty(&rx_tid->rx_frags)) {
3472*4882a593Smuzhiyun 		/* Flush stored fragments and start a new sequence */
3473*4882a593Smuzhiyun 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3474*4882a593Smuzhiyun 		rx_tid->cur_sn = seqno;
3475*4882a593Smuzhiyun 	}
3476*4882a593Smuzhiyun 
3477*4882a593Smuzhiyun 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3478*4882a593Smuzhiyun 		/* Fragment already present */
3479*4882a593Smuzhiyun 		ret = -EINVAL;
3480*4882a593Smuzhiyun 		goto out_unlock;
3481*4882a593Smuzhiyun 	}
3482*4882a593Smuzhiyun 
3483*4882a593Smuzhiyun 	if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3484*4882a593Smuzhiyun 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3485*4882a593Smuzhiyun 	else
3486*4882a593Smuzhiyun 		ath11k_dp_rx_h_sort_frags(&rx_tid->rx_frags, msdu);
3487*4882a593Smuzhiyun 
3488*4882a593Smuzhiyun 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3489*4882a593Smuzhiyun 	if (!more_frags)
3490*4882a593Smuzhiyun 		rx_tid->last_frag_no = frag_no;
3491*4882a593Smuzhiyun 
3492*4882a593Smuzhiyun 	if (frag_no == 0) {
3493*4882a593Smuzhiyun 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3494*4882a593Smuzhiyun 						sizeof(*rx_tid->dst_ring_desc),
3495*4882a593Smuzhiyun 						GFP_ATOMIC);
3496*4882a593Smuzhiyun 		if (!rx_tid->dst_ring_desc) {
3497*4882a593Smuzhiyun 			ret = -ENOMEM;
3498*4882a593Smuzhiyun 			goto out_unlock;
3499*4882a593Smuzhiyun 		}
3500*4882a593Smuzhiyun 	} else {
3501*4882a593Smuzhiyun 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3502*4882a593Smuzhiyun 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3503*4882a593Smuzhiyun 	}
3504*4882a593Smuzhiyun 
3505*4882a593Smuzhiyun 	if (!rx_tid->last_frag_no ||
3506*4882a593Smuzhiyun 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3507*4882a593Smuzhiyun 		mod_timer(&rx_tid->frag_timer, jiffies +
3508*4882a593Smuzhiyun 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3509*4882a593Smuzhiyun 		goto out_unlock;
3510*4882a593Smuzhiyun 	}
3511*4882a593Smuzhiyun 
3512*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
3513*4882a593Smuzhiyun 	del_timer_sync(&rx_tid->frag_timer);
3514*4882a593Smuzhiyun 	spin_lock_bh(&ab->base_lock);
3515*4882a593Smuzhiyun 
3516*4882a593Smuzhiyun 	peer = ath11k_peer_find_by_id(ab, peer_id);
3517*4882a593Smuzhiyun 	if (!peer)
3518*4882a593Smuzhiyun 		goto err_frags_cleanup;
3519*4882a593Smuzhiyun 
3520*4882a593Smuzhiyun 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3521*4882a593Smuzhiyun 		goto err_frags_cleanup;
3522*4882a593Smuzhiyun 
3523*4882a593Smuzhiyun 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3524*4882a593Smuzhiyun 		goto err_frags_cleanup;
3525*4882a593Smuzhiyun 
3526*4882a593Smuzhiyun 	if (!defrag_skb)
3527*4882a593Smuzhiyun 		goto err_frags_cleanup;
3528*4882a593Smuzhiyun 
3529*4882a593Smuzhiyun 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3530*4882a593Smuzhiyun 		goto err_frags_cleanup;
3531*4882a593Smuzhiyun 
3532*4882a593Smuzhiyun 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3533*4882a593Smuzhiyun 	goto out_unlock;
3534*4882a593Smuzhiyun 
3535*4882a593Smuzhiyun err_frags_cleanup:
3536*4882a593Smuzhiyun 	dev_kfree_skb_any(defrag_skb);
3537*4882a593Smuzhiyun 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3538*4882a593Smuzhiyun out_unlock:
3539*4882a593Smuzhiyun 	spin_unlock_bh(&ab->base_lock);
3540*4882a593Smuzhiyun 	return ret;
3541*4882a593Smuzhiyun }
3542*4882a593Smuzhiyun 
3543*4882a593Smuzhiyun static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3544*4882a593Smuzhiyun ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3545*4882a593Smuzhiyun {
3546*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
3547*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3548*4882a593Smuzhiyun 	struct sk_buff *msdu;
3549*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
3550*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc;
3551*4882a593Smuzhiyun 	u8 *hdr_status;
3552*4882a593Smuzhiyun 	u16 msdu_len;
3553*4882a593Smuzhiyun 
3554*4882a593Smuzhiyun 	spin_lock_bh(&rx_ring->idr_lock);
3555*4882a593Smuzhiyun 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3556*4882a593Smuzhiyun 	if (!msdu) {
3557*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3558*4882a593Smuzhiyun 			    buf_id);
3559*4882a593Smuzhiyun 		spin_unlock_bh(&rx_ring->idr_lock);
3560*4882a593Smuzhiyun 		return -EINVAL;
3561*4882a593Smuzhiyun 	}
3562*4882a593Smuzhiyun 
3563*4882a593Smuzhiyun 	idr_remove(&rx_ring->bufs_idr, buf_id);
3564*4882a593Smuzhiyun 	spin_unlock_bh(&rx_ring->idr_lock);
3565*4882a593Smuzhiyun 
3566*4882a593Smuzhiyun 	rxcb = ATH11K_SKB_RXCB(msdu);
3567*4882a593Smuzhiyun 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3568*4882a593Smuzhiyun 			 msdu->len + skb_tailroom(msdu),
3569*4882a593Smuzhiyun 			 DMA_FROM_DEVICE);
3570*4882a593Smuzhiyun 
3571*4882a593Smuzhiyun 	if (drop) {
3572*4882a593Smuzhiyun 		dev_kfree_skb_any(msdu);
3573*4882a593Smuzhiyun 		return 0;
3574*4882a593Smuzhiyun 	}
3575*4882a593Smuzhiyun 
3576*4882a593Smuzhiyun 	rcu_read_lock();
3577*4882a593Smuzhiyun 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3578*4882a593Smuzhiyun 		dev_kfree_skb_any(msdu);
3579*4882a593Smuzhiyun 		goto exit;
3580*4882a593Smuzhiyun 	}
3581*4882a593Smuzhiyun 
3582*4882a593Smuzhiyun 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3583*4882a593Smuzhiyun 		dev_kfree_skb_any(msdu);
3584*4882a593Smuzhiyun 		goto exit;
3585*4882a593Smuzhiyun 	}
3586*4882a593Smuzhiyun 
3587*4882a593Smuzhiyun 	rx_desc = (struct hal_rx_desc *)msdu->data;
3588*4882a593Smuzhiyun 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc);
3589*4882a593Smuzhiyun 	if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) {
3590*4882a593Smuzhiyun 		hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc);
3591*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3592*4882a593Smuzhiyun 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3593*4882a593Smuzhiyun 				sizeof(struct ieee80211_hdr));
3594*4882a593Smuzhiyun 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3595*4882a593Smuzhiyun 				sizeof(struct hal_rx_desc));
3596*4882a593Smuzhiyun 		dev_kfree_skb_any(msdu);
3597*4882a593Smuzhiyun 		goto exit;
3598*4882a593Smuzhiyun 	}
3599*4882a593Smuzhiyun 
3600*4882a593Smuzhiyun 	skb_put(msdu, HAL_RX_DESC_SIZE + msdu_len);
3601*4882a593Smuzhiyun 
3602*4882a593Smuzhiyun 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3603*4882a593Smuzhiyun 		dev_kfree_skb_any(msdu);
3604*4882a593Smuzhiyun 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3605*4882a593Smuzhiyun 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3606*4882a593Smuzhiyun 	}
3607*4882a593Smuzhiyun exit:
3608*4882a593Smuzhiyun 	rcu_read_unlock();
3609*4882a593Smuzhiyun 	return 0;
3610*4882a593Smuzhiyun }
3611*4882a593Smuzhiyun 
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3612*4882a593Smuzhiyun int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3613*4882a593Smuzhiyun 			     int budget)
3614*4882a593Smuzhiyun {
3615*4882a593Smuzhiyun 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3616*4882a593Smuzhiyun 	struct dp_link_desc_bank *link_desc_banks;
3617*4882a593Smuzhiyun 	enum hal_rx_buf_return_buf_manager rbm;
3618*4882a593Smuzhiyun 	int tot_n_bufs_reaped, quota, ret, i;
3619*4882a593Smuzhiyun 	int n_bufs_reaped[MAX_RADIOS] = {0};
3620*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring;
3621*4882a593Smuzhiyun 	struct dp_srng *reo_except;
3622*4882a593Smuzhiyun 	u32 desc_bank, num_msdus;
3623*4882a593Smuzhiyun 	struct hal_srng *srng;
3624*4882a593Smuzhiyun 	struct ath11k_dp *dp;
3625*4882a593Smuzhiyun 	void *link_desc_va;
3626*4882a593Smuzhiyun 	int buf_id, mac_id;
3627*4882a593Smuzhiyun 	struct ath11k *ar;
3628*4882a593Smuzhiyun 	dma_addr_t paddr;
3629*4882a593Smuzhiyun 	u32 *desc;
3630*4882a593Smuzhiyun 	bool is_frag;
3631*4882a593Smuzhiyun 	u8 drop = 0;
3632*4882a593Smuzhiyun 
3633*4882a593Smuzhiyun 	tot_n_bufs_reaped = 0;
3634*4882a593Smuzhiyun 	quota = budget;
3635*4882a593Smuzhiyun 
3636*4882a593Smuzhiyun 	dp = &ab->dp;
3637*4882a593Smuzhiyun 	reo_except = &dp->reo_except_ring;
3638*4882a593Smuzhiyun 	link_desc_banks = dp->link_desc_banks;
3639*4882a593Smuzhiyun 
3640*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[reo_except->ring_id];
3641*4882a593Smuzhiyun 
3642*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
3643*4882a593Smuzhiyun 
3644*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
3645*4882a593Smuzhiyun 
3646*4882a593Smuzhiyun 	while (budget &&
3647*4882a593Smuzhiyun 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3648*4882a593Smuzhiyun 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3649*4882a593Smuzhiyun 
3650*4882a593Smuzhiyun 		ab->soc_stats.err_ring_pkts++;
3651*4882a593Smuzhiyun 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3652*4882a593Smuzhiyun 						    &desc_bank);
3653*4882a593Smuzhiyun 		if (ret) {
3654*4882a593Smuzhiyun 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3655*4882a593Smuzhiyun 				    ret);
3656*4882a593Smuzhiyun 			continue;
3657*4882a593Smuzhiyun 		}
3658*4882a593Smuzhiyun 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3659*4882a593Smuzhiyun 			       (paddr - link_desc_banks[desc_bank].paddr);
3660*4882a593Smuzhiyun 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3661*4882a593Smuzhiyun 						 &rbm);
3662*4882a593Smuzhiyun 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3663*4882a593Smuzhiyun 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3664*4882a593Smuzhiyun 			ab->soc_stats.invalid_rbm++;
3665*4882a593Smuzhiyun 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3666*4882a593Smuzhiyun 			ath11k_dp_rx_link_desc_return(ab, desc,
3667*4882a593Smuzhiyun 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3668*4882a593Smuzhiyun 			continue;
3669*4882a593Smuzhiyun 		}
3670*4882a593Smuzhiyun 
3671*4882a593Smuzhiyun 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3672*4882a593Smuzhiyun 
3673*4882a593Smuzhiyun 		/* Process only rx fragments with one msdu per link desc below, and drop
3674*4882a593Smuzhiyun 		 * msdu's indicated due to error reasons.
3675*4882a593Smuzhiyun 		 */
3676*4882a593Smuzhiyun 		if (!is_frag || num_msdus > 1) {
3677*4882a593Smuzhiyun 			drop = 1;
3678*4882a593Smuzhiyun 			/* Return the link desc back to wbm idle list */
3679*4882a593Smuzhiyun 			ath11k_dp_rx_link_desc_return(ab, desc,
3680*4882a593Smuzhiyun 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3681*4882a593Smuzhiyun 		}
3682*4882a593Smuzhiyun 
3683*4882a593Smuzhiyun 		for (i = 0; i < num_msdus; i++) {
3684*4882a593Smuzhiyun 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3685*4882a593Smuzhiyun 					   msdu_cookies[i]);
3686*4882a593Smuzhiyun 
3687*4882a593Smuzhiyun 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3688*4882a593Smuzhiyun 					   msdu_cookies[i]);
3689*4882a593Smuzhiyun 
3690*4882a593Smuzhiyun 			ar = ab->pdevs[mac_id].ar;
3691*4882a593Smuzhiyun 
3692*4882a593Smuzhiyun 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3693*4882a593Smuzhiyun 				n_bufs_reaped[mac_id]++;
3694*4882a593Smuzhiyun 				tot_n_bufs_reaped++;
3695*4882a593Smuzhiyun 			}
3696*4882a593Smuzhiyun 		}
3697*4882a593Smuzhiyun 
3698*4882a593Smuzhiyun 		if (tot_n_bufs_reaped >= quota) {
3699*4882a593Smuzhiyun 			tot_n_bufs_reaped = quota;
3700*4882a593Smuzhiyun 			goto exit;
3701*4882a593Smuzhiyun 		}
3702*4882a593Smuzhiyun 
3703*4882a593Smuzhiyun 		budget = quota - tot_n_bufs_reaped;
3704*4882a593Smuzhiyun 	}
3705*4882a593Smuzhiyun 
3706*4882a593Smuzhiyun exit:
3707*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
3708*4882a593Smuzhiyun 
3709*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
3710*4882a593Smuzhiyun 
3711*4882a593Smuzhiyun 	for (i = 0; i <  ab->num_radios; i++) {
3712*4882a593Smuzhiyun 		if (!n_bufs_reaped[i])
3713*4882a593Smuzhiyun 			continue;
3714*4882a593Smuzhiyun 
3715*4882a593Smuzhiyun 		ar = ab->pdevs[i].ar;
3716*4882a593Smuzhiyun 		rx_ring = &ar->dp.rx_refill_buf_ring;
3717*4882a593Smuzhiyun 
3718*4882a593Smuzhiyun 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3719*4882a593Smuzhiyun 					   HAL_RX_BUF_RBM_SW3_BM);
3720*4882a593Smuzhiyun 	}
3721*4882a593Smuzhiyun 
3722*4882a593Smuzhiyun 	return tot_n_bufs_reaped;
3723*4882a593Smuzhiyun }
3724*4882a593Smuzhiyun 
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3725*4882a593Smuzhiyun static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3726*4882a593Smuzhiyun 					     int msdu_len,
3727*4882a593Smuzhiyun 					     struct sk_buff_head *msdu_list)
3728*4882a593Smuzhiyun {
3729*4882a593Smuzhiyun 	struct sk_buff *skb, *tmp;
3730*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
3731*4882a593Smuzhiyun 	int n_buffs;
3732*4882a593Smuzhiyun 
3733*4882a593Smuzhiyun 	n_buffs = DIV_ROUND_UP(msdu_len,
3734*4882a593Smuzhiyun 			       (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE));
3735*4882a593Smuzhiyun 
3736*4882a593Smuzhiyun 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3737*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(skb);
3738*4882a593Smuzhiyun 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3739*4882a593Smuzhiyun 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3740*4882a593Smuzhiyun 			if (!n_buffs)
3741*4882a593Smuzhiyun 				break;
3742*4882a593Smuzhiyun 			__skb_unlink(skb, msdu_list);
3743*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
3744*4882a593Smuzhiyun 			n_buffs--;
3745*4882a593Smuzhiyun 		}
3746*4882a593Smuzhiyun 	}
3747*4882a593Smuzhiyun }
3748*4882a593Smuzhiyun 
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3749*4882a593Smuzhiyun static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3750*4882a593Smuzhiyun 				      struct ieee80211_rx_status *status,
3751*4882a593Smuzhiyun 				      struct sk_buff_head *msdu_list)
3752*4882a593Smuzhiyun {
3753*4882a593Smuzhiyun 	u16 msdu_len;
3754*4882a593Smuzhiyun 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3755*4882a593Smuzhiyun 	u8 l3pad_bytes;
3756*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3757*4882a593Smuzhiyun 
3758*4882a593Smuzhiyun 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc);
3759*4882a593Smuzhiyun 
3760*4882a593Smuzhiyun 	if (!rxcb->is_frag && ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE)) {
3761*4882a593Smuzhiyun 		/* First buffer will be freed by the caller, so deduct it's length */
3762*4882a593Smuzhiyun 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE);
3763*4882a593Smuzhiyun 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3764*4882a593Smuzhiyun 		return -EINVAL;
3765*4882a593Smuzhiyun 	}
3766*4882a593Smuzhiyun 
3767*4882a593Smuzhiyun 	if (!ath11k_dp_rx_h_attn_msdu_done(desc)) {
3768*4882a593Smuzhiyun 		ath11k_warn(ar->ab,
3769*4882a593Smuzhiyun 			    "msdu_done bit not set in null_q_des processing\n");
3770*4882a593Smuzhiyun 		__skb_queue_purge(msdu_list);
3771*4882a593Smuzhiyun 		return -EIO;
3772*4882a593Smuzhiyun 	}
3773*4882a593Smuzhiyun 
3774*4882a593Smuzhiyun 	/* Handle NULL queue descriptor violations arising out a missing
3775*4882a593Smuzhiyun 	 * REO queue for a given peer or a given TID. This typically
3776*4882a593Smuzhiyun 	 * may happen if a packet is received on a QOS enabled TID before the
3777*4882a593Smuzhiyun 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3778*4882a593Smuzhiyun 	 * it may also happen for MC/BC frames if they are not routed to the
3779*4882a593Smuzhiyun 	 * non-QOS TID queue, in the absence of any other default TID queue.
3780*4882a593Smuzhiyun 	 * This error can show up both in a REO destination or WBM release ring.
3781*4882a593Smuzhiyun 	 */
3782*4882a593Smuzhiyun 
3783*4882a593Smuzhiyun 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc);
3784*4882a593Smuzhiyun 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc);
3785*4882a593Smuzhiyun 
3786*4882a593Smuzhiyun 	if (rxcb->is_frag) {
3787*4882a593Smuzhiyun 		skb_pull(msdu, HAL_RX_DESC_SIZE);
3788*4882a593Smuzhiyun 	} else {
3789*4882a593Smuzhiyun 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc);
3790*4882a593Smuzhiyun 
3791*4882a593Smuzhiyun 		if ((HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3792*4882a593Smuzhiyun 			return -EINVAL;
3793*4882a593Smuzhiyun 
3794*4882a593Smuzhiyun 		skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len);
3795*4882a593Smuzhiyun 		skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes);
3796*4882a593Smuzhiyun 	}
3797*4882a593Smuzhiyun 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3798*4882a593Smuzhiyun 
3799*4882a593Smuzhiyun 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3800*4882a593Smuzhiyun 
3801*4882a593Smuzhiyun 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(desc);
3802*4882a593Smuzhiyun 
3803*4882a593Smuzhiyun 	/* Please note that caller will having the access to msdu and completing
3804*4882a593Smuzhiyun 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3805*4882a593Smuzhiyun 	 */
3806*4882a593Smuzhiyun 
3807*4882a593Smuzhiyun 	return 0;
3808*4882a593Smuzhiyun }
3809*4882a593Smuzhiyun 
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3810*4882a593Smuzhiyun static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3811*4882a593Smuzhiyun 				   struct ieee80211_rx_status *status,
3812*4882a593Smuzhiyun 				   struct sk_buff_head *msdu_list)
3813*4882a593Smuzhiyun {
3814*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3815*4882a593Smuzhiyun 	bool drop = false;
3816*4882a593Smuzhiyun 
3817*4882a593Smuzhiyun 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3818*4882a593Smuzhiyun 
3819*4882a593Smuzhiyun 	switch (rxcb->err_code) {
3820*4882a593Smuzhiyun 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3821*4882a593Smuzhiyun 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3822*4882a593Smuzhiyun 			drop = true;
3823*4882a593Smuzhiyun 		break;
3824*4882a593Smuzhiyun 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3825*4882a593Smuzhiyun 		/* TODO: Do not drop PN failed packets in the driver;
3826*4882a593Smuzhiyun 		 * instead, it is good to drop such packets in mac80211
3827*4882a593Smuzhiyun 		 * after incrementing the replay counters.
3828*4882a593Smuzhiyun 		 */
3829*4882a593Smuzhiyun 		fallthrough;
3830*4882a593Smuzhiyun 	default:
3831*4882a593Smuzhiyun 		/* TODO: Review other errors and process them to mac80211
3832*4882a593Smuzhiyun 		 * as appropriate.
3833*4882a593Smuzhiyun 		 */
3834*4882a593Smuzhiyun 		drop = true;
3835*4882a593Smuzhiyun 		break;
3836*4882a593Smuzhiyun 	}
3837*4882a593Smuzhiyun 
3838*4882a593Smuzhiyun 	return drop;
3839*4882a593Smuzhiyun }
3840*4882a593Smuzhiyun 
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3841*4882a593Smuzhiyun static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3842*4882a593Smuzhiyun 					struct ieee80211_rx_status *status)
3843*4882a593Smuzhiyun {
3844*4882a593Smuzhiyun 	u16 msdu_len;
3845*4882a593Smuzhiyun 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3846*4882a593Smuzhiyun 	u8 l3pad_bytes;
3847*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3848*4882a593Smuzhiyun 
3849*4882a593Smuzhiyun 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc);
3850*4882a593Smuzhiyun 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc);
3851*4882a593Smuzhiyun 
3852*4882a593Smuzhiyun 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc);
3853*4882a593Smuzhiyun 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc);
3854*4882a593Smuzhiyun 	skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len);
3855*4882a593Smuzhiyun 	skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes);
3856*4882a593Smuzhiyun 
3857*4882a593Smuzhiyun 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3858*4882a593Smuzhiyun 
3859*4882a593Smuzhiyun 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3860*4882a593Smuzhiyun 			 RX_FLAG_DECRYPTED);
3861*4882a593Smuzhiyun 
3862*4882a593Smuzhiyun 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
3863*4882a593Smuzhiyun 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3864*4882a593Smuzhiyun }
3865*4882a593Smuzhiyun 
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3866*4882a593Smuzhiyun static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
3867*4882a593Smuzhiyun 				     struct ieee80211_rx_status *status)
3868*4882a593Smuzhiyun {
3869*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3870*4882a593Smuzhiyun 	bool drop = false;
3871*4882a593Smuzhiyun 
3872*4882a593Smuzhiyun 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3873*4882a593Smuzhiyun 
3874*4882a593Smuzhiyun 	switch (rxcb->err_code) {
3875*4882a593Smuzhiyun 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3876*4882a593Smuzhiyun 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3877*4882a593Smuzhiyun 		break;
3878*4882a593Smuzhiyun 	default:
3879*4882a593Smuzhiyun 		/* TODO: Review other rxdma error code to check if anything is
3880*4882a593Smuzhiyun 		 * worth reporting to mac80211
3881*4882a593Smuzhiyun 		 */
3882*4882a593Smuzhiyun 		drop = true;
3883*4882a593Smuzhiyun 		break;
3884*4882a593Smuzhiyun 	}
3885*4882a593Smuzhiyun 
3886*4882a593Smuzhiyun 	return drop;
3887*4882a593Smuzhiyun }
3888*4882a593Smuzhiyun 
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3889*4882a593Smuzhiyun static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
3890*4882a593Smuzhiyun 				 struct napi_struct *napi,
3891*4882a593Smuzhiyun 				 struct sk_buff *msdu,
3892*4882a593Smuzhiyun 				 struct sk_buff_head *msdu_list)
3893*4882a593Smuzhiyun {
3894*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3895*4882a593Smuzhiyun 	struct ieee80211_rx_status rxs = {0};
3896*4882a593Smuzhiyun 	struct ieee80211_rx_status *status;
3897*4882a593Smuzhiyun 	bool drop = true;
3898*4882a593Smuzhiyun 
3899*4882a593Smuzhiyun 	switch (rxcb->err_rel_src) {
3900*4882a593Smuzhiyun 	case HAL_WBM_REL_SRC_MODULE_REO:
3901*4882a593Smuzhiyun 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3902*4882a593Smuzhiyun 		break;
3903*4882a593Smuzhiyun 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
3904*4882a593Smuzhiyun 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3905*4882a593Smuzhiyun 		break;
3906*4882a593Smuzhiyun 	default:
3907*4882a593Smuzhiyun 		/* msdu will get freed */
3908*4882a593Smuzhiyun 		break;
3909*4882a593Smuzhiyun 	}
3910*4882a593Smuzhiyun 
3911*4882a593Smuzhiyun 	if (drop) {
3912*4882a593Smuzhiyun 		dev_kfree_skb_any(msdu);
3913*4882a593Smuzhiyun 		return;
3914*4882a593Smuzhiyun 	}
3915*4882a593Smuzhiyun 
3916*4882a593Smuzhiyun 	status = IEEE80211_SKB_RXCB(msdu);
3917*4882a593Smuzhiyun 	*status = rxs;
3918*4882a593Smuzhiyun 
3919*4882a593Smuzhiyun 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
3920*4882a593Smuzhiyun }
3921*4882a593Smuzhiyun 
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3922*4882a593Smuzhiyun int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
3923*4882a593Smuzhiyun 				 struct napi_struct *napi, int budget)
3924*4882a593Smuzhiyun {
3925*4882a593Smuzhiyun 	struct ath11k *ar;
3926*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
3927*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring;
3928*4882a593Smuzhiyun 	struct hal_rx_wbm_rel_info err_info;
3929*4882a593Smuzhiyun 	struct hal_srng *srng;
3930*4882a593Smuzhiyun 	struct sk_buff *msdu;
3931*4882a593Smuzhiyun 	struct sk_buff_head msdu_list[MAX_RADIOS];
3932*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
3933*4882a593Smuzhiyun 	u32 *rx_desc;
3934*4882a593Smuzhiyun 	int buf_id, mac_id;
3935*4882a593Smuzhiyun 	int num_buffs_reaped[MAX_RADIOS] = {0};
3936*4882a593Smuzhiyun 	int total_num_buffs_reaped = 0;
3937*4882a593Smuzhiyun 	int ret, i;
3938*4882a593Smuzhiyun 
3939*4882a593Smuzhiyun 	for (i = 0; i < ab->num_radios; i++)
3940*4882a593Smuzhiyun 		__skb_queue_head_init(&msdu_list[i]);
3941*4882a593Smuzhiyun 
3942*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3943*4882a593Smuzhiyun 
3944*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
3945*4882a593Smuzhiyun 
3946*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
3947*4882a593Smuzhiyun 
3948*4882a593Smuzhiyun 	while (budget) {
3949*4882a593Smuzhiyun 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
3950*4882a593Smuzhiyun 		if (!rx_desc)
3951*4882a593Smuzhiyun 			break;
3952*4882a593Smuzhiyun 
3953*4882a593Smuzhiyun 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3954*4882a593Smuzhiyun 		if (ret) {
3955*4882a593Smuzhiyun 			ath11k_warn(ab,
3956*4882a593Smuzhiyun 				    "failed to parse rx error in wbm_rel ring desc %d\n",
3957*4882a593Smuzhiyun 				    ret);
3958*4882a593Smuzhiyun 			continue;
3959*4882a593Smuzhiyun 		}
3960*4882a593Smuzhiyun 
3961*4882a593Smuzhiyun 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
3962*4882a593Smuzhiyun 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
3963*4882a593Smuzhiyun 
3964*4882a593Smuzhiyun 		ar = ab->pdevs[mac_id].ar;
3965*4882a593Smuzhiyun 		rx_ring = &ar->dp.rx_refill_buf_ring;
3966*4882a593Smuzhiyun 
3967*4882a593Smuzhiyun 		spin_lock_bh(&rx_ring->idr_lock);
3968*4882a593Smuzhiyun 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3969*4882a593Smuzhiyun 		if (!msdu) {
3970*4882a593Smuzhiyun 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
3971*4882a593Smuzhiyun 				    buf_id, mac_id);
3972*4882a593Smuzhiyun 			spin_unlock_bh(&rx_ring->idr_lock);
3973*4882a593Smuzhiyun 			continue;
3974*4882a593Smuzhiyun 		}
3975*4882a593Smuzhiyun 
3976*4882a593Smuzhiyun 		idr_remove(&rx_ring->bufs_idr, buf_id);
3977*4882a593Smuzhiyun 		spin_unlock_bh(&rx_ring->idr_lock);
3978*4882a593Smuzhiyun 
3979*4882a593Smuzhiyun 		rxcb = ATH11K_SKB_RXCB(msdu);
3980*4882a593Smuzhiyun 		dma_unmap_single(ab->dev, rxcb->paddr,
3981*4882a593Smuzhiyun 				 msdu->len + skb_tailroom(msdu),
3982*4882a593Smuzhiyun 				 DMA_FROM_DEVICE);
3983*4882a593Smuzhiyun 
3984*4882a593Smuzhiyun 		num_buffs_reaped[mac_id]++;
3985*4882a593Smuzhiyun 		total_num_buffs_reaped++;
3986*4882a593Smuzhiyun 		budget--;
3987*4882a593Smuzhiyun 
3988*4882a593Smuzhiyun 		if (err_info.push_reason !=
3989*4882a593Smuzhiyun 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
3990*4882a593Smuzhiyun 			dev_kfree_skb_any(msdu);
3991*4882a593Smuzhiyun 			continue;
3992*4882a593Smuzhiyun 		}
3993*4882a593Smuzhiyun 
3994*4882a593Smuzhiyun 		rxcb->err_rel_src = err_info.err_rel_src;
3995*4882a593Smuzhiyun 		rxcb->err_code = err_info.err_code;
3996*4882a593Smuzhiyun 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
3997*4882a593Smuzhiyun 		__skb_queue_tail(&msdu_list[mac_id], msdu);
3998*4882a593Smuzhiyun 	}
3999*4882a593Smuzhiyun 
4000*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
4001*4882a593Smuzhiyun 
4002*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
4003*4882a593Smuzhiyun 
4004*4882a593Smuzhiyun 	if (!total_num_buffs_reaped)
4005*4882a593Smuzhiyun 		goto done;
4006*4882a593Smuzhiyun 
4007*4882a593Smuzhiyun 	for (i = 0; i <  ab->num_radios; i++) {
4008*4882a593Smuzhiyun 		if (!num_buffs_reaped[i])
4009*4882a593Smuzhiyun 			continue;
4010*4882a593Smuzhiyun 
4011*4882a593Smuzhiyun 		ar = ab->pdevs[i].ar;
4012*4882a593Smuzhiyun 		rx_ring = &ar->dp.rx_refill_buf_ring;
4013*4882a593Smuzhiyun 
4014*4882a593Smuzhiyun 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4015*4882a593Smuzhiyun 					   HAL_RX_BUF_RBM_SW3_BM);
4016*4882a593Smuzhiyun 	}
4017*4882a593Smuzhiyun 
4018*4882a593Smuzhiyun 	rcu_read_lock();
4019*4882a593Smuzhiyun 	for (i = 0; i <  ab->num_radios; i++) {
4020*4882a593Smuzhiyun 		if (!rcu_dereference(ab->pdevs_active[i])) {
4021*4882a593Smuzhiyun 			__skb_queue_purge(&msdu_list[i]);
4022*4882a593Smuzhiyun 			continue;
4023*4882a593Smuzhiyun 		}
4024*4882a593Smuzhiyun 
4025*4882a593Smuzhiyun 		ar = ab->pdevs[i].ar;
4026*4882a593Smuzhiyun 
4027*4882a593Smuzhiyun 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4028*4882a593Smuzhiyun 			__skb_queue_purge(&msdu_list[i]);
4029*4882a593Smuzhiyun 			continue;
4030*4882a593Smuzhiyun 		}
4031*4882a593Smuzhiyun 
4032*4882a593Smuzhiyun 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4033*4882a593Smuzhiyun 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4034*4882a593Smuzhiyun 	}
4035*4882a593Smuzhiyun 	rcu_read_unlock();
4036*4882a593Smuzhiyun done:
4037*4882a593Smuzhiyun 	return total_num_buffs_reaped;
4038*4882a593Smuzhiyun }
4039*4882a593Smuzhiyun 
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4040*4882a593Smuzhiyun int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4041*4882a593Smuzhiyun {
4042*4882a593Smuzhiyun 	struct ath11k *ar;
4043*4882a593Smuzhiyun 	struct dp_srng *err_ring;
4044*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring;
4045*4882a593Smuzhiyun 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4046*4882a593Smuzhiyun 	struct hal_srng *srng;
4047*4882a593Smuzhiyun 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4048*4882a593Smuzhiyun 	enum hal_rx_buf_return_buf_manager rbm;
4049*4882a593Smuzhiyun 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4050*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
4051*4882a593Smuzhiyun 	struct sk_buff *skb;
4052*4882a593Smuzhiyun 	struct hal_reo_entrance_ring *entr_ring;
4053*4882a593Smuzhiyun 	void *desc;
4054*4882a593Smuzhiyun 	int num_buf_freed = 0;
4055*4882a593Smuzhiyun 	int quota = budget;
4056*4882a593Smuzhiyun 	dma_addr_t paddr;
4057*4882a593Smuzhiyun 	u32 desc_bank;
4058*4882a593Smuzhiyun 	void *link_desc_va;
4059*4882a593Smuzhiyun 	int num_msdus;
4060*4882a593Smuzhiyun 	int i;
4061*4882a593Smuzhiyun 	int buf_id;
4062*4882a593Smuzhiyun 
4063*4882a593Smuzhiyun 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4064*4882a593Smuzhiyun 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4065*4882a593Smuzhiyun 									  mac_id)];
4066*4882a593Smuzhiyun 	rx_ring = &ar->dp.rx_refill_buf_ring;
4067*4882a593Smuzhiyun 
4068*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[err_ring->ring_id];
4069*4882a593Smuzhiyun 
4070*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
4071*4882a593Smuzhiyun 
4072*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
4073*4882a593Smuzhiyun 
4074*4882a593Smuzhiyun 	while (quota-- &&
4075*4882a593Smuzhiyun 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4076*4882a593Smuzhiyun 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4077*4882a593Smuzhiyun 
4078*4882a593Smuzhiyun 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4079*4882a593Smuzhiyun 		rxdma_err_code =
4080*4882a593Smuzhiyun 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4081*4882a593Smuzhiyun 				  entr_ring->info1);
4082*4882a593Smuzhiyun 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4083*4882a593Smuzhiyun 
4084*4882a593Smuzhiyun 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4085*4882a593Smuzhiyun 			       (paddr - link_desc_banks[desc_bank].paddr);
4086*4882a593Smuzhiyun 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4087*4882a593Smuzhiyun 						 msdu_cookies, &rbm);
4088*4882a593Smuzhiyun 
4089*4882a593Smuzhiyun 		for (i = 0; i < num_msdus; i++) {
4090*4882a593Smuzhiyun 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4091*4882a593Smuzhiyun 					   msdu_cookies[i]);
4092*4882a593Smuzhiyun 
4093*4882a593Smuzhiyun 			spin_lock_bh(&rx_ring->idr_lock);
4094*4882a593Smuzhiyun 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4095*4882a593Smuzhiyun 			if (!skb) {
4096*4882a593Smuzhiyun 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4097*4882a593Smuzhiyun 					    buf_id);
4098*4882a593Smuzhiyun 				spin_unlock_bh(&rx_ring->idr_lock);
4099*4882a593Smuzhiyun 				continue;
4100*4882a593Smuzhiyun 			}
4101*4882a593Smuzhiyun 
4102*4882a593Smuzhiyun 			idr_remove(&rx_ring->bufs_idr, buf_id);
4103*4882a593Smuzhiyun 			spin_unlock_bh(&rx_ring->idr_lock);
4104*4882a593Smuzhiyun 
4105*4882a593Smuzhiyun 			rxcb = ATH11K_SKB_RXCB(skb);
4106*4882a593Smuzhiyun 			dma_unmap_single(ab->dev, rxcb->paddr,
4107*4882a593Smuzhiyun 					 skb->len + skb_tailroom(skb),
4108*4882a593Smuzhiyun 					 DMA_FROM_DEVICE);
4109*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
4110*4882a593Smuzhiyun 
4111*4882a593Smuzhiyun 			num_buf_freed++;
4112*4882a593Smuzhiyun 		}
4113*4882a593Smuzhiyun 
4114*4882a593Smuzhiyun 		ath11k_dp_rx_link_desc_return(ab, desc,
4115*4882a593Smuzhiyun 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4116*4882a593Smuzhiyun 	}
4117*4882a593Smuzhiyun 
4118*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
4119*4882a593Smuzhiyun 
4120*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
4121*4882a593Smuzhiyun 
4122*4882a593Smuzhiyun 	if (num_buf_freed)
4123*4882a593Smuzhiyun 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4124*4882a593Smuzhiyun 					   HAL_RX_BUF_RBM_SW3_BM);
4125*4882a593Smuzhiyun 
4126*4882a593Smuzhiyun 	return budget - quota;
4127*4882a593Smuzhiyun }
4128*4882a593Smuzhiyun 
ath11k_dp_process_reo_status(struct ath11k_base * ab)4129*4882a593Smuzhiyun void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4130*4882a593Smuzhiyun {
4131*4882a593Smuzhiyun 	struct ath11k_dp *dp = &ab->dp;
4132*4882a593Smuzhiyun 	struct hal_srng *srng;
4133*4882a593Smuzhiyun 	struct dp_reo_cmd *cmd, *tmp;
4134*4882a593Smuzhiyun 	bool found = false;
4135*4882a593Smuzhiyun 	u32 *reo_desc;
4136*4882a593Smuzhiyun 	u16 tag;
4137*4882a593Smuzhiyun 	struct hal_reo_status reo_status;
4138*4882a593Smuzhiyun 
4139*4882a593Smuzhiyun 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4140*4882a593Smuzhiyun 
4141*4882a593Smuzhiyun 	memset(&reo_status, 0, sizeof(reo_status));
4142*4882a593Smuzhiyun 
4143*4882a593Smuzhiyun 	spin_lock_bh(&srng->lock);
4144*4882a593Smuzhiyun 
4145*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ab, srng);
4146*4882a593Smuzhiyun 
4147*4882a593Smuzhiyun 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4148*4882a593Smuzhiyun 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4149*4882a593Smuzhiyun 
4150*4882a593Smuzhiyun 		switch (tag) {
4151*4882a593Smuzhiyun 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4152*4882a593Smuzhiyun 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4153*4882a593Smuzhiyun 							  &reo_status);
4154*4882a593Smuzhiyun 			break;
4155*4882a593Smuzhiyun 		case HAL_REO_FLUSH_QUEUE_STATUS:
4156*4882a593Smuzhiyun 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4157*4882a593Smuzhiyun 							  &reo_status);
4158*4882a593Smuzhiyun 			break;
4159*4882a593Smuzhiyun 		case HAL_REO_FLUSH_CACHE_STATUS:
4160*4882a593Smuzhiyun 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4161*4882a593Smuzhiyun 							  &reo_status);
4162*4882a593Smuzhiyun 			break;
4163*4882a593Smuzhiyun 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4164*4882a593Smuzhiyun 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4165*4882a593Smuzhiyun 							  &reo_status);
4166*4882a593Smuzhiyun 			break;
4167*4882a593Smuzhiyun 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4168*4882a593Smuzhiyun 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4169*4882a593Smuzhiyun 								 &reo_status);
4170*4882a593Smuzhiyun 			break;
4171*4882a593Smuzhiyun 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4172*4882a593Smuzhiyun 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4173*4882a593Smuzhiyun 								  &reo_status);
4174*4882a593Smuzhiyun 			break;
4175*4882a593Smuzhiyun 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4176*4882a593Smuzhiyun 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4177*4882a593Smuzhiyun 								  &reo_status);
4178*4882a593Smuzhiyun 			break;
4179*4882a593Smuzhiyun 		default:
4180*4882a593Smuzhiyun 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4181*4882a593Smuzhiyun 			continue;
4182*4882a593Smuzhiyun 		}
4183*4882a593Smuzhiyun 
4184*4882a593Smuzhiyun 		spin_lock_bh(&dp->reo_cmd_lock);
4185*4882a593Smuzhiyun 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4186*4882a593Smuzhiyun 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4187*4882a593Smuzhiyun 				found = true;
4188*4882a593Smuzhiyun 				list_del(&cmd->list);
4189*4882a593Smuzhiyun 				break;
4190*4882a593Smuzhiyun 			}
4191*4882a593Smuzhiyun 		}
4192*4882a593Smuzhiyun 		spin_unlock_bh(&dp->reo_cmd_lock);
4193*4882a593Smuzhiyun 
4194*4882a593Smuzhiyun 		if (found) {
4195*4882a593Smuzhiyun 			cmd->handler(dp, (void *)&cmd->data,
4196*4882a593Smuzhiyun 				     reo_status.uniform_hdr.cmd_status);
4197*4882a593Smuzhiyun 			kfree(cmd);
4198*4882a593Smuzhiyun 		}
4199*4882a593Smuzhiyun 
4200*4882a593Smuzhiyun 		found = false;
4201*4882a593Smuzhiyun 	}
4202*4882a593Smuzhiyun 
4203*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ab, srng);
4204*4882a593Smuzhiyun 
4205*4882a593Smuzhiyun 	spin_unlock_bh(&srng->lock);
4206*4882a593Smuzhiyun }
4207*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4208*4882a593Smuzhiyun void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4209*4882a593Smuzhiyun {
4210*4882a593Smuzhiyun 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4211*4882a593Smuzhiyun 
4212*4882a593Smuzhiyun 	ath11k_dp_rx_pdev_srng_free(ar);
4213*4882a593Smuzhiyun 	ath11k_dp_rxdma_pdev_buf_free(ar);
4214*4882a593Smuzhiyun }
4215*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4216*4882a593Smuzhiyun int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4217*4882a593Smuzhiyun {
4218*4882a593Smuzhiyun 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4219*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4220*4882a593Smuzhiyun 	u32 ring_id;
4221*4882a593Smuzhiyun 	int i;
4222*4882a593Smuzhiyun 	int ret;
4223*4882a593Smuzhiyun 
4224*4882a593Smuzhiyun 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4225*4882a593Smuzhiyun 	if (ret) {
4226*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to setup rx srngs\n");
4227*4882a593Smuzhiyun 		return ret;
4228*4882a593Smuzhiyun 	}
4229*4882a593Smuzhiyun 
4230*4882a593Smuzhiyun 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4231*4882a593Smuzhiyun 	if (ret) {
4232*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4233*4882a593Smuzhiyun 		return ret;
4234*4882a593Smuzhiyun 	}
4235*4882a593Smuzhiyun 
4236*4882a593Smuzhiyun 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4237*4882a593Smuzhiyun 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4238*4882a593Smuzhiyun 	if (ret) {
4239*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4240*4882a593Smuzhiyun 			    ret);
4241*4882a593Smuzhiyun 		return ret;
4242*4882a593Smuzhiyun 	}
4243*4882a593Smuzhiyun 
4244*4882a593Smuzhiyun 	if (ab->hw_params.rx_mac_buf_ring) {
4245*4882a593Smuzhiyun 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4246*4882a593Smuzhiyun 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4247*4882a593Smuzhiyun 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4248*4882a593Smuzhiyun 							  mac_id + i, HAL_RXDMA_BUF);
4249*4882a593Smuzhiyun 			if (ret) {
4250*4882a593Smuzhiyun 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4251*4882a593Smuzhiyun 					    i, ret);
4252*4882a593Smuzhiyun 				return ret;
4253*4882a593Smuzhiyun 			}
4254*4882a593Smuzhiyun 		}
4255*4882a593Smuzhiyun 	}
4256*4882a593Smuzhiyun 
4257*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4258*4882a593Smuzhiyun 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4259*4882a593Smuzhiyun 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4260*4882a593Smuzhiyun 						  mac_id + i, HAL_RXDMA_DST);
4261*4882a593Smuzhiyun 		if (ret) {
4262*4882a593Smuzhiyun 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4263*4882a593Smuzhiyun 				    i, ret);
4264*4882a593Smuzhiyun 			return ret;
4265*4882a593Smuzhiyun 		}
4266*4882a593Smuzhiyun 	}
4267*4882a593Smuzhiyun 
4268*4882a593Smuzhiyun 	if (!ab->hw_params.rxdma1_enable)
4269*4882a593Smuzhiyun 		goto config_refill_ring;
4270*4882a593Smuzhiyun 
4271*4882a593Smuzhiyun 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4272*4882a593Smuzhiyun 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4273*4882a593Smuzhiyun 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4274*4882a593Smuzhiyun 	if (ret) {
4275*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4276*4882a593Smuzhiyun 			    ret);
4277*4882a593Smuzhiyun 		return ret;
4278*4882a593Smuzhiyun 	}
4279*4882a593Smuzhiyun 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4280*4882a593Smuzhiyun 					  dp->rxdma_mon_dst_ring.ring_id,
4281*4882a593Smuzhiyun 					  mac_id, HAL_RXDMA_MONITOR_DST);
4282*4882a593Smuzhiyun 	if (ret) {
4283*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4284*4882a593Smuzhiyun 			    ret);
4285*4882a593Smuzhiyun 		return ret;
4286*4882a593Smuzhiyun 	}
4287*4882a593Smuzhiyun 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4288*4882a593Smuzhiyun 					  dp->rxdma_mon_desc_ring.ring_id,
4289*4882a593Smuzhiyun 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4290*4882a593Smuzhiyun 	if (ret) {
4291*4882a593Smuzhiyun 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4292*4882a593Smuzhiyun 			    ret);
4293*4882a593Smuzhiyun 		return ret;
4294*4882a593Smuzhiyun 	}
4295*4882a593Smuzhiyun 
4296*4882a593Smuzhiyun config_refill_ring:
4297*4882a593Smuzhiyun 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4298*4882a593Smuzhiyun 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4299*4882a593Smuzhiyun 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4300*4882a593Smuzhiyun 						  HAL_RXDMA_MONITOR_STATUS);
4301*4882a593Smuzhiyun 		if (ret) {
4302*4882a593Smuzhiyun 			ath11k_warn(ab,
4303*4882a593Smuzhiyun 				    "failed to configure mon_status_refill_ring%d %d\n",
4304*4882a593Smuzhiyun 				    i, ret);
4305*4882a593Smuzhiyun 			return ret;
4306*4882a593Smuzhiyun 		}
4307*4882a593Smuzhiyun 	}
4308*4882a593Smuzhiyun 
4309*4882a593Smuzhiyun 	return 0;
4310*4882a593Smuzhiyun }
4311*4882a593Smuzhiyun 
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4312*4882a593Smuzhiyun static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4313*4882a593Smuzhiyun {
4314*4882a593Smuzhiyun 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4315*4882a593Smuzhiyun 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4316*4882a593Smuzhiyun 		*total_len -= *frag_len;
4317*4882a593Smuzhiyun 	} else {
4318*4882a593Smuzhiyun 		*frag_len = *total_len;
4319*4882a593Smuzhiyun 		*total_len = 0;
4320*4882a593Smuzhiyun 	}
4321*4882a593Smuzhiyun }
4322*4882a593Smuzhiyun 
4323*4882a593Smuzhiyun static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4324*4882a593Smuzhiyun int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4325*4882a593Smuzhiyun 					  void *p_last_buf_addr_info,
4326*4882a593Smuzhiyun 					  u8 mac_id)
4327*4882a593Smuzhiyun {
4328*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4329*4882a593Smuzhiyun 	struct dp_srng *dp_srng;
4330*4882a593Smuzhiyun 	void *hal_srng;
4331*4882a593Smuzhiyun 	void *src_srng_desc;
4332*4882a593Smuzhiyun 	int ret = 0;
4333*4882a593Smuzhiyun 
4334*4882a593Smuzhiyun 	if (ar->ab->hw_params.rxdma1_enable) {
4335*4882a593Smuzhiyun 		dp_srng = &dp->rxdma_mon_desc_ring;
4336*4882a593Smuzhiyun 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4337*4882a593Smuzhiyun 	} else {
4338*4882a593Smuzhiyun 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4339*4882a593Smuzhiyun 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4340*4882a593Smuzhiyun 	}
4341*4882a593Smuzhiyun 
4342*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4343*4882a593Smuzhiyun 
4344*4882a593Smuzhiyun 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4345*4882a593Smuzhiyun 
4346*4882a593Smuzhiyun 	if (src_srng_desc) {
4347*4882a593Smuzhiyun 		struct ath11k_buffer_addr *src_desc =
4348*4882a593Smuzhiyun 				(struct ath11k_buffer_addr *)src_srng_desc;
4349*4882a593Smuzhiyun 
4350*4882a593Smuzhiyun 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4351*4882a593Smuzhiyun 	} else {
4352*4882a593Smuzhiyun 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4353*4882a593Smuzhiyun 			   "Monitor Link Desc Ring %d Full", mac_id);
4354*4882a593Smuzhiyun 		ret = -ENOMEM;
4355*4882a593Smuzhiyun 	}
4356*4882a593Smuzhiyun 
4357*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4358*4882a593Smuzhiyun 	return ret;
4359*4882a593Smuzhiyun }
4360*4882a593Smuzhiyun 
4361*4882a593Smuzhiyun static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4362*4882a593Smuzhiyun void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4363*4882a593Smuzhiyun 					 dma_addr_t *paddr, u32 *sw_cookie,
4364*4882a593Smuzhiyun 					 u8 *rbm,
4365*4882a593Smuzhiyun 					 void **pp_buf_addr_info)
4366*4882a593Smuzhiyun {
4367*4882a593Smuzhiyun 	struct hal_rx_msdu_link *msdu_link =
4368*4882a593Smuzhiyun 			(struct hal_rx_msdu_link *)rx_msdu_link_desc;
4369*4882a593Smuzhiyun 	struct ath11k_buffer_addr *buf_addr_info;
4370*4882a593Smuzhiyun 
4371*4882a593Smuzhiyun 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4372*4882a593Smuzhiyun 
4373*4882a593Smuzhiyun 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4374*4882a593Smuzhiyun 
4375*4882a593Smuzhiyun 	*pp_buf_addr_info = (void *)buf_addr_info;
4376*4882a593Smuzhiyun }
4377*4882a593Smuzhiyun 
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4378*4882a593Smuzhiyun static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4379*4882a593Smuzhiyun {
4380*4882a593Smuzhiyun 	if (skb->len > len) {
4381*4882a593Smuzhiyun 		skb_trim(skb, len);
4382*4882a593Smuzhiyun 	} else {
4383*4882a593Smuzhiyun 		if (skb_tailroom(skb) < len - skb->len) {
4384*4882a593Smuzhiyun 			if ((pskb_expand_head(skb, 0,
4385*4882a593Smuzhiyun 					      len - skb->len - skb_tailroom(skb),
4386*4882a593Smuzhiyun 					      GFP_ATOMIC))) {
4387*4882a593Smuzhiyun 				dev_kfree_skb_any(skb);
4388*4882a593Smuzhiyun 				return -ENOMEM;
4389*4882a593Smuzhiyun 			}
4390*4882a593Smuzhiyun 		}
4391*4882a593Smuzhiyun 		skb_put(skb, (len - skb->len));
4392*4882a593Smuzhiyun 	}
4393*4882a593Smuzhiyun 	return 0;
4394*4882a593Smuzhiyun }
4395*4882a593Smuzhiyun 
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4396*4882a593Smuzhiyun static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4397*4882a593Smuzhiyun 					void *msdu_link_desc,
4398*4882a593Smuzhiyun 					struct hal_rx_msdu_list *msdu_list,
4399*4882a593Smuzhiyun 					u16 *num_msdus)
4400*4882a593Smuzhiyun {
4401*4882a593Smuzhiyun 	struct hal_rx_msdu_details *msdu_details = NULL;
4402*4882a593Smuzhiyun 	struct rx_msdu_desc *msdu_desc_info = NULL;
4403*4882a593Smuzhiyun 	struct hal_rx_msdu_link *msdu_link = NULL;
4404*4882a593Smuzhiyun 	int i;
4405*4882a593Smuzhiyun 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4406*4882a593Smuzhiyun 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4407*4882a593Smuzhiyun 	u8  tmp  = 0;
4408*4882a593Smuzhiyun 
4409*4882a593Smuzhiyun 	msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4410*4882a593Smuzhiyun 	msdu_details = &msdu_link->msdu_link[0];
4411*4882a593Smuzhiyun 
4412*4882a593Smuzhiyun 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4413*4882a593Smuzhiyun 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4414*4882a593Smuzhiyun 			      msdu_details[i].buf_addr_info.info0) == 0) {
4415*4882a593Smuzhiyun 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4416*4882a593Smuzhiyun 			msdu_desc_info->info0 |= last;
4417*4882a593Smuzhiyun 			;
4418*4882a593Smuzhiyun 			break;
4419*4882a593Smuzhiyun 		}
4420*4882a593Smuzhiyun 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4421*4882a593Smuzhiyun 
4422*4882a593Smuzhiyun 		if (!i)
4423*4882a593Smuzhiyun 			msdu_desc_info->info0 |= first;
4424*4882a593Smuzhiyun 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4425*4882a593Smuzhiyun 			msdu_desc_info->info0 |= last;
4426*4882a593Smuzhiyun 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4427*4882a593Smuzhiyun 		msdu_list->msdu_info[i].msdu_len =
4428*4882a593Smuzhiyun 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4429*4882a593Smuzhiyun 		msdu_list->sw_cookie[i] =
4430*4882a593Smuzhiyun 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4431*4882a593Smuzhiyun 				  msdu_details[i].buf_addr_info.info1);
4432*4882a593Smuzhiyun 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4433*4882a593Smuzhiyun 				msdu_details[i].buf_addr_info.info1);
4434*4882a593Smuzhiyun 		msdu_list->rbm[i] = tmp;
4435*4882a593Smuzhiyun 	}
4436*4882a593Smuzhiyun 	*num_msdus = i;
4437*4882a593Smuzhiyun }
4438*4882a593Smuzhiyun 
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4439*4882a593Smuzhiyun static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4440*4882a593Smuzhiyun 					u32 *rx_bufs_used)
4441*4882a593Smuzhiyun {
4442*4882a593Smuzhiyun 	u32 ret = 0;
4443*4882a593Smuzhiyun 
4444*4882a593Smuzhiyun 	if ((*ppdu_id < msdu_ppdu_id) &&
4445*4882a593Smuzhiyun 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4446*4882a593Smuzhiyun 		*ppdu_id = msdu_ppdu_id;
4447*4882a593Smuzhiyun 		ret = msdu_ppdu_id;
4448*4882a593Smuzhiyun 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4449*4882a593Smuzhiyun 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4450*4882a593Smuzhiyun 		/* mon_dst is behind than mon_status
4451*4882a593Smuzhiyun 		 * skip dst_ring and free it
4452*4882a593Smuzhiyun 		 */
4453*4882a593Smuzhiyun 		*rx_bufs_used += 1;
4454*4882a593Smuzhiyun 		*ppdu_id = msdu_ppdu_id;
4455*4882a593Smuzhiyun 		ret = msdu_ppdu_id;
4456*4882a593Smuzhiyun 	}
4457*4882a593Smuzhiyun 	return ret;
4458*4882a593Smuzhiyun }
4459*4882a593Smuzhiyun 
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4460*4882a593Smuzhiyun static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4461*4882a593Smuzhiyun 				      bool *is_frag, u32 *total_len,
4462*4882a593Smuzhiyun 				      u32 *frag_len, u32 *msdu_cnt)
4463*4882a593Smuzhiyun {
4464*4882a593Smuzhiyun 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4465*4882a593Smuzhiyun 		if (!*is_frag) {
4466*4882a593Smuzhiyun 			*total_len = info->msdu_len;
4467*4882a593Smuzhiyun 			*is_frag = true;
4468*4882a593Smuzhiyun 		}
4469*4882a593Smuzhiyun 		ath11k_dp_mon_set_frag_len(total_len,
4470*4882a593Smuzhiyun 					   frag_len);
4471*4882a593Smuzhiyun 	} else {
4472*4882a593Smuzhiyun 		if (*is_frag) {
4473*4882a593Smuzhiyun 			ath11k_dp_mon_set_frag_len(total_len,
4474*4882a593Smuzhiyun 						   frag_len);
4475*4882a593Smuzhiyun 		} else {
4476*4882a593Smuzhiyun 			*frag_len = info->msdu_len;
4477*4882a593Smuzhiyun 		}
4478*4882a593Smuzhiyun 		*is_frag = false;
4479*4882a593Smuzhiyun 		*msdu_cnt -= 1;
4480*4882a593Smuzhiyun 	}
4481*4882a593Smuzhiyun }
4482*4882a593Smuzhiyun 
4483*4882a593Smuzhiyun static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4484*4882a593Smuzhiyun ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4485*4882a593Smuzhiyun 			  void *ring_entry, struct sk_buff **head_msdu,
4486*4882a593Smuzhiyun 			  struct sk_buff **tail_msdu, u32 *npackets,
4487*4882a593Smuzhiyun 			  u32 *ppdu_id)
4488*4882a593Smuzhiyun {
4489*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4490*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4491*4882a593Smuzhiyun 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4492*4882a593Smuzhiyun 	struct sk_buff *msdu = NULL, *last = NULL;
4493*4882a593Smuzhiyun 	struct hal_rx_msdu_list msdu_list;
4494*4882a593Smuzhiyun 	void *p_buf_addr_info, *p_last_buf_addr_info;
4495*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc;
4496*4882a593Smuzhiyun 	void *rx_msdu_link_desc;
4497*4882a593Smuzhiyun 	dma_addr_t paddr;
4498*4882a593Smuzhiyun 	u16 num_msdus = 0;
4499*4882a593Smuzhiyun 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4500*4882a593Smuzhiyun 	u32 rx_bufs_used = 0, i = 0;
4501*4882a593Smuzhiyun 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4502*4882a593Smuzhiyun 	u32 total_len = 0, frag_len = 0;
4503*4882a593Smuzhiyun 	bool is_frag, is_first_msdu;
4504*4882a593Smuzhiyun 	bool drop_mpdu = false;
4505*4882a593Smuzhiyun 	struct ath11k_skb_rxcb *rxcb;
4506*4882a593Smuzhiyun 	struct hal_reo_entrance_ring *ent_desc =
4507*4882a593Smuzhiyun 			(struct hal_reo_entrance_ring *)ring_entry;
4508*4882a593Smuzhiyun 	int buf_id;
4509*4882a593Smuzhiyun 	u32 rx_link_buf_info[2];
4510*4882a593Smuzhiyun 	u8 rbm;
4511*4882a593Smuzhiyun 
4512*4882a593Smuzhiyun 	if (!ar->ab->hw_params.rxdma1_enable)
4513*4882a593Smuzhiyun 		rx_ring = &dp->rx_refill_buf_ring;
4514*4882a593Smuzhiyun 
4515*4882a593Smuzhiyun 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4516*4882a593Smuzhiyun 					    &sw_cookie,
4517*4882a593Smuzhiyun 					    &p_last_buf_addr_info, &rbm,
4518*4882a593Smuzhiyun 					    &msdu_cnt);
4519*4882a593Smuzhiyun 
4520*4882a593Smuzhiyun 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4521*4882a593Smuzhiyun 		      ent_desc->info1) ==
4522*4882a593Smuzhiyun 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4523*4882a593Smuzhiyun 		u8 rxdma_err =
4524*4882a593Smuzhiyun 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4525*4882a593Smuzhiyun 				  ent_desc->info1);
4526*4882a593Smuzhiyun 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4527*4882a593Smuzhiyun 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4528*4882a593Smuzhiyun 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4529*4882a593Smuzhiyun 			drop_mpdu = true;
4530*4882a593Smuzhiyun 			pmon->rx_mon_stats.dest_mpdu_drop++;
4531*4882a593Smuzhiyun 		}
4532*4882a593Smuzhiyun 	}
4533*4882a593Smuzhiyun 
4534*4882a593Smuzhiyun 	is_frag = false;
4535*4882a593Smuzhiyun 	is_first_msdu = true;
4536*4882a593Smuzhiyun 
4537*4882a593Smuzhiyun 	do {
4538*4882a593Smuzhiyun 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4539*4882a593Smuzhiyun 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4540*4882a593Smuzhiyun 			return rx_bufs_used;
4541*4882a593Smuzhiyun 		}
4542*4882a593Smuzhiyun 
4543*4882a593Smuzhiyun 		if (ar->ab->hw_params.rxdma1_enable)
4544*4882a593Smuzhiyun 			rx_msdu_link_desc =
4545*4882a593Smuzhiyun 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4546*4882a593Smuzhiyun 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4547*4882a593Smuzhiyun 		else
4548*4882a593Smuzhiyun 			rx_msdu_link_desc =
4549*4882a593Smuzhiyun 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4550*4882a593Smuzhiyun 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4551*4882a593Smuzhiyun 
4552*4882a593Smuzhiyun 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4553*4882a593Smuzhiyun 					    &num_msdus);
4554*4882a593Smuzhiyun 
4555*4882a593Smuzhiyun 		for (i = 0; i < num_msdus; i++) {
4556*4882a593Smuzhiyun 			u32 l2_hdr_offset;
4557*4882a593Smuzhiyun 
4558*4882a593Smuzhiyun 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4559*4882a593Smuzhiyun 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4560*4882a593Smuzhiyun 					   "i %d last_cookie %d is same\n",
4561*4882a593Smuzhiyun 					   i, pmon->mon_last_buf_cookie);
4562*4882a593Smuzhiyun 				drop_mpdu = true;
4563*4882a593Smuzhiyun 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4564*4882a593Smuzhiyun 				continue;
4565*4882a593Smuzhiyun 			}
4566*4882a593Smuzhiyun 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4567*4882a593Smuzhiyun 					   msdu_list.sw_cookie[i]);
4568*4882a593Smuzhiyun 
4569*4882a593Smuzhiyun 			spin_lock_bh(&rx_ring->idr_lock);
4570*4882a593Smuzhiyun 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4571*4882a593Smuzhiyun 			spin_unlock_bh(&rx_ring->idr_lock);
4572*4882a593Smuzhiyun 			if (!msdu) {
4573*4882a593Smuzhiyun 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4574*4882a593Smuzhiyun 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4575*4882a593Smuzhiyun 				break;
4576*4882a593Smuzhiyun 			}
4577*4882a593Smuzhiyun 			rxcb = ATH11K_SKB_RXCB(msdu);
4578*4882a593Smuzhiyun 			if (!rxcb->unmapped) {
4579*4882a593Smuzhiyun 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4580*4882a593Smuzhiyun 						 msdu->len +
4581*4882a593Smuzhiyun 						 skb_tailroom(msdu),
4582*4882a593Smuzhiyun 						 DMA_FROM_DEVICE);
4583*4882a593Smuzhiyun 				rxcb->unmapped = 1;
4584*4882a593Smuzhiyun 			}
4585*4882a593Smuzhiyun 			if (drop_mpdu) {
4586*4882a593Smuzhiyun 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4587*4882a593Smuzhiyun 					   "i %d drop msdu %p *ppdu_id %x\n",
4588*4882a593Smuzhiyun 					   i, msdu, *ppdu_id);
4589*4882a593Smuzhiyun 				dev_kfree_skb_any(msdu);
4590*4882a593Smuzhiyun 				msdu = NULL;
4591*4882a593Smuzhiyun 				goto next_msdu;
4592*4882a593Smuzhiyun 			}
4593*4882a593Smuzhiyun 
4594*4882a593Smuzhiyun 			rx_desc = (struct hal_rx_desc *)msdu->data;
4595*4882a593Smuzhiyun 
4596*4882a593Smuzhiyun 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4597*4882a593Smuzhiyun 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(rx_desc);
4598*4882a593Smuzhiyun 
4599*4882a593Smuzhiyun 			if (is_first_msdu) {
4600*4882a593Smuzhiyun 				if (!ath11k_dp_rxdesc_mpdu_valid(rx_desc)) {
4601*4882a593Smuzhiyun 					drop_mpdu = true;
4602*4882a593Smuzhiyun 					dev_kfree_skb_any(msdu);
4603*4882a593Smuzhiyun 					msdu = NULL;
4604*4882a593Smuzhiyun 					pmon->mon_last_linkdesc_paddr = paddr;
4605*4882a593Smuzhiyun 					goto next_msdu;
4606*4882a593Smuzhiyun 				}
4607*4882a593Smuzhiyun 
4608*4882a593Smuzhiyun 				msdu_ppdu_id =
4609*4882a593Smuzhiyun 					ath11k_dp_rxdesc_get_ppduid(rx_desc);
4610*4882a593Smuzhiyun 
4611*4882a593Smuzhiyun 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4612*4882a593Smuzhiyun 								 ppdu_id,
4613*4882a593Smuzhiyun 								 &rx_bufs_used)) {
4614*4882a593Smuzhiyun 					if (rx_bufs_used) {
4615*4882a593Smuzhiyun 						drop_mpdu = true;
4616*4882a593Smuzhiyun 						dev_kfree_skb_any(msdu);
4617*4882a593Smuzhiyun 						msdu = NULL;
4618*4882a593Smuzhiyun 						goto next_msdu;
4619*4882a593Smuzhiyun 					}
4620*4882a593Smuzhiyun 					return rx_bufs_used;
4621*4882a593Smuzhiyun 				}
4622*4882a593Smuzhiyun 				pmon->mon_last_linkdesc_paddr = paddr;
4623*4882a593Smuzhiyun 				is_first_msdu = false;
4624*4882a593Smuzhiyun 			}
4625*4882a593Smuzhiyun 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4626*4882a593Smuzhiyun 						  &is_frag, &total_len,
4627*4882a593Smuzhiyun 						  &frag_len, &msdu_cnt);
4628*4882a593Smuzhiyun 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4629*4882a593Smuzhiyun 
4630*4882a593Smuzhiyun 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4631*4882a593Smuzhiyun 
4632*4882a593Smuzhiyun 			if (!(*head_msdu))
4633*4882a593Smuzhiyun 				*head_msdu = msdu;
4634*4882a593Smuzhiyun 			else if (last)
4635*4882a593Smuzhiyun 				last->next = msdu;
4636*4882a593Smuzhiyun 
4637*4882a593Smuzhiyun 			last = msdu;
4638*4882a593Smuzhiyun next_msdu:
4639*4882a593Smuzhiyun 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4640*4882a593Smuzhiyun 			rx_bufs_used++;
4641*4882a593Smuzhiyun 			spin_lock_bh(&rx_ring->idr_lock);
4642*4882a593Smuzhiyun 			idr_remove(&rx_ring->bufs_idr, buf_id);
4643*4882a593Smuzhiyun 			spin_unlock_bh(&rx_ring->idr_lock);
4644*4882a593Smuzhiyun 		}
4645*4882a593Smuzhiyun 
4646*4882a593Smuzhiyun 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4647*4882a593Smuzhiyun 
4648*4882a593Smuzhiyun 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4649*4882a593Smuzhiyun 						    &sw_cookie, &rbm,
4650*4882a593Smuzhiyun 						    &p_buf_addr_info);
4651*4882a593Smuzhiyun 
4652*4882a593Smuzhiyun 		if (ar->ab->hw_params.rxdma1_enable) {
4653*4882a593Smuzhiyun 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4654*4882a593Smuzhiyun 								  p_last_buf_addr_info,
4655*4882a593Smuzhiyun 								  dp->mac_id))
4656*4882a593Smuzhiyun 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4657*4882a593Smuzhiyun 					   "dp_rx_monitor_link_desc_return failed");
4658*4882a593Smuzhiyun 		} else {
4659*4882a593Smuzhiyun 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4660*4882a593Smuzhiyun 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4661*4882a593Smuzhiyun 		}
4662*4882a593Smuzhiyun 
4663*4882a593Smuzhiyun 		p_last_buf_addr_info = p_buf_addr_info;
4664*4882a593Smuzhiyun 
4665*4882a593Smuzhiyun 	} while (paddr && msdu_cnt);
4666*4882a593Smuzhiyun 
4667*4882a593Smuzhiyun 	if (last)
4668*4882a593Smuzhiyun 		last->next = NULL;
4669*4882a593Smuzhiyun 
4670*4882a593Smuzhiyun 	*tail_msdu = msdu;
4671*4882a593Smuzhiyun 
4672*4882a593Smuzhiyun 	if (msdu_cnt == 0)
4673*4882a593Smuzhiyun 		*npackets = 1;
4674*4882a593Smuzhiyun 
4675*4882a593Smuzhiyun 	return rx_bufs_used;
4676*4882a593Smuzhiyun }
4677*4882a593Smuzhiyun 
ath11k_dp_rx_msdus_set_payload(struct sk_buff * msdu)4678*4882a593Smuzhiyun static void ath11k_dp_rx_msdus_set_payload(struct sk_buff *msdu)
4679*4882a593Smuzhiyun {
4680*4882a593Smuzhiyun 	u32 rx_pkt_offset, l2_hdr_offset;
4681*4882a593Smuzhiyun 
4682*4882a593Smuzhiyun 	rx_pkt_offset = sizeof(struct hal_rx_desc);
4683*4882a593Smuzhiyun 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad((struct hal_rx_desc *)msdu->data);
4684*4882a593Smuzhiyun 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4685*4882a593Smuzhiyun }
4686*4882a593Smuzhiyun 
4687*4882a593Smuzhiyun static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs)4688*4882a593Smuzhiyun ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4689*4882a593Smuzhiyun 			    u32 mac_id, struct sk_buff *head_msdu,
4690*4882a593Smuzhiyun 			    struct sk_buff *last_msdu,
4691*4882a593Smuzhiyun 			    struct ieee80211_rx_status *rxs)
4692*4882a593Smuzhiyun {
4693*4882a593Smuzhiyun 	struct sk_buff *msdu, *mpdu_buf, *prev_buf;
4694*4882a593Smuzhiyun 	u32 decap_format, wifi_hdr_len;
4695*4882a593Smuzhiyun 	struct hal_rx_desc *rx_desc;
4696*4882a593Smuzhiyun 	char *hdr_desc;
4697*4882a593Smuzhiyun 	u8 *dest;
4698*4882a593Smuzhiyun 	struct ieee80211_hdr_3addr *wh;
4699*4882a593Smuzhiyun 
4700*4882a593Smuzhiyun 	mpdu_buf = NULL;
4701*4882a593Smuzhiyun 
4702*4882a593Smuzhiyun 	if (!head_msdu)
4703*4882a593Smuzhiyun 		goto err_merge_fail;
4704*4882a593Smuzhiyun 
4705*4882a593Smuzhiyun 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4706*4882a593Smuzhiyun 
4707*4882a593Smuzhiyun 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_desc))
4708*4882a593Smuzhiyun 		return NULL;
4709*4882a593Smuzhiyun 
4710*4882a593Smuzhiyun 	decap_format = ath11k_dp_rxdesc_get_decap_format(rx_desc);
4711*4882a593Smuzhiyun 
4712*4882a593Smuzhiyun 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4713*4882a593Smuzhiyun 
4714*4882a593Smuzhiyun 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4715*4882a593Smuzhiyun 		ath11k_dp_rx_msdus_set_payload(head_msdu);
4716*4882a593Smuzhiyun 
4717*4882a593Smuzhiyun 		prev_buf = head_msdu;
4718*4882a593Smuzhiyun 		msdu = head_msdu->next;
4719*4882a593Smuzhiyun 
4720*4882a593Smuzhiyun 		while (msdu) {
4721*4882a593Smuzhiyun 			ath11k_dp_rx_msdus_set_payload(msdu);
4722*4882a593Smuzhiyun 
4723*4882a593Smuzhiyun 			prev_buf = msdu;
4724*4882a593Smuzhiyun 			msdu = msdu->next;
4725*4882a593Smuzhiyun 		}
4726*4882a593Smuzhiyun 
4727*4882a593Smuzhiyun 		prev_buf->next = NULL;
4728*4882a593Smuzhiyun 
4729*4882a593Smuzhiyun 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4730*4882a593Smuzhiyun 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4731*4882a593Smuzhiyun 		__le16 qos_field;
4732*4882a593Smuzhiyun 		u8 qos_pkt = 0;
4733*4882a593Smuzhiyun 
4734*4882a593Smuzhiyun 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4735*4882a593Smuzhiyun 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc);
4736*4882a593Smuzhiyun 
4737*4882a593Smuzhiyun 		/* Base size */
4738*4882a593Smuzhiyun 		wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr);
4739*4882a593Smuzhiyun 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4740*4882a593Smuzhiyun 
4741*4882a593Smuzhiyun 		if (ieee80211_is_data_qos(wh->frame_control)) {
4742*4882a593Smuzhiyun 			struct ieee80211_qos_hdr *qwh =
4743*4882a593Smuzhiyun 					(struct ieee80211_qos_hdr *)hdr_desc;
4744*4882a593Smuzhiyun 
4745*4882a593Smuzhiyun 			qos_field = qwh->qos_ctrl;
4746*4882a593Smuzhiyun 			qos_pkt = 1;
4747*4882a593Smuzhiyun 		}
4748*4882a593Smuzhiyun 		msdu = head_msdu;
4749*4882a593Smuzhiyun 
4750*4882a593Smuzhiyun 		while (msdu) {
4751*4882a593Smuzhiyun 			rx_desc = (struct hal_rx_desc *)msdu->data;
4752*4882a593Smuzhiyun 			hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc);
4753*4882a593Smuzhiyun 
4754*4882a593Smuzhiyun 			if (qos_pkt) {
4755*4882a593Smuzhiyun 				dest = skb_push(msdu, sizeof(__le16));
4756*4882a593Smuzhiyun 				if (!dest)
4757*4882a593Smuzhiyun 					goto err_merge_fail;
4758*4882a593Smuzhiyun 				memcpy(dest, hdr_desc, wifi_hdr_len);
4759*4882a593Smuzhiyun 				memcpy(dest + wifi_hdr_len,
4760*4882a593Smuzhiyun 				       (u8 *)&qos_field, sizeof(__le16));
4761*4882a593Smuzhiyun 			}
4762*4882a593Smuzhiyun 			ath11k_dp_rx_msdus_set_payload(msdu);
4763*4882a593Smuzhiyun 			prev_buf = msdu;
4764*4882a593Smuzhiyun 			msdu = msdu->next;
4765*4882a593Smuzhiyun 		}
4766*4882a593Smuzhiyun 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4767*4882a593Smuzhiyun 		if (!dest)
4768*4882a593Smuzhiyun 			goto err_merge_fail;
4769*4882a593Smuzhiyun 
4770*4882a593Smuzhiyun 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4771*4882a593Smuzhiyun 			   "mpdu_buf %pK mpdu_buf->len %u",
4772*4882a593Smuzhiyun 			   prev_buf, prev_buf->len);
4773*4882a593Smuzhiyun 	} else {
4774*4882a593Smuzhiyun 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4775*4882a593Smuzhiyun 			   "decap format %d is not supported!\n",
4776*4882a593Smuzhiyun 			   decap_format);
4777*4882a593Smuzhiyun 		goto err_merge_fail;
4778*4882a593Smuzhiyun 	}
4779*4882a593Smuzhiyun 
4780*4882a593Smuzhiyun 	return head_msdu;
4781*4882a593Smuzhiyun 
4782*4882a593Smuzhiyun err_merge_fail:
4783*4882a593Smuzhiyun 	if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
4784*4882a593Smuzhiyun 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4785*4882a593Smuzhiyun 			   "err_merge_fail mpdu_buf %pK", mpdu_buf);
4786*4882a593Smuzhiyun 		/* Free the head buffer */
4787*4882a593Smuzhiyun 		dev_kfree_skb_any(mpdu_buf);
4788*4882a593Smuzhiyun 	}
4789*4882a593Smuzhiyun 	return NULL;
4790*4882a593Smuzhiyun }
4791*4882a593Smuzhiyun 
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct napi_struct * napi)4792*4882a593Smuzhiyun static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
4793*4882a593Smuzhiyun 				    struct sk_buff *head_msdu,
4794*4882a593Smuzhiyun 				    struct sk_buff *tail_msdu,
4795*4882a593Smuzhiyun 				    struct napi_struct *napi)
4796*4882a593Smuzhiyun {
4797*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4798*4882a593Smuzhiyun 	struct sk_buff *mon_skb, *skb_next, *header;
4799*4882a593Smuzhiyun 	struct ieee80211_rx_status *rxs = &dp->rx_status, *status;
4800*4882a593Smuzhiyun 
4801*4882a593Smuzhiyun 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
4802*4882a593Smuzhiyun 					      tail_msdu, rxs);
4803*4882a593Smuzhiyun 
4804*4882a593Smuzhiyun 	if (!mon_skb)
4805*4882a593Smuzhiyun 		goto mon_deliver_fail;
4806*4882a593Smuzhiyun 
4807*4882a593Smuzhiyun 	header = mon_skb;
4808*4882a593Smuzhiyun 
4809*4882a593Smuzhiyun 	rxs->flag = 0;
4810*4882a593Smuzhiyun 	do {
4811*4882a593Smuzhiyun 		skb_next = mon_skb->next;
4812*4882a593Smuzhiyun 		if (!skb_next)
4813*4882a593Smuzhiyun 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
4814*4882a593Smuzhiyun 		else
4815*4882a593Smuzhiyun 			rxs->flag |= RX_FLAG_AMSDU_MORE;
4816*4882a593Smuzhiyun 
4817*4882a593Smuzhiyun 		if (mon_skb == header) {
4818*4882a593Smuzhiyun 			header = NULL;
4819*4882a593Smuzhiyun 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
4820*4882a593Smuzhiyun 		} else {
4821*4882a593Smuzhiyun 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
4822*4882a593Smuzhiyun 		}
4823*4882a593Smuzhiyun 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
4824*4882a593Smuzhiyun 
4825*4882a593Smuzhiyun 		status = IEEE80211_SKB_RXCB(mon_skb);
4826*4882a593Smuzhiyun 		*status = *rxs;
4827*4882a593Smuzhiyun 
4828*4882a593Smuzhiyun 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb);
4829*4882a593Smuzhiyun 		mon_skb = skb_next;
4830*4882a593Smuzhiyun 	} while (mon_skb);
4831*4882a593Smuzhiyun 	rxs->flag = 0;
4832*4882a593Smuzhiyun 
4833*4882a593Smuzhiyun 	return 0;
4834*4882a593Smuzhiyun 
4835*4882a593Smuzhiyun mon_deliver_fail:
4836*4882a593Smuzhiyun 	mon_skb = head_msdu;
4837*4882a593Smuzhiyun 	while (mon_skb) {
4838*4882a593Smuzhiyun 		skb_next = mon_skb->next;
4839*4882a593Smuzhiyun 		dev_kfree_skb_any(mon_skb);
4840*4882a593Smuzhiyun 		mon_skb = skb_next;
4841*4882a593Smuzhiyun 	}
4842*4882a593Smuzhiyun 	return -EINVAL;
4843*4882a593Smuzhiyun }
4844*4882a593Smuzhiyun 
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4845*4882a593Smuzhiyun static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
4846*4882a593Smuzhiyun 					  u32 quota, struct napi_struct *napi)
4847*4882a593Smuzhiyun {
4848*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4849*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4850*4882a593Smuzhiyun 	void *ring_entry;
4851*4882a593Smuzhiyun 	void *mon_dst_srng;
4852*4882a593Smuzhiyun 	u32 ppdu_id;
4853*4882a593Smuzhiyun 	u32 rx_bufs_used;
4854*4882a593Smuzhiyun 	u32 ring_id;
4855*4882a593Smuzhiyun 	struct ath11k_pdev_mon_stats *rx_mon_stats;
4856*4882a593Smuzhiyun 	u32	 npackets = 0;
4857*4882a593Smuzhiyun 
4858*4882a593Smuzhiyun 	if (ar->ab->hw_params.rxdma1_enable)
4859*4882a593Smuzhiyun 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
4860*4882a593Smuzhiyun 	else
4861*4882a593Smuzhiyun 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
4862*4882a593Smuzhiyun 
4863*4882a593Smuzhiyun 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
4864*4882a593Smuzhiyun 
4865*4882a593Smuzhiyun 	if (!mon_dst_srng) {
4866*4882a593Smuzhiyun 		ath11k_warn(ar->ab,
4867*4882a593Smuzhiyun 			    "HAL Monitor Destination Ring Init Failed -- %pK",
4868*4882a593Smuzhiyun 			    mon_dst_srng);
4869*4882a593Smuzhiyun 		return;
4870*4882a593Smuzhiyun 	}
4871*4882a593Smuzhiyun 
4872*4882a593Smuzhiyun 	spin_lock_bh(&pmon->mon_lock);
4873*4882a593Smuzhiyun 
4874*4882a593Smuzhiyun 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
4875*4882a593Smuzhiyun 
4876*4882a593Smuzhiyun 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
4877*4882a593Smuzhiyun 	rx_bufs_used = 0;
4878*4882a593Smuzhiyun 	rx_mon_stats = &pmon->rx_mon_stats;
4879*4882a593Smuzhiyun 
4880*4882a593Smuzhiyun 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
4881*4882a593Smuzhiyun 		struct sk_buff *head_msdu, *tail_msdu;
4882*4882a593Smuzhiyun 
4883*4882a593Smuzhiyun 		head_msdu = NULL;
4884*4882a593Smuzhiyun 		tail_msdu = NULL;
4885*4882a593Smuzhiyun 
4886*4882a593Smuzhiyun 		rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
4887*4882a593Smuzhiyun 							  &head_msdu,
4888*4882a593Smuzhiyun 							  &tail_msdu,
4889*4882a593Smuzhiyun 							  &npackets, &ppdu_id);
4890*4882a593Smuzhiyun 
4891*4882a593Smuzhiyun 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
4892*4882a593Smuzhiyun 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4893*4882a593Smuzhiyun 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4894*4882a593Smuzhiyun 				   "dest_rx: new ppdu_id %x != status ppdu_id %x",
4895*4882a593Smuzhiyun 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id);
4896*4882a593Smuzhiyun 			break;
4897*4882a593Smuzhiyun 		}
4898*4882a593Smuzhiyun 		if (head_msdu && tail_msdu) {
4899*4882a593Smuzhiyun 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
4900*4882a593Smuzhiyun 						 tail_msdu, napi);
4901*4882a593Smuzhiyun 			rx_mon_stats->dest_mpdu_done++;
4902*4882a593Smuzhiyun 		}
4903*4882a593Smuzhiyun 
4904*4882a593Smuzhiyun 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
4905*4882a593Smuzhiyun 								mon_dst_srng);
4906*4882a593Smuzhiyun 	}
4907*4882a593Smuzhiyun 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
4908*4882a593Smuzhiyun 
4909*4882a593Smuzhiyun 	spin_unlock_bh(&pmon->mon_lock);
4910*4882a593Smuzhiyun 
4911*4882a593Smuzhiyun 	if (rx_bufs_used) {
4912*4882a593Smuzhiyun 		rx_mon_stats->dest_ppdu_done++;
4913*4882a593Smuzhiyun 		if (ar->ab->hw_params.rxdma1_enable)
4914*4882a593Smuzhiyun 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4915*4882a593Smuzhiyun 						   &dp->rxdma_mon_buf_ring,
4916*4882a593Smuzhiyun 						   rx_bufs_used,
4917*4882a593Smuzhiyun 						   HAL_RX_BUF_RBM_SW3_BM);
4918*4882a593Smuzhiyun 		else
4919*4882a593Smuzhiyun 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4920*4882a593Smuzhiyun 						   &dp->rx_refill_buf_ring,
4921*4882a593Smuzhiyun 						   rx_bufs_used,
4922*4882a593Smuzhiyun 						   HAL_RX_BUF_RBM_SW3_BM);
4923*4882a593Smuzhiyun 	}
4924*4882a593Smuzhiyun }
4925*4882a593Smuzhiyun 
ath11k_dp_rx_mon_status_process_tlv(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4926*4882a593Smuzhiyun static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar,
4927*4882a593Smuzhiyun 						int mac_id, u32 quota,
4928*4882a593Smuzhiyun 						struct napi_struct *napi)
4929*4882a593Smuzhiyun {
4930*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4931*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4932*4882a593Smuzhiyun 	struct hal_rx_mon_ppdu_info *ppdu_info;
4933*4882a593Smuzhiyun 	struct sk_buff *status_skb;
4934*4882a593Smuzhiyun 	u32 tlv_status = HAL_TLV_STATUS_BUF_DONE;
4935*4882a593Smuzhiyun 	struct ath11k_pdev_mon_stats *rx_mon_stats;
4936*4882a593Smuzhiyun 
4937*4882a593Smuzhiyun 	ppdu_info = &pmon->mon_ppdu_info;
4938*4882a593Smuzhiyun 	rx_mon_stats = &pmon->rx_mon_stats;
4939*4882a593Smuzhiyun 
4940*4882a593Smuzhiyun 	if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START)
4941*4882a593Smuzhiyun 		return;
4942*4882a593Smuzhiyun 
4943*4882a593Smuzhiyun 	while (!skb_queue_empty(&pmon->rx_status_q)) {
4944*4882a593Smuzhiyun 		status_skb = skb_dequeue(&pmon->rx_status_q);
4945*4882a593Smuzhiyun 
4946*4882a593Smuzhiyun 		tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info,
4947*4882a593Smuzhiyun 							    status_skb);
4948*4882a593Smuzhiyun 		if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
4949*4882a593Smuzhiyun 			rx_mon_stats->status_ppdu_done++;
4950*4882a593Smuzhiyun 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
4951*4882a593Smuzhiyun 			ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi);
4952*4882a593Smuzhiyun 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4953*4882a593Smuzhiyun 		}
4954*4882a593Smuzhiyun 		dev_kfree_skb_any(status_skb);
4955*4882a593Smuzhiyun 	}
4956*4882a593Smuzhiyun }
4957*4882a593Smuzhiyun 
ath11k_dp_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)4958*4882a593Smuzhiyun static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id,
4959*4882a593Smuzhiyun 				    struct napi_struct *napi, int budget)
4960*4882a593Smuzhiyun {
4961*4882a593Smuzhiyun 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
4962*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4963*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4964*4882a593Smuzhiyun 	int num_buffs_reaped = 0;
4965*4882a593Smuzhiyun 
4966*4882a593Smuzhiyun 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget,
4967*4882a593Smuzhiyun 							     &pmon->rx_status_q);
4968*4882a593Smuzhiyun 	if (num_buffs_reaped)
4969*4882a593Smuzhiyun 		ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi);
4970*4882a593Smuzhiyun 
4971*4882a593Smuzhiyun 	return num_buffs_reaped;
4972*4882a593Smuzhiyun }
4973*4882a593Smuzhiyun 
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)4974*4882a593Smuzhiyun int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
4975*4882a593Smuzhiyun 				   struct napi_struct *napi, int budget)
4976*4882a593Smuzhiyun {
4977*4882a593Smuzhiyun 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
4978*4882a593Smuzhiyun 	int ret = 0;
4979*4882a593Smuzhiyun 
4980*4882a593Smuzhiyun 	if (test_bit(ATH11K_FLAG_MONITOR_ENABLED, &ar->monitor_flags))
4981*4882a593Smuzhiyun 		ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget);
4982*4882a593Smuzhiyun 	else
4983*4882a593Smuzhiyun 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
4984*4882a593Smuzhiyun 	return ret;
4985*4882a593Smuzhiyun }
4986*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)4987*4882a593Smuzhiyun static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
4988*4882a593Smuzhiyun {
4989*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
4990*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4991*4882a593Smuzhiyun 
4992*4882a593Smuzhiyun 	skb_queue_head_init(&pmon->rx_status_q);
4993*4882a593Smuzhiyun 
4994*4882a593Smuzhiyun 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4995*4882a593Smuzhiyun 
4996*4882a593Smuzhiyun 	memset(&pmon->rx_mon_stats, 0,
4997*4882a593Smuzhiyun 	       sizeof(pmon->rx_mon_stats));
4998*4882a593Smuzhiyun 	return 0;
4999*4882a593Smuzhiyun }
5000*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5001*4882a593Smuzhiyun int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5002*4882a593Smuzhiyun {
5003*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
5004*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = &dp->mon_data;
5005*4882a593Smuzhiyun 	struct hal_srng *mon_desc_srng = NULL;
5006*4882a593Smuzhiyun 	struct dp_srng *dp_srng;
5007*4882a593Smuzhiyun 	int ret = 0;
5008*4882a593Smuzhiyun 	u32 n_link_desc = 0;
5009*4882a593Smuzhiyun 
5010*4882a593Smuzhiyun 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5011*4882a593Smuzhiyun 	if (ret) {
5012*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5013*4882a593Smuzhiyun 		return ret;
5014*4882a593Smuzhiyun 	}
5015*4882a593Smuzhiyun 
5016*4882a593Smuzhiyun 	/* if rxdma1_enable is false, no need to setup
5017*4882a593Smuzhiyun 	 * rxdma_mon_desc_ring.
5018*4882a593Smuzhiyun 	 */
5019*4882a593Smuzhiyun 	if (!ar->ab->hw_params.rxdma1_enable)
5020*4882a593Smuzhiyun 		return 0;
5021*4882a593Smuzhiyun 
5022*4882a593Smuzhiyun 	dp_srng = &dp->rxdma_mon_desc_ring;
5023*4882a593Smuzhiyun 	n_link_desc = dp_srng->size /
5024*4882a593Smuzhiyun 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5025*4882a593Smuzhiyun 	mon_desc_srng =
5026*4882a593Smuzhiyun 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5027*4882a593Smuzhiyun 
5028*4882a593Smuzhiyun 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5029*4882a593Smuzhiyun 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5030*4882a593Smuzhiyun 					n_link_desc);
5031*4882a593Smuzhiyun 	if (ret) {
5032*4882a593Smuzhiyun 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5033*4882a593Smuzhiyun 		return ret;
5034*4882a593Smuzhiyun 	}
5035*4882a593Smuzhiyun 	pmon->mon_last_linkdesc_paddr = 0;
5036*4882a593Smuzhiyun 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5037*4882a593Smuzhiyun 	spin_lock_init(&pmon->mon_lock);
5038*4882a593Smuzhiyun 
5039*4882a593Smuzhiyun 	return 0;
5040*4882a593Smuzhiyun }
5041*4882a593Smuzhiyun 
ath11k_dp_mon_link_free(struct ath11k * ar)5042*4882a593Smuzhiyun static int ath11k_dp_mon_link_free(struct ath11k *ar)
5043*4882a593Smuzhiyun {
5044*4882a593Smuzhiyun 	struct ath11k_pdev_dp *dp = &ar->dp;
5045*4882a593Smuzhiyun 	struct ath11k_mon_data *pmon = &dp->mon_data;
5046*4882a593Smuzhiyun 
5047*4882a593Smuzhiyun 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5048*4882a593Smuzhiyun 				    HAL_RXDMA_MONITOR_DESC,
5049*4882a593Smuzhiyun 				    &dp->rxdma_mon_desc_ring);
5050*4882a593Smuzhiyun 	return 0;
5051*4882a593Smuzhiyun }
5052*4882a593Smuzhiyun 
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5053*4882a593Smuzhiyun int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5054*4882a593Smuzhiyun {
5055*4882a593Smuzhiyun 	ath11k_dp_mon_link_free(ar);
5056*4882a593Smuzhiyun 	return 0;
5057*4882a593Smuzhiyun }
5058