1*4882a593Smuzhiyun // SPDX-License-Identifier: BSD-3-Clause-Clear
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include "core.h"
7*4882a593Smuzhiyun #include "debug.h"
8*4882a593Smuzhiyun
ath11k_dbring_bufs_replenish(struct ath11k * ar,struct ath11k_dbring * ring,struct ath11k_dbring_element * buff)9*4882a593Smuzhiyun static int ath11k_dbring_bufs_replenish(struct ath11k *ar,
10*4882a593Smuzhiyun struct ath11k_dbring *ring,
11*4882a593Smuzhiyun struct ath11k_dbring_element *buff)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
14*4882a593Smuzhiyun struct hal_srng *srng;
15*4882a593Smuzhiyun dma_addr_t paddr;
16*4882a593Smuzhiyun void *ptr_aligned, *ptr_unaligned, *desc;
17*4882a593Smuzhiyun int ret;
18*4882a593Smuzhiyun int buf_id;
19*4882a593Smuzhiyun u32 cookie;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun lockdep_assert_held(&srng->lock);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun ath11k_hal_srng_access_begin(ab, srng);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun ptr_unaligned = buff->payload;
28*4882a593Smuzhiyun ptr_aligned = PTR_ALIGN(ptr_unaligned, ring->buf_align);
29*4882a593Smuzhiyun paddr = dma_map_single(ab->dev, ptr_aligned, ring->buf_sz,
30*4882a593Smuzhiyun DMA_FROM_DEVICE);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun ret = dma_mapping_error(ab->dev, paddr);
33*4882a593Smuzhiyun if (ret)
34*4882a593Smuzhiyun goto err;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun spin_lock_bh(&ring->idr_lock);
37*4882a593Smuzhiyun buf_id = idr_alloc(&ring->bufs_idr, buff, 0, ring->bufs_max, GFP_ATOMIC);
38*4882a593Smuzhiyun spin_unlock_bh(&ring->idr_lock);
39*4882a593Smuzhiyun if (buf_id < 0) {
40*4882a593Smuzhiyun ret = -ENOBUFS;
41*4882a593Smuzhiyun goto err_dma_unmap;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
45*4882a593Smuzhiyun if (!desc) {
46*4882a593Smuzhiyun ret = -ENOENT;
47*4882a593Smuzhiyun goto err_idr_remove;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun buff->paddr = paddr;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, ar->pdev_idx) |
53*4882a593Smuzhiyun FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, 0);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ath11k_hal_srng_access_end(ab, srng);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun err_idr_remove:
62*4882a593Smuzhiyun spin_lock_bh(&ring->idr_lock);
63*4882a593Smuzhiyun idr_remove(&ring->bufs_idr, buf_id);
64*4882a593Smuzhiyun spin_unlock_bh(&ring->idr_lock);
65*4882a593Smuzhiyun err_dma_unmap:
66*4882a593Smuzhiyun dma_unmap_single(ab->dev, paddr, ring->buf_sz,
67*4882a593Smuzhiyun DMA_FROM_DEVICE);
68*4882a593Smuzhiyun err:
69*4882a593Smuzhiyun ath11k_hal_srng_access_end(ab, srng);
70*4882a593Smuzhiyun return ret;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
ath11k_dbring_fill_bufs(struct ath11k * ar,struct ath11k_dbring * ring)73*4882a593Smuzhiyun static int ath11k_dbring_fill_bufs(struct ath11k *ar,
74*4882a593Smuzhiyun struct ath11k_dbring *ring)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct ath11k_dbring_element *buff;
77*4882a593Smuzhiyun struct hal_srng *srng;
78*4882a593Smuzhiyun int num_remain, req_entries, num_free;
79*4882a593Smuzhiyun u32 align;
80*4882a593Smuzhiyun int size, ret;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun srng = &ar->ab->hal.srng_list[ring->refill_srng.ring_id];
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun spin_lock_bh(&srng->lock);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun num_free = ath11k_hal_srng_src_num_free(ar->ab, srng, true);
87*4882a593Smuzhiyun req_entries = min(num_free, ring->bufs_max);
88*4882a593Smuzhiyun num_remain = req_entries;
89*4882a593Smuzhiyun align = ring->buf_align;
90*4882a593Smuzhiyun size = sizeof(*buff) + ring->buf_sz + align - 1;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun while (num_remain > 0) {
93*4882a593Smuzhiyun buff = kzalloc(size, GFP_ATOMIC);
94*4882a593Smuzhiyun if (!buff)
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun ret = ath11k_dbring_bufs_replenish(ar, ring, buff);
98*4882a593Smuzhiyun if (ret) {
99*4882a593Smuzhiyun ath11k_warn(ar->ab, "failed to replenish db ring num_remain %d req_ent %d\n",
100*4882a593Smuzhiyun num_remain, req_entries);
101*4882a593Smuzhiyun kfree(buff);
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun num_remain--;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun spin_unlock_bh(&srng->lock);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return num_remain;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
ath11k_dbring_wmi_cfg_setup(struct ath11k * ar,struct ath11k_dbring * ring,enum wmi_direct_buffer_module id)112*4882a593Smuzhiyun int ath11k_dbring_wmi_cfg_setup(struct ath11k *ar,
113*4882a593Smuzhiyun struct ath11k_dbring *ring,
114*4882a593Smuzhiyun enum wmi_direct_buffer_module id)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd param = {0};
117*4882a593Smuzhiyun int ret;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (id >= WMI_DIRECT_BUF_MAX)
120*4882a593Smuzhiyun return -EINVAL;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun param.pdev_id = DP_SW2HW_MACID(ring->pdev_id);
123*4882a593Smuzhiyun param.module_id = id;
124*4882a593Smuzhiyun param.base_paddr_lo = lower_32_bits(ring->refill_srng.paddr);
125*4882a593Smuzhiyun param.base_paddr_hi = upper_32_bits(ring->refill_srng.paddr);
126*4882a593Smuzhiyun param.head_idx_paddr_lo = lower_32_bits(ring->hp_addr);
127*4882a593Smuzhiyun param.head_idx_paddr_hi = upper_32_bits(ring->hp_addr);
128*4882a593Smuzhiyun param.tail_idx_paddr_lo = lower_32_bits(ring->tp_addr);
129*4882a593Smuzhiyun param.tail_idx_paddr_hi = upper_32_bits(ring->tp_addr);
130*4882a593Smuzhiyun param.num_elems = ring->bufs_max;
131*4882a593Smuzhiyun param.buf_size = ring->buf_sz;
132*4882a593Smuzhiyun param.num_resp_per_event = ring->num_resp_per_event;
133*4882a593Smuzhiyun param.event_timeout_ms = ring->event_timeout_ms;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun ret = ath11k_wmi_pdev_dma_ring_cfg(ar, ¶m);
136*4882a593Smuzhiyun if (ret) {
137*4882a593Smuzhiyun ath11k_warn(ar->ab, "failed to setup db ring cfg\n");
138*4882a593Smuzhiyun return ret;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
ath11k_dbring_set_cfg(struct ath11k * ar,struct ath11k_dbring * ring,u32 num_resp_per_event,u32 event_timeout_ms,int (* handler)(struct ath11k *,struct ath11k_dbring_data *))144*4882a593Smuzhiyun int ath11k_dbring_set_cfg(struct ath11k *ar, struct ath11k_dbring *ring,
145*4882a593Smuzhiyun u32 num_resp_per_event, u32 event_timeout_ms,
146*4882a593Smuzhiyun int (*handler)(struct ath11k *,
147*4882a593Smuzhiyun struct ath11k_dbring_data *))
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun if (WARN_ON(!ring))
150*4882a593Smuzhiyun return -EINVAL;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun ring->num_resp_per_event = num_resp_per_event;
153*4882a593Smuzhiyun ring->event_timeout_ms = event_timeout_ms;
154*4882a593Smuzhiyun ring->handler = handler;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
ath11k_dbring_buf_setup(struct ath11k * ar,struct ath11k_dbring * ring,struct ath11k_dbring_cap * db_cap)159*4882a593Smuzhiyun int ath11k_dbring_buf_setup(struct ath11k *ar,
160*4882a593Smuzhiyun struct ath11k_dbring *ring,
161*4882a593Smuzhiyun struct ath11k_dbring_cap *db_cap)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct ath11k_base *ab = ar->ab;
164*4882a593Smuzhiyun struct hal_srng *srng;
165*4882a593Smuzhiyun int ret;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
168*4882a593Smuzhiyun ring->bufs_max = ring->refill_srng.size /
169*4882a593Smuzhiyun ath11k_hal_srng_get_entrysize(ab, HAL_RXDMA_DIR_BUF);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun ring->buf_sz = db_cap->min_buf_sz;
172*4882a593Smuzhiyun ring->buf_align = db_cap->min_buf_align;
173*4882a593Smuzhiyun ring->pdev_id = db_cap->pdev_id;
174*4882a593Smuzhiyun ring->hp_addr = ath11k_hal_srng_get_hp_addr(ar->ab, srng);
175*4882a593Smuzhiyun ring->tp_addr = ath11k_hal_srng_get_tp_addr(ar->ab, srng);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ret = ath11k_dbring_fill_bufs(ar, ring);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
ath11k_dbring_srng_setup(struct ath11k * ar,struct ath11k_dbring * ring,int ring_num,int num_entries)182*4882a593Smuzhiyun int ath11k_dbring_srng_setup(struct ath11k *ar, struct ath11k_dbring *ring,
183*4882a593Smuzhiyun int ring_num, int num_entries)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun int ret;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun ret = ath11k_dp_srng_setup(ar->ab, &ring->refill_srng, HAL_RXDMA_DIR_BUF,
188*4882a593Smuzhiyun ring_num, ar->pdev_idx, num_entries);
189*4882a593Smuzhiyun if (ret < 0) {
190*4882a593Smuzhiyun ath11k_warn(ar->ab, "failed to setup srng: %d ring_id %d\n",
191*4882a593Smuzhiyun ret, ring_num);
192*4882a593Smuzhiyun goto err;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun err:
197*4882a593Smuzhiyun ath11k_dp_srng_cleanup(ar->ab, &ring->refill_srng);
198*4882a593Smuzhiyun return ret;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
ath11k_dbring_get_cap(struct ath11k_base * ab,u8 pdev_idx,enum wmi_direct_buffer_module id,struct ath11k_dbring_cap * db_cap)201*4882a593Smuzhiyun int ath11k_dbring_get_cap(struct ath11k_base *ab,
202*4882a593Smuzhiyun u8 pdev_idx,
203*4882a593Smuzhiyun enum wmi_direct_buffer_module id,
204*4882a593Smuzhiyun struct ath11k_dbring_cap *db_cap)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun int i;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (!ab->num_db_cap || !ab->db_caps)
209*4882a593Smuzhiyun return -ENOENT;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (id >= WMI_DIRECT_BUF_MAX)
212*4882a593Smuzhiyun return -EINVAL;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun for (i = 0; i < ab->num_db_cap; i++) {
215*4882a593Smuzhiyun if (pdev_idx == ab->db_caps[i].pdev_id &&
216*4882a593Smuzhiyun id == ab->db_caps[i].id) {
217*4882a593Smuzhiyun *db_cap = ab->db_caps[i];
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun return 0;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return -ENOENT;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
ath11k_dbring_buffer_release_event(struct ath11k_base * ab,struct ath11k_dbring_buf_release_event * ev)226*4882a593Smuzhiyun int ath11k_dbring_buffer_release_event(struct ath11k_base *ab,
227*4882a593Smuzhiyun struct ath11k_dbring_buf_release_event *ev)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct ath11k_dbring *ring;
230*4882a593Smuzhiyun struct hal_srng *srng;
231*4882a593Smuzhiyun struct ath11k *ar;
232*4882a593Smuzhiyun struct ath11k_dbring_element *buff;
233*4882a593Smuzhiyun struct ath11k_dbring_data handler_data;
234*4882a593Smuzhiyun struct ath11k_buffer_addr desc;
235*4882a593Smuzhiyun u8 *vaddr_unalign;
236*4882a593Smuzhiyun u32 num_entry, num_buff_reaped;
237*4882a593Smuzhiyun u8 pdev_idx, rbm;
238*4882a593Smuzhiyun u32 cookie;
239*4882a593Smuzhiyun int buf_id;
240*4882a593Smuzhiyun int size;
241*4882a593Smuzhiyun dma_addr_t paddr;
242*4882a593Smuzhiyun int ret = 0;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun pdev_idx = ev->fixed.pdev_id;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (pdev_idx >= ab->num_radios) {
247*4882a593Smuzhiyun ath11k_warn(ab, "Invalid pdev id %d\n", pdev_idx);
248*4882a593Smuzhiyun return -EINVAL;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (ev->fixed.num_buf_release_entry !=
252*4882a593Smuzhiyun ev->fixed.num_meta_data_entry) {
253*4882a593Smuzhiyun ath11k_warn(ab, "Buffer entry %d mismatch meta entry %d\n",
254*4882a593Smuzhiyun ev->fixed.num_buf_release_entry,
255*4882a593Smuzhiyun ev->fixed.num_meta_data_entry);
256*4882a593Smuzhiyun return -EINVAL;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun ar = ab->pdevs[pdev_idx].ar;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun rcu_read_lock();
262*4882a593Smuzhiyun if (!rcu_dereference(ab->pdevs_active[pdev_idx])) {
263*4882a593Smuzhiyun ret = -EINVAL;
264*4882a593Smuzhiyun goto rcu_unlock;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun switch (ev->fixed.module_id) {
268*4882a593Smuzhiyun case WMI_DIRECT_BUF_SPECTRAL:
269*4882a593Smuzhiyun ring = ath11k_spectral_get_dbring(ar);
270*4882a593Smuzhiyun break;
271*4882a593Smuzhiyun default:
272*4882a593Smuzhiyun ring = NULL;
273*4882a593Smuzhiyun ath11k_warn(ab, "Recv dma buffer release ev on unsupp module %d\n",
274*4882a593Smuzhiyun ev->fixed.module_id);
275*4882a593Smuzhiyun break;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun if (!ring) {
279*4882a593Smuzhiyun ret = -EINVAL;
280*4882a593Smuzhiyun goto rcu_unlock;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
284*4882a593Smuzhiyun num_entry = ev->fixed.num_buf_release_entry;
285*4882a593Smuzhiyun size = sizeof(*buff) + ring->buf_sz + ring->buf_align - 1;
286*4882a593Smuzhiyun num_buff_reaped = 0;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun spin_lock_bh(&srng->lock);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun while (num_buff_reaped < num_entry) {
291*4882a593Smuzhiyun desc.info0 = ev->buf_entry[num_buff_reaped].paddr_lo;
292*4882a593Smuzhiyun desc.info1 = ev->buf_entry[num_buff_reaped].paddr_hi;
293*4882a593Smuzhiyun handler_data.meta = ev->meta_data[num_buff_reaped];
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun num_buff_reaped++;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun ath11k_hal_rx_buf_addr_info_get(&desc, &paddr, &cookie, &rbm);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun spin_lock_bh(&ring->idr_lock);
302*4882a593Smuzhiyun buff = idr_find(&ring->bufs_idr, buf_id);
303*4882a593Smuzhiyun if (!buff) {
304*4882a593Smuzhiyun spin_unlock_bh(&ring->idr_lock);
305*4882a593Smuzhiyun continue;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun idr_remove(&ring->bufs_idr, buf_id);
308*4882a593Smuzhiyun spin_unlock_bh(&ring->idr_lock);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun dma_unmap_single(ab->dev, buff->paddr, ring->buf_sz,
311*4882a593Smuzhiyun DMA_FROM_DEVICE);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (ring->handler) {
314*4882a593Smuzhiyun vaddr_unalign = buff->payload;
315*4882a593Smuzhiyun handler_data.data = PTR_ALIGN(vaddr_unalign,
316*4882a593Smuzhiyun ring->buf_align);
317*4882a593Smuzhiyun handler_data.data_sz = ring->buf_sz;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun ring->handler(ar, &handler_data);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun memset(buff, 0, size);
323*4882a593Smuzhiyun ath11k_dbring_bufs_replenish(ar, ring, buff);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun spin_unlock_bh(&srng->lock);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun rcu_unlock:
329*4882a593Smuzhiyun rcu_read_unlock();
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return ret;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
ath11k_dbring_srng_cleanup(struct ath11k * ar,struct ath11k_dbring * ring)334*4882a593Smuzhiyun void ath11k_dbring_srng_cleanup(struct ath11k *ar, struct ath11k_dbring *ring)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun ath11k_dp_srng_cleanup(ar->ab, &ring->refill_srng);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
ath11k_dbring_buf_cleanup(struct ath11k * ar,struct ath11k_dbring * ring)339*4882a593Smuzhiyun void ath11k_dbring_buf_cleanup(struct ath11k *ar, struct ath11k_dbring *ring)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun struct ath11k_dbring_element *buff;
342*4882a593Smuzhiyun int buf_id;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun spin_lock_bh(&ring->idr_lock);
345*4882a593Smuzhiyun idr_for_each_entry(&ring->bufs_idr, buff, buf_id) {
346*4882a593Smuzhiyun idr_remove(&ring->bufs_idr, buf_id);
347*4882a593Smuzhiyun dma_unmap_single(ar->ab->dev, buff->paddr,
348*4882a593Smuzhiyun ring->buf_sz, DMA_FROM_DEVICE);
349*4882a593Smuzhiyun kfree(buff);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun idr_destroy(&ring->bufs_idr);
353*4882a593Smuzhiyun spin_unlock_bh(&ring->idr_lock);
354*4882a593Smuzhiyun }
355