1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015-2016 Qualcomm Atheros, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _SWAP_H_ 7*4882a593Smuzhiyun #define _SWAP_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX (512 * 1024) 10*4882a593Smuzhiyun #define ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ 12 11*4882a593Smuzhiyun #define ATH10K_SWAP_CODE_SEG_NUM_MAX 16 12*4882a593Smuzhiyun /* Currently only one swap segment is supported */ 13*4882a593Smuzhiyun #define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct ath10k_fw_file; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct ath10k_swap_code_seg_tlv { 18*4882a593Smuzhiyun __le32 address; 19*4882a593Smuzhiyun __le32 length; 20*4882a593Smuzhiyun u8 data[0]; 21*4882a593Smuzhiyun } __packed; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct ath10k_swap_code_seg_tail { 24*4882a593Smuzhiyun u8 magic_signature[ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ]; 25*4882a593Smuzhiyun __le32 bmi_write_addr; 26*4882a593Smuzhiyun } __packed; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun union ath10k_swap_code_seg_item { 29*4882a593Smuzhiyun struct ath10k_swap_code_seg_tlv tlv; 30*4882a593Smuzhiyun struct ath10k_swap_code_seg_tail tail; 31*4882a593Smuzhiyun } __packed; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct ath10k_swap_code_seg_hw_info { 34*4882a593Smuzhiyun /* Swap binary image size */ 35*4882a593Smuzhiyun __le32 swap_size; 36*4882a593Smuzhiyun __le32 num_segs; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Swap data size */ 39*4882a593Smuzhiyun __le32 size; 40*4882a593Smuzhiyun __le32 size_log2; 41*4882a593Smuzhiyun __le32 bus_addr[ATH10K_SWAP_CODE_SEG_NUM_MAX]; 42*4882a593Smuzhiyun __le64 reserved[ATH10K_SWAP_CODE_SEG_NUM_MAX]; 43*4882a593Smuzhiyun } __packed; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct ath10k_swap_code_seg_info { 46*4882a593Smuzhiyun struct ath10k_swap_code_seg_hw_info seg_hw_info; 47*4882a593Smuzhiyun void *virt_address[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED]; 48*4882a593Smuzhiyun u32 target_addr; 49*4882a593Smuzhiyun dma_addr_t paddr[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED]; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun int ath10k_swap_code_seg_configure(struct ath10k *ar, 53*4882a593Smuzhiyun const struct ath10k_fw_file *fw_file); 54*4882a593Smuzhiyun void ath10k_swap_code_seg_release(struct ath10k *ar, 55*4882a593Smuzhiyun struct ath10k_fw_file *fw_file); 56*4882a593Smuzhiyun int ath10k_swap_code_seg_init(struct ath10k *ar, 57*4882a593Smuzhiyun struct ath10k_fw_file *fw_file); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif 60