1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _SNOC_H_ 7*4882a593Smuzhiyun #define _SNOC_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "hw.h" 10*4882a593Smuzhiyun #include "ce.h" 11*4882a593Smuzhiyun #include "qmi.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct ath10k_snoc_drv_priv { 14*4882a593Smuzhiyun enum ath10k_hw_rev hw_rev; 15*4882a593Smuzhiyun u64 dma_mask; 16*4882a593Smuzhiyun u32 msa_size; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct snoc_state { 20*4882a593Smuzhiyun u32 pipe_cfg_addr; 21*4882a593Smuzhiyun u32 svc_to_pipe_map; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct ath10k_snoc_pipe { 25*4882a593Smuzhiyun struct ath10k_ce_pipe *ce_hdl; 26*4882a593Smuzhiyun u8 pipe_num; 27*4882a593Smuzhiyun struct ath10k *hif_ce_state; 28*4882a593Smuzhiyun size_t buf_sz; 29*4882a593Smuzhiyun /* protect ce info */ 30*4882a593Smuzhiyun spinlock_t pipe_lock; 31*4882a593Smuzhiyun struct ath10k_snoc *ar_snoc; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct ath10k_snoc_target_info { 35*4882a593Smuzhiyun u32 target_version; 36*4882a593Smuzhiyun u32 target_type; 37*4882a593Smuzhiyun u32 target_revision; 38*4882a593Smuzhiyun u32 soc_version; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct ath10k_snoc_ce_irq { 42*4882a593Smuzhiyun u32 irq_line; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum ath10k_snoc_flags { 46*4882a593Smuzhiyun ATH10K_SNOC_FLAG_REGISTERED, 47*4882a593Smuzhiyun ATH10K_SNOC_FLAG_UNREGISTERING, 48*4882a593Smuzhiyun ATH10K_SNOC_FLAG_RECOVERY, 49*4882a593Smuzhiyun ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct clk_bulk_data; 53*4882a593Smuzhiyun struct regulator_bulk_data; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct ath10k_snoc { 56*4882a593Smuzhiyun struct platform_device *dev; 57*4882a593Smuzhiyun struct ath10k *ar; 58*4882a593Smuzhiyun unsigned int use_tz; 59*4882a593Smuzhiyun struct ath10k_firmware { 60*4882a593Smuzhiyun struct device *dev; 61*4882a593Smuzhiyun dma_addr_t fw_start_addr; 62*4882a593Smuzhiyun struct iommu_domain *iommu_domain; 63*4882a593Smuzhiyun size_t mapped_mem_size; 64*4882a593Smuzhiyun } fw; 65*4882a593Smuzhiyun void __iomem *mem; 66*4882a593Smuzhiyun dma_addr_t mem_pa; 67*4882a593Smuzhiyun struct ath10k_snoc_target_info target_info; 68*4882a593Smuzhiyun size_t mem_len; 69*4882a593Smuzhiyun struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX]; 70*4882a593Smuzhiyun struct ath10k_snoc_ce_irq ce_irqs[CE_COUNT_MAX]; 71*4882a593Smuzhiyun struct ath10k_ce ce; 72*4882a593Smuzhiyun struct timer_list rx_post_retry; 73*4882a593Smuzhiyun struct regulator_bulk_data *vregs; 74*4882a593Smuzhiyun size_t num_vregs; 75*4882a593Smuzhiyun struct clk_bulk_data *clks; 76*4882a593Smuzhiyun size_t num_clks; 77*4882a593Smuzhiyun struct ath10k_qmi *qmi; 78*4882a593Smuzhiyun unsigned long flags; 79*4882a593Smuzhiyun bool xo_cal_supported; 80*4882a593Smuzhiyun u32 xo_cal_data; 81*4882a593Smuzhiyun DECLARE_BITMAP(pending_ce_irqs, CE_COUNT_MAX); 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun ath10k_snoc_priv(struct ath10k * ar)84*4882a593Smuzhiyunstatic inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar) 85*4882a593Smuzhiyun { 86*4882a593Smuzhiyun return (struct ath10k_snoc *)ar->drv_priv; 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type); 90*4882a593Smuzhiyun void ath10k_snoc_fw_crashed_dump(struct ath10k *ar); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* _SNOC_H_ */ 93