1*4882a593Smuzhiyun /* SPDX-License-Identifier: ISC */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _ATH10K_QMI_H_ 6*4882a593Smuzhiyun #define _ATH10K_QMI_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/soc/qcom/qmi.h> 9*4882a593Smuzhiyun #include <linux/qrtr.h> 10*4882a593Smuzhiyun #include "qmi_wlfw_v01.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MAX_NUM_MEMORY_REGIONS 2 13*4882a593Smuzhiyun #define MAX_TIMESTAMP_LEN 32 14*4882a593Smuzhiyun #define MAX_BUILD_ID_LEN 128 15*4882a593Smuzhiyun #define MAX_NUM_CAL_V01 5 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun enum ath10k_qmi_driver_event_type { 18*4882a593Smuzhiyun ATH10K_QMI_EVENT_SERVER_ARRIVE, 19*4882a593Smuzhiyun ATH10K_QMI_EVENT_SERVER_EXIT, 20*4882a593Smuzhiyun ATH10K_QMI_EVENT_FW_READY_IND, 21*4882a593Smuzhiyun ATH10K_QMI_EVENT_FW_DOWN_IND, 22*4882a593Smuzhiyun ATH10K_QMI_EVENT_MSA_READY_IND, 23*4882a593Smuzhiyun ATH10K_QMI_EVENT_MAX, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct ath10k_msa_mem_info { 27*4882a593Smuzhiyun phys_addr_t addr; 28*4882a593Smuzhiyun u32 size; 29*4882a593Smuzhiyun bool secure; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct ath10k_qmi_chip_info { 33*4882a593Smuzhiyun u32 chip_id; 34*4882a593Smuzhiyun u32 chip_family; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct ath10k_qmi_board_info { 38*4882a593Smuzhiyun u32 board_id; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct ath10k_qmi_soc_info { 42*4882a593Smuzhiyun u32 soc_id; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct ath10k_qmi_cal_data { 46*4882a593Smuzhiyun u32 cal_id; 47*4882a593Smuzhiyun u32 total_size; 48*4882a593Smuzhiyun u8 *data; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct ath10k_tgt_pipe_cfg { 52*4882a593Smuzhiyun __le32 pipe_num; 53*4882a593Smuzhiyun __le32 pipe_dir; 54*4882a593Smuzhiyun __le32 nentries; 55*4882a593Smuzhiyun __le32 nbytes_max; 56*4882a593Smuzhiyun __le32 flags; 57*4882a593Smuzhiyun __le32 reserved; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct ath10k_svc_pipe_cfg { 61*4882a593Smuzhiyun __le32 service_id; 62*4882a593Smuzhiyun __le32 pipe_dir; 63*4882a593Smuzhiyun __le32 pipe_num; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct ath10k_shadow_reg_cfg { 67*4882a593Smuzhiyun __le16 ce_id; 68*4882a593Smuzhiyun __le16 reg_offset; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct ath10k_qmi_wlan_enable_cfg { 72*4882a593Smuzhiyun u32 num_ce_tgt_cfg; 73*4882a593Smuzhiyun struct ath10k_tgt_pipe_cfg *ce_tgt_cfg; 74*4882a593Smuzhiyun u32 num_ce_svc_pipe_cfg; 75*4882a593Smuzhiyun struct ath10k_svc_pipe_cfg *ce_svc_cfg; 76*4882a593Smuzhiyun u32 num_shadow_reg_cfg; 77*4882a593Smuzhiyun struct ath10k_shadow_reg_cfg *shadow_reg_cfg; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct ath10k_qmi_driver_event { 81*4882a593Smuzhiyun struct list_head list; 82*4882a593Smuzhiyun enum ath10k_qmi_driver_event_type type; 83*4882a593Smuzhiyun void *data; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun enum ath10k_qmi_state { 87*4882a593Smuzhiyun ATH10K_QMI_STATE_INIT_DONE, 88*4882a593Smuzhiyun ATH10K_QMI_STATE_DEINIT, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun struct ath10k_qmi { 92*4882a593Smuzhiyun struct ath10k *ar; 93*4882a593Smuzhiyun struct qmi_handle qmi_hdl; 94*4882a593Smuzhiyun struct sockaddr_qrtr sq; 95*4882a593Smuzhiyun struct work_struct event_work; 96*4882a593Smuzhiyun struct workqueue_struct *event_wq; 97*4882a593Smuzhiyun struct list_head event_list; 98*4882a593Smuzhiyun spinlock_t event_lock; /* spinlock for qmi event list */ 99*4882a593Smuzhiyun u32 nr_mem_region; 100*4882a593Smuzhiyun struct ath10k_msa_mem_info mem_region[MAX_NUM_MEMORY_REGIONS]; 101*4882a593Smuzhiyun struct ath10k_qmi_chip_info chip_info; 102*4882a593Smuzhiyun struct ath10k_qmi_board_info board_info; 103*4882a593Smuzhiyun struct ath10k_qmi_soc_info soc_info; 104*4882a593Smuzhiyun char fw_build_id[MAX_BUILD_ID_LEN + 1]; 105*4882a593Smuzhiyun u32 fw_version; 106*4882a593Smuzhiyun bool fw_ready; 107*4882a593Smuzhiyun char fw_build_timestamp[MAX_TIMESTAMP_LEN + 1]; 108*4882a593Smuzhiyun struct ath10k_qmi_cal_data cal_data[MAX_NUM_CAL_V01]; 109*4882a593Smuzhiyun bool msa_fixed_perm; 110*4882a593Smuzhiyun enum ath10k_qmi_state state; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun int ath10k_qmi_wlan_enable(struct ath10k *ar, 114*4882a593Smuzhiyun struct ath10k_qmi_wlan_enable_cfg *config, 115*4882a593Smuzhiyun enum wlfw_driver_mode_enum_v01 mode, 116*4882a593Smuzhiyun const char *version); 117*4882a593Smuzhiyun int ath10k_qmi_wlan_disable(struct ath10k *ar); 118*4882a593Smuzhiyun int ath10k_qmi_init(struct ath10k *ar, u32 msa_size); 119*4882a593Smuzhiyun int ath10k_qmi_deinit(struct ath10k *ar); 120*4882a593Smuzhiyun int ath10k_qmi_set_fw_log_mode(struct ath10k *ar, u8 fw_log_mode); 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* ATH10K_QMI_H */ 123