1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drivers/tdm/line_ctrl/slic_ds26522.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Zhao Qiang <B45475@freescale.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define DS26522_RF_ADDR_START 0x00 11*4882a593Smuzhiyun #define DS26522_RF_ADDR_END 0xef 12*4882a593Smuzhiyun #define DS26522_GLB_ADDR_START 0xf0 13*4882a593Smuzhiyun #define DS26522_GLB_ADDR_END 0xff 14*4882a593Smuzhiyun #define DS26522_TF_ADDR_START 0x100 15*4882a593Smuzhiyun #define DS26522_TF_ADDR_END 0x1ef 16*4882a593Smuzhiyun #define DS26522_LIU_ADDR_START 0x1000 17*4882a593Smuzhiyun #define DS26522_LIU_ADDR_END 0x101f 18*4882a593Smuzhiyun #define DS26522_TEST_ADDR_START 0x1008 19*4882a593Smuzhiyun #define DS26522_TEST_ADDR_END 0x101f 20*4882a593Smuzhiyun #define DS26522_BERT_ADDR_START 0x1100 21*4882a593Smuzhiyun #define DS26522_BERT_ADDR_END 0x110f 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define DS26522_RMMR_ADDR 0x80 24*4882a593Smuzhiyun #define DS26522_RCR1_ADDR 0x81 25*4882a593Smuzhiyun #define DS26522_RCR3_ADDR 0x83 26*4882a593Smuzhiyun #define DS26522_RIOCR_ADDR 0x84 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define DS26522_GTCR1_ADDR 0xf0 29*4882a593Smuzhiyun #define DS26522_GFCR_ADDR 0xf1 30*4882a593Smuzhiyun #define DS26522_GTCR2_ADDR 0xf2 31*4882a593Smuzhiyun #define DS26522_GTCCR_ADDR 0xf3 32*4882a593Smuzhiyun #define DS26522_GLSRR_ADDR 0xf5 33*4882a593Smuzhiyun #define DS26522_GFSRR_ADDR 0xf6 34*4882a593Smuzhiyun #define DS26522_IDR_ADDR 0xf8 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define DS26522_E1TAF_ADDR 0x164 37*4882a593Smuzhiyun #define DS26522_E1TNAF_ADDR 0x165 38*4882a593Smuzhiyun #define DS26522_TMMR_ADDR 0x180 39*4882a593Smuzhiyun #define DS26522_TCR1_ADDR 0x181 40*4882a593Smuzhiyun #define DS26522_TIOCR_ADDR 0x184 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define DS26522_LTRCR_ADDR 0x1000 43*4882a593Smuzhiyun #define DS26522_LTITSR_ADDR 0x1001 44*4882a593Smuzhiyun #define DS26522_LMCR_ADDR 0x1002 45*4882a593Smuzhiyun #define DS26522_LRISMR_ADDR 0x1007 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MAX_NUM_OF_CHANNELS 8 48*4882a593Smuzhiyun #define PQ_MDS_8E1T1_BRD_REV 0x00 49*4882a593Smuzhiyun #define PQ_MDS_8E1T1_PLD_REV 0x00 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0 52*4882a593Smuzhiyun #define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08 53*4882a593Smuzhiyun #define DS26522_GTCCR_FREQSEL_1544KHZ 0x04 54*4882a593Smuzhiyun #define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00 55*4882a593Smuzhiyun #define DS26522_GTCCR_FREQSEL_2048KHZ 0x00 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define DS26522_GFCR_BPCLK_2048KHZ 0x00 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define DS26522_GTCR2_TSSYNCOUT 0x02 60*4882a593Smuzhiyun #define DS26522_GTCR1 0x00 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define DS26522_GFSRR_RESET 0x01 63*4882a593Smuzhiyun #define DS26522_GFSRR_NORMAL 0x00 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define DS26522_GLSRR_RESET 0x01 66*4882a593Smuzhiyun #define DS26522_GLSRR_NORMAL 0x00 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define DS26522_RMMR_SFTRST 0x02 69*4882a593Smuzhiyun #define DS26522_RMMR_FRM_EN 0x80 70*4882a593Smuzhiyun #define DS26522_RMMR_INIT_DONE 0x40 71*4882a593Smuzhiyun #define DS26522_RMMR_T1 0x00 72*4882a593Smuzhiyun #define DS26522_RMMR_E1 0x01 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define DS26522_E1TAF_DEFAULT 0x1b 75*4882a593Smuzhiyun #define DS26522_E1TNAF_DEFAULT 0x40 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define DS26522_TMMR_SFTRST 0x02 78*4882a593Smuzhiyun #define DS26522_TMMR_FRM_EN 0x80 79*4882a593Smuzhiyun #define DS26522_TMMR_INIT_DONE 0x40 80*4882a593Smuzhiyun #define DS26522_TMMR_T1 0x00 81*4882a593Smuzhiyun #define DS26522_TMMR_E1 0x01 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define DS26522_RCR1_T1_SYNCT 0x80 84*4882a593Smuzhiyun #define DS26522_RCR1_T1_RB8ZS 0x40 85*4882a593Smuzhiyun #define DS26522_RCR1_T1_SYNCC 0x08 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define DS26522_RCR1_E1_HDB3 0x40 88*4882a593Smuzhiyun #define DS26522_RCR1_E1_CCS 0x20 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define DS26522_RIOCR_1544KHZ 0x00 91*4882a593Smuzhiyun #define DS26522_RIOCR_2048KHZ 0x10 92*4882a593Smuzhiyun #define DS26522_RIOCR_RSIO_OUT 0x00 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define DS26522_RCR3_FLB 0x01 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define DS26522_TIOCR_1544KHZ 0x00 97*4882a593Smuzhiyun #define DS26522_TIOCR_2048KHZ 0x10 98*4882a593Smuzhiyun #define DS26522_TIOCR_TSIO_OUT 0x04 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define DS26522_TCR1_TB8ZS 0x04 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define DS26522_LTRCR_T1 0x02 103*4882a593Smuzhiyun #define DS26522_LTRCR_E1 0x00 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define DS26522_LTITSR_TLIS_75OHM 0x00 106*4882a593Smuzhiyun #define DS26522_LTITSR_LBOS_75OHM 0x00 107*4882a593Smuzhiyun #define DS26522_LTITSR_TLIS_100OHM 0x10 108*4882a593Smuzhiyun #define DS26522_LTITSR_TLIS_0DB_CSU 0x00 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define DS26522_LRISMR_75OHM 0x00 111*4882a593Smuzhiyun #define DS26522_LRISMR_100OHM 0x10 112*4882a593Smuzhiyun #define DS26522_LRISMR_MAX 0x03 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define DS26522_LMCR_TE 0x01 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun enum line_rate { 117*4882a593Smuzhiyun LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */ 118*4882a593Smuzhiyun LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */ 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun enum tdm_trans_mode { 122*4882a593Smuzhiyun NORMAL = 0, 123*4882a593Smuzhiyun FRAMER_LB 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun enum card_support_type { 127*4882a593Smuzhiyun LM_CARD = 0, 128*4882a593Smuzhiyun DS26522_CARD, 129*4882a593Smuzhiyun NO_CARD 130*4882a593Smuzhiyun }; 131