1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/net/wan/slic_ds26522.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author:Zhao Qiang<qiang.zhao@nxp.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bitrev.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/sched.h>
15*4882a593Smuzhiyun #include <linux/kthread.h>
16*4882a593Smuzhiyun #include <linux/spi/spi.h>
17*4882a593Smuzhiyun #include <linux/wait.h>
18*4882a593Smuzhiyun #include <linux/param.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/of_address.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun #include "slic_ds26522.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define SLIC_TRANS_LEN 1
26*4882a593Smuzhiyun #define SLIC_TWO_LEN 2
27*4882a593Smuzhiyun #define SLIC_THREE_LEN 3
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static struct spi_device *g_spi;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun MODULE_LICENSE("GPL");
32*4882a593Smuzhiyun MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>");
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* the read/write format of address is
35*4882a593Smuzhiyun * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x
36*4882a593Smuzhiyun */
slic_write(struct spi_device * spi,u16 addr,u8 data)37*4882a593Smuzhiyun static void slic_write(struct spi_device *spi, u16 addr,
38*4882a593Smuzhiyun u8 data)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun u8 temp[3];
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun addr = bitrev16(addr) >> 1;
43*4882a593Smuzhiyun data = bitrev8(data);
44*4882a593Smuzhiyun temp[0] = (u8)((addr >> 8) & 0x7f);
45*4882a593Smuzhiyun temp[1] = (u8)(addr & 0xfe);
46*4882a593Smuzhiyun temp[2] = data;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* write spi addr and value */
49*4882a593Smuzhiyun spi_write(spi, &temp[0], SLIC_THREE_LEN);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
slic_read(struct spi_device * spi,u16 addr)52*4882a593Smuzhiyun static u8 slic_read(struct spi_device *spi, u16 addr)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u8 temp[2];
55*4882a593Smuzhiyun u8 data;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun addr = bitrev16(addr) >> 1;
58*4882a593Smuzhiyun temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80);
59*4882a593Smuzhiyun temp[1] = (u8)(addr & 0xfe);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data,
62*4882a593Smuzhiyun SLIC_TRANS_LEN);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun data = bitrev8(data);
65*4882a593Smuzhiyun return data;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
get_slic_product_code(struct spi_device * spi)68*4882a593Smuzhiyun static bool get_slic_product_code(struct spi_device *spi)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun u8 device_id;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun device_id = slic_read(spi, DS26522_IDR_ADDR);
73*4882a593Smuzhiyun if ((device_id & 0xf8) == 0x68)
74*4882a593Smuzhiyun return true;
75*4882a593Smuzhiyun else
76*4882a593Smuzhiyun return false;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
ds26522_e1_spec_config(struct spi_device * spi)79*4882a593Smuzhiyun static void ds26522_e1_spec_config(struct spi_device *spi)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun /* Receive E1 Mode, Framer Disabled */
82*4882a593Smuzhiyun slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Transmit E1 Mode, Framer Disable */
85*4882a593Smuzhiyun slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Receive E1 Mode Framer Enable */
88*4882a593Smuzhiyun slic_write(spi, DS26522_RMMR_ADDR,
89*4882a593Smuzhiyun slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Transmit E1 Mode Framer Enable */
92*4882a593Smuzhiyun slic_write(spi, DS26522_TMMR_ADDR,
93*4882a593Smuzhiyun slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* RCR1, receive E1 B8zs & ESF */
96*4882a593Smuzhiyun slic_write(spi, DS26522_RCR1_ADDR,
97*4882a593Smuzhiyun DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* RSYSCLK=2.048MHz, RSYNC-Output */
100*4882a593Smuzhiyun slic_write(spi, DS26522_RIOCR_ADDR,
101*4882a593Smuzhiyun DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* TCR1 Transmit E1 b8zs */
104*4882a593Smuzhiyun slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* TSYSCLK=2.048MHz, TSYNC-Output */
107*4882a593Smuzhiyun slic_write(spi, DS26522_TIOCR_ADDR,
108*4882a593Smuzhiyun DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* Set E1TAF */
111*4882a593Smuzhiyun slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Set E1TNAF register */
114*4882a593Smuzhiyun slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* Receive E1 Mode Framer Enable & init Done */
117*4882a593Smuzhiyun slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
118*4882a593Smuzhiyun DS26522_RMMR_INIT_DONE);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Transmit E1 Mode Framer Enable & init Done */
121*4882a593Smuzhiyun slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
122*4882a593Smuzhiyun DS26522_TMMR_INIT_DONE);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Configure LIU E1 mode */
125*4882a593Smuzhiyun slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */
128*4882a593Smuzhiyun slic_write(spi, DS26522_LTITSR_ADDR,
129*4882a593Smuzhiyun DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */
132*4882a593Smuzhiyun slic_write(spi, DS26522_LRISMR_ADDR,
133*4882a593Smuzhiyun DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* Enable Transmit output */
136*4882a593Smuzhiyun slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
slic_ds26522_init_configure(struct spi_device * spi)139*4882a593Smuzhiyun static int slic_ds26522_init_configure(struct spi_device *spi)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun u16 addr;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* set clock */
144*4882a593Smuzhiyun slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
145*4882a593Smuzhiyun DS26522_GTCCR_BFREQSEL_2048KHZ |
146*4882a593Smuzhiyun DS26522_GTCCR_FREQSEL_2048KHZ);
147*4882a593Smuzhiyun slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
148*4882a593Smuzhiyun slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* set gtcr */
151*4882a593Smuzhiyun slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Global LIU Software Reset Register */
154*4882a593Smuzhiyun slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Global Framer and BERT Software Reset Register */
157*4882a593Smuzhiyun slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun usleep_range(100, 120);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
162*4882a593Smuzhiyun slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun /* Perform RX/TX SRESET,Reset receiver */
165*4882a593Smuzhiyun slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* Reset tranceiver */
168*4882a593Smuzhiyun slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun usleep_range(100, 120);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* Zero all Framer Registers */
173*4882a593Smuzhiyun for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END;
174*4882a593Smuzhiyun addr++)
175*4882a593Smuzhiyun slic_write(spi, addr, 0);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END;
178*4882a593Smuzhiyun addr++)
179*4882a593Smuzhiyun slic_write(spi, addr, 0);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END;
182*4882a593Smuzhiyun addr++)
183*4882a593Smuzhiyun slic_write(spi, addr, 0);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END;
186*4882a593Smuzhiyun addr++)
187*4882a593Smuzhiyun slic_write(spi, addr, 0);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* setup ds26522 for E1 specification */
190*4882a593Smuzhiyun ds26522_e1_spec_config(spi);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun return 0;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
slic_ds26522_remove(struct spi_device * spi)197*4882a593Smuzhiyun static int slic_ds26522_remove(struct spi_device *spi)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun pr_info("DS26522 module uninstalled\n");
200*4882a593Smuzhiyun return 0;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
slic_ds26522_probe(struct spi_device * spi)203*4882a593Smuzhiyun static int slic_ds26522_probe(struct spi_device *spi)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun int ret = 0;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun g_spi = spi;
208*4882a593Smuzhiyun spi->bits_per_word = 8;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun if (!get_slic_product_code(spi))
211*4882a593Smuzhiyun return ret;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun ret = slic_ds26522_init_configure(spi);
214*4882a593Smuzhiyun if (ret == 0)
215*4882a593Smuzhiyun pr_info("DS26522 cs%d configured\n", spi->chip_select);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun static const struct spi_device_id slic_ds26522_id[] = {
221*4882a593Smuzhiyun { .name = "ds26522" },
222*4882a593Smuzhiyun { /* sentinel */ },
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, slic_ds26522_id);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static const struct of_device_id slic_ds26522_match[] = {
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun .compatible = "maxim,ds26522",
229*4882a593Smuzhiyun },
230*4882a593Smuzhiyun {},
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, slic_ds26522_match);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun static struct spi_driver slic_ds26522_driver = {
235*4882a593Smuzhiyun .driver = {
236*4882a593Smuzhiyun .name = "ds26522",
237*4882a593Smuzhiyun .bus = &spi_bus_type,
238*4882a593Smuzhiyun .of_match_table = slic_ds26522_match,
239*4882a593Smuzhiyun },
240*4882a593Smuzhiyun .probe = slic_ds26522_probe,
241*4882a593Smuzhiyun .remove = slic_ds26522_remove,
242*4882a593Smuzhiyun .id_table = slic_ds26522_id,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun module_spi_driver(slic_ds26522_driver);
246