1*4882a593Smuzhiyun /* sbni.h: definitions for a Granch SBNI12 driver, version 5.0.0 2*4882a593Smuzhiyun * Written 2001 Denis I.Timofeev (timofeev@granch.ru) 3*4882a593Smuzhiyun * This file is distributed under the GNU GPL 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef SBNI_H 7*4882a593Smuzhiyun #define SBNI_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifdef SBNI_DEBUG 10*4882a593Smuzhiyun #define DP( A ) A 11*4882a593Smuzhiyun #else 12*4882a593Smuzhiyun #define DP( A ) 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* We don't have official vendor id yet... */ 17*4882a593Smuzhiyun #define SBNI_PCI_VENDOR 0x55 18*4882a593Smuzhiyun #define SBNI_PCI_DEVICE 0x9f 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define ISA_MODE 0x00 21*4882a593Smuzhiyun #define PCI_MODE 0x01 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SBNI_IO_EXTENT 4 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enum sbni_reg { 26*4882a593Smuzhiyun CSR0 = 0, 27*4882a593Smuzhiyun CSR1 = 1, 28*4882a593Smuzhiyun DAT = 2 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* CSR0 mapping */ 32*4882a593Smuzhiyun enum { 33*4882a593Smuzhiyun BU_EMP = 0x02, 34*4882a593Smuzhiyun RC_CHK = 0x04, 35*4882a593Smuzhiyun CT_ZER = 0x08, 36*4882a593Smuzhiyun TR_REQ = 0x10, 37*4882a593Smuzhiyun TR_RDY = 0x20, 38*4882a593Smuzhiyun EN_INT = 0x40, 39*4882a593Smuzhiyun RC_RDY = 0x80 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* CSR1 mapping */ 44*4882a593Smuzhiyun #define PR_RES 0x80 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct sbni_csr1 { 47*4882a593Smuzhiyun #ifdef __LITTLE_ENDIAN_BITFIELD 48*4882a593Smuzhiyun u8 rxl : 5; 49*4882a593Smuzhiyun u8 rate : 2; 50*4882a593Smuzhiyun u8 : 1; 51*4882a593Smuzhiyun #else 52*4882a593Smuzhiyun u8 : 1; 53*4882a593Smuzhiyun u8 rate : 2; 54*4882a593Smuzhiyun u8 rxl : 5; 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* fields in frame header */ 59*4882a593Smuzhiyun #define FRAME_ACK_MASK (unsigned short)0x7000 60*4882a593Smuzhiyun #define FRAME_LEN_MASK (unsigned short)0x03FF 61*4882a593Smuzhiyun #define FRAME_FIRST (unsigned short)0x8000 62*4882a593Smuzhiyun #define FRAME_RETRY (unsigned short)0x0800 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define FRAME_SENT_BAD (unsigned short)0x4000 65*4882a593Smuzhiyun #define FRAME_SENT_OK (unsigned short)0x3000 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* state flags */ 69*4882a593Smuzhiyun enum { 70*4882a593Smuzhiyun FL_WAIT_ACK = 0x01, 71*4882a593Smuzhiyun FL_NEED_RESEND = 0x02, 72*4882a593Smuzhiyun FL_PREV_OK = 0x04, 73*4882a593Smuzhiyun FL_SLOW_MODE = 0x08, 74*4882a593Smuzhiyun FL_SECONDARY = 0x10, 75*4882a593Smuzhiyun #ifdef CONFIG_SBNI_MULTILINE 76*4882a593Smuzhiyun FL_SLAVE = 0x20, 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun FL_LINE_DOWN = 0x40 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun enum { 83*4882a593Smuzhiyun DEFAULT_IOBASEADDR = 0x210, 84*4882a593Smuzhiyun DEFAULT_INTERRUPTNUMBER = 5, 85*4882a593Smuzhiyun DEFAULT_RATE = 0, 86*4882a593Smuzhiyun DEFAULT_FRAME_LEN = 1012 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define DEF_RXL_DELTA -1 90*4882a593Smuzhiyun #define DEF_RXL 0xf 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define SBNI_SIG 0x5a 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define SBNI_MIN_LEN 60 /* Shortest Ethernet frame without FCS */ 95*4882a593Smuzhiyun #define SBNI_MAX_FRAME 1023 96*4882a593Smuzhiyun #define ETHER_MAX_LEN 1518 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define SBNI_TIMEOUT (HZ/10) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define TR_ERROR_COUNT 32 101*4882a593Smuzhiyun #define CHANGE_LEVEL_START_TICKS 4 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define SBNI_MAX_NUM_CARDS 16 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* internal SBNI-specific statistics */ 106*4882a593Smuzhiyun struct sbni_in_stats { 107*4882a593Smuzhiyun u32 all_rx_number; 108*4882a593Smuzhiyun u32 bad_rx_number; 109*4882a593Smuzhiyun u32 timeout_number; 110*4882a593Smuzhiyun u32 all_tx_number; 111*4882a593Smuzhiyun u32 resend_tx_number; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* SBNI ioctl params */ 115*4882a593Smuzhiyun #define SIOCDEVGETINSTATS SIOCDEVPRIVATE 116*4882a593Smuzhiyun #define SIOCDEVRESINSTATS SIOCDEVPRIVATE+1 117*4882a593Smuzhiyun #define SIOCDEVGHWSTATE SIOCDEVPRIVATE+2 118*4882a593Smuzhiyun #define SIOCDEVSHWSTATE SIOCDEVPRIVATE+3 119*4882a593Smuzhiyun #define SIOCDEVENSLAVE SIOCDEVPRIVATE+4 120*4882a593Smuzhiyun #define SIOCDEVEMANSIPATE SIOCDEVPRIVATE+5 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* data packet for SIOCDEVGHWSTATE/SIOCDEVSHWSTATE ioctl requests */ 124*4882a593Smuzhiyun struct sbni_flags { 125*4882a593Smuzhiyun u32 rxl : 4; 126*4882a593Smuzhiyun u32 rate : 2; 127*4882a593Smuzhiyun u32 fixed_rxl : 1; 128*4882a593Smuzhiyun u32 slow_mode : 1; 129*4882a593Smuzhiyun u32 mac_addr : 24; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* 133*4882a593Smuzhiyun * CRC-32 stuff 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun #define CRC32(c,crc) (crc32tab[((size_t)(crc) ^ (c)) & 0xff] ^ (((crc) >> 8) & 0x00FFFFFF)) 136*4882a593Smuzhiyun /* CRC generator 0xEDB88320 */ 137*4882a593Smuzhiyun /* CRC remainder 0x2144DF1C */ 138*4882a593Smuzhiyun /* CRC initial value 0x00000000 */ 139*4882a593Smuzhiyun #define CRC32_REMAINDER 0x2144DF1C 140*4882a593Smuzhiyun #define CRC32_INITIAL 0x00000000 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #ifndef __initdata 143*4882a593Smuzhiyun #define __initdata 144*4882a593Smuzhiyun #endif 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif 147*4882a593Smuzhiyun 148