1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* Freescale QUICC Engine HDLC Device Driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _UCC_HDLC_H_ 8*4882a593Smuzhiyun #define _UCC_HDLC_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/kernel.h> 11*4882a593Smuzhiyun #include <linux/list.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <soc/fsl/qe/immap_qe.h> 14*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <soc/fsl/qe/ucc.h> 17*4882a593Smuzhiyun #include <soc/fsl/qe/ucc_fast.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* UCC HDLC event register */ 20*4882a593Smuzhiyun #define UCCE_HDLC_RX_EVENTS \ 21*4882a593Smuzhiyun (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY) 22*4882a593Smuzhiyun #define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct ucc_hdlc_param { 25*4882a593Smuzhiyun __be16 riptr; 26*4882a593Smuzhiyun __be16 tiptr; 27*4882a593Smuzhiyun __be16 res0; 28*4882a593Smuzhiyun __be16 mrblr; 29*4882a593Smuzhiyun __be32 rstate; 30*4882a593Smuzhiyun __be32 rbase; 31*4882a593Smuzhiyun __be16 rbdstat; 32*4882a593Smuzhiyun __be16 rbdlen; 33*4882a593Smuzhiyun __be32 rdptr; 34*4882a593Smuzhiyun __be32 tstate; 35*4882a593Smuzhiyun __be32 tbase; 36*4882a593Smuzhiyun __be16 tbdstat; 37*4882a593Smuzhiyun __be16 tbdlen; 38*4882a593Smuzhiyun __be32 tdptr; 39*4882a593Smuzhiyun __be32 rbptr; 40*4882a593Smuzhiyun __be32 tbptr; 41*4882a593Smuzhiyun __be32 rcrc; 42*4882a593Smuzhiyun __be32 res1; 43*4882a593Smuzhiyun __be32 tcrc; 44*4882a593Smuzhiyun __be32 res2; 45*4882a593Smuzhiyun __be32 res3; 46*4882a593Smuzhiyun __be32 c_mask; 47*4882a593Smuzhiyun __be32 c_pres; 48*4882a593Smuzhiyun __be16 disfc; 49*4882a593Smuzhiyun __be16 crcec; 50*4882a593Smuzhiyun __be16 abtsc; 51*4882a593Smuzhiyun __be16 nmarc; 52*4882a593Smuzhiyun __be32 max_cnt; 53*4882a593Smuzhiyun __be16 mflr; 54*4882a593Smuzhiyun __be16 rfthr; 55*4882a593Smuzhiyun __be16 rfcnt; 56*4882a593Smuzhiyun __be16 hmask; 57*4882a593Smuzhiyun __be16 haddr1; 58*4882a593Smuzhiyun __be16 haddr2; 59*4882a593Smuzhiyun __be16 haddr3; 60*4882a593Smuzhiyun __be16 haddr4; 61*4882a593Smuzhiyun __be16 ts_tmp; 62*4882a593Smuzhiyun __be16 tmp_mb; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct ucc_hdlc_private { 66*4882a593Smuzhiyun struct ucc_tdm *utdm; 67*4882a593Smuzhiyun struct ucc_tdm_info *ut_info; 68*4882a593Smuzhiyun struct ucc_fast_private *uccf; 69*4882a593Smuzhiyun struct device *dev; 70*4882a593Smuzhiyun struct net_device *ndev; 71*4882a593Smuzhiyun struct napi_struct napi; 72*4882a593Smuzhiyun struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */ 73*4882a593Smuzhiyun struct ucc_hdlc_param __iomem *ucc_pram; 74*4882a593Smuzhiyun u16 tsa; 75*4882a593Smuzhiyun bool hdlc_busy; 76*4882a593Smuzhiyun bool loopback; 77*4882a593Smuzhiyun bool hdlc_bus; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun u8 *tx_buffer; 80*4882a593Smuzhiyun u8 *rx_buffer; 81*4882a593Smuzhiyun dma_addr_t dma_tx_addr; 82*4882a593Smuzhiyun dma_addr_t dma_rx_addr; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct qe_bd *tx_bd_base; 85*4882a593Smuzhiyun struct qe_bd *rx_bd_base; 86*4882a593Smuzhiyun dma_addr_t dma_tx_bd; 87*4882a593Smuzhiyun dma_addr_t dma_rx_bd; 88*4882a593Smuzhiyun struct qe_bd *curtx_bd; 89*4882a593Smuzhiyun struct qe_bd *currx_bd; 90*4882a593Smuzhiyun struct qe_bd *dirty_tx; 91*4882a593Smuzhiyun u16 currx_bdnum; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct sk_buff **tx_skbuff; 94*4882a593Smuzhiyun struct sk_buff **rx_skbuff; 95*4882a593Smuzhiyun u16 skb_curtx; 96*4882a593Smuzhiyun u16 skb_currx; 97*4882a593Smuzhiyun unsigned short skb_dirtytx; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun unsigned short tx_ring_size; 100*4882a593Smuzhiyun unsigned short rx_ring_size; 101*4882a593Smuzhiyun s32 ucc_pram_offset; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun unsigned short encoding; 104*4882a593Smuzhiyun unsigned short parity; 105*4882a593Smuzhiyun unsigned short hmask; 106*4882a593Smuzhiyun u32 clocking; 107*4882a593Smuzhiyun spinlock_t lock; /* lock for Tx BD and Tx buffer */ 108*4882a593Smuzhiyun #ifdef CONFIG_PM 109*4882a593Smuzhiyun struct ucc_hdlc_param *ucc_pram_bak; 110*4882a593Smuzhiyun u32 gumr; 111*4882a593Smuzhiyun u8 guemr; 112*4882a593Smuzhiyun u32 cmxsi1cr_l, cmxsi1cr_h; 113*4882a593Smuzhiyun u32 cmxsi1syr; 114*4882a593Smuzhiyun u32 cmxucr[4]; 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define TX_BD_RING_LEN 0x10 119*4882a593Smuzhiyun #define RX_BD_RING_LEN 0x20 120*4882a593Smuzhiyun #define RX_CLEAN_MAX 0x10 121*4882a593Smuzhiyun #define NUM_OF_BUF 4 122*4882a593Smuzhiyun #define MAX_RX_BUF_LENGTH (48 * 0x20) 123*4882a593Smuzhiyun #define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8) 124*4882a593Smuzhiyun #define ALIGNMENT_OF_UCC_HDLC_PRAM 64 125*4882a593Smuzhiyun #define SI_BANK_SIZE 128 126*4882a593Smuzhiyun #define MAX_HDLC_NUM 4 127*4882a593Smuzhiyun #define HDLC_HEAD_LEN 2 128*4882a593Smuzhiyun #define HDLC_CRC_SIZE 2 129*4882a593Smuzhiyun #define TX_RING_MOD_MASK(size) (size - 1) 130*4882a593Smuzhiyun #define RX_RING_MOD_MASK(size) (size - 1) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define HDLC_HEAD_MASK 0x0000 133*4882a593Smuzhiyun #define DEFAULT_HDLC_HEAD 0xff44 134*4882a593Smuzhiyun #define DEFAULT_ADDR_MASK 0x00ff 135*4882a593Smuzhiyun #define DEFAULT_HDLC_ADDR 0x00ff 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define BMR_GBL 0x20000000 138*4882a593Smuzhiyun #define BMR_BIG_ENDIAN 0x10000000 139*4882a593Smuzhiyun #define CRC_16BIT_MASK 0x0000F0B8 140*4882a593Smuzhiyun #define CRC_16BIT_PRES 0x0000FFFF 141*4882a593Smuzhiyun #define DEFAULT_RFTHR 1 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define DEFAULT_PPP_HEAD 0xff03 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif 146