1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author : Liu Junliang <liujunliang_ljl@163.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SR9700_H 9*4882a593Smuzhiyun #define _SR9700_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* sr9700 spec. register table on Linux platform */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Network Control Reg */ 14*4882a593Smuzhiyun #define SR_NCR 0x00 15*4882a593Smuzhiyun #define NCR_RST (1 << 0) 16*4882a593Smuzhiyun #define NCR_LBK (3 << 1) 17*4882a593Smuzhiyun #define NCR_FDX (1 << 3) 18*4882a593Smuzhiyun #define NCR_WAKEEN (1 << 6) 19*4882a593Smuzhiyun /* Network Status Reg */ 20*4882a593Smuzhiyun #define SR_NSR 0x01 21*4882a593Smuzhiyun #define NSR_RXRDY (1 << 0) 22*4882a593Smuzhiyun #define NSR_RXOV (1 << 1) 23*4882a593Smuzhiyun #define NSR_TX1END (1 << 2) 24*4882a593Smuzhiyun #define NSR_TX2END (1 << 3) 25*4882a593Smuzhiyun #define NSR_TXFULL (1 << 4) 26*4882a593Smuzhiyun #define NSR_WAKEST (1 << 5) 27*4882a593Smuzhiyun #define NSR_LINKST (1 << 6) 28*4882a593Smuzhiyun #define NSR_SPEED (1 << 7) 29*4882a593Smuzhiyun /* Tx Control Reg */ 30*4882a593Smuzhiyun #define SR_TCR 0x02 31*4882a593Smuzhiyun #define TCR_CRC_DIS (1 << 1) 32*4882a593Smuzhiyun #define TCR_PAD_DIS (1 << 2) 33*4882a593Smuzhiyun #define TCR_LC_CARE (1 << 3) 34*4882a593Smuzhiyun #define TCR_CRS_CARE (1 << 4) 35*4882a593Smuzhiyun #define TCR_EXCECM (1 << 5) 36*4882a593Smuzhiyun #define TCR_LF_EN (1 << 6) 37*4882a593Smuzhiyun /* Tx Status Reg for Packet Index 1 */ 38*4882a593Smuzhiyun #define SR_TSR1 0x03 39*4882a593Smuzhiyun #define TSR1_EC (1 << 2) 40*4882a593Smuzhiyun #define TSR1_COL (1 << 3) 41*4882a593Smuzhiyun #define TSR1_LC (1 << 4) 42*4882a593Smuzhiyun #define TSR1_NC (1 << 5) 43*4882a593Smuzhiyun #define TSR1_LOC (1 << 6) 44*4882a593Smuzhiyun #define TSR1_TLF (1 << 7) 45*4882a593Smuzhiyun /* Tx Status Reg for Packet Index 2 */ 46*4882a593Smuzhiyun #define SR_TSR2 0x04 47*4882a593Smuzhiyun #define TSR2_EC (1 << 2) 48*4882a593Smuzhiyun #define TSR2_COL (1 << 3) 49*4882a593Smuzhiyun #define TSR2_LC (1 << 4) 50*4882a593Smuzhiyun #define TSR2_NC (1 << 5) 51*4882a593Smuzhiyun #define TSR2_LOC (1 << 6) 52*4882a593Smuzhiyun #define TSR2_TLF (1 << 7) 53*4882a593Smuzhiyun /* Rx Control Reg*/ 54*4882a593Smuzhiyun #define SR_RCR 0x05 55*4882a593Smuzhiyun #define RCR_RXEN (1 << 0) 56*4882a593Smuzhiyun #define RCR_PRMSC (1 << 1) 57*4882a593Smuzhiyun #define RCR_RUNT (1 << 2) 58*4882a593Smuzhiyun #define RCR_ALL (1 << 3) 59*4882a593Smuzhiyun #define RCR_DIS_CRC (1 << 4) 60*4882a593Smuzhiyun #define RCR_DIS_LONG (1 << 5) 61*4882a593Smuzhiyun /* Rx Status Reg */ 62*4882a593Smuzhiyun #define SR_RSR 0x06 63*4882a593Smuzhiyun #define RSR_AE (1 << 2) 64*4882a593Smuzhiyun #define RSR_MF (1 << 6) 65*4882a593Smuzhiyun #define RSR_RF (1 << 7) 66*4882a593Smuzhiyun /* Rx Overflow Counter Reg */ 67*4882a593Smuzhiyun #define SR_ROCR 0x07 68*4882a593Smuzhiyun #define ROCR_ROC (0x7F << 0) 69*4882a593Smuzhiyun #define ROCR_RXFU (1 << 7) 70*4882a593Smuzhiyun /* Back Pressure Threshold Reg */ 71*4882a593Smuzhiyun #define SR_BPTR 0x08 72*4882a593Smuzhiyun #define BPTR_JPT (0x0F << 0) 73*4882a593Smuzhiyun #define BPTR_BPHW (0x0F << 4) 74*4882a593Smuzhiyun /* Flow Control Threshold Reg */ 75*4882a593Smuzhiyun #define SR_FCTR 0x09 76*4882a593Smuzhiyun #define FCTR_LWOT (0x0F << 0) 77*4882a593Smuzhiyun #define FCTR_HWOT (0x0F << 4) 78*4882a593Smuzhiyun /* rx/tx Flow Control Reg */ 79*4882a593Smuzhiyun #define SR_FCR 0x0A 80*4882a593Smuzhiyun #define FCR_FLCE (1 << 0) 81*4882a593Smuzhiyun #define FCR_BKPA (1 << 4) 82*4882a593Smuzhiyun #define FCR_TXPEN (1 << 5) 83*4882a593Smuzhiyun #define FCR_TXPF (1 << 6) 84*4882a593Smuzhiyun #define FCR_TXP0 (1 << 7) 85*4882a593Smuzhiyun /* Eeprom & Phy Control Reg */ 86*4882a593Smuzhiyun #define SR_EPCR 0x0B 87*4882a593Smuzhiyun #define EPCR_ERRE (1 << 0) 88*4882a593Smuzhiyun #define EPCR_ERPRW (1 << 1) 89*4882a593Smuzhiyun #define EPCR_ERPRR (1 << 2) 90*4882a593Smuzhiyun #define EPCR_EPOS (1 << 3) 91*4882a593Smuzhiyun #define EPCR_WEP (1 << 4) 92*4882a593Smuzhiyun /* Eeprom & Phy Address Reg */ 93*4882a593Smuzhiyun #define SR_EPAR 0x0C 94*4882a593Smuzhiyun #define EPAR_EROA (0x3F << 0) 95*4882a593Smuzhiyun #define EPAR_PHY_ADR_MASK (0x03 << 6) 96*4882a593Smuzhiyun #define EPAR_PHY_ADR (0x01 << 6) 97*4882a593Smuzhiyun /* Eeprom & Phy Data Reg */ 98*4882a593Smuzhiyun #define SR_EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */ 99*4882a593Smuzhiyun /* Wakeup Control Reg */ 100*4882a593Smuzhiyun #define SR_WCR 0x0F 101*4882a593Smuzhiyun #define WCR_MAGICST (1 << 0) 102*4882a593Smuzhiyun #define WCR_LINKST (1 << 2) 103*4882a593Smuzhiyun #define WCR_MAGICEN (1 << 3) 104*4882a593Smuzhiyun #define WCR_LINKEN (1 << 5) 105*4882a593Smuzhiyun /* Physical Address Reg */ 106*4882a593Smuzhiyun #define SR_PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */ 107*4882a593Smuzhiyun /* Multicast Address Reg */ 108*4882a593Smuzhiyun #define SR_MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */ 109*4882a593Smuzhiyun /* 0x1e unused */ 110*4882a593Smuzhiyun /* Phy Reset Reg */ 111*4882a593Smuzhiyun #define SR_PRR 0x1F 112*4882a593Smuzhiyun #define PRR_PHY_RST (1 << 0) 113*4882a593Smuzhiyun /* Tx sdram Write Pointer Address Low */ 114*4882a593Smuzhiyun #define SR_TWPAL 0x20 115*4882a593Smuzhiyun /* Tx sdram Write Pointer Address High */ 116*4882a593Smuzhiyun #define SR_TWPAH 0x21 117*4882a593Smuzhiyun /* Tx sdram Read Pointer Address Low */ 118*4882a593Smuzhiyun #define SR_TRPAL 0x22 119*4882a593Smuzhiyun /* Tx sdram Read Pointer Address High */ 120*4882a593Smuzhiyun #define SR_TRPAH 0x23 121*4882a593Smuzhiyun /* Rx sdram Write Pointer Address Low */ 122*4882a593Smuzhiyun #define SR_RWPAL 0x24 123*4882a593Smuzhiyun /* Rx sdram Write Pointer Address High */ 124*4882a593Smuzhiyun #define SR_RWPAH 0x25 125*4882a593Smuzhiyun /* Rx sdram Read Pointer Address Low */ 126*4882a593Smuzhiyun #define SR_RRPAL 0x26 127*4882a593Smuzhiyun /* Rx sdram Read Pointer Address High */ 128*4882a593Smuzhiyun #define SR_RRPAH 0x27 129*4882a593Smuzhiyun /* Vendor ID register */ 130*4882a593Smuzhiyun #define SR_VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */ 131*4882a593Smuzhiyun /* Product ID register */ 132*4882a593Smuzhiyun #define SR_PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */ 133*4882a593Smuzhiyun /* CHIP Revision register */ 134*4882a593Smuzhiyun #define SR_CHIPR 0x2C 135*4882a593Smuzhiyun /* 0x2D --> 0xEF unused */ 136*4882a593Smuzhiyun /* USB Device Address */ 137*4882a593Smuzhiyun #define SR_USBDA 0xF0 138*4882a593Smuzhiyun #define USBDA_USBFA (0x7F << 0) 139*4882a593Smuzhiyun /* RX packet Counter Reg */ 140*4882a593Smuzhiyun #define SR_RXC 0xF1 141*4882a593Smuzhiyun /* Tx packet Counter & USB Status Reg */ 142*4882a593Smuzhiyun #define SR_TXC_USBS 0xF2 143*4882a593Smuzhiyun #define TXC_USBS_TXC0 (1 << 0) 144*4882a593Smuzhiyun #define TXC_USBS_TXC1 (1 << 1) 145*4882a593Smuzhiyun #define TXC_USBS_TXC2 (1 << 2) 146*4882a593Smuzhiyun #define TXC_USBS_EP1RDY (1 << 5) 147*4882a593Smuzhiyun #define TXC_USBS_SUSFLAG (1 << 6) 148*4882a593Smuzhiyun #define TXC_USBS_RXFAULT (1 << 7) 149*4882a593Smuzhiyun /* USB Control register */ 150*4882a593Smuzhiyun #define SR_USBC 0xF4 151*4882a593Smuzhiyun #define USBC_EP3NAK (1 << 4) 152*4882a593Smuzhiyun #define USBC_EP3ACK (1 << 5) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Register access commands and flags */ 155*4882a593Smuzhiyun #define SR_RD_REGS 0x00 156*4882a593Smuzhiyun #define SR_WR_REGS 0x01 157*4882a593Smuzhiyun #define SR_WR_REG 0x03 158*4882a593Smuzhiyun #define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE) 159*4882a593Smuzhiyun #define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* parameters */ 162*4882a593Smuzhiyun #define SR_SHARE_TIMEOUT 1000 163*4882a593Smuzhiyun #define SR_EEPROM_LEN 256 164*4882a593Smuzhiyun #define SR_MCAST_SIZE 8 165*4882a593Smuzhiyun #define SR_MCAST_ADDR_FLAG 0x80 166*4882a593Smuzhiyun #define SR_MCAST_MAX 64 167*4882a593Smuzhiyun #define SR_TX_OVERHEAD 2 /* 2bytes header */ 168*4882a593Smuzhiyun #define SR_RX_OVERHEAD 7 /* 3bytes header + 4crc tail */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #endif /* _SR9700_H */ 171