1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /* Xilinx GMII2RGMII Converter driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2016 Xilinx, Inc.
5*4882a593Smuzhiyun * Copyright (C) 2016 Andrew Lunn <andrew@lunn.ch>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Andrew Lunn <andrew@lunn.ch>
8*4882a593Smuzhiyun * Author: Kedareswara rao Appana <appanad@xilinx.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Description:
11*4882a593Smuzhiyun * This driver is developed for Xilinx GMII2RGMII Converter
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/mii.h>
16*4882a593Smuzhiyun #include <linux/mdio.h>
17*4882a593Smuzhiyun #include <linux/phy.h>
18*4882a593Smuzhiyun #include <linux/of_mdio.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define XILINX_GMII2RGMII_REG 0x10
21*4882a593Smuzhiyun #define XILINX_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct gmii2rgmii {
24*4882a593Smuzhiyun struct phy_device *phy_dev;
25*4882a593Smuzhiyun struct phy_driver *phy_drv;
26*4882a593Smuzhiyun struct phy_driver conv_phy_drv;
27*4882a593Smuzhiyun struct mdio_device *mdio;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
xgmiitorgmii_read_status(struct phy_device * phydev)30*4882a593Smuzhiyun static int xgmiitorgmii_read_status(struct phy_device *phydev)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct gmii2rgmii *priv = mdiodev_get_drvdata(&phydev->mdio);
33*4882a593Smuzhiyun struct mii_bus *bus = priv->mdio->bus;
34*4882a593Smuzhiyun int addr = priv->mdio->addr;
35*4882a593Smuzhiyun u16 val = 0;
36*4882a593Smuzhiyun int err;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun if (priv->phy_drv->read_status)
39*4882a593Smuzhiyun err = priv->phy_drv->read_status(phydev);
40*4882a593Smuzhiyun else
41*4882a593Smuzhiyun err = genphy_read_status(phydev);
42*4882a593Smuzhiyun if (err < 0)
43*4882a593Smuzhiyun return err;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun val = mdiobus_read(bus, addr, XILINX_GMII2RGMII_REG);
46*4882a593Smuzhiyun val &= ~XILINX_GMII2RGMII_SPEED_MASK;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (phydev->speed == SPEED_1000)
49*4882a593Smuzhiyun val |= BMCR_SPEED1000;
50*4882a593Smuzhiyun else if (phydev->speed == SPEED_100)
51*4882a593Smuzhiyun val |= BMCR_SPEED100;
52*4882a593Smuzhiyun else
53*4882a593Smuzhiyun val |= BMCR_SPEED10;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun mdiobus_write(bus, addr, XILINX_GMII2RGMII_REG, val);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
xgmiitorgmii_probe(struct mdio_device * mdiodev)60*4882a593Smuzhiyun static int xgmiitorgmii_probe(struct mdio_device *mdiodev)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct device *dev = &mdiodev->dev;
63*4882a593Smuzhiyun struct device_node *np = dev->of_node, *phy_node;
64*4882a593Smuzhiyun struct gmii2rgmii *priv;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
67*4882a593Smuzhiyun if (!priv)
68*4882a593Smuzhiyun return -ENOMEM;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun phy_node = of_parse_phandle(np, "phy-handle", 0);
71*4882a593Smuzhiyun if (!phy_node) {
72*4882a593Smuzhiyun dev_err(dev, "Couldn't parse phy-handle\n");
73*4882a593Smuzhiyun return -ENODEV;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun priv->phy_dev = of_phy_find_device(phy_node);
77*4882a593Smuzhiyun of_node_put(phy_node);
78*4882a593Smuzhiyun if (!priv->phy_dev) {
79*4882a593Smuzhiyun dev_info(dev, "Couldn't find phydev\n");
80*4882a593Smuzhiyun return -EPROBE_DEFER;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (!priv->phy_dev->drv) {
84*4882a593Smuzhiyun dev_info(dev, "Attached phy not ready\n");
85*4882a593Smuzhiyun return -EPROBE_DEFER;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun priv->mdio = mdiodev;
89*4882a593Smuzhiyun priv->phy_drv = priv->phy_dev->drv;
90*4882a593Smuzhiyun memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
91*4882a593Smuzhiyun sizeof(struct phy_driver));
92*4882a593Smuzhiyun priv->conv_phy_drv.read_status = xgmiitorgmii_read_status;
93*4882a593Smuzhiyun mdiodev_set_drvdata(&priv->phy_dev->mdio, priv);
94*4882a593Smuzhiyun priv->phy_dev->drv = &priv->conv_phy_drv;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct of_device_id xgmiitorgmii_of_match[] = {
100*4882a593Smuzhiyun { .compatible = "xlnx,gmii-to-rgmii-1.0" },
101*4882a593Smuzhiyun {},
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, xgmiitorgmii_of_match);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static struct mdio_driver xgmiitorgmii_driver = {
106*4882a593Smuzhiyun .probe = xgmiitorgmii_probe,
107*4882a593Smuzhiyun .mdiodrv.driver = {
108*4882a593Smuzhiyun .name = "xgmiitorgmii",
109*4882a593Smuzhiyun .of_match_table = xgmiitorgmii_of_match,
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun mdio_module_driver(xgmiitorgmii_driver);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun MODULE_DESCRIPTION("Xilinx GMII2RGMII converter driver");
116*4882a593Smuzhiyun MODULE_LICENSE("GPL");
117