1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/net/phy/ste10Xp.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for STMicroelectronics STe10Xp PHYs
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (c) 2008 STMicroelectronics Limited
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/sched.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/moduleparam.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/netdevice.h>
19*4882a593Smuzhiyun #include <linux/ethtool.h>
20*4882a593Smuzhiyun #include <linux/mii.h>
21*4882a593Smuzhiyun #include <linux/phy.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MII_XCIIS 0x11 /* Configuration Info IRQ & Status Reg */
24*4882a593Smuzhiyun #define MII_XIE 0x12 /* Interrupt Enable Register */
25*4882a593Smuzhiyun #define MII_XIE_DEFAULT_MASK 0x0070 /* ANE complete, Remote Fault, Link Down */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define STE101P_PHY_ID 0x00061c50
28*4882a593Smuzhiyun #define STE100P_PHY_ID 0x1c040011
29*4882a593Smuzhiyun
ste10Xp_config_init(struct phy_device * phydev)30*4882a593Smuzhiyun static int ste10Xp_config_init(struct phy_device *phydev)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun int value, err;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Software Reset PHY */
35*4882a593Smuzhiyun value = phy_read(phydev, MII_BMCR);
36*4882a593Smuzhiyun if (value < 0)
37*4882a593Smuzhiyun return value;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun value |= BMCR_RESET;
40*4882a593Smuzhiyun err = phy_write(phydev, MII_BMCR, value);
41*4882a593Smuzhiyun if (err < 0)
42*4882a593Smuzhiyun return err;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun do {
45*4882a593Smuzhiyun value = phy_read(phydev, MII_BMCR);
46*4882a593Smuzhiyun } while (value & BMCR_RESET);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
ste10Xp_config_intr(struct phy_device * phydev)51*4882a593Smuzhiyun static int ste10Xp_config_intr(struct phy_device *phydev)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun int err, value;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
56*4882a593Smuzhiyun /* Enable all STe101P interrupts (PR12) */
57*4882a593Smuzhiyun err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK);
58*4882a593Smuzhiyun /* clear any pending interrupts */
59*4882a593Smuzhiyun if (err == 0) {
60*4882a593Smuzhiyun value = phy_read(phydev, MII_XCIIS);
61*4882a593Smuzhiyun if (value < 0)
62*4882a593Smuzhiyun err = value;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun } else
65*4882a593Smuzhiyun err = phy_write(phydev, MII_XIE, 0);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return err;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
ste10Xp_ack_interrupt(struct phy_device * phydev)70*4882a593Smuzhiyun static int ste10Xp_ack_interrupt(struct phy_device *phydev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun int err = phy_read(phydev, MII_XCIIS);
73*4882a593Smuzhiyun if (err < 0)
74*4882a593Smuzhiyun return err;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static struct phy_driver ste10xp_pdriver[] = {
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun .phy_id = STE101P_PHY_ID,
82*4882a593Smuzhiyun .phy_id_mask = 0xfffffff0,
83*4882a593Smuzhiyun .name = "STe101p",
84*4882a593Smuzhiyun /* PHY_BASIC_FEATURES */
85*4882a593Smuzhiyun .config_init = ste10Xp_config_init,
86*4882a593Smuzhiyun .ack_interrupt = ste10Xp_ack_interrupt,
87*4882a593Smuzhiyun .config_intr = ste10Xp_config_intr,
88*4882a593Smuzhiyun .suspend = genphy_suspend,
89*4882a593Smuzhiyun .resume = genphy_resume,
90*4882a593Smuzhiyun }, {
91*4882a593Smuzhiyun .phy_id = STE100P_PHY_ID,
92*4882a593Smuzhiyun .phy_id_mask = 0xffffffff,
93*4882a593Smuzhiyun .name = "STe100p",
94*4882a593Smuzhiyun /* PHY_BASIC_FEATURES */
95*4882a593Smuzhiyun .config_init = ste10Xp_config_init,
96*4882a593Smuzhiyun .ack_interrupt = ste10Xp_ack_interrupt,
97*4882a593Smuzhiyun .config_intr = ste10Xp_config_intr,
98*4882a593Smuzhiyun .suspend = genphy_suspend,
99*4882a593Smuzhiyun .resume = genphy_resume,
100*4882a593Smuzhiyun } };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun module_phy_driver(ste10xp_pdriver);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static struct mdio_device_id __maybe_unused ste10Xp_tbl[] = {
105*4882a593Smuzhiyun { STE101P_PHY_ID, 0xfffffff0 },
106*4882a593Smuzhiyun { STE100P_PHY_ID, 0xffffffff },
107*4882a593Smuzhiyun { }
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun MODULE_DEVICE_TABLE(mdio, ste10Xp_tbl);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun MODULE_DESCRIPTION("STMicroelectronics STe10Xp PHY driver");
113*4882a593Smuzhiyun MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
114*4882a593Smuzhiyun MODULE_LICENSE("GPL");
115