1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Microsemi VSC85xx PHYs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Microsemi Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MSCC_PHY_FC_BUFFER_H_ 9*4882a593Smuzhiyun #define _MSCC_PHY_FC_BUFFER_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MSCC_FCBUF_ENA_CFG 0x00 12*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG 0x01 13*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG 0x02 14*4882a593Smuzhiyun #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG 0x03 15*4882a593Smuzhiyun #define MSCC_FCBUF_TX_DATA_QUEUE_CFG 0x04 16*4882a593Smuzhiyun #define MSCC_FCBUF_RX_DATA_QUEUE_CFG 0x05 17*4882a593Smuzhiyun #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG 0x06 18*4882a593Smuzhiyun #define MSCC_FCBUF_FC_READ_THRESH_CFG 0x07 19*4882a593Smuzhiyun #define MSCC_FCBUF_TX_FRM_GAP_COMP 0x08 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MSCC_FCBUF_ENA_CFG_TX_ENA BIT(0) 22*4882a593Smuzhiyun #define MSCC_FCBUF_ENA_CFG_RX_ENA BIT(4) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR BIT(4) 25*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA BIT(8) 26*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA BIT(12) 27*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA BIT(16) 28*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA BIT(20) 29*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA BIT(24) 30*4882a593Smuzhiyun #define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN BIT(28) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x) (x) 33*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M GENMASK(15, 0) 34*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x) ((x) << 16) 35*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M GENMASK(19, 16) 36*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x) ((x) << 20) 37*4882a593Smuzhiyun #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M GENMASK(31, 20) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x) (x) 40*4882a593Smuzhiyun #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M GENMASK(15, 0) 41*4882a593Smuzhiyun #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x) ((x) << 16) 42*4882a593Smuzhiyun #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M GENMASK(31, 16) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x) (x) 45*4882a593Smuzhiyun #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M GENMASK(15, 0) 46*4882a593Smuzhiyun #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x) ((x) << 16) 47*4882a593Smuzhiyun #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M GENMASK(31, 16) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x) (x) 50*4882a593Smuzhiyun #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M GENMASK(15, 0) 51*4882a593Smuzhiyun #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x) ((x) << 16) 52*4882a593Smuzhiyun #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M GENMASK(31, 16) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x) (x) 55*4882a593Smuzhiyun #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M GENMASK(15, 0) 56*4882a593Smuzhiyun #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x) ((x) << 16) 57*4882a593Smuzhiyun #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x) (x) 60*4882a593Smuzhiyun #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M GENMASK(15, 0) 61*4882a593Smuzhiyun #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x) ((x) << 16) 62*4882a593Smuzhiyun #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* _MSCC_PHY_FC_BUFFER_H_ */ 65