1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/net/phy/marvell.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for Marvell PHYs
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Andy Fleming
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (c) 2004 Freescale Semiconductor, Inc.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/string.h>
15*4882a593Smuzhiyun #include <linux/ctype.h>
16*4882a593Smuzhiyun #include <linux/errno.h>
17*4882a593Smuzhiyun #include <linux/unistd.h>
18*4882a593Smuzhiyun #include <linux/hwmon.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/netdevice.h>
23*4882a593Smuzhiyun #include <linux/etherdevice.h>
24*4882a593Smuzhiyun #include <linux/skbuff.h>
25*4882a593Smuzhiyun #include <linux/spinlock.h>
26*4882a593Smuzhiyun #include <linux/mm.h>
27*4882a593Smuzhiyun #include <linux/module.h>
28*4882a593Smuzhiyun #include <linux/mii.h>
29*4882a593Smuzhiyun #include <linux/ethtool.h>
30*4882a593Smuzhiyun #include <linux/ethtool_netlink.h>
31*4882a593Smuzhiyun #include <linux/phy.h>
32*4882a593Smuzhiyun #include <linux/marvell_phy.h>
33*4882a593Smuzhiyun #include <linux/bitfield.h>
34*4882a593Smuzhiyun #include <linux/of.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include <linux/io.h>
37*4882a593Smuzhiyun #include <asm/irq.h>
38*4882a593Smuzhiyun #include <linux/uaccess.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define MII_MARVELL_PHY_PAGE 22
41*4882a593Smuzhiyun #define MII_MARVELL_COPPER_PAGE 0x00
42*4882a593Smuzhiyun #define MII_MARVELL_FIBER_PAGE 0x01
43*4882a593Smuzhiyun #define MII_MARVELL_MSCR_PAGE 0x02
44*4882a593Smuzhiyun #define MII_MARVELL_LED_PAGE 0x03
45*4882a593Smuzhiyun #define MII_MARVELL_VCT5_PAGE 0x05
46*4882a593Smuzhiyun #define MII_MARVELL_MISC_TEST_PAGE 0x06
47*4882a593Smuzhiyun #define MII_MARVELL_VCT7_PAGE 0x07
48*4882a593Smuzhiyun #define MII_MARVELL_WOL_PAGE 0x11
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define MII_M1011_IEVENT 0x13
51*4882a593Smuzhiyun #define MII_M1011_IEVENT_CLEAR 0x0000
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define MII_M1011_IMASK 0x12
54*4882a593Smuzhiyun #define MII_M1011_IMASK_INIT 0x6400
55*4882a593Smuzhiyun #define MII_M1011_IMASK_CLEAR 0x0000
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define MII_M1011_PHY_SCR 0x10
58*4882a593Smuzhiyun #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
59*4882a593Smuzhiyun #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
60*4882a593Smuzhiyun #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
61*4882a593Smuzhiyun #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
62*4882a593Smuzhiyun #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
63*4882a593Smuzhiyun #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define MII_M1011_PHY_SSR 0x11
66*4882a593Smuzhiyun #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define MII_M1111_PHY_LED_CONTROL 0x18
69*4882a593Smuzhiyun #define MII_M1111_PHY_LED_DIRECT 0x4100
70*4882a593Smuzhiyun #define MII_M1111_PHY_LED_COMBINE 0x411c
71*4882a593Smuzhiyun #define MII_M1111_PHY_EXT_CR 0x14
72*4882a593Smuzhiyun #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
73*4882a593Smuzhiyun #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
74*4882a593Smuzhiyun #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
75*4882a593Smuzhiyun #define MII_M1111_RGMII_RX_DELAY BIT(7)
76*4882a593Smuzhiyun #define MII_M1111_RGMII_TX_DELAY BIT(1)
77*4882a593Smuzhiyun #define MII_M1111_PHY_EXT_SR 0x1b
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define MII_M1111_HWCFG_MODE_MASK 0xf
80*4882a593Smuzhiyun #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81*4882a593Smuzhiyun #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82*4882a593Smuzhiyun #define MII_M1111_HWCFG_MODE_RTBI 0x7
83*4882a593Smuzhiyun #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
84*4882a593Smuzhiyun #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
85*4882a593Smuzhiyun #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
86*4882a593Smuzhiyun #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define MII_88E1121_PHY_MSCR_REG 21
89*4882a593Smuzhiyun #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90*4882a593Smuzhiyun #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91*4882a593Smuzhiyun #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define MII_88E1121_MISC_TEST 0x1a
94*4882a593Smuzhiyun #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
95*4882a593Smuzhiyun #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
96*4882a593Smuzhiyun #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
97*4882a593Smuzhiyun #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
98*4882a593Smuzhiyun #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
99*4882a593Smuzhiyun #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define MII_88E1510_TEMP_SENSOR 0x1b
102*4882a593Smuzhiyun #define MII_88E1510_TEMP_SENSOR_MASK 0xff
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3 0x1a
105*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
106*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
107*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
108*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
109*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
110*4882a593Smuzhiyun #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #define MII_88E6390_MISC_TEST 0x1b
113*4882a593Smuzhiyun #define MII_88E6390_MISC_TEST_SAMPLE_1S 0
114*4882a593Smuzhiyun #define MII_88E6390_MISC_TEST_SAMPLE_10MS BIT(14)
115*4882a593Smuzhiyun #define MII_88E6390_MISC_TEST_SAMPLE_DISABLE BIT(15)
116*4882a593Smuzhiyun #define MII_88E6390_MISC_TEST_SAMPLE_ENABLE 0
117*4882a593Smuzhiyun #define MII_88E6390_MISC_TEST_SAMPLE_MASK (0x3 << 14)
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define MII_88E6390_TEMP_SENSOR 0x1c
120*4882a593Smuzhiyun #define MII_88E6390_TEMP_SENSOR_MASK 0xff
121*4882a593Smuzhiyun #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #define MII_88E1318S_PHY_MSCR1_REG 16
124*4882a593Smuzhiyun #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* Copper Specific Interrupt Enable Register */
127*4882a593Smuzhiyun #define MII_88E1318S_PHY_CSIER 0x12
128*4882a593Smuzhiyun /* WOL Event Interrupt Enable */
129*4882a593Smuzhiyun #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* LED Timer Control Register */
132*4882a593Smuzhiyun #define MII_88E1318S_PHY_LED_TCR 0x12
133*4882a593Smuzhiyun #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
134*4882a593Smuzhiyun #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
135*4882a593Smuzhiyun #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Magic Packet MAC address registers */
138*4882a593Smuzhiyun #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
139*4882a593Smuzhiyun #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
140*4882a593Smuzhiyun #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #define MII_88E1318S_PHY_WOL_CTRL 0x10
143*4882a593Smuzhiyun #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
144*4882a593Smuzhiyun #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun #define MII_PHY_LED_CTRL 16
147*4882a593Smuzhiyun #define MII_88E1121_PHY_LED_DEF 0x0030
148*4882a593Smuzhiyun #define MII_88E1510_PHY_LED_DEF 0x1177
149*4882a593Smuzhiyun #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS 0x11
152*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS_1000 0x8000
153*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS_100 0x4000
154*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
155*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
156*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
157*4882a593Smuzhiyun #define MII_M1011_PHY_STATUS_LINK 0x0400
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun #define MII_88E3016_PHY_SPEC_CTRL 0x10
160*4882a593Smuzhiyun #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
161*4882a593Smuzhiyun #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun #define MII_88E1510_GEN_CTRL_REG_1 0x14
164*4882a593Smuzhiyun #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
165*4882a593Smuzhiyun #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
166*4882a593Smuzhiyun #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
169*4882a593Smuzhiyun #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
170*4882a593Smuzhiyun #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
171*4882a593Smuzhiyun #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
172*4882a593Smuzhiyun #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
173*4882a593Smuzhiyun #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
174*4882a593Smuzhiyun #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define MII_VCT5_CTRL 0x17
177*4882a593Smuzhiyun #define MII_VCT5_CTRL_ENABLE BIT(15)
178*4882a593Smuzhiyun #define MII_VCT5_CTRL_COMPLETE BIT(14)
179*4882a593Smuzhiyun #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
180*4882a593Smuzhiyun #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
181*4882a593Smuzhiyun #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
182*4882a593Smuzhiyun #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
183*4882a593Smuzhiyun #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
184*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
185*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
186*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
187*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
188*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
189*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
190*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
191*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
192*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
193*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
194*4882a593Smuzhiyun #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
195*4882a593Smuzhiyun #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
196*4882a593Smuzhiyun #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
197*4882a593Smuzhiyun #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
198*4882a593Smuzhiyun #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
201*4882a593Smuzhiyun #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
202*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL 0x1c
203*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
204*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
205*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
206*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
207*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
208*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
209*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
210*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
211*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
212*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
213*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
214*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
215*4882a593Smuzhiyun #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* For TDR measurements less than 11 meters, a short pulse should be
218*4882a593Smuzhiyun * used.
219*4882a593Smuzhiyun */
220*4882a593Smuzhiyun #define TDR_SHORT_CABLE_LENGTH 11
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun #define MII_VCT7_PAIR_0_DISTANCE 0x10
223*4882a593Smuzhiyun #define MII_VCT7_PAIR_1_DISTANCE 0x11
224*4882a593Smuzhiyun #define MII_VCT7_PAIR_2_DISTANCE 0x12
225*4882a593Smuzhiyun #define MII_VCT7_PAIR_3_DISTANCE 0x13
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun #define MII_VCT7_RESULTS 0x14
228*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
229*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
230*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
231*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
232*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
233*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
234*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
235*4882a593Smuzhiyun #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
236*4882a593Smuzhiyun #define MII_VCT7_RESULTS_INVALID 0
237*4882a593Smuzhiyun #define MII_VCT7_RESULTS_OK 1
238*4882a593Smuzhiyun #define MII_VCT7_RESULTS_OPEN 2
239*4882a593Smuzhiyun #define MII_VCT7_RESULTS_SAME_SHORT 3
240*4882a593Smuzhiyun #define MII_VCT7_RESULTS_CROSS_SHORT 4
241*4882a593Smuzhiyun #define MII_VCT7_RESULTS_BUSY 9
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun #define MII_VCT7_CTRL 0x15
244*4882a593Smuzhiyun #define MII_VCT7_CTRL_RUN_NOW BIT(15)
245*4882a593Smuzhiyun #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
246*4882a593Smuzhiyun #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
247*4882a593Smuzhiyun #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
248*4882a593Smuzhiyun #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
249*4882a593Smuzhiyun #define MII_VCT7_CTRL_METERS BIT(10)
250*4882a593Smuzhiyun #define MII_VCT7_CTRL_CENTIMETERS 0
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun #define LPA_PAUSE_FIBER 0x180
253*4882a593Smuzhiyun #define LPA_PAUSE_ASYM_FIBER 0x100
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun #define NB_FIBER_STATS 1
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun MODULE_DESCRIPTION("Marvell PHY driver");
258*4882a593Smuzhiyun MODULE_AUTHOR("Andy Fleming");
259*4882a593Smuzhiyun MODULE_LICENSE("GPL");
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun struct marvell_hw_stat {
262*4882a593Smuzhiyun const char *string;
263*4882a593Smuzhiyun u8 page;
264*4882a593Smuzhiyun u8 reg;
265*4882a593Smuzhiyun u8 bits;
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun static struct marvell_hw_stat marvell_hw_stats[] = {
269*4882a593Smuzhiyun { "phy_receive_errors_copper", 0, 21, 16},
270*4882a593Smuzhiyun { "phy_idle_errors", 0, 10, 8 },
271*4882a593Smuzhiyun { "phy_receive_errors_fiber", 1, 21, 16},
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun struct marvell_priv {
275*4882a593Smuzhiyun u64 stats[ARRAY_SIZE(marvell_hw_stats)];
276*4882a593Smuzhiyun char *hwmon_name;
277*4882a593Smuzhiyun struct device *hwmon_dev;
278*4882a593Smuzhiyun bool cable_test_tdr;
279*4882a593Smuzhiyun u32 first;
280*4882a593Smuzhiyun u32 last;
281*4882a593Smuzhiyun u32 step;
282*4882a593Smuzhiyun s8 pair;
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun
marvell_read_page(struct phy_device * phydev)285*4882a593Smuzhiyun static int marvell_read_page(struct phy_device *phydev)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
marvell_write_page(struct phy_device * phydev,int page)290*4882a593Smuzhiyun static int marvell_write_page(struct phy_device *phydev, int page)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
marvell_set_page(struct phy_device * phydev,int page)295*4882a593Smuzhiyun static int marvell_set_page(struct phy_device *phydev, int page)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
marvell_ack_interrupt(struct phy_device * phydev)300*4882a593Smuzhiyun static int marvell_ack_interrupt(struct phy_device *phydev)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun int err;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* Clear the interrupts by reading the reg */
305*4882a593Smuzhiyun err = phy_read(phydev, MII_M1011_IEVENT);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun if (err < 0)
308*4882a593Smuzhiyun return err;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
marvell_config_intr(struct phy_device * phydev)313*4882a593Smuzhiyun static int marvell_config_intr(struct phy_device *phydev)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun int err;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
318*4882a593Smuzhiyun err = phy_write(phydev, MII_M1011_IMASK,
319*4882a593Smuzhiyun MII_M1011_IMASK_INIT);
320*4882a593Smuzhiyun else
321*4882a593Smuzhiyun err = phy_write(phydev, MII_M1011_IMASK,
322*4882a593Smuzhiyun MII_M1011_IMASK_CLEAR);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun return err;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
marvell_set_polarity(struct phy_device * phydev,int polarity)327*4882a593Smuzhiyun static int marvell_set_polarity(struct phy_device *phydev, int polarity)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun int reg;
330*4882a593Smuzhiyun int err;
331*4882a593Smuzhiyun int val;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /* get the current settings */
334*4882a593Smuzhiyun reg = phy_read(phydev, MII_M1011_PHY_SCR);
335*4882a593Smuzhiyun if (reg < 0)
336*4882a593Smuzhiyun return reg;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun val = reg;
339*4882a593Smuzhiyun val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
340*4882a593Smuzhiyun switch (polarity) {
341*4882a593Smuzhiyun case ETH_TP_MDI:
342*4882a593Smuzhiyun val |= MII_M1011_PHY_SCR_MDI;
343*4882a593Smuzhiyun break;
344*4882a593Smuzhiyun case ETH_TP_MDI_X:
345*4882a593Smuzhiyun val |= MII_M1011_PHY_SCR_MDI_X;
346*4882a593Smuzhiyun break;
347*4882a593Smuzhiyun case ETH_TP_MDI_AUTO:
348*4882a593Smuzhiyun case ETH_TP_MDI_INVALID:
349*4882a593Smuzhiyun default:
350*4882a593Smuzhiyun val |= MII_M1011_PHY_SCR_AUTO_CROSS;
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun if (val != reg) {
355*4882a593Smuzhiyun /* Set the new polarity value in the register */
356*4882a593Smuzhiyun err = phy_write(phydev, MII_M1011_PHY_SCR, val);
357*4882a593Smuzhiyun if (err)
358*4882a593Smuzhiyun return err;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun return val != reg;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
marvell_config_aneg(struct phy_device * phydev)364*4882a593Smuzhiyun static int marvell_config_aneg(struct phy_device *phydev)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun int changed = 0;
367*4882a593Smuzhiyun int err;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
370*4882a593Smuzhiyun if (err < 0)
371*4882a593Smuzhiyun return err;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun changed = err;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
376*4882a593Smuzhiyun MII_M1111_PHY_LED_DIRECT);
377*4882a593Smuzhiyun if (err < 0)
378*4882a593Smuzhiyun return err;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun err = genphy_config_aneg(phydev);
381*4882a593Smuzhiyun if (err < 0)
382*4882a593Smuzhiyun return err;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun if (phydev->autoneg != AUTONEG_ENABLE || changed) {
385*4882a593Smuzhiyun /* A write to speed/duplex bits (that is performed by
386*4882a593Smuzhiyun * genphy_config_aneg() call above) must be followed by
387*4882a593Smuzhiyun * a software reset. Otherwise, the write has no effect.
388*4882a593Smuzhiyun */
389*4882a593Smuzhiyun err = genphy_soft_reset(phydev);
390*4882a593Smuzhiyun if (err < 0)
391*4882a593Smuzhiyun return err;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
m88e1101_config_aneg(struct phy_device * phydev)397*4882a593Smuzhiyun static int m88e1101_config_aneg(struct phy_device *phydev)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun int err;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* This Marvell PHY has an errata which requires
402*4882a593Smuzhiyun * that certain registers get written in order
403*4882a593Smuzhiyun * to restart autonegotiation
404*4882a593Smuzhiyun */
405*4882a593Smuzhiyun err = genphy_soft_reset(phydev);
406*4882a593Smuzhiyun if (err < 0)
407*4882a593Smuzhiyun return err;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun err = phy_write(phydev, 0x1d, 0x1f);
410*4882a593Smuzhiyun if (err < 0)
411*4882a593Smuzhiyun return err;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun err = phy_write(phydev, 0x1e, 0x200c);
414*4882a593Smuzhiyun if (err < 0)
415*4882a593Smuzhiyun return err;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun err = phy_write(phydev, 0x1d, 0x5);
418*4882a593Smuzhiyun if (err < 0)
419*4882a593Smuzhiyun return err;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun err = phy_write(phydev, 0x1e, 0);
422*4882a593Smuzhiyun if (err < 0)
423*4882a593Smuzhiyun return err;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun err = phy_write(phydev, 0x1e, 0x100);
426*4882a593Smuzhiyun if (err < 0)
427*4882a593Smuzhiyun return err;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun return marvell_config_aneg(phydev);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF_MDIO)
433*4882a593Smuzhiyun /* Set and/or override some configuration registers based on the
434*4882a593Smuzhiyun * marvell,reg-init property stored in the of_node for the phydev.
435*4882a593Smuzhiyun *
436*4882a593Smuzhiyun * marvell,reg-init = <reg-page reg mask value>,...;
437*4882a593Smuzhiyun *
438*4882a593Smuzhiyun * There may be one or more sets of <reg-page reg mask value>:
439*4882a593Smuzhiyun *
440*4882a593Smuzhiyun * reg-page: which register bank to use.
441*4882a593Smuzhiyun * reg: the register.
442*4882a593Smuzhiyun * mask: if non-zero, ANDed with existing register value.
443*4882a593Smuzhiyun * value: ORed with the masked value and written to the regiser.
444*4882a593Smuzhiyun *
445*4882a593Smuzhiyun */
marvell_of_reg_init(struct phy_device * phydev)446*4882a593Smuzhiyun static int marvell_of_reg_init(struct phy_device *phydev)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun const __be32 *paddr;
449*4882a593Smuzhiyun int len, i, saved_page, current_page, ret = 0;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun if (!phydev->mdio.dev.of_node)
452*4882a593Smuzhiyun return 0;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun paddr = of_get_property(phydev->mdio.dev.of_node,
455*4882a593Smuzhiyun "marvell,reg-init", &len);
456*4882a593Smuzhiyun if (!paddr || len < (4 * sizeof(*paddr)))
457*4882a593Smuzhiyun return 0;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun saved_page = phy_save_page(phydev);
460*4882a593Smuzhiyun if (saved_page < 0)
461*4882a593Smuzhiyun goto err;
462*4882a593Smuzhiyun current_page = saved_page;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun len /= sizeof(*paddr);
465*4882a593Smuzhiyun for (i = 0; i < len - 3; i += 4) {
466*4882a593Smuzhiyun u16 page = be32_to_cpup(paddr + i);
467*4882a593Smuzhiyun u16 reg = be32_to_cpup(paddr + i + 1);
468*4882a593Smuzhiyun u16 mask = be32_to_cpup(paddr + i + 2);
469*4882a593Smuzhiyun u16 val_bits = be32_to_cpup(paddr + i + 3);
470*4882a593Smuzhiyun int val;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun if (page != current_page) {
473*4882a593Smuzhiyun current_page = page;
474*4882a593Smuzhiyun ret = marvell_write_page(phydev, page);
475*4882a593Smuzhiyun if (ret < 0)
476*4882a593Smuzhiyun goto err;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun val = 0;
480*4882a593Smuzhiyun if (mask) {
481*4882a593Smuzhiyun val = __phy_read(phydev, reg);
482*4882a593Smuzhiyun if (val < 0) {
483*4882a593Smuzhiyun ret = val;
484*4882a593Smuzhiyun goto err;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun val &= mask;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun val |= val_bits;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun ret = __phy_write(phydev, reg, val);
491*4882a593Smuzhiyun if (ret < 0)
492*4882a593Smuzhiyun goto err;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun err:
495*4882a593Smuzhiyun return phy_restore_page(phydev, saved_page, ret);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun #else
marvell_of_reg_init(struct phy_device * phydev)498*4882a593Smuzhiyun static int marvell_of_reg_init(struct phy_device *phydev)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun return 0;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun #endif /* CONFIG_OF_MDIO */
503*4882a593Smuzhiyun
m88e1121_config_aneg_rgmii_delays(struct phy_device * phydev)504*4882a593Smuzhiyun static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun int mscr;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
509*4882a593Smuzhiyun mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
510*4882a593Smuzhiyun MII_88E1121_PHY_MSCR_TX_DELAY;
511*4882a593Smuzhiyun else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
512*4882a593Smuzhiyun mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
513*4882a593Smuzhiyun else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
514*4882a593Smuzhiyun mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
515*4882a593Smuzhiyun else
516*4882a593Smuzhiyun mscr = 0;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun return phy_modify_paged_changed(phydev, MII_MARVELL_MSCR_PAGE,
519*4882a593Smuzhiyun MII_88E1121_PHY_MSCR_REG,
520*4882a593Smuzhiyun MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
m88e1121_config_aneg(struct phy_device * phydev)523*4882a593Smuzhiyun static int m88e1121_config_aneg(struct phy_device *phydev)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun int changed = 0;
526*4882a593Smuzhiyun int err = 0;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (phy_interface_is_rgmii(phydev)) {
529*4882a593Smuzhiyun err = m88e1121_config_aneg_rgmii_delays(phydev);
530*4882a593Smuzhiyun if (err < 0)
531*4882a593Smuzhiyun return err;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun changed = err;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
537*4882a593Smuzhiyun if (err < 0)
538*4882a593Smuzhiyun return err;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun changed |= err;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun err = genphy_config_aneg(phydev);
543*4882a593Smuzhiyun if (err < 0)
544*4882a593Smuzhiyun return err;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun if (phydev->autoneg != AUTONEG_ENABLE || changed) {
547*4882a593Smuzhiyun /* A software reset is used to ensure a "commit" of the
548*4882a593Smuzhiyun * changes is done.
549*4882a593Smuzhiyun */
550*4882a593Smuzhiyun err = genphy_soft_reset(phydev);
551*4882a593Smuzhiyun if (err < 0)
552*4882a593Smuzhiyun return err;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun return 0;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
m88e1318_config_aneg(struct phy_device * phydev)558*4882a593Smuzhiyun static int m88e1318_config_aneg(struct phy_device *phydev)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun int err;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
563*4882a593Smuzhiyun MII_88E1318S_PHY_MSCR1_REG,
564*4882a593Smuzhiyun 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
565*4882a593Smuzhiyun if (err < 0)
566*4882a593Smuzhiyun return err;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun return m88e1121_config_aneg(phydev);
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /**
572*4882a593Smuzhiyun * linkmode_adv_to_fiber_adv_t
573*4882a593Smuzhiyun * @advertise: the linkmode advertisement settings
574*4882a593Smuzhiyun *
575*4882a593Smuzhiyun * A small helper function that translates linkmode advertisement
576*4882a593Smuzhiyun * settings to phy autonegotiation advertisements for the MII_ADV
577*4882a593Smuzhiyun * register for fiber link.
578*4882a593Smuzhiyun */
linkmode_adv_to_fiber_adv_t(unsigned long * advertise)579*4882a593Smuzhiyun static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun u32 result = 0;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
584*4882a593Smuzhiyun result |= ADVERTISE_1000XHALF;
585*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
586*4882a593Smuzhiyun result |= ADVERTISE_1000XFULL;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
589*4882a593Smuzhiyun linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
590*4882a593Smuzhiyun result |= ADVERTISE_1000XPSE_ASYM;
591*4882a593Smuzhiyun else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
592*4882a593Smuzhiyun result |= ADVERTISE_1000XPAUSE;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun return result;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun /**
598*4882a593Smuzhiyun * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
599*4882a593Smuzhiyun * @phydev: target phy_device struct
600*4882a593Smuzhiyun *
601*4882a593Smuzhiyun * Description: If auto-negotiation is enabled, we configure the
602*4882a593Smuzhiyun * advertising, and then restart auto-negotiation. If it is not
603*4882a593Smuzhiyun * enabled, then we write the BMCR. Adapted for fiber link in
604*4882a593Smuzhiyun * some Marvell's devices.
605*4882a593Smuzhiyun */
marvell_config_aneg_fiber(struct phy_device * phydev)606*4882a593Smuzhiyun static int marvell_config_aneg_fiber(struct phy_device *phydev)
607*4882a593Smuzhiyun {
608*4882a593Smuzhiyun int changed = 0;
609*4882a593Smuzhiyun int err;
610*4882a593Smuzhiyun u16 adv;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun if (phydev->autoneg != AUTONEG_ENABLE)
613*4882a593Smuzhiyun return genphy_setup_forced(phydev);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /* Only allow advertising what this PHY supports */
616*4882a593Smuzhiyun linkmode_and(phydev->advertising, phydev->advertising,
617*4882a593Smuzhiyun phydev->supported);
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /* Setup fiber advertisement */
622*4882a593Smuzhiyun err = phy_modify_changed(phydev, MII_ADVERTISE,
623*4882a593Smuzhiyun ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
624*4882a593Smuzhiyun ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
625*4882a593Smuzhiyun adv);
626*4882a593Smuzhiyun if (err < 0)
627*4882a593Smuzhiyun return err;
628*4882a593Smuzhiyun if (err > 0)
629*4882a593Smuzhiyun changed = 1;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun return genphy_check_and_restart_aneg(phydev, changed);
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
m88e1510_config_aneg(struct phy_device * phydev)634*4882a593Smuzhiyun static int m88e1510_config_aneg(struct phy_device *phydev)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun int err;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
639*4882a593Smuzhiyun if (err < 0)
640*4882a593Smuzhiyun goto error;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun /* Configure the copper link first */
643*4882a593Smuzhiyun err = m88e1318_config_aneg(phydev);
644*4882a593Smuzhiyun if (err < 0)
645*4882a593Smuzhiyun goto error;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /* Do not touch the fiber page if we're in copper->sgmii mode */
648*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
649*4882a593Smuzhiyun return 0;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun /* Then the fiber link */
652*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
653*4882a593Smuzhiyun if (err < 0)
654*4882a593Smuzhiyun goto error;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun err = marvell_config_aneg_fiber(phydev);
657*4882a593Smuzhiyun if (err < 0)
658*4882a593Smuzhiyun goto error;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun error:
663*4882a593Smuzhiyun marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
664*4882a593Smuzhiyun return err;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
marvell_config_led(struct phy_device * phydev)667*4882a593Smuzhiyun static void marvell_config_led(struct phy_device *phydev)
668*4882a593Smuzhiyun {
669*4882a593Smuzhiyun u16 def_config;
670*4882a593Smuzhiyun int err;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
673*4882a593Smuzhiyun /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
674*4882a593Smuzhiyun case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
675*4882a593Smuzhiyun case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
676*4882a593Smuzhiyun def_config = MII_88E1121_PHY_LED_DEF;
677*4882a593Smuzhiyun break;
678*4882a593Smuzhiyun /* Default PHY LED config:
679*4882a593Smuzhiyun * LED[0] .. 1000Mbps Link
680*4882a593Smuzhiyun * LED[1] .. 100Mbps Link
681*4882a593Smuzhiyun * LED[2] .. Blink, Activity
682*4882a593Smuzhiyun */
683*4882a593Smuzhiyun case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
684*4882a593Smuzhiyun if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
685*4882a593Smuzhiyun def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
686*4882a593Smuzhiyun else
687*4882a593Smuzhiyun def_config = MII_88E1510_PHY_LED_DEF;
688*4882a593Smuzhiyun break;
689*4882a593Smuzhiyun default:
690*4882a593Smuzhiyun return;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
694*4882a593Smuzhiyun def_config);
695*4882a593Smuzhiyun if (err < 0)
696*4882a593Smuzhiyun phydev_warn(phydev, "Fail to config marvell phy LED.\n");
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
marvell_config_init(struct phy_device * phydev)699*4882a593Smuzhiyun static int marvell_config_init(struct phy_device *phydev)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun /* Set defalut LED */
702*4882a593Smuzhiyun marvell_config_led(phydev);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun /* Set registers from marvell,reg-init DT property */
705*4882a593Smuzhiyun return marvell_of_reg_init(phydev);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
m88e3016_config_init(struct phy_device * phydev)708*4882a593Smuzhiyun static int m88e3016_config_init(struct phy_device *phydev)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun int ret;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun /* Enable Scrambler and Auto-Crossover */
713*4882a593Smuzhiyun ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
714*4882a593Smuzhiyun MII_88E3016_DISABLE_SCRAMBLER,
715*4882a593Smuzhiyun MII_88E3016_AUTO_MDIX_CROSSOVER);
716*4882a593Smuzhiyun if (ret < 0)
717*4882a593Smuzhiyun return ret;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun return marvell_config_init(phydev);
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
m88e1111_config_init_hwcfg_mode(struct phy_device * phydev,u16 mode,int fibre_copper_auto)722*4882a593Smuzhiyun static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
723*4882a593Smuzhiyun u16 mode,
724*4882a593Smuzhiyun int fibre_copper_auto)
725*4882a593Smuzhiyun {
726*4882a593Smuzhiyun if (fibre_copper_auto)
727*4882a593Smuzhiyun mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
730*4882a593Smuzhiyun MII_M1111_HWCFG_MODE_MASK |
731*4882a593Smuzhiyun MII_M1111_HWCFG_FIBER_COPPER_AUTO |
732*4882a593Smuzhiyun MII_M1111_HWCFG_FIBER_COPPER_RES,
733*4882a593Smuzhiyun mode);
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
m88e1111_config_init_rgmii_delays(struct phy_device * phydev)736*4882a593Smuzhiyun static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun int delay;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
741*4882a593Smuzhiyun delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
742*4882a593Smuzhiyun } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
743*4882a593Smuzhiyun delay = MII_M1111_RGMII_RX_DELAY;
744*4882a593Smuzhiyun } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
745*4882a593Smuzhiyun delay = MII_M1111_RGMII_TX_DELAY;
746*4882a593Smuzhiyun } else {
747*4882a593Smuzhiyun delay = 0;
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
751*4882a593Smuzhiyun MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
752*4882a593Smuzhiyun delay);
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
m88e1111_config_init_rgmii(struct phy_device * phydev)755*4882a593Smuzhiyun static int m88e1111_config_init_rgmii(struct phy_device *phydev)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun int temp;
758*4882a593Smuzhiyun int err;
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun err = m88e1111_config_init_rgmii_delays(phydev);
761*4882a593Smuzhiyun if (err < 0)
762*4882a593Smuzhiyun return err;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
765*4882a593Smuzhiyun if (temp < 0)
766*4882a593Smuzhiyun return temp;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun temp &= ~(MII_M1111_HWCFG_MODE_MASK);
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
771*4882a593Smuzhiyun temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
772*4882a593Smuzhiyun else
773*4882a593Smuzhiyun temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun
m88e1111_config_init_sgmii(struct phy_device * phydev)778*4882a593Smuzhiyun static int m88e1111_config_init_sgmii(struct phy_device *phydev)
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun int err;
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun err = m88e1111_config_init_hwcfg_mode(
783*4882a593Smuzhiyun phydev,
784*4882a593Smuzhiyun MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
785*4882a593Smuzhiyun MII_M1111_HWCFG_FIBER_COPPER_AUTO);
786*4882a593Smuzhiyun if (err < 0)
787*4882a593Smuzhiyun return err;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun /* make sure copper is selected */
790*4882a593Smuzhiyun return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun
m88e1111_config_init_rtbi(struct phy_device * phydev)793*4882a593Smuzhiyun static int m88e1111_config_init_rtbi(struct phy_device *phydev)
794*4882a593Smuzhiyun {
795*4882a593Smuzhiyun int err;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun err = m88e1111_config_init_rgmii_delays(phydev);
798*4882a593Smuzhiyun if (err < 0)
799*4882a593Smuzhiyun return err;
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun err = m88e1111_config_init_hwcfg_mode(
802*4882a593Smuzhiyun phydev,
803*4882a593Smuzhiyun MII_M1111_HWCFG_MODE_RTBI,
804*4882a593Smuzhiyun MII_M1111_HWCFG_FIBER_COPPER_AUTO);
805*4882a593Smuzhiyun if (err < 0)
806*4882a593Smuzhiyun return err;
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun /* soft reset */
809*4882a593Smuzhiyun err = genphy_soft_reset(phydev);
810*4882a593Smuzhiyun if (err < 0)
811*4882a593Smuzhiyun return err;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun return m88e1111_config_init_hwcfg_mode(
814*4882a593Smuzhiyun phydev,
815*4882a593Smuzhiyun MII_M1111_HWCFG_MODE_RTBI,
816*4882a593Smuzhiyun MII_M1111_HWCFG_FIBER_COPPER_AUTO);
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun
m88e1111_config_init(struct phy_device * phydev)819*4882a593Smuzhiyun static int m88e1111_config_init(struct phy_device *phydev)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun int err;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun if (phy_interface_is_rgmii(phydev)) {
824*4882a593Smuzhiyun err = m88e1111_config_init_rgmii(phydev);
825*4882a593Smuzhiyun if (err < 0)
826*4882a593Smuzhiyun return err;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
830*4882a593Smuzhiyun err = m88e1111_config_init_sgmii(phydev);
831*4882a593Smuzhiyun if (err < 0)
832*4882a593Smuzhiyun return err;
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
836*4882a593Smuzhiyun err = m88e1111_config_init_rtbi(phydev);
837*4882a593Smuzhiyun if (err < 0)
838*4882a593Smuzhiyun return err;
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun err = marvell_of_reg_init(phydev);
842*4882a593Smuzhiyun if (err < 0)
843*4882a593Smuzhiyun return err;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun return genphy_soft_reset(phydev);
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun
m88e1111_get_downshift(struct phy_device * phydev,u8 * data)848*4882a593Smuzhiyun static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun int val, cnt, enable;
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
853*4882a593Smuzhiyun if (val < 0)
854*4882a593Smuzhiyun return val;
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
857*4882a593Smuzhiyun cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun return 0;
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun
m88e1111_set_downshift(struct phy_device * phydev,u8 cnt)864*4882a593Smuzhiyun static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
865*4882a593Smuzhiyun {
866*4882a593Smuzhiyun int val, err;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
869*4882a593Smuzhiyun return -E2BIG;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun if (!cnt) {
872*4882a593Smuzhiyun err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
873*4882a593Smuzhiyun MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
874*4882a593Smuzhiyun } else {
875*4882a593Smuzhiyun val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
876*4882a593Smuzhiyun val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
879*4882a593Smuzhiyun MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
880*4882a593Smuzhiyun MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
881*4882a593Smuzhiyun val);
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun if (err < 0)
885*4882a593Smuzhiyun return err;
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun return genphy_soft_reset(phydev);
888*4882a593Smuzhiyun }
889*4882a593Smuzhiyun
m88e1111_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)890*4882a593Smuzhiyun static int m88e1111_get_tunable(struct phy_device *phydev,
891*4882a593Smuzhiyun struct ethtool_tunable *tuna, void *data)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun switch (tuna->id) {
894*4882a593Smuzhiyun case ETHTOOL_PHY_DOWNSHIFT:
895*4882a593Smuzhiyun return m88e1111_get_downshift(phydev, data);
896*4882a593Smuzhiyun default:
897*4882a593Smuzhiyun return -EOPNOTSUPP;
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun }
900*4882a593Smuzhiyun
m88e1111_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)901*4882a593Smuzhiyun static int m88e1111_set_tunable(struct phy_device *phydev,
902*4882a593Smuzhiyun struct ethtool_tunable *tuna, const void *data)
903*4882a593Smuzhiyun {
904*4882a593Smuzhiyun switch (tuna->id) {
905*4882a593Smuzhiyun case ETHTOOL_PHY_DOWNSHIFT:
906*4882a593Smuzhiyun return m88e1111_set_downshift(phydev, *(const u8 *)data);
907*4882a593Smuzhiyun default:
908*4882a593Smuzhiyun return -EOPNOTSUPP;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
m88e1011_get_downshift(struct phy_device * phydev,u8 * data)912*4882a593Smuzhiyun static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun int val, cnt, enable;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun val = phy_read(phydev, MII_M1011_PHY_SCR);
917*4882a593Smuzhiyun if (val < 0)
918*4882a593Smuzhiyun return val;
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
921*4882a593Smuzhiyun cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun return 0;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun
m88e1011_set_downshift(struct phy_device * phydev,u8 cnt)928*4882a593Smuzhiyun static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
929*4882a593Smuzhiyun {
930*4882a593Smuzhiyun int val, err;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
933*4882a593Smuzhiyun return -E2BIG;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun if (!cnt) {
936*4882a593Smuzhiyun err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
937*4882a593Smuzhiyun MII_M1011_PHY_SCR_DOWNSHIFT_EN);
938*4882a593Smuzhiyun } else {
939*4882a593Smuzhiyun val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
940*4882a593Smuzhiyun val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun err = phy_modify(phydev, MII_M1011_PHY_SCR,
943*4882a593Smuzhiyun MII_M1011_PHY_SCR_DOWNSHIFT_EN |
944*4882a593Smuzhiyun MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
945*4882a593Smuzhiyun val);
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun if (err < 0)
949*4882a593Smuzhiyun return err;
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun return genphy_soft_reset(phydev);
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun
m88e1011_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)954*4882a593Smuzhiyun static int m88e1011_get_tunable(struct phy_device *phydev,
955*4882a593Smuzhiyun struct ethtool_tunable *tuna, void *data)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun switch (tuna->id) {
958*4882a593Smuzhiyun case ETHTOOL_PHY_DOWNSHIFT:
959*4882a593Smuzhiyun return m88e1011_get_downshift(phydev, data);
960*4882a593Smuzhiyun default:
961*4882a593Smuzhiyun return -EOPNOTSUPP;
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun
m88e1011_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)965*4882a593Smuzhiyun static int m88e1011_set_tunable(struct phy_device *phydev,
966*4882a593Smuzhiyun struct ethtool_tunable *tuna, const void *data)
967*4882a593Smuzhiyun {
968*4882a593Smuzhiyun switch (tuna->id) {
969*4882a593Smuzhiyun case ETHTOOL_PHY_DOWNSHIFT:
970*4882a593Smuzhiyun return m88e1011_set_downshift(phydev, *(const u8 *)data);
971*4882a593Smuzhiyun default:
972*4882a593Smuzhiyun return -EOPNOTSUPP;
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun
m88e1116r_config_init(struct phy_device * phydev)976*4882a593Smuzhiyun static int m88e1116r_config_init(struct phy_device *phydev)
977*4882a593Smuzhiyun {
978*4882a593Smuzhiyun int err;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun err = genphy_soft_reset(phydev);
981*4882a593Smuzhiyun if (err < 0)
982*4882a593Smuzhiyun return err;
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun msleep(500);
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
987*4882a593Smuzhiyun if (err < 0)
988*4882a593Smuzhiyun return err;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
991*4882a593Smuzhiyun if (err < 0)
992*4882a593Smuzhiyun return err;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun err = m88e1011_set_downshift(phydev, 8);
995*4882a593Smuzhiyun if (err < 0)
996*4882a593Smuzhiyun return err;
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun if (phy_interface_is_rgmii(phydev)) {
999*4882a593Smuzhiyun err = m88e1121_config_aneg_rgmii_delays(phydev);
1000*4882a593Smuzhiyun if (err < 0)
1001*4882a593Smuzhiyun return err;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun err = genphy_soft_reset(phydev);
1005*4882a593Smuzhiyun if (err < 0)
1006*4882a593Smuzhiyun return err;
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun return marvell_config_init(phydev);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
m88e1318_config_init(struct phy_device * phydev)1011*4882a593Smuzhiyun static int m88e1318_config_init(struct phy_device *phydev)
1012*4882a593Smuzhiyun {
1013*4882a593Smuzhiyun if (phy_interrupt_is_valid(phydev)) {
1014*4882a593Smuzhiyun int err = phy_modify_paged(
1015*4882a593Smuzhiyun phydev, MII_MARVELL_LED_PAGE,
1016*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR,
1017*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1018*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1019*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1020*4882a593Smuzhiyun if (err < 0)
1021*4882a593Smuzhiyun return err;
1022*4882a593Smuzhiyun }
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun return marvell_config_init(phydev);
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun
m88e1510_config_init(struct phy_device * phydev)1027*4882a593Smuzhiyun static int m88e1510_config_init(struct phy_device *phydev)
1028*4882a593Smuzhiyun {
1029*4882a593Smuzhiyun int err;
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun /* SGMII-to-Copper mode initialization */
1032*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1033*4882a593Smuzhiyun /* Select page 18 */
1034*4882a593Smuzhiyun err = marvell_set_page(phydev, 18);
1035*4882a593Smuzhiyun if (err < 0)
1036*4882a593Smuzhiyun return err;
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1039*4882a593Smuzhiyun err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1040*4882a593Smuzhiyun MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1041*4882a593Smuzhiyun MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1042*4882a593Smuzhiyun if (err < 0)
1043*4882a593Smuzhiyun return err;
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun /* PHY reset is necessary after changing MODE[2:0] */
1046*4882a593Smuzhiyun err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, 0,
1047*4882a593Smuzhiyun MII_88E1510_GEN_CTRL_REG_1_RESET);
1048*4882a593Smuzhiyun if (err < 0)
1049*4882a593Smuzhiyun return err;
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun /* Reset page selection */
1052*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1053*4882a593Smuzhiyun if (err < 0)
1054*4882a593Smuzhiyun return err;
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun return m88e1318_config_init(phydev);
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
m88e1118_config_aneg(struct phy_device * phydev)1060*4882a593Smuzhiyun static int m88e1118_config_aneg(struct phy_device *phydev)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun int err;
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1065*4882a593Smuzhiyun if (err < 0)
1066*4882a593Smuzhiyun return err;
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun err = genphy_config_aneg(phydev);
1069*4882a593Smuzhiyun if (err < 0)
1070*4882a593Smuzhiyun return err;
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun return genphy_soft_reset(phydev);
1073*4882a593Smuzhiyun }
1074*4882a593Smuzhiyun
m88e1118_config_init(struct phy_device * phydev)1075*4882a593Smuzhiyun static int m88e1118_config_init(struct phy_device *phydev)
1076*4882a593Smuzhiyun {
1077*4882a593Smuzhiyun int err;
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun /* Change address */
1080*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1081*4882a593Smuzhiyun if (err < 0)
1082*4882a593Smuzhiyun return err;
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun /* Enable 1000 Mbit */
1085*4882a593Smuzhiyun err = phy_write(phydev, 0x15, 0x1070);
1086*4882a593Smuzhiyun if (err < 0)
1087*4882a593Smuzhiyun return err;
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun /* Change address */
1090*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
1091*4882a593Smuzhiyun if (err < 0)
1092*4882a593Smuzhiyun return err;
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun if (phy_interface_is_rgmii(phydev)) {
1095*4882a593Smuzhiyun err = m88e1121_config_aneg_rgmii_delays(phydev);
1096*4882a593Smuzhiyun if (err < 0)
1097*4882a593Smuzhiyun return err;
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun /* Adjust LED Control */
1101*4882a593Smuzhiyun if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1102*4882a593Smuzhiyun err = phy_write(phydev, 0x10, 0x1100);
1103*4882a593Smuzhiyun else
1104*4882a593Smuzhiyun err = phy_write(phydev, 0x10, 0x021e);
1105*4882a593Smuzhiyun if (err < 0)
1106*4882a593Smuzhiyun return err;
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun err = marvell_of_reg_init(phydev);
1109*4882a593Smuzhiyun if (err < 0)
1110*4882a593Smuzhiyun return err;
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun /* Reset address */
1113*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1114*4882a593Smuzhiyun if (err < 0)
1115*4882a593Smuzhiyun return err;
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun return genphy_soft_reset(phydev);
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun
m88e1149_config_init(struct phy_device * phydev)1120*4882a593Smuzhiyun static int m88e1149_config_init(struct phy_device *phydev)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun int err;
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun /* Change address */
1125*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1126*4882a593Smuzhiyun if (err < 0)
1127*4882a593Smuzhiyun return err;
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun /* Enable 1000 Mbit */
1130*4882a593Smuzhiyun err = phy_write(phydev, 0x15, 0x1048);
1131*4882a593Smuzhiyun if (err < 0)
1132*4882a593Smuzhiyun return err;
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun err = marvell_of_reg_init(phydev);
1135*4882a593Smuzhiyun if (err < 0)
1136*4882a593Smuzhiyun return err;
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun /* Reset address */
1139*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1140*4882a593Smuzhiyun if (err < 0)
1141*4882a593Smuzhiyun return err;
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun return genphy_soft_reset(phydev);
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun
m88e1145_config_init_rgmii(struct phy_device * phydev)1146*4882a593Smuzhiyun static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1147*4882a593Smuzhiyun {
1148*4882a593Smuzhiyun int err;
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun err = m88e1111_config_init_rgmii_delays(phydev);
1151*4882a593Smuzhiyun if (err < 0)
1152*4882a593Smuzhiyun return err;
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1155*4882a593Smuzhiyun err = phy_write(phydev, 0x1d, 0x0012);
1156*4882a593Smuzhiyun if (err < 0)
1157*4882a593Smuzhiyun return err;
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun err = phy_modify(phydev, 0x1e, 0x0fc0,
1160*4882a593Smuzhiyun 2 << 9 | /* 36 ohm */
1161*4882a593Smuzhiyun 2 << 6); /* 39 ohm */
1162*4882a593Smuzhiyun if (err < 0)
1163*4882a593Smuzhiyun return err;
1164*4882a593Smuzhiyun
1165*4882a593Smuzhiyun err = phy_write(phydev, 0x1d, 0x3);
1166*4882a593Smuzhiyun if (err < 0)
1167*4882a593Smuzhiyun return err;
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun err = phy_write(phydev, 0x1e, 0x8000);
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun return err;
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun
m88e1145_config_init_sgmii(struct phy_device * phydev)1174*4882a593Smuzhiyun static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun return m88e1111_config_init_hwcfg_mode(
1177*4882a593Smuzhiyun phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1178*4882a593Smuzhiyun MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1179*4882a593Smuzhiyun }
1180*4882a593Smuzhiyun
m88e1145_config_init(struct phy_device * phydev)1181*4882a593Smuzhiyun static int m88e1145_config_init(struct phy_device *phydev)
1182*4882a593Smuzhiyun {
1183*4882a593Smuzhiyun int err;
1184*4882a593Smuzhiyun
1185*4882a593Smuzhiyun /* Take care of errata E0 & E1 */
1186*4882a593Smuzhiyun err = phy_write(phydev, 0x1d, 0x001b);
1187*4882a593Smuzhiyun if (err < 0)
1188*4882a593Smuzhiyun return err;
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun err = phy_write(phydev, 0x1e, 0x418f);
1191*4882a593Smuzhiyun if (err < 0)
1192*4882a593Smuzhiyun return err;
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun err = phy_write(phydev, 0x1d, 0x0016);
1195*4882a593Smuzhiyun if (err < 0)
1196*4882a593Smuzhiyun return err;
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun err = phy_write(phydev, 0x1e, 0xa2da);
1199*4882a593Smuzhiyun if (err < 0)
1200*4882a593Smuzhiyun return err;
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1203*4882a593Smuzhiyun err = m88e1145_config_init_rgmii(phydev);
1204*4882a593Smuzhiyun if (err < 0)
1205*4882a593Smuzhiyun return err;
1206*4882a593Smuzhiyun }
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1209*4882a593Smuzhiyun err = m88e1145_config_init_sgmii(phydev);
1210*4882a593Smuzhiyun if (err < 0)
1211*4882a593Smuzhiyun return err;
1212*4882a593Smuzhiyun }
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun err = marvell_of_reg_init(phydev);
1215*4882a593Smuzhiyun if (err < 0)
1216*4882a593Smuzhiyun return err;
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun return 0;
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun
m88e1540_get_fld(struct phy_device * phydev,u8 * msecs)1221*4882a593Smuzhiyun static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun int val;
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1226*4882a593Smuzhiyun if (val < 0)
1227*4882a593Smuzhiyun return val;
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1230*4882a593Smuzhiyun *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1231*4882a593Smuzhiyun return 0;
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun switch (val) {
1237*4882a593Smuzhiyun case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1238*4882a593Smuzhiyun *msecs = 0;
1239*4882a593Smuzhiyun break;
1240*4882a593Smuzhiyun case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1241*4882a593Smuzhiyun *msecs = 10;
1242*4882a593Smuzhiyun break;
1243*4882a593Smuzhiyun case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1244*4882a593Smuzhiyun *msecs = 20;
1245*4882a593Smuzhiyun break;
1246*4882a593Smuzhiyun case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1247*4882a593Smuzhiyun *msecs = 40;
1248*4882a593Smuzhiyun break;
1249*4882a593Smuzhiyun default:
1250*4882a593Smuzhiyun return -EINVAL;
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun return 0;
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun
m88e1540_set_fld(struct phy_device * phydev,const u8 * msecs)1256*4882a593Smuzhiyun static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun struct ethtool_eee eee;
1259*4882a593Smuzhiyun int val, ret;
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1262*4882a593Smuzhiyun return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1263*4882a593Smuzhiyun MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun /* According to the Marvell data sheet EEE must be disabled for
1266*4882a593Smuzhiyun * Fast Link Down detection to work properly
1267*4882a593Smuzhiyun */
1268*4882a593Smuzhiyun ret = phy_ethtool_get_eee(phydev, &eee);
1269*4882a593Smuzhiyun if (!ret && eee.eee_enabled) {
1270*4882a593Smuzhiyun phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1271*4882a593Smuzhiyun return -EBUSY;
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun if (*msecs <= 5)
1275*4882a593Smuzhiyun val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1276*4882a593Smuzhiyun else if (*msecs <= 15)
1277*4882a593Smuzhiyun val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1278*4882a593Smuzhiyun else if (*msecs <= 30)
1279*4882a593Smuzhiyun val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1280*4882a593Smuzhiyun else
1281*4882a593Smuzhiyun val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1286*4882a593Smuzhiyun MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1287*4882a593Smuzhiyun if (ret)
1288*4882a593Smuzhiyun return ret;
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1291*4882a593Smuzhiyun MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1292*4882a593Smuzhiyun }
1293*4882a593Smuzhiyun
m88e1540_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)1294*4882a593Smuzhiyun static int m88e1540_get_tunable(struct phy_device *phydev,
1295*4882a593Smuzhiyun struct ethtool_tunable *tuna, void *data)
1296*4882a593Smuzhiyun {
1297*4882a593Smuzhiyun switch (tuna->id) {
1298*4882a593Smuzhiyun case ETHTOOL_PHY_FAST_LINK_DOWN:
1299*4882a593Smuzhiyun return m88e1540_get_fld(phydev, data);
1300*4882a593Smuzhiyun case ETHTOOL_PHY_DOWNSHIFT:
1301*4882a593Smuzhiyun return m88e1011_get_downshift(phydev, data);
1302*4882a593Smuzhiyun default:
1303*4882a593Smuzhiyun return -EOPNOTSUPP;
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun
m88e1540_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)1307*4882a593Smuzhiyun static int m88e1540_set_tunable(struct phy_device *phydev,
1308*4882a593Smuzhiyun struct ethtool_tunable *tuna, const void *data)
1309*4882a593Smuzhiyun {
1310*4882a593Smuzhiyun switch (tuna->id) {
1311*4882a593Smuzhiyun case ETHTOOL_PHY_FAST_LINK_DOWN:
1312*4882a593Smuzhiyun return m88e1540_set_fld(phydev, data);
1313*4882a593Smuzhiyun case ETHTOOL_PHY_DOWNSHIFT:
1314*4882a593Smuzhiyun return m88e1011_set_downshift(phydev, *(const u8 *)data);
1315*4882a593Smuzhiyun default:
1316*4882a593Smuzhiyun return -EOPNOTSUPP;
1317*4882a593Smuzhiyun }
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun /* The VOD can be out of specification on link up. Poke an
1321*4882a593Smuzhiyun * undocumented register, in an undocumented page, with a magic value
1322*4882a593Smuzhiyun * to fix this.
1323*4882a593Smuzhiyun */
m88e6390_errata(struct phy_device * phydev)1324*4882a593Smuzhiyun static int m88e6390_errata(struct phy_device *phydev)
1325*4882a593Smuzhiyun {
1326*4882a593Smuzhiyun int err;
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun err = phy_write(phydev, MII_BMCR,
1329*4882a593Smuzhiyun BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1330*4882a593Smuzhiyun if (err)
1331*4882a593Smuzhiyun return err;
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun usleep_range(300, 400);
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1336*4882a593Smuzhiyun if (err)
1337*4882a593Smuzhiyun return err;
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun return genphy_soft_reset(phydev);
1340*4882a593Smuzhiyun }
1341*4882a593Smuzhiyun
m88e6390_config_aneg(struct phy_device * phydev)1342*4882a593Smuzhiyun static int m88e6390_config_aneg(struct phy_device *phydev)
1343*4882a593Smuzhiyun {
1344*4882a593Smuzhiyun int err;
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun err = m88e6390_errata(phydev);
1347*4882a593Smuzhiyun if (err)
1348*4882a593Smuzhiyun return err;
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun return m88e1510_config_aneg(phydev);
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun /**
1354*4882a593Smuzhiyun * fiber_lpa_mod_linkmode_lpa_t
1355*4882a593Smuzhiyun * @advertising: the linkmode advertisement settings
1356*4882a593Smuzhiyun * @lpa: value of the MII_LPA register for fiber link
1357*4882a593Smuzhiyun *
1358*4882a593Smuzhiyun * A small helper function that translates MII_LPA bits to linkmode LP
1359*4882a593Smuzhiyun * advertisement settings. Other bits in advertising are left
1360*4882a593Smuzhiyun * unchanged.
1361*4882a593Smuzhiyun */
fiber_lpa_mod_linkmode_lpa_t(unsigned long * advertising,u32 lpa)1362*4882a593Smuzhiyun static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1363*4882a593Smuzhiyun {
1364*4882a593Smuzhiyun linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1365*4882a593Smuzhiyun advertising, lpa & LPA_1000XHALF);
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1368*4882a593Smuzhiyun advertising, lpa & LPA_1000XFULL);
1369*4882a593Smuzhiyun }
1370*4882a593Smuzhiyun
marvell_read_status_page_an(struct phy_device * phydev,int fiber,int status)1371*4882a593Smuzhiyun static int marvell_read_status_page_an(struct phy_device *phydev,
1372*4882a593Smuzhiyun int fiber, int status)
1373*4882a593Smuzhiyun {
1374*4882a593Smuzhiyun int lpa;
1375*4882a593Smuzhiyun int err;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1378*4882a593Smuzhiyun phydev->link = 0;
1379*4882a593Smuzhiyun return 0;
1380*4882a593Smuzhiyun }
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1383*4882a593Smuzhiyun phydev->duplex = DUPLEX_FULL;
1384*4882a593Smuzhiyun else
1385*4882a593Smuzhiyun phydev->duplex = DUPLEX_HALF;
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1388*4882a593Smuzhiyun case MII_M1011_PHY_STATUS_1000:
1389*4882a593Smuzhiyun phydev->speed = SPEED_1000;
1390*4882a593Smuzhiyun break;
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun case MII_M1011_PHY_STATUS_100:
1393*4882a593Smuzhiyun phydev->speed = SPEED_100;
1394*4882a593Smuzhiyun break;
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun default:
1397*4882a593Smuzhiyun phydev->speed = SPEED_10;
1398*4882a593Smuzhiyun break;
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun if (!fiber) {
1402*4882a593Smuzhiyun err = genphy_read_lpa(phydev);
1403*4882a593Smuzhiyun if (err < 0)
1404*4882a593Smuzhiyun return err;
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun phy_resolve_aneg_pause(phydev);
1407*4882a593Smuzhiyun } else {
1408*4882a593Smuzhiyun lpa = phy_read(phydev, MII_LPA);
1409*4882a593Smuzhiyun if (lpa < 0)
1410*4882a593Smuzhiyun return lpa;
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun /* The fiber link is only 1000M capable */
1413*4882a593Smuzhiyun fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun if (phydev->duplex == DUPLEX_FULL) {
1416*4882a593Smuzhiyun if (!(lpa & LPA_PAUSE_FIBER)) {
1417*4882a593Smuzhiyun phydev->pause = 0;
1418*4882a593Smuzhiyun phydev->asym_pause = 0;
1419*4882a593Smuzhiyun } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1420*4882a593Smuzhiyun phydev->pause = 1;
1421*4882a593Smuzhiyun phydev->asym_pause = 1;
1422*4882a593Smuzhiyun } else {
1423*4882a593Smuzhiyun phydev->pause = 1;
1424*4882a593Smuzhiyun phydev->asym_pause = 0;
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun return 0;
1430*4882a593Smuzhiyun }
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun /* marvell_read_status_page
1433*4882a593Smuzhiyun *
1434*4882a593Smuzhiyun * Description:
1435*4882a593Smuzhiyun * Check the link, then figure out the current state
1436*4882a593Smuzhiyun * by comparing what we advertise with what the link partner
1437*4882a593Smuzhiyun * advertises. Start by checking the gigabit possibilities,
1438*4882a593Smuzhiyun * then move on to 10/100.
1439*4882a593Smuzhiyun */
marvell_read_status_page(struct phy_device * phydev,int page)1440*4882a593Smuzhiyun static int marvell_read_status_page(struct phy_device *phydev, int page)
1441*4882a593Smuzhiyun {
1442*4882a593Smuzhiyun int status;
1443*4882a593Smuzhiyun int fiber;
1444*4882a593Smuzhiyun int err;
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun status = phy_read(phydev, MII_M1011_PHY_STATUS);
1447*4882a593Smuzhiyun if (status < 0)
1448*4882a593Smuzhiyun return status;
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun /* Use the generic register for copper link status,
1451*4882a593Smuzhiyun * and the PHY status register for fiber link status.
1452*4882a593Smuzhiyun */
1453*4882a593Smuzhiyun if (page == MII_MARVELL_FIBER_PAGE) {
1454*4882a593Smuzhiyun phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1455*4882a593Smuzhiyun } else {
1456*4882a593Smuzhiyun err = genphy_update_link(phydev);
1457*4882a593Smuzhiyun if (err)
1458*4882a593Smuzhiyun return err;
1459*4882a593Smuzhiyun }
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun if (page == MII_MARVELL_FIBER_PAGE)
1462*4882a593Smuzhiyun fiber = 1;
1463*4882a593Smuzhiyun else
1464*4882a593Smuzhiyun fiber = 0;
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun linkmode_zero(phydev->lp_advertising);
1467*4882a593Smuzhiyun phydev->pause = 0;
1468*4882a593Smuzhiyun phydev->asym_pause = 0;
1469*4882a593Smuzhiyun phydev->speed = SPEED_UNKNOWN;
1470*4882a593Smuzhiyun phydev->duplex = DUPLEX_UNKNOWN;
1471*4882a593Smuzhiyun phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun if (phydev->autoneg == AUTONEG_ENABLE)
1474*4882a593Smuzhiyun err = marvell_read_status_page_an(phydev, fiber, status);
1475*4882a593Smuzhiyun else
1476*4882a593Smuzhiyun err = genphy_read_status_fixed(phydev);
1477*4882a593Smuzhiyun
1478*4882a593Smuzhiyun return err;
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun /* marvell_read_status
1482*4882a593Smuzhiyun *
1483*4882a593Smuzhiyun * Some Marvell's phys have two modes: fiber and copper.
1484*4882a593Smuzhiyun * Both need status checked.
1485*4882a593Smuzhiyun * Description:
1486*4882a593Smuzhiyun * First, check the fiber link and status.
1487*4882a593Smuzhiyun * If the fiber link is down, check the copper link and status which
1488*4882a593Smuzhiyun * will be the default value if both link are down.
1489*4882a593Smuzhiyun */
marvell_read_status(struct phy_device * phydev)1490*4882a593Smuzhiyun static int marvell_read_status(struct phy_device *phydev)
1491*4882a593Smuzhiyun {
1492*4882a593Smuzhiyun int err;
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun /* Check the fiber mode first */
1495*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1496*4882a593Smuzhiyun phydev->supported) &&
1497*4882a593Smuzhiyun phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1498*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1499*4882a593Smuzhiyun if (err < 0)
1500*4882a593Smuzhiyun goto error;
1501*4882a593Smuzhiyun
1502*4882a593Smuzhiyun err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1503*4882a593Smuzhiyun if (err < 0)
1504*4882a593Smuzhiyun goto error;
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun /* If the fiber link is up, it is the selected and
1507*4882a593Smuzhiyun * used link. In this case, we need to stay in the
1508*4882a593Smuzhiyun * fiber page. Please to be careful about that, avoid
1509*4882a593Smuzhiyun * to restore Copper page in other functions which
1510*4882a593Smuzhiyun * could break the behaviour for some fiber phy like
1511*4882a593Smuzhiyun * 88E1512.
1512*4882a593Smuzhiyun */
1513*4882a593Smuzhiyun if (phydev->link)
1514*4882a593Smuzhiyun return 0;
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun /* If fiber link is down, check and save copper mode state */
1517*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1518*4882a593Smuzhiyun if (err < 0)
1519*4882a593Smuzhiyun goto error;
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun error:
1525*4882a593Smuzhiyun marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1526*4882a593Smuzhiyun return err;
1527*4882a593Smuzhiyun }
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun /* marvell_suspend
1530*4882a593Smuzhiyun *
1531*4882a593Smuzhiyun * Some Marvell's phys have two modes: fiber and copper.
1532*4882a593Smuzhiyun * Both need to be suspended
1533*4882a593Smuzhiyun */
marvell_suspend(struct phy_device * phydev)1534*4882a593Smuzhiyun static int marvell_suspend(struct phy_device *phydev)
1535*4882a593Smuzhiyun {
1536*4882a593Smuzhiyun int err;
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun /* Suspend the fiber mode first */
1539*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1540*4882a593Smuzhiyun phydev->supported)) {
1541*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1542*4882a593Smuzhiyun if (err < 0)
1543*4882a593Smuzhiyun goto error;
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun /* With the page set, use the generic suspend */
1546*4882a593Smuzhiyun err = genphy_suspend(phydev);
1547*4882a593Smuzhiyun if (err < 0)
1548*4882a593Smuzhiyun goto error;
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun /* Then, the copper link */
1551*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1552*4882a593Smuzhiyun if (err < 0)
1553*4882a593Smuzhiyun goto error;
1554*4882a593Smuzhiyun }
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun /* With the page set, use the generic suspend */
1557*4882a593Smuzhiyun return genphy_suspend(phydev);
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun error:
1560*4882a593Smuzhiyun marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1561*4882a593Smuzhiyun return err;
1562*4882a593Smuzhiyun }
1563*4882a593Smuzhiyun
1564*4882a593Smuzhiyun /* marvell_resume
1565*4882a593Smuzhiyun *
1566*4882a593Smuzhiyun * Some Marvell's phys have two modes: fiber and copper.
1567*4882a593Smuzhiyun * Both need to be resumed
1568*4882a593Smuzhiyun */
marvell_resume(struct phy_device * phydev)1569*4882a593Smuzhiyun static int marvell_resume(struct phy_device *phydev)
1570*4882a593Smuzhiyun {
1571*4882a593Smuzhiyun int err;
1572*4882a593Smuzhiyun
1573*4882a593Smuzhiyun /* Resume the fiber mode first */
1574*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1575*4882a593Smuzhiyun phydev->supported)) {
1576*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1577*4882a593Smuzhiyun if (err < 0)
1578*4882a593Smuzhiyun goto error;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun /* With the page set, use the generic resume */
1581*4882a593Smuzhiyun err = genphy_resume(phydev);
1582*4882a593Smuzhiyun if (err < 0)
1583*4882a593Smuzhiyun goto error;
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun /* Then, the copper link */
1586*4882a593Smuzhiyun err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1587*4882a593Smuzhiyun if (err < 0)
1588*4882a593Smuzhiyun goto error;
1589*4882a593Smuzhiyun }
1590*4882a593Smuzhiyun
1591*4882a593Smuzhiyun /* With the page set, use the generic resume */
1592*4882a593Smuzhiyun return genphy_resume(phydev);
1593*4882a593Smuzhiyun
1594*4882a593Smuzhiyun error:
1595*4882a593Smuzhiyun marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1596*4882a593Smuzhiyun return err;
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun
marvell_aneg_done(struct phy_device * phydev)1599*4882a593Smuzhiyun static int marvell_aneg_done(struct phy_device *phydev)
1600*4882a593Smuzhiyun {
1601*4882a593Smuzhiyun int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1602*4882a593Smuzhiyun
1603*4882a593Smuzhiyun return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun
m88e1121_did_interrupt(struct phy_device * phydev)1606*4882a593Smuzhiyun static int m88e1121_did_interrupt(struct phy_device *phydev)
1607*4882a593Smuzhiyun {
1608*4882a593Smuzhiyun int imask;
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun imask = phy_read(phydev, MII_M1011_IEVENT);
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun if (imask & MII_M1011_IMASK_INIT)
1613*4882a593Smuzhiyun return 1;
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun return 0;
1616*4882a593Smuzhiyun }
1617*4882a593Smuzhiyun
m88e1318_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)1618*4882a593Smuzhiyun static void m88e1318_get_wol(struct phy_device *phydev,
1619*4882a593Smuzhiyun struct ethtool_wolinfo *wol)
1620*4882a593Smuzhiyun {
1621*4882a593Smuzhiyun int ret;
1622*4882a593Smuzhiyun
1623*4882a593Smuzhiyun wol->supported = WAKE_MAGIC;
1624*4882a593Smuzhiyun wol->wolopts = 0;
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1627*4882a593Smuzhiyun MII_88E1318S_PHY_WOL_CTRL);
1628*4882a593Smuzhiyun if (ret >= 0 && ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1629*4882a593Smuzhiyun wol->wolopts |= WAKE_MAGIC;
1630*4882a593Smuzhiyun }
1631*4882a593Smuzhiyun
m88e1318_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)1632*4882a593Smuzhiyun static int m88e1318_set_wol(struct phy_device *phydev,
1633*4882a593Smuzhiyun struct ethtool_wolinfo *wol)
1634*4882a593Smuzhiyun {
1635*4882a593Smuzhiyun int err = 0, oldpage;
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun oldpage = phy_save_page(phydev);
1638*4882a593Smuzhiyun if (oldpage < 0)
1639*4882a593Smuzhiyun goto error;
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun if (wol->wolopts & WAKE_MAGIC) {
1642*4882a593Smuzhiyun /* Explicitly switch to page 0x00, just to be sure */
1643*4882a593Smuzhiyun err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1644*4882a593Smuzhiyun if (err < 0)
1645*4882a593Smuzhiyun goto error;
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun /* If WOL event happened once, the LED[2] interrupt pin
1648*4882a593Smuzhiyun * will not be cleared unless we reading the interrupt status
1649*4882a593Smuzhiyun * register. If interrupts are in use, the normal interrupt
1650*4882a593Smuzhiyun * handling will clear the WOL event. Clear the WOL event
1651*4882a593Smuzhiyun * before enabling it if !phy_interrupt_is_valid()
1652*4882a593Smuzhiyun */
1653*4882a593Smuzhiyun if (!phy_interrupt_is_valid(phydev))
1654*4882a593Smuzhiyun __phy_read(phydev, MII_M1011_IEVENT);
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun /* Enable the WOL interrupt */
1657*4882a593Smuzhiyun err = __phy_modify(phydev, MII_88E1318S_PHY_CSIER, 0,
1658*4882a593Smuzhiyun MII_88E1318S_PHY_CSIER_WOL_EIE);
1659*4882a593Smuzhiyun if (err < 0)
1660*4882a593Smuzhiyun goto error;
1661*4882a593Smuzhiyun
1662*4882a593Smuzhiyun err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1663*4882a593Smuzhiyun if (err < 0)
1664*4882a593Smuzhiyun goto error;
1665*4882a593Smuzhiyun
1666*4882a593Smuzhiyun /* Setup LED[2] as interrupt pin (active low) */
1667*4882a593Smuzhiyun err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1668*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1669*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1670*4882a593Smuzhiyun MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1671*4882a593Smuzhiyun if (err < 0)
1672*4882a593Smuzhiyun goto error;
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1675*4882a593Smuzhiyun if (err < 0)
1676*4882a593Smuzhiyun goto error;
1677*4882a593Smuzhiyun
1678*4882a593Smuzhiyun /* Store the device address for the magic packet */
1679*4882a593Smuzhiyun err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1680*4882a593Smuzhiyun ((phydev->attached_dev->dev_addr[5] << 8) |
1681*4882a593Smuzhiyun phydev->attached_dev->dev_addr[4]));
1682*4882a593Smuzhiyun if (err < 0)
1683*4882a593Smuzhiyun goto error;
1684*4882a593Smuzhiyun err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1685*4882a593Smuzhiyun ((phydev->attached_dev->dev_addr[3] << 8) |
1686*4882a593Smuzhiyun phydev->attached_dev->dev_addr[2]));
1687*4882a593Smuzhiyun if (err < 0)
1688*4882a593Smuzhiyun goto error;
1689*4882a593Smuzhiyun err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1690*4882a593Smuzhiyun ((phydev->attached_dev->dev_addr[1] << 8) |
1691*4882a593Smuzhiyun phydev->attached_dev->dev_addr[0]));
1692*4882a593Smuzhiyun if (err < 0)
1693*4882a593Smuzhiyun goto error;
1694*4882a593Smuzhiyun
1695*4882a593Smuzhiyun /* Clear WOL status and enable magic packet matching */
1696*4882a593Smuzhiyun err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1697*4882a593Smuzhiyun MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1698*4882a593Smuzhiyun MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1699*4882a593Smuzhiyun if (err < 0)
1700*4882a593Smuzhiyun goto error;
1701*4882a593Smuzhiyun } else {
1702*4882a593Smuzhiyun err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1703*4882a593Smuzhiyun if (err < 0)
1704*4882a593Smuzhiyun goto error;
1705*4882a593Smuzhiyun
1706*4882a593Smuzhiyun /* Clear WOL status and disable magic packet matching */
1707*4882a593Smuzhiyun err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1708*4882a593Smuzhiyun MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1709*4882a593Smuzhiyun MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1710*4882a593Smuzhiyun if (err < 0)
1711*4882a593Smuzhiyun goto error;
1712*4882a593Smuzhiyun }
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun error:
1715*4882a593Smuzhiyun return phy_restore_page(phydev, oldpage, err);
1716*4882a593Smuzhiyun }
1717*4882a593Smuzhiyun
marvell_get_sset_count(struct phy_device * phydev)1718*4882a593Smuzhiyun static int marvell_get_sset_count(struct phy_device *phydev)
1719*4882a593Smuzhiyun {
1720*4882a593Smuzhiyun if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1721*4882a593Smuzhiyun phydev->supported))
1722*4882a593Smuzhiyun return ARRAY_SIZE(marvell_hw_stats);
1723*4882a593Smuzhiyun else
1724*4882a593Smuzhiyun return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1725*4882a593Smuzhiyun }
1726*4882a593Smuzhiyun
marvell_get_strings(struct phy_device * phydev,u8 * data)1727*4882a593Smuzhiyun static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1728*4882a593Smuzhiyun {
1729*4882a593Smuzhiyun int count = marvell_get_sset_count(phydev);
1730*4882a593Smuzhiyun int i;
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun for (i = 0; i < count; i++) {
1733*4882a593Smuzhiyun strlcpy(data + i * ETH_GSTRING_LEN,
1734*4882a593Smuzhiyun marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1735*4882a593Smuzhiyun }
1736*4882a593Smuzhiyun }
1737*4882a593Smuzhiyun
marvell_get_stat(struct phy_device * phydev,int i)1738*4882a593Smuzhiyun static u64 marvell_get_stat(struct phy_device *phydev, int i)
1739*4882a593Smuzhiyun {
1740*4882a593Smuzhiyun struct marvell_hw_stat stat = marvell_hw_stats[i];
1741*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
1742*4882a593Smuzhiyun int val;
1743*4882a593Smuzhiyun u64 ret;
1744*4882a593Smuzhiyun
1745*4882a593Smuzhiyun val = phy_read_paged(phydev, stat.page, stat.reg);
1746*4882a593Smuzhiyun if (val < 0) {
1747*4882a593Smuzhiyun ret = U64_MAX;
1748*4882a593Smuzhiyun } else {
1749*4882a593Smuzhiyun val = val & ((1 << stat.bits) - 1);
1750*4882a593Smuzhiyun priv->stats[i] += val;
1751*4882a593Smuzhiyun ret = priv->stats[i];
1752*4882a593Smuzhiyun }
1753*4882a593Smuzhiyun
1754*4882a593Smuzhiyun return ret;
1755*4882a593Smuzhiyun }
1756*4882a593Smuzhiyun
marvell_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)1757*4882a593Smuzhiyun static void marvell_get_stats(struct phy_device *phydev,
1758*4882a593Smuzhiyun struct ethtool_stats *stats, u64 *data)
1759*4882a593Smuzhiyun {
1760*4882a593Smuzhiyun int count = marvell_get_sset_count(phydev);
1761*4882a593Smuzhiyun int i;
1762*4882a593Smuzhiyun
1763*4882a593Smuzhiyun for (i = 0; i < count; i++)
1764*4882a593Smuzhiyun data[i] = marvell_get_stat(phydev, i);
1765*4882a593Smuzhiyun }
1766*4882a593Smuzhiyun
marvell_vct5_wait_complete(struct phy_device * phydev)1767*4882a593Smuzhiyun static int marvell_vct5_wait_complete(struct phy_device *phydev)
1768*4882a593Smuzhiyun {
1769*4882a593Smuzhiyun int i;
1770*4882a593Smuzhiyun int val;
1771*4882a593Smuzhiyun
1772*4882a593Smuzhiyun for (i = 0; i < 32; i++) {
1773*4882a593Smuzhiyun val = __phy_read(phydev, MII_VCT5_CTRL);
1774*4882a593Smuzhiyun if (val < 0)
1775*4882a593Smuzhiyun return val;
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun if (val & MII_VCT5_CTRL_COMPLETE)
1778*4882a593Smuzhiyun return 0;
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
1782*4882a593Smuzhiyun return -ETIMEDOUT;
1783*4882a593Smuzhiyun }
1784*4882a593Smuzhiyun
marvell_vct5_amplitude(struct phy_device * phydev,int pair)1785*4882a593Smuzhiyun static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
1786*4882a593Smuzhiyun {
1787*4882a593Smuzhiyun int amplitude;
1788*4882a593Smuzhiyun int val;
1789*4882a593Smuzhiyun int reg;
1790*4882a593Smuzhiyun
1791*4882a593Smuzhiyun reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
1792*4882a593Smuzhiyun val = __phy_read(phydev, reg);
1793*4882a593Smuzhiyun
1794*4882a593Smuzhiyun if (val < 0)
1795*4882a593Smuzhiyun return 0;
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
1798*4882a593Smuzhiyun MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
1801*4882a593Smuzhiyun amplitude = -amplitude;
1802*4882a593Smuzhiyun
1803*4882a593Smuzhiyun return 1000 * amplitude / 128;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun
marvell_vct5_distance2cm(int distance)1806*4882a593Smuzhiyun static u32 marvell_vct5_distance2cm(int distance)
1807*4882a593Smuzhiyun {
1808*4882a593Smuzhiyun return distance * 805 / 10;
1809*4882a593Smuzhiyun }
1810*4882a593Smuzhiyun
marvell_vct5_cm2distance(int cm)1811*4882a593Smuzhiyun static u32 marvell_vct5_cm2distance(int cm)
1812*4882a593Smuzhiyun {
1813*4882a593Smuzhiyun return cm * 10 / 805;
1814*4882a593Smuzhiyun }
1815*4882a593Smuzhiyun
marvell_vct5_amplitude_distance(struct phy_device * phydev,int distance,int pair)1816*4882a593Smuzhiyun static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
1817*4882a593Smuzhiyun int distance, int pair)
1818*4882a593Smuzhiyun {
1819*4882a593Smuzhiyun u16 reg;
1820*4882a593Smuzhiyun int err;
1821*4882a593Smuzhiyun int mV;
1822*4882a593Smuzhiyun int i;
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
1825*4882a593Smuzhiyun distance);
1826*4882a593Smuzhiyun if (err)
1827*4882a593Smuzhiyun return err;
1828*4882a593Smuzhiyun
1829*4882a593Smuzhiyun reg = MII_VCT5_CTRL_ENABLE |
1830*4882a593Smuzhiyun MII_VCT5_CTRL_TX_SAME_CHANNEL |
1831*4882a593Smuzhiyun MII_VCT5_CTRL_SAMPLES_DEFAULT |
1832*4882a593Smuzhiyun MII_VCT5_CTRL_SAMPLE_POINT |
1833*4882a593Smuzhiyun MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
1834*4882a593Smuzhiyun err = __phy_write(phydev, MII_VCT5_CTRL, reg);
1835*4882a593Smuzhiyun if (err)
1836*4882a593Smuzhiyun return err;
1837*4882a593Smuzhiyun
1838*4882a593Smuzhiyun err = marvell_vct5_wait_complete(phydev);
1839*4882a593Smuzhiyun if (err)
1840*4882a593Smuzhiyun return err;
1841*4882a593Smuzhiyun
1842*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
1843*4882a593Smuzhiyun if (pair != PHY_PAIR_ALL && i != pair)
1844*4882a593Smuzhiyun continue;
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun mV = marvell_vct5_amplitude(phydev, i);
1847*4882a593Smuzhiyun ethnl_cable_test_amplitude(phydev, i, mV);
1848*4882a593Smuzhiyun }
1849*4882a593Smuzhiyun
1850*4882a593Smuzhiyun return 0;
1851*4882a593Smuzhiyun }
1852*4882a593Smuzhiyun
marvell_vct5_amplitude_graph(struct phy_device * phydev)1853*4882a593Smuzhiyun static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
1854*4882a593Smuzhiyun {
1855*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
1856*4882a593Smuzhiyun int distance;
1857*4882a593Smuzhiyun u16 width;
1858*4882a593Smuzhiyun int page;
1859*4882a593Smuzhiyun int err;
1860*4882a593Smuzhiyun u16 reg;
1861*4882a593Smuzhiyun
1862*4882a593Smuzhiyun if (priv->first <= TDR_SHORT_CABLE_LENGTH)
1863*4882a593Smuzhiyun width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
1864*4882a593Smuzhiyun else
1865*4882a593Smuzhiyun width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1868*4882a593Smuzhiyun MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1869*4882a593Smuzhiyun MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1870*4882a593Smuzhiyun
1871*4882a593Smuzhiyun err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1872*4882a593Smuzhiyun MII_VCT5_TX_PULSE_CTRL, reg);
1873*4882a593Smuzhiyun if (err)
1874*4882a593Smuzhiyun return err;
1875*4882a593Smuzhiyun
1876*4882a593Smuzhiyun /* Reading the TDR data is very MDIO heavy. We need to optimize
1877*4882a593Smuzhiyun * access to keep the time to a minimum. So lock the bus once,
1878*4882a593Smuzhiyun * and don't release it until complete. We can then avoid having
1879*4882a593Smuzhiyun * to change the page for every access, greatly speeding things
1880*4882a593Smuzhiyun * up.
1881*4882a593Smuzhiyun */
1882*4882a593Smuzhiyun page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
1883*4882a593Smuzhiyun if (page < 0)
1884*4882a593Smuzhiyun goto restore_page;
1885*4882a593Smuzhiyun
1886*4882a593Smuzhiyun for (distance = priv->first;
1887*4882a593Smuzhiyun distance <= priv->last;
1888*4882a593Smuzhiyun distance += priv->step) {
1889*4882a593Smuzhiyun err = marvell_vct5_amplitude_distance(phydev, distance,
1890*4882a593Smuzhiyun priv->pair);
1891*4882a593Smuzhiyun if (err)
1892*4882a593Smuzhiyun goto restore_page;
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun if (distance > TDR_SHORT_CABLE_LENGTH &&
1895*4882a593Smuzhiyun width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
1896*4882a593Smuzhiyun width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1897*4882a593Smuzhiyun reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1898*4882a593Smuzhiyun MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1899*4882a593Smuzhiyun MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1900*4882a593Smuzhiyun err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
1901*4882a593Smuzhiyun if (err)
1902*4882a593Smuzhiyun goto restore_page;
1903*4882a593Smuzhiyun }
1904*4882a593Smuzhiyun }
1905*4882a593Smuzhiyun
1906*4882a593Smuzhiyun restore_page:
1907*4882a593Smuzhiyun return phy_restore_page(phydev, page, err);
1908*4882a593Smuzhiyun }
1909*4882a593Smuzhiyun
marvell_cable_test_start_common(struct phy_device * phydev)1910*4882a593Smuzhiyun static int marvell_cable_test_start_common(struct phy_device *phydev)
1911*4882a593Smuzhiyun {
1912*4882a593Smuzhiyun int bmcr, bmsr, ret;
1913*4882a593Smuzhiyun
1914*4882a593Smuzhiyun /* If auto-negotiation is enabled, but not complete, the cable
1915*4882a593Smuzhiyun * test never completes. So disable auto-neg.
1916*4882a593Smuzhiyun */
1917*4882a593Smuzhiyun bmcr = phy_read(phydev, MII_BMCR);
1918*4882a593Smuzhiyun if (bmcr < 0)
1919*4882a593Smuzhiyun return bmcr;
1920*4882a593Smuzhiyun
1921*4882a593Smuzhiyun bmsr = phy_read(phydev, MII_BMSR);
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun if (bmsr < 0)
1924*4882a593Smuzhiyun return bmsr;
1925*4882a593Smuzhiyun
1926*4882a593Smuzhiyun if (bmcr & BMCR_ANENABLE) {
1927*4882a593Smuzhiyun ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1928*4882a593Smuzhiyun if (ret < 0)
1929*4882a593Smuzhiyun return ret;
1930*4882a593Smuzhiyun ret = genphy_soft_reset(phydev);
1931*4882a593Smuzhiyun if (ret < 0)
1932*4882a593Smuzhiyun return ret;
1933*4882a593Smuzhiyun }
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun /* If the link is up, allow it some time to go down */
1936*4882a593Smuzhiyun if (bmsr & BMSR_LSTATUS)
1937*4882a593Smuzhiyun msleep(1500);
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun return 0;
1940*4882a593Smuzhiyun }
1941*4882a593Smuzhiyun
marvell_vct7_cable_test_start(struct phy_device * phydev)1942*4882a593Smuzhiyun static int marvell_vct7_cable_test_start(struct phy_device *phydev)
1943*4882a593Smuzhiyun {
1944*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
1945*4882a593Smuzhiyun int ret;
1946*4882a593Smuzhiyun
1947*4882a593Smuzhiyun ret = marvell_cable_test_start_common(phydev);
1948*4882a593Smuzhiyun if (ret)
1949*4882a593Smuzhiyun return ret;
1950*4882a593Smuzhiyun
1951*4882a593Smuzhiyun priv->cable_test_tdr = false;
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun /* Reset the VCT5 API control to defaults, otherwise
1954*4882a593Smuzhiyun * VCT7 does not work correctly.
1955*4882a593Smuzhiyun */
1956*4882a593Smuzhiyun ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1957*4882a593Smuzhiyun MII_VCT5_CTRL,
1958*4882a593Smuzhiyun MII_VCT5_CTRL_TX_SAME_CHANNEL |
1959*4882a593Smuzhiyun MII_VCT5_CTRL_SAMPLES_DEFAULT |
1960*4882a593Smuzhiyun MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
1961*4882a593Smuzhiyun MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
1962*4882a593Smuzhiyun if (ret)
1963*4882a593Smuzhiyun return ret;
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1966*4882a593Smuzhiyun MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
1967*4882a593Smuzhiyun if (ret)
1968*4882a593Smuzhiyun return ret;
1969*4882a593Smuzhiyun
1970*4882a593Smuzhiyun return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
1971*4882a593Smuzhiyun MII_VCT7_CTRL,
1972*4882a593Smuzhiyun MII_VCT7_CTRL_RUN_NOW |
1973*4882a593Smuzhiyun MII_VCT7_CTRL_CENTIMETERS);
1974*4882a593Smuzhiyun }
1975*4882a593Smuzhiyun
marvell_vct5_cable_test_tdr_start(struct phy_device * phydev,const struct phy_tdr_config * cfg)1976*4882a593Smuzhiyun static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
1977*4882a593Smuzhiyun const struct phy_tdr_config *cfg)
1978*4882a593Smuzhiyun {
1979*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
1980*4882a593Smuzhiyun int ret;
1981*4882a593Smuzhiyun
1982*4882a593Smuzhiyun priv->cable_test_tdr = true;
1983*4882a593Smuzhiyun priv->first = marvell_vct5_cm2distance(cfg->first);
1984*4882a593Smuzhiyun priv->last = marvell_vct5_cm2distance(cfg->last);
1985*4882a593Smuzhiyun priv->step = marvell_vct5_cm2distance(cfg->step);
1986*4882a593Smuzhiyun priv->pair = cfg->pair;
1987*4882a593Smuzhiyun
1988*4882a593Smuzhiyun if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
1989*4882a593Smuzhiyun return -EINVAL;
1990*4882a593Smuzhiyun
1991*4882a593Smuzhiyun if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
1992*4882a593Smuzhiyun return -EINVAL;
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun /* Disable VCT7 */
1995*4882a593Smuzhiyun ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
1996*4882a593Smuzhiyun MII_VCT7_CTRL, 0);
1997*4882a593Smuzhiyun if (ret)
1998*4882a593Smuzhiyun return ret;
1999*4882a593Smuzhiyun
2000*4882a593Smuzhiyun ret = marvell_cable_test_start_common(phydev);
2001*4882a593Smuzhiyun if (ret)
2002*4882a593Smuzhiyun return ret;
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun ret = ethnl_cable_test_pulse(phydev, 1000);
2005*4882a593Smuzhiyun if (ret)
2006*4882a593Smuzhiyun return ret;
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun return ethnl_cable_test_step(phydev,
2009*4882a593Smuzhiyun marvell_vct5_distance2cm(priv->first),
2010*4882a593Smuzhiyun marvell_vct5_distance2cm(priv->last),
2011*4882a593Smuzhiyun marvell_vct5_distance2cm(priv->step));
2012*4882a593Smuzhiyun }
2013*4882a593Smuzhiyun
marvell_vct7_distance_to_length(int distance,bool meter)2014*4882a593Smuzhiyun static int marvell_vct7_distance_to_length(int distance, bool meter)
2015*4882a593Smuzhiyun {
2016*4882a593Smuzhiyun if (meter)
2017*4882a593Smuzhiyun distance *= 100;
2018*4882a593Smuzhiyun
2019*4882a593Smuzhiyun return distance;
2020*4882a593Smuzhiyun }
2021*4882a593Smuzhiyun
marvell_vct7_distance_valid(int result)2022*4882a593Smuzhiyun static bool marvell_vct7_distance_valid(int result)
2023*4882a593Smuzhiyun {
2024*4882a593Smuzhiyun switch (result) {
2025*4882a593Smuzhiyun case MII_VCT7_RESULTS_OPEN:
2026*4882a593Smuzhiyun case MII_VCT7_RESULTS_SAME_SHORT:
2027*4882a593Smuzhiyun case MII_VCT7_RESULTS_CROSS_SHORT:
2028*4882a593Smuzhiyun return true;
2029*4882a593Smuzhiyun }
2030*4882a593Smuzhiyun return false;
2031*4882a593Smuzhiyun }
2032*4882a593Smuzhiyun
marvell_vct7_report_length(struct phy_device * phydev,int pair,bool meter)2033*4882a593Smuzhiyun static int marvell_vct7_report_length(struct phy_device *phydev,
2034*4882a593Smuzhiyun int pair, bool meter)
2035*4882a593Smuzhiyun {
2036*4882a593Smuzhiyun int length;
2037*4882a593Smuzhiyun int ret;
2038*4882a593Smuzhiyun
2039*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2040*4882a593Smuzhiyun MII_VCT7_PAIR_0_DISTANCE + pair);
2041*4882a593Smuzhiyun if (ret < 0)
2042*4882a593Smuzhiyun return ret;
2043*4882a593Smuzhiyun
2044*4882a593Smuzhiyun length = marvell_vct7_distance_to_length(ret, meter);
2045*4882a593Smuzhiyun
2046*4882a593Smuzhiyun ethnl_cable_test_fault_length(phydev, pair, length);
2047*4882a593Smuzhiyun
2048*4882a593Smuzhiyun return 0;
2049*4882a593Smuzhiyun }
2050*4882a593Smuzhiyun
marvell_vct7_cable_test_report_trans(int result)2051*4882a593Smuzhiyun static int marvell_vct7_cable_test_report_trans(int result)
2052*4882a593Smuzhiyun {
2053*4882a593Smuzhiyun switch (result) {
2054*4882a593Smuzhiyun case MII_VCT7_RESULTS_OK:
2055*4882a593Smuzhiyun return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2056*4882a593Smuzhiyun case MII_VCT7_RESULTS_OPEN:
2057*4882a593Smuzhiyun return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2058*4882a593Smuzhiyun case MII_VCT7_RESULTS_SAME_SHORT:
2059*4882a593Smuzhiyun return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2060*4882a593Smuzhiyun case MII_VCT7_RESULTS_CROSS_SHORT:
2061*4882a593Smuzhiyun return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2062*4882a593Smuzhiyun default:
2063*4882a593Smuzhiyun return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2064*4882a593Smuzhiyun }
2065*4882a593Smuzhiyun }
2066*4882a593Smuzhiyun
marvell_vct7_cable_test_report(struct phy_device * phydev)2067*4882a593Smuzhiyun static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2068*4882a593Smuzhiyun {
2069*4882a593Smuzhiyun int pair0, pair1, pair2, pair3;
2070*4882a593Smuzhiyun bool meter;
2071*4882a593Smuzhiyun int ret;
2072*4882a593Smuzhiyun
2073*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2074*4882a593Smuzhiyun MII_VCT7_RESULTS);
2075*4882a593Smuzhiyun if (ret < 0)
2076*4882a593Smuzhiyun return ret;
2077*4882a593Smuzhiyun
2078*4882a593Smuzhiyun pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2079*4882a593Smuzhiyun MII_VCT7_RESULTS_PAIR3_SHIFT;
2080*4882a593Smuzhiyun pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2081*4882a593Smuzhiyun MII_VCT7_RESULTS_PAIR2_SHIFT;
2082*4882a593Smuzhiyun pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2083*4882a593Smuzhiyun MII_VCT7_RESULTS_PAIR1_SHIFT;
2084*4882a593Smuzhiyun pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2085*4882a593Smuzhiyun MII_VCT7_RESULTS_PAIR0_SHIFT;
2086*4882a593Smuzhiyun
2087*4882a593Smuzhiyun ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2088*4882a593Smuzhiyun marvell_vct7_cable_test_report_trans(pair0));
2089*4882a593Smuzhiyun ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2090*4882a593Smuzhiyun marvell_vct7_cable_test_report_trans(pair1));
2091*4882a593Smuzhiyun ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2092*4882a593Smuzhiyun marvell_vct7_cable_test_report_trans(pair2));
2093*4882a593Smuzhiyun ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2094*4882a593Smuzhiyun marvell_vct7_cable_test_report_trans(pair3));
2095*4882a593Smuzhiyun
2096*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2097*4882a593Smuzhiyun if (ret < 0)
2098*4882a593Smuzhiyun return ret;
2099*4882a593Smuzhiyun
2100*4882a593Smuzhiyun meter = ret & MII_VCT7_CTRL_METERS;
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun if (marvell_vct7_distance_valid(pair0))
2103*4882a593Smuzhiyun marvell_vct7_report_length(phydev, 0, meter);
2104*4882a593Smuzhiyun if (marvell_vct7_distance_valid(pair1))
2105*4882a593Smuzhiyun marvell_vct7_report_length(phydev, 1, meter);
2106*4882a593Smuzhiyun if (marvell_vct7_distance_valid(pair2))
2107*4882a593Smuzhiyun marvell_vct7_report_length(phydev, 2, meter);
2108*4882a593Smuzhiyun if (marvell_vct7_distance_valid(pair3))
2109*4882a593Smuzhiyun marvell_vct7_report_length(phydev, 3, meter);
2110*4882a593Smuzhiyun
2111*4882a593Smuzhiyun return 0;
2112*4882a593Smuzhiyun }
2113*4882a593Smuzhiyun
marvell_vct7_cable_test_get_status(struct phy_device * phydev,bool * finished)2114*4882a593Smuzhiyun static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2115*4882a593Smuzhiyun bool *finished)
2116*4882a593Smuzhiyun {
2117*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
2118*4882a593Smuzhiyun int ret;
2119*4882a593Smuzhiyun
2120*4882a593Smuzhiyun if (priv->cable_test_tdr) {
2121*4882a593Smuzhiyun ret = marvell_vct5_amplitude_graph(phydev);
2122*4882a593Smuzhiyun *finished = true;
2123*4882a593Smuzhiyun return ret;
2124*4882a593Smuzhiyun }
2125*4882a593Smuzhiyun
2126*4882a593Smuzhiyun *finished = false;
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2129*4882a593Smuzhiyun MII_VCT7_CTRL);
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun if (ret < 0)
2132*4882a593Smuzhiyun return ret;
2133*4882a593Smuzhiyun
2134*4882a593Smuzhiyun if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2135*4882a593Smuzhiyun *finished = true;
2136*4882a593Smuzhiyun
2137*4882a593Smuzhiyun return marvell_vct7_cable_test_report(phydev);
2138*4882a593Smuzhiyun }
2139*4882a593Smuzhiyun
2140*4882a593Smuzhiyun return 0;
2141*4882a593Smuzhiyun }
2142*4882a593Smuzhiyun
2143*4882a593Smuzhiyun #ifdef CONFIG_HWMON
m88e1121_get_temp(struct phy_device * phydev,long * temp)2144*4882a593Smuzhiyun static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2145*4882a593Smuzhiyun {
2146*4882a593Smuzhiyun int oldpage;
2147*4882a593Smuzhiyun int ret = 0;
2148*4882a593Smuzhiyun int val;
2149*4882a593Smuzhiyun
2150*4882a593Smuzhiyun *temp = 0;
2151*4882a593Smuzhiyun
2152*4882a593Smuzhiyun oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2153*4882a593Smuzhiyun if (oldpage < 0)
2154*4882a593Smuzhiyun goto error;
2155*4882a593Smuzhiyun
2156*4882a593Smuzhiyun /* Enable temperature sensor */
2157*4882a593Smuzhiyun ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2158*4882a593Smuzhiyun if (ret < 0)
2159*4882a593Smuzhiyun goto error;
2160*4882a593Smuzhiyun
2161*4882a593Smuzhiyun ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2162*4882a593Smuzhiyun ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2163*4882a593Smuzhiyun if (ret < 0)
2164*4882a593Smuzhiyun goto error;
2165*4882a593Smuzhiyun
2166*4882a593Smuzhiyun /* Wait for temperature to stabilize */
2167*4882a593Smuzhiyun usleep_range(10000, 12000);
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2170*4882a593Smuzhiyun if (val < 0) {
2171*4882a593Smuzhiyun ret = val;
2172*4882a593Smuzhiyun goto error;
2173*4882a593Smuzhiyun }
2174*4882a593Smuzhiyun
2175*4882a593Smuzhiyun /* Disable temperature sensor */
2176*4882a593Smuzhiyun ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2177*4882a593Smuzhiyun ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2178*4882a593Smuzhiyun if (ret < 0)
2179*4882a593Smuzhiyun goto error;
2180*4882a593Smuzhiyun
2181*4882a593Smuzhiyun *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2182*4882a593Smuzhiyun
2183*4882a593Smuzhiyun error:
2184*4882a593Smuzhiyun return phy_restore_page(phydev, oldpage, ret);
2185*4882a593Smuzhiyun }
2186*4882a593Smuzhiyun
m88e1121_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * temp)2187*4882a593Smuzhiyun static int m88e1121_hwmon_read(struct device *dev,
2188*4882a593Smuzhiyun enum hwmon_sensor_types type,
2189*4882a593Smuzhiyun u32 attr, int channel, long *temp)
2190*4882a593Smuzhiyun {
2191*4882a593Smuzhiyun struct phy_device *phydev = dev_get_drvdata(dev);
2192*4882a593Smuzhiyun int err;
2193*4882a593Smuzhiyun
2194*4882a593Smuzhiyun switch (attr) {
2195*4882a593Smuzhiyun case hwmon_temp_input:
2196*4882a593Smuzhiyun err = m88e1121_get_temp(phydev, temp);
2197*4882a593Smuzhiyun break;
2198*4882a593Smuzhiyun default:
2199*4882a593Smuzhiyun return -EOPNOTSUPP;
2200*4882a593Smuzhiyun }
2201*4882a593Smuzhiyun
2202*4882a593Smuzhiyun return err;
2203*4882a593Smuzhiyun }
2204*4882a593Smuzhiyun
m88e1121_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)2205*4882a593Smuzhiyun static umode_t m88e1121_hwmon_is_visible(const void *data,
2206*4882a593Smuzhiyun enum hwmon_sensor_types type,
2207*4882a593Smuzhiyun u32 attr, int channel)
2208*4882a593Smuzhiyun {
2209*4882a593Smuzhiyun if (type != hwmon_temp)
2210*4882a593Smuzhiyun return 0;
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun switch (attr) {
2213*4882a593Smuzhiyun case hwmon_temp_input:
2214*4882a593Smuzhiyun return 0444;
2215*4882a593Smuzhiyun default:
2216*4882a593Smuzhiyun return 0;
2217*4882a593Smuzhiyun }
2218*4882a593Smuzhiyun }
2219*4882a593Smuzhiyun
2220*4882a593Smuzhiyun static u32 m88e1121_hwmon_chip_config[] = {
2221*4882a593Smuzhiyun HWMON_C_REGISTER_TZ,
2222*4882a593Smuzhiyun 0
2223*4882a593Smuzhiyun };
2224*4882a593Smuzhiyun
2225*4882a593Smuzhiyun static const struct hwmon_channel_info m88e1121_hwmon_chip = {
2226*4882a593Smuzhiyun .type = hwmon_chip,
2227*4882a593Smuzhiyun .config = m88e1121_hwmon_chip_config,
2228*4882a593Smuzhiyun };
2229*4882a593Smuzhiyun
2230*4882a593Smuzhiyun static u32 m88e1121_hwmon_temp_config[] = {
2231*4882a593Smuzhiyun HWMON_T_INPUT,
2232*4882a593Smuzhiyun 0
2233*4882a593Smuzhiyun };
2234*4882a593Smuzhiyun
2235*4882a593Smuzhiyun static const struct hwmon_channel_info m88e1121_hwmon_temp = {
2236*4882a593Smuzhiyun .type = hwmon_temp,
2237*4882a593Smuzhiyun .config = m88e1121_hwmon_temp_config,
2238*4882a593Smuzhiyun };
2239*4882a593Smuzhiyun
2240*4882a593Smuzhiyun static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
2241*4882a593Smuzhiyun &m88e1121_hwmon_chip,
2242*4882a593Smuzhiyun &m88e1121_hwmon_temp,
2243*4882a593Smuzhiyun NULL
2244*4882a593Smuzhiyun };
2245*4882a593Smuzhiyun
2246*4882a593Smuzhiyun static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
2247*4882a593Smuzhiyun .is_visible = m88e1121_hwmon_is_visible,
2248*4882a593Smuzhiyun .read = m88e1121_hwmon_read,
2249*4882a593Smuzhiyun };
2250*4882a593Smuzhiyun
2251*4882a593Smuzhiyun static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
2252*4882a593Smuzhiyun .ops = &m88e1121_hwmon_hwmon_ops,
2253*4882a593Smuzhiyun .info = m88e1121_hwmon_info,
2254*4882a593Smuzhiyun };
2255*4882a593Smuzhiyun
m88e1510_get_temp(struct phy_device * phydev,long * temp)2256*4882a593Smuzhiyun static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2257*4882a593Smuzhiyun {
2258*4882a593Smuzhiyun int ret;
2259*4882a593Smuzhiyun
2260*4882a593Smuzhiyun *temp = 0;
2261*4882a593Smuzhiyun
2262*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2263*4882a593Smuzhiyun MII_88E1510_TEMP_SENSOR);
2264*4882a593Smuzhiyun if (ret < 0)
2265*4882a593Smuzhiyun return ret;
2266*4882a593Smuzhiyun
2267*4882a593Smuzhiyun *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2268*4882a593Smuzhiyun
2269*4882a593Smuzhiyun return 0;
2270*4882a593Smuzhiyun }
2271*4882a593Smuzhiyun
m88e1510_get_temp_critical(struct phy_device * phydev,long * temp)2272*4882a593Smuzhiyun static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2273*4882a593Smuzhiyun {
2274*4882a593Smuzhiyun int ret;
2275*4882a593Smuzhiyun
2276*4882a593Smuzhiyun *temp = 0;
2277*4882a593Smuzhiyun
2278*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2279*4882a593Smuzhiyun MII_88E1121_MISC_TEST);
2280*4882a593Smuzhiyun if (ret < 0)
2281*4882a593Smuzhiyun return ret;
2282*4882a593Smuzhiyun
2283*4882a593Smuzhiyun *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2284*4882a593Smuzhiyun MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2285*4882a593Smuzhiyun /* convert to mC */
2286*4882a593Smuzhiyun *temp *= 1000;
2287*4882a593Smuzhiyun
2288*4882a593Smuzhiyun return 0;
2289*4882a593Smuzhiyun }
2290*4882a593Smuzhiyun
m88e1510_set_temp_critical(struct phy_device * phydev,long temp)2291*4882a593Smuzhiyun static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2292*4882a593Smuzhiyun {
2293*4882a593Smuzhiyun temp = temp / 1000;
2294*4882a593Smuzhiyun temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2295*4882a593Smuzhiyun
2296*4882a593Smuzhiyun return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2297*4882a593Smuzhiyun MII_88E1121_MISC_TEST,
2298*4882a593Smuzhiyun MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2299*4882a593Smuzhiyun temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2300*4882a593Smuzhiyun }
2301*4882a593Smuzhiyun
m88e1510_get_temp_alarm(struct phy_device * phydev,long * alarm)2302*4882a593Smuzhiyun static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2303*4882a593Smuzhiyun {
2304*4882a593Smuzhiyun int ret;
2305*4882a593Smuzhiyun
2306*4882a593Smuzhiyun *alarm = false;
2307*4882a593Smuzhiyun
2308*4882a593Smuzhiyun ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2309*4882a593Smuzhiyun MII_88E1121_MISC_TEST);
2310*4882a593Smuzhiyun if (ret < 0)
2311*4882a593Smuzhiyun return ret;
2312*4882a593Smuzhiyun
2313*4882a593Smuzhiyun *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2314*4882a593Smuzhiyun
2315*4882a593Smuzhiyun return 0;
2316*4882a593Smuzhiyun }
2317*4882a593Smuzhiyun
m88e1510_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * temp)2318*4882a593Smuzhiyun static int m88e1510_hwmon_read(struct device *dev,
2319*4882a593Smuzhiyun enum hwmon_sensor_types type,
2320*4882a593Smuzhiyun u32 attr, int channel, long *temp)
2321*4882a593Smuzhiyun {
2322*4882a593Smuzhiyun struct phy_device *phydev = dev_get_drvdata(dev);
2323*4882a593Smuzhiyun int err;
2324*4882a593Smuzhiyun
2325*4882a593Smuzhiyun switch (attr) {
2326*4882a593Smuzhiyun case hwmon_temp_input:
2327*4882a593Smuzhiyun err = m88e1510_get_temp(phydev, temp);
2328*4882a593Smuzhiyun break;
2329*4882a593Smuzhiyun case hwmon_temp_crit:
2330*4882a593Smuzhiyun err = m88e1510_get_temp_critical(phydev, temp);
2331*4882a593Smuzhiyun break;
2332*4882a593Smuzhiyun case hwmon_temp_max_alarm:
2333*4882a593Smuzhiyun err = m88e1510_get_temp_alarm(phydev, temp);
2334*4882a593Smuzhiyun break;
2335*4882a593Smuzhiyun default:
2336*4882a593Smuzhiyun return -EOPNOTSUPP;
2337*4882a593Smuzhiyun }
2338*4882a593Smuzhiyun
2339*4882a593Smuzhiyun return err;
2340*4882a593Smuzhiyun }
2341*4882a593Smuzhiyun
m88e1510_hwmon_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long temp)2342*4882a593Smuzhiyun static int m88e1510_hwmon_write(struct device *dev,
2343*4882a593Smuzhiyun enum hwmon_sensor_types type,
2344*4882a593Smuzhiyun u32 attr, int channel, long temp)
2345*4882a593Smuzhiyun {
2346*4882a593Smuzhiyun struct phy_device *phydev = dev_get_drvdata(dev);
2347*4882a593Smuzhiyun int err;
2348*4882a593Smuzhiyun
2349*4882a593Smuzhiyun switch (attr) {
2350*4882a593Smuzhiyun case hwmon_temp_crit:
2351*4882a593Smuzhiyun err = m88e1510_set_temp_critical(phydev, temp);
2352*4882a593Smuzhiyun break;
2353*4882a593Smuzhiyun default:
2354*4882a593Smuzhiyun return -EOPNOTSUPP;
2355*4882a593Smuzhiyun }
2356*4882a593Smuzhiyun return err;
2357*4882a593Smuzhiyun }
2358*4882a593Smuzhiyun
m88e1510_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)2359*4882a593Smuzhiyun static umode_t m88e1510_hwmon_is_visible(const void *data,
2360*4882a593Smuzhiyun enum hwmon_sensor_types type,
2361*4882a593Smuzhiyun u32 attr, int channel)
2362*4882a593Smuzhiyun {
2363*4882a593Smuzhiyun if (type != hwmon_temp)
2364*4882a593Smuzhiyun return 0;
2365*4882a593Smuzhiyun
2366*4882a593Smuzhiyun switch (attr) {
2367*4882a593Smuzhiyun case hwmon_temp_input:
2368*4882a593Smuzhiyun case hwmon_temp_max_alarm:
2369*4882a593Smuzhiyun return 0444;
2370*4882a593Smuzhiyun case hwmon_temp_crit:
2371*4882a593Smuzhiyun return 0644;
2372*4882a593Smuzhiyun default:
2373*4882a593Smuzhiyun return 0;
2374*4882a593Smuzhiyun }
2375*4882a593Smuzhiyun }
2376*4882a593Smuzhiyun
2377*4882a593Smuzhiyun static u32 m88e1510_hwmon_temp_config[] = {
2378*4882a593Smuzhiyun HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2379*4882a593Smuzhiyun 0
2380*4882a593Smuzhiyun };
2381*4882a593Smuzhiyun
2382*4882a593Smuzhiyun static const struct hwmon_channel_info m88e1510_hwmon_temp = {
2383*4882a593Smuzhiyun .type = hwmon_temp,
2384*4882a593Smuzhiyun .config = m88e1510_hwmon_temp_config,
2385*4882a593Smuzhiyun };
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
2388*4882a593Smuzhiyun &m88e1121_hwmon_chip,
2389*4882a593Smuzhiyun &m88e1510_hwmon_temp,
2390*4882a593Smuzhiyun NULL
2391*4882a593Smuzhiyun };
2392*4882a593Smuzhiyun
2393*4882a593Smuzhiyun static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
2394*4882a593Smuzhiyun .is_visible = m88e1510_hwmon_is_visible,
2395*4882a593Smuzhiyun .read = m88e1510_hwmon_read,
2396*4882a593Smuzhiyun .write = m88e1510_hwmon_write,
2397*4882a593Smuzhiyun };
2398*4882a593Smuzhiyun
2399*4882a593Smuzhiyun static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
2400*4882a593Smuzhiyun .ops = &m88e1510_hwmon_hwmon_ops,
2401*4882a593Smuzhiyun .info = m88e1510_hwmon_info,
2402*4882a593Smuzhiyun };
2403*4882a593Smuzhiyun
m88e6390_get_temp(struct phy_device * phydev,long * temp)2404*4882a593Smuzhiyun static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2405*4882a593Smuzhiyun {
2406*4882a593Smuzhiyun int sum = 0;
2407*4882a593Smuzhiyun int oldpage;
2408*4882a593Smuzhiyun int ret = 0;
2409*4882a593Smuzhiyun int i;
2410*4882a593Smuzhiyun
2411*4882a593Smuzhiyun *temp = 0;
2412*4882a593Smuzhiyun
2413*4882a593Smuzhiyun oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2414*4882a593Smuzhiyun if (oldpage < 0)
2415*4882a593Smuzhiyun goto error;
2416*4882a593Smuzhiyun
2417*4882a593Smuzhiyun /* Enable temperature sensor */
2418*4882a593Smuzhiyun ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2419*4882a593Smuzhiyun if (ret < 0)
2420*4882a593Smuzhiyun goto error;
2421*4882a593Smuzhiyun
2422*4882a593Smuzhiyun ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
2423*4882a593Smuzhiyun ret |= MII_88E6390_MISC_TEST_SAMPLE_ENABLE |
2424*4882a593Smuzhiyun MII_88E6390_MISC_TEST_SAMPLE_1S;
2425*4882a593Smuzhiyun
2426*4882a593Smuzhiyun ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2427*4882a593Smuzhiyun if (ret < 0)
2428*4882a593Smuzhiyun goto error;
2429*4882a593Smuzhiyun
2430*4882a593Smuzhiyun /* Wait for temperature to stabilize */
2431*4882a593Smuzhiyun usleep_range(10000, 12000);
2432*4882a593Smuzhiyun
2433*4882a593Smuzhiyun /* Reading the temperature sense has an errata. You need to read
2434*4882a593Smuzhiyun * a number of times and take an average.
2435*4882a593Smuzhiyun */
2436*4882a593Smuzhiyun for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2437*4882a593Smuzhiyun ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2438*4882a593Smuzhiyun if (ret < 0)
2439*4882a593Smuzhiyun goto error;
2440*4882a593Smuzhiyun sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2441*4882a593Smuzhiyun }
2442*4882a593Smuzhiyun
2443*4882a593Smuzhiyun sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2444*4882a593Smuzhiyun *temp = (sum - 75) * 1000;
2445*4882a593Smuzhiyun
2446*4882a593Smuzhiyun /* Disable temperature sensor */
2447*4882a593Smuzhiyun ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2448*4882a593Smuzhiyun if (ret < 0)
2449*4882a593Smuzhiyun goto error;
2450*4882a593Smuzhiyun
2451*4882a593Smuzhiyun ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
2452*4882a593Smuzhiyun ret |= MII_88E6390_MISC_TEST_SAMPLE_DISABLE;
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2455*4882a593Smuzhiyun
2456*4882a593Smuzhiyun error:
2457*4882a593Smuzhiyun phy_restore_page(phydev, oldpage, ret);
2458*4882a593Smuzhiyun
2459*4882a593Smuzhiyun return ret;
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
m88e6390_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * temp)2462*4882a593Smuzhiyun static int m88e6390_hwmon_read(struct device *dev,
2463*4882a593Smuzhiyun enum hwmon_sensor_types type,
2464*4882a593Smuzhiyun u32 attr, int channel, long *temp)
2465*4882a593Smuzhiyun {
2466*4882a593Smuzhiyun struct phy_device *phydev = dev_get_drvdata(dev);
2467*4882a593Smuzhiyun int err;
2468*4882a593Smuzhiyun
2469*4882a593Smuzhiyun switch (attr) {
2470*4882a593Smuzhiyun case hwmon_temp_input:
2471*4882a593Smuzhiyun err = m88e6390_get_temp(phydev, temp);
2472*4882a593Smuzhiyun break;
2473*4882a593Smuzhiyun default:
2474*4882a593Smuzhiyun return -EOPNOTSUPP;
2475*4882a593Smuzhiyun }
2476*4882a593Smuzhiyun
2477*4882a593Smuzhiyun return err;
2478*4882a593Smuzhiyun }
2479*4882a593Smuzhiyun
m88e6390_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)2480*4882a593Smuzhiyun static umode_t m88e6390_hwmon_is_visible(const void *data,
2481*4882a593Smuzhiyun enum hwmon_sensor_types type,
2482*4882a593Smuzhiyun u32 attr, int channel)
2483*4882a593Smuzhiyun {
2484*4882a593Smuzhiyun if (type != hwmon_temp)
2485*4882a593Smuzhiyun return 0;
2486*4882a593Smuzhiyun
2487*4882a593Smuzhiyun switch (attr) {
2488*4882a593Smuzhiyun case hwmon_temp_input:
2489*4882a593Smuzhiyun return 0444;
2490*4882a593Smuzhiyun default:
2491*4882a593Smuzhiyun return 0;
2492*4882a593Smuzhiyun }
2493*4882a593Smuzhiyun }
2494*4882a593Smuzhiyun
2495*4882a593Smuzhiyun static u32 m88e6390_hwmon_temp_config[] = {
2496*4882a593Smuzhiyun HWMON_T_INPUT,
2497*4882a593Smuzhiyun 0
2498*4882a593Smuzhiyun };
2499*4882a593Smuzhiyun
2500*4882a593Smuzhiyun static const struct hwmon_channel_info m88e6390_hwmon_temp = {
2501*4882a593Smuzhiyun .type = hwmon_temp,
2502*4882a593Smuzhiyun .config = m88e6390_hwmon_temp_config,
2503*4882a593Smuzhiyun };
2504*4882a593Smuzhiyun
2505*4882a593Smuzhiyun static const struct hwmon_channel_info *m88e6390_hwmon_info[] = {
2506*4882a593Smuzhiyun &m88e1121_hwmon_chip,
2507*4882a593Smuzhiyun &m88e6390_hwmon_temp,
2508*4882a593Smuzhiyun NULL
2509*4882a593Smuzhiyun };
2510*4882a593Smuzhiyun
2511*4882a593Smuzhiyun static const struct hwmon_ops m88e6390_hwmon_hwmon_ops = {
2512*4882a593Smuzhiyun .is_visible = m88e6390_hwmon_is_visible,
2513*4882a593Smuzhiyun .read = m88e6390_hwmon_read,
2514*4882a593Smuzhiyun };
2515*4882a593Smuzhiyun
2516*4882a593Smuzhiyun static const struct hwmon_chip_info m88e6390_hwmon_chip_info = {
2517*4882a593Smuzhiyun .ops = &m88e6390_hwmon_hwmon_ops,
2518*4882a593Smuzhiyun .info = m88e6390_hwmon_info,
2519*4882a593Smuzhiyun };
2520*4882a593Smuzhiyun
marvell_hwmon_name(struct phy_device * phydev)2521*4882a593Smuzhiyun static int marvell_hwmon_name(struct phy_device *phydev)
2522*4882a593Smuzhiyun {
2523*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
2524*4882a593Smuzhiyun struct device *dev = &phydev->mdio.dev;
2525*4882a593Smuzhiyun const char *devname = dev_name(dev);
2526*4882a593Smuzhiyun size_t len = strlen(devname);
2527*4882a593Smuzhiyun int i, j;
2528*4882a593Smuzhiyun
2529*4882a593Smuzhiyun priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2530*4882a593Smuzhiyun if (!priv->hwmon_name)
2531*4882a593Smuzhiyun return -ENOMEM;
2532*4882a593Smuzhiyun
2533*4882a593Smuzhiyun for (i = j = 0; i < len && devname[i]; i++) {
2534*4882a593Smuzhiyun if (isalnum(devname[i]))
2535*4882a593Smuzhiyun priv->hwmon_name[j++] = devname[i];
2536*4882a593Smuzhiyun }
2537*4882a593Smuzhiyun
2538*4882a593Smuzhiyun return 0;
2539*4882a593Smuzhiyun }
2540*4882a593Smuzhiyun
marvell_hwmon_probe(struct phy_device * phydev,const struct hwmon_chip_info * chip)2541*4882a593Smuzhiyun static int marvell_hwmon_probe(struct phy_device *phydev,
2542*4882a593Smuzhiyun const struct hwmon_chip_info *chip)
2543*4882a593Smuzhiyun {
2544*4882a593Smuzhiyun struct marvell_priv *priv = phydev->priv;
2545*4882a593Smuzhiyun struct device *dev = &phydev->mdio.dev;
2546*4882a593Smuzhiyun int err;
2547*4882a593Smuzhiyun
2548*4882a593Smuzhiyun err = marvell_hwmon_name(phydev);
2549*4882a593Smuzhiyun if (err)
2550*4882a593Smuzhiyun return err;
2551*4882a593Smuzhiyun
2552*4882a593Smuzhiyun priv->hwmon_dev = devm_hwmon_device_register_with_info(
2553*4882a593Smuzhiyun dev, priv->hwmon_name, phydev, chip, NULL);
2554*4882a593Smuzhiyun
2555*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(priv->hwmon_dev);
2556*4882a593Smuzhiyun }
2557*4882a593Smuzhiyun
m88e1121_hwmon_probe(struct phy_device * phydev)2558*4882a593Smuzhiyun static int m88e1121_hwmon_probe(struct phy_device *phydev)
2559*4882a593Smuzhiyun {
2560*4882a593Smuzhiyun return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
2561*4882a593Smuzhiyun }
2562*4882a593Smuzhiyun
m88e1510_hwmon_probe(struct phy_device * phydev)2563*4882a593Smuzhiyun static int m88e1510_hwmon_probe(struct phy_device *phydev)
2564*4882a593Smuzhiyun {
2565*4882a593Smuzhiyun return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
2566*4882a593Smuzhiyun }
2567*4882a593Smuzhiyun
m88e6390_hwmon_probe(struct phy_device * phydev)2568*4882a593Smuzhiyun static int m88e6390_hwmon_probe(struct phy_device *phydev)
2569*4882a593Smuzhiyun {
2570*4882a593Smuzhiyun return marvell_hwmon_probe(phydev, &m88e6390_hwmon_chip_info);
2571*4882a593Smuzhiyun }
2572*4882a593Smuzhiyun #else
m88e1121_hwmon_probe(struct phy_device * phydev)2573*4882a593Smuzhiyun static int m88e1121_hwmon_probe(struct phy_device *phydev)
2574*4882a593Smuzhiyun {
2575*4882a593Smuzhiyun return 0;
2576*4882a593Smuzhiyun }
2577*4882a593Smuzhiyun
m88e1510_hwmon_probe(struct phy_device * phydev)2578*4882a593Smuzhiyun static int m88e1510_hwmon_probe(struct phy_device *phydev)
2579*4882a593Smuzhiyun {
2580*4882a593Smuzhiyun return 0;
2581*4882a593Smuzhiyun }
2582*4882a593Smuzhiyun
m88e6390_hwmon_probe(struct phy_device * phydev)2583*4882a593Smuzhiyun static int m88e6390_hwmon_probe(struct phy_device *phydev)
2584*4882a593Smuzhiyun {
2585*4882a593Smuzhiyun return 0;
2586*4882a593Smuzhiyun }
2587*4882a593Smuzhiyun #endif
2588*4882a593Smuzhiyun
marvell_probe(struct phy_device * phydev)2589*4882a593Smuzhiyun static int marvell_probe(struct phy_device *phydev)
2590*4882a593Smuzhiyun {
2591*4882a593Smuzhiyun struct marvell_priv *priv;
2592*4882a593Smuzhiyun
2593*4882a593Smuzhiyun priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2594*4882a593Smuzhiyun if (!priv)
2595*4882a593Smuzhiyun return -ENOMEM;
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun phydev->priv = priv;
2598*4882a593Smuzhiyun
2599*4882a593Smuzhiyun return 0;
2600*4882a593Smuzhiyun }
2601*4882a593Smuzhiyun
m88e1121_probe(struct phy_device * phydev)2602*4882a593Smuzhiyun static int m88e1121_probe(struct phy_device *phydev)
2603*4882a593Smuzhiyun {
2604*4882a593Smuzhiyun int err;
2605*4882a593Smuzhiyun
2606*4882a593Smuzhiyun err = marvell_probe(phydev);
2607*4882a593Smuzhiyun if (err)
2608*4882a593Smuzhiyun return err;
2609*4882a593Smuzhiyun
2610*4882a593Smuzhiyun return m88e1121_hwmon_probe(phydev);
2611*4882a593Smuzhiyun }
2612*4882a593Smuzhiyun
m88e1510_probe(struct phy_device * phydev)2613*4882a593Smuzhiyun static int m88e1510_probe(struct phy_device *phydev)
2614*4882a593Smuzhiyun {
2615*4882a593Smuzhiyun int err;
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun err = marvell_probe(phydev);
2618*4882a593Smuzhiyun if (err)
2619*4882a593Smuzhiyun return err;
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun return m88e1510_hwmon_probe(phydev);
2622*4882a593Smuzhiyun }
2623*4882a593Smuzhiyun
m88e6390_probe(struct phy_device * phydev)2624*4882a593Smuzhiyun static int m88e6390_probe(struct phy_device *phydev)
2625*4882a593Smuzhiyun {
2626*4882a593Smuzhiyun int err;
2627*4882a593Smuzhiyun
2628*4882a593Smuzhiyun err = marvell_probe(phydev);
2629*4882a593Smuzhiyun if (err)
2630*4882a593Smuzhiyun return err;
2631*4882a593Smuzhiyun
2632*4882a593Smuzhiyun return m88e6390_hwmon_probe(phydev);
2633*4882a593Smuzhiyun }
2634*4882a593Smuzhiyun
2635*4882a593Smuzhiyun static struct phy_driver marvell_drivers[] = {
2636*4882a593Smuzhiyun {
2637*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1101,
2638*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2639*4882a593Smuzhiyun .name = "Marvell 88E1101",
2640*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2641*4882a593Smuzhiyun .probe = marvell_probe,
2642*4882a593Smuzhiyun .config_init = marvell_config_init,
2643*4882a593Smuzhiyun .config_aneg = m88e1101_config_aneg,
2644*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2645*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2646*4882a593Smuzhiyun .resume = genphy_resume,
2647*4882a593Smuzhiyun .suspend = genphy_suspend,
2648*4882a593Smuzhiyun .read_page = marvell_read_page,
2649*4882a593Smuzhiyun .write_page = marvell_write_page,
2650*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2651*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2652*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2653*4882a593Smuzhiyun },
2654*4882a593Smuzhiyun {
2655*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1112,
2656*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2657*4882a593Smuzhiyun .name = "Marvell 88E1112",
2658*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2659*4882a593Smuzhiyun .probe = marvell_probe,
2660*4882a593Smuzhiyun .config_init = m88e1111_config_init,
2661*4882a593Smuzhiyun .config_aneg = marvell_config_aneg,
2662*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2663*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2664*4882a593Smuzhiyun .resume = genphy_resume,
2665*4882a593Smuzhiyun .suspend = genphy_suspend,
2666*4882a593Smuzhiyun .read_page = marvell_read_page,
2667*4882a593Smuzhiyun .write_page = marvell_write_page,
2668*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2669*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2670*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2671*4882a593Smuzhiyun .get_tunable = m88e1011_get_tunable,
2672*4882a593Smuzhiyun .set_tunable = m88e1011_set_tunable,
2673*4882a593Smuzhiyun },
2674*4882a593Smuzhiyun {
2675*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1111,
2676*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2677*4882a593Smuzhiyun .name = "Marvell 88E1111",
2678*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2679*4882a593Smuzhiyun .probe = marvell_probe,
2680*4882a593Smuzhiyun .config_init = m88e1111_config_init,
2681*4882a593Smuzhiyun .config_aneg = marvell_config_aneg,
2682*4882a593Smuzhiyun .read_status = marvell_read_status,
2683*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2684*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2685*4882a593Smuzhiyun .resume = genphy_resume,
2686*4882a593Smuzhiyun .suspend = genphy_suspend,
2687*4882a593Smuzhiyun .read_page = marvell_read_page,
2688*4882a593Smuzhiyun .write_page = marvell_write_page,
2689*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2690*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2691*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2692*4882a593Smuzhiyun .get_tunable = m88e1111_get_tunable,
2693*4882a593Smuzhiyun .set_tunable = m88e1111_set_tunable,
2694*4882a593Smuzhiyun },
2695*4882a593Smuzhiyun {
2696*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1118,
2697*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2698*4882a593Smuzhiyun .name = "Marvell 88E1118",
2699*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2700*4882a593Smuzhiyun .probe = marvell_probe,
2701*4882a593Smuzhiyun .config_init = m88e1118_config_init,
2702*4882a593Smuzhiyun .config_aneg = m88e1118_config_aneg,
2703*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2704*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2705*4882a593Smuzhiyun .resume = genphy_resume,
2706*4882a593Smuzhiyun .suspend = genphy_suspend,
2707*4882a593Smuzhiyun .read_page = marvell_read_page,
2708*4882a593Smuzhiyun .write_page = marvell_write_page,
2709*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2710*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2711*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2712*4882a593Smuzhiyun },
2713*4882a593Smuzhiyun {
2714*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1121R,
2715*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2716*4882a593Smuzhiyun .name = "Marvell 88E1121R",
2717*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2718*4882a593Smuzhiyun .probe = m88e1121_probe,
2719*4882a593Smuzhiyun .config_init = marvell_config_init,
2720*4882a593Smuzhiyun .config_aneg = m88e1121_config_aneg,
2721*4882a593Smuzhiyun .read_status = marvell_read_status,
2722*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2723*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2724*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2725*4882a593Smuzhiyun .resume = genphy_resume,
2726*4882a593Smuzhiyun .suspend = genphy_suspend,
2727*4882a593Smuzhiyun .read_page = marvell_read_page,
2728*4882a593Smuzhiyun .write_page = marvell_write_page,
2729*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2730*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2731*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2732*4882a593Smuzhiyun .get_tunable = m88e1011_get_tunable,
2733*4882a593Smuzhiyun .set_tunable = m88e1011_set_tunable,
2734*4882a593Smuzhiyun },
2735*4882a593Smuzhiyun {
2736*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1318S,
2737*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2738*4882a593Smuzhiyun .name = "Marvell 88E1318S",
2739*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2740*4882a593Smuzhiyun .probe = marvell_probe,
2741*4882a593Smuzhiyun .config_init = m88e1318_config_init,
2742*4882a593Smuzhiyun .config_aneg = m88e1318_config_aneg,
2743*4882a593Smuzhiyun .read_status = marvell_read_status,
2744*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2745*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2746*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2747*4882a593Smuzhiyun .get_wol = m88e1318_get_wol,
2748*4882a593Smuzhiyun .set_wol = m88e1318_set_wol,
2749*4882a593Smuzhiyun .resume = genphy_resume,
2750*4882a593Smuzhiyun .suspend = genphy_suspend,
2751*4882a593Smuzhiyun .read_page = marvell_read_page,
2752*4882a593Smuzhiyun .write_page = marvell_write_page,
2753*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2754*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2755*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2756*4882a593Smuzhiyun },
2757*4882a593Smuzhiyun {
2758*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1145,
2759*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2760*4882a593Smuzhiyun .name = "Marvell 88E1145",
2761*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2762*4882a593Smuzhiyun .probe = marvell_probe,
2763*4882a593Smuzhiyun .config_init = m88e1145_config_init,
2764*4882a593Smuzhiyun .config_aneg = m88e1101_config_aneg,
2765*4882a593Smuzhiyun .read_status = genphy_read_status,
2766*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2767*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2768*4882a593Smuzhiyun .resume = genphy_resume,
2769*4882a593Smuzhiyun .suspend = genphy_suspend,
2770*4882a593Smuzhiyun .read_page = marvell_read_page,
2771*4882a593Smuzhiyun .write_page = marvell_write_page,
2772*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2773*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2774*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2775*4882a593Smuzhiyun .get_tunable = m88e1111_get_tunable,
2776*4882a593Smuzhiyun .set_tunable = m88e1111_set_tunable,
2777*4882a593Smuzhiyun },
2778*4882a593Smuzhiyun {
2779*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1149R,
2780*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2781*4882a593Smuzhiyun .name = "Marvell 88E1149R",
2782*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2783*4882a593Smuzhiyun .probe = marvell_probe,
2784*4882a593Smuzhiyun .config_init = m88e1149_config_init,
2785*4882a593Smuzhiyun .config_aneg = m88e1118_config_aneg,
2786*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2787*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2788*4882a593Smuzhiyun .resume = genphy_resume,
2789*4882a593Smuzhiyun .suspend = genphy_suspend,
2790*4882a593Smuzhiyun .read_page = marvell_read_page,
2791*4882a593Smuzhiyun .write_page = marvell_write_page,
2792*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2793*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2794*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2795*4882a593Smuzhiyun },
2796*4882a593Smuzhiyun {
2797*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1240,
2798*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2799*4882a593Smuzhiyun .name = "Marvell 88E1240",
2800*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2801*4882a593Smuzhiyun .probe = marvell_probe,
2802*4882a593Smuzhiyun .config_init = m88e1111_config_init,
2803*4882a593Smuzhiyun .config_aneg = marvell_config_aneg,
2804*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2805*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2806*4882a593Smuzhiyun .resume = genphy_resume,
2807*4882a593Smuzhiyun .suspend = genphy_suspend,
2808*4882a593Smuzhiyun .read_page = marvell_read_page,
2809*4882a593Smuzhiyun .write_page = marvell_write_page,
2810*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2811*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2812*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2813*4882a593Smuzhiyun },
2814*4882a593Smuzhiyun {
2815*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1116R,
2816*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2817*4882a593Smuzhiyun .name = "Marvell 88E1116R",
2818*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2819*4882a593Smuzhiyun .probe = marvell_probe,
2820*4882a593Smuzhiyun .config_init = m88e1116r_config_init,
2821*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2822*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2823*4882a593Smuzhiyun .resume = genphy_resume,
2824*4882a593Smuzhiyun .suspend = genphy_suspend,
2825*4882a593Smuzhiyun .read_page = marvell_read_page,
2826*4882a593Smuzhiyun .write_page = marvell_write_page,
2827*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2828*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2829*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2830*4882a593Smuzhiyun .get_tunable = m88e1011_get_tunable,
2831*4882a593Smuzhiyun .set_tunable = m88e1011_set_tunable,
2832*4882a593Smuzhiyun },
2833*4882a593Smuzhiyun {
2834*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1510,
2835*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2836*4882a593Smuzhiyun .name = "Marvell 88E1510",
2837*4882a593Smuzhiyun .features = PHY_GBIT_FIBRE_FEATURES,
2838*4882a593Smuzhiyun .flags = PHY_POLL_CABLE_TEST,
2839*4882a593Smuzhiyun .probe = m88e1510_probe,
2840*4882a593Smuzhiyun .config_init = m88e1510_config_init,
2841*4882a593Smuzhiyun .config_aneg = m88e1510_config_aneg,
2842*4882a593Smuzhiyun .read_status = marvell_read_status,
2843*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2844*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2845*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2846*4882a593Smuzhiyun .get_wol = m88e1318_get_wol,
2847*4882a593Smuzhiyun .set_wol = m88e1318_set_wol,
2848*4882a593Smuzhiyun .resume = marvell_resume,
2849*4882a593Smuzhiyun .suspend = marvell_suspend,
2850*4882a593Smuzhiyun .read_page = marvell_read_page,
2851*4882a593Smuzhiyun .write_page = marvell_write_page,
2852*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2853*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2854*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2855*4882a593Smuzhiyun .set_loopback = genphy_loopback,
2856*4882a593Smuzhiyun .get_tunable = m88e1011_get_tunable,
2857*4882a593Smuzhiyun .set_tunable = m88e1011_set_tunable,
2858*4882a593Smuzhiyun .cable_test_start = marvell_vct7_cable_test_start,
2859*4882a593Smuzhiyun .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2860*4882a593Smuzhiyun .cable_test_get_status = marvell_vct7_cable_test_get_status,
2861*4882a593Smuzhiyun },
2862*4882a593Smuzhiyun {
2863*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1540,
2864*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2865*4882a593Smuzhiyun .name = "Marvell 88E1540",
2866*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2867*4882a593Smuzhiyun .flags = PHY_POLL_CABLE_TEST,
2868*4882a593Smuzhiyun .probe = m88e1510_probe,
2869*4882a593Smuzhiyun .config_init = marvell_config_init,
2870*4882a593Smuzhiyun .config_aneg = m88e1510_config_aneg,
2871*4882a593Smuzhiyun .read_status = marvell_read_status,
2872*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2873*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2874*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2875*4882a593Smuzhiyun .resume = genphy_resume,
2876*4882a593Smuzhiyun .suspend = genphy_suspend,
2877*4882a593Smuzhiyun .read_page = marvell_read_page,
2878*4882a593Smuzhiyun .write_page = marvell_write_page,
2879*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2880*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2881*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2882*4882a593Smuzhiyun .get_tunable = m88e1540_get_tunable,
2883*4882a593Smuzhiyun .set_tunable = m88e1540_set_tunable,
2884*4882a593Smuzhiyun .cable_test_start = marvell_vct7_cable_test_start,
2885*4882a593Smuzhiyun .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2886*4882a593Smuzhiyun .cable_test_get_status = marvell_vct7_cable_test_get_status,
2887*4882a593Smuzhiyun },
2888*4882a593Smuzhiyun {
2889*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1545,
2890*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2891*4882a593Smuzhiyun .name = "Marvell 88E1545",
2892*4882a593Smuzhiyun .probe = m88e1510_probe,
2893*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2894*4882a593Smuzhiyun .flags = PHY_POLL_CABLE_TEST,
2895*4882a593Smuzhiyun .config_init = marvell_config_init,
2896*4882a593Smuzhiyun .config_aneg = m88e1510_config_aneg,
2897*4882a593Smuzhiyun .read_status = marvell_read_status,
2898*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2899*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2900*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2901*4882a593Smuzhiyun .resume = genphy_resume,
2902*4882a593Smuzhiyun .suspend = genphy_suspend,
2903*4882a593Smuzhiyun .read_page = marvell_read_page,
2904*4882a593Smuzhiyun .write_page = marvell_write_page,
2905*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2906*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2907*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2908*4882a593Smuzhiyun .get_tunable = m88e1540_get_tunable,
2909*4882a593Smuzhiyun .set_tunable = m88e1540_set_tunable,
2910*4882a593Smuzhiyun .cable_test_start = marvell_vct7_cable_test_start,
2911*4882a593Smuzhiyun .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2912*4882a593Smuzhiyun .cable_test_get_status = marvell_vct7_cable_test_get_status,
2913*4882a593Smuzhiyun },
2914*4882a593Smuzhiyun {
2915*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E3016,
2916*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2917*4882a593Smuzhiyun .name = "Marvell 88E3016",
2918*4882a593Smuzhiyun /* PHY_BASIC_FEATURES */
2919*4882a593Smuzhiyun .probe = marvell_probe,
2920*4882a593Smuzhiyun .config_init = m88e3016_config_init,
2921*4882a593Smuzhiyun .aneg_done = marvell_aneg_done,
2922*4882a593Smuzhiyun .read_status = marvell_read_status,
2923*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2924*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2925*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2926*4882a593Smuzhiyun .resume = genphy_resume,
2927*4882a593Smuzhiyun .suspend = genphy_suspend,
2928*4882a593Smuzhiyun .read_page = marvell_read_page,
2929*4882a593Smuzhiyun .write_page = marvell_write_page,
2930*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2931*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2932*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2933*4882a593Smuzhiyun },
2934*4882a593Smuzhiyun {
2935*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
2936*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2937*4882a593Smuzhiyun .name = "Marvell 88E6341 Family",
2938*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2939*4882a593Smuzhiyun .flags = PHY_POLL_CABLE_TEST,
2940*4882a593Smuzhiyun .probe = m88e1510_probe,
2941*4882a593Smuzhiyun .config_init = marvell_config_init,
2942*4882a593Smuzhiyun .config_aneg = m88e6390_config_aneg,
2943*4882a593Smuzhiyun .read_status = marvell_read_status,
2944*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2945*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2946*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2947*4882a593Smuzhiyun .resume = genphy_resume,
2948*4882a593Smuzhiyun .suspend = genphy_suspend,
2949*4882a593Smuzhiyun .read_page = marvell_read_page,
2950*4882a593Smuzhiyun .write_page = marvell_write_page,
2951*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2952*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2953*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2954*4882a593Smuzhiyun .get_tunable = m88e1540_get_tunable,
2955*4882a593Smuzhiyun .set_tunable = m88e1540_set_tunable,
2956*4882a593Smuzhiyun .cable_test_start = marvell_vct7_cable_test_start,
2957*4882a593Smuzhiyun .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2958*4882a593Smuzhiyun .cable_test_get_status = marvell_vct7_cable_test_get_status,
2959*4882a593Smuzhiyun },
2960*4882a593Smuzhiyun {
2961*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
2962*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2963*4882a593Smuzhiyun .name = "Marvell 88E6390 Family",
2964*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2965*4882a593Smuzhiyun .flags = PHY_POLL_CABLE_TEST,
2966*4882a593Smuzhiyun .probe = m88e6390_probe,
2967*4882a593Smuzhiyun .config_init = marvell_config_init,
2968*4882a593Smuzhiyun .config_aneg = m88e6390_config_aneg,
2969*4882a593Smuzhiyun .read_status = marvell_read_status,
2970*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2971*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2972*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2973*4882a593Smuzhiyun .resume = genphy_resume,
2974*4882a593Smuzhiyun .suspend = genphy_suspend,
2975*4882a593Smuzhiyun .read_page = marvell_read_page,
2976*4882a593Smuzhiyun .write_page = marvell_write_page,
2977*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
2978*4882a593Smuzhiyun .get_strings = marvell_get_strings,
2979*4882a593Smuzhiyun .get_stats = marvell_get_stats,
2980*4882a593Smuzhiyun .get_tunable = m88e1540_get_tunable,
2981*4882a593Smuzhiyun .set_tunable = m88e1540_set_tunable,
2982*4882a593Smuzhiyun .cable_test_start = marvell_vct7_cable_test_start,
2983*4882a593Smuzhiyun .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2984*4882a593Smuzhiyun .cable_test_get_status = marvell_vct7_cable_test_get_status,
2985*4882a593Smuzhiyun },
2986*4882a593Smuzhiyun {
2987*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1340S,
2988*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
2989*4882a593Smuzhiyun .name = "Marvell 88E1340S",
2990*4882a593Smuzhiyun .probe = m88e1510_probe,
2991*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
2992*4882a593Smuzhiyun .config_init = marvell_config_init,
2993*4882a593Smuzhiyun .config_aneg = m88e1510_config_aneg,
2994*4882a593Smuzhiyun .read_status = marvell_read_status,
2995*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
2996*4882a593Smuzhiyun .config_intr = marvell_config_intr,
2997*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
2998*4882a593Smuzhiyun .resume = genphy_resume,
2999*4882a593Smuzhiyun .suspend = genphy_suspend,
3000*4882a593Smuzhiyun .read_page = marvell_read_page,
3001*4882a593Smuzhiyun .write_page = marvell_write_page,
3002*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
3003*4882a593Smuzhiyun .get_strings = marvell_get_strings,
3004*4882a593Smuzhiyun .get_stats = marvell_get_stats,
3005*4882a593Smuzhiyun .get_tunable = m88e1540_get_tunable,
3006*4882a593Smuzhiyun .set_tunable = m88e1540_set_tunable,
3007*4882a593Smuzhiyun },
3008*4882a593Smuzhiyun {
3009*4882a593Smuzhiyun .phy_id = MARVELL_PHY_ID_88E1548P,
3010*4882a593Smuzhiyun .phy_id_mask = MARVELL_PHY_ID_MASK,
3011*4882a593Smuzhiyun .name = "Marvell 88E1548P",
3012*4882a593Smuzhiyun .probe = m88e1510_probe,
3013*4882a593Smuzhiyun .features = PHY_GBIT_FIBRE_FEATURES,
3014*4882a593Smuzhiyun .config_init = marvell_config_init,
3015*4882a593Smuzhiyun .config_aneg = m88e1510_config_aneg,
3016*4882a593Smuzhiyun .read_status = marvell_read_status,
3017*4882a593Smuzhiyun .ack_interrupt = marvell_ack_interrupt,
3018*4882a593Smuzhiyun .config_intr = marvell_config_intr,
3019*4882a593Smuzhiyun .did_interrupt = m88e1121_did_interrupt,
3020*4882a593Smuzhiyun .resume = genphy_resume,
3021*4882a593Smuzhiyun .suspend = genphy_suspend,
3022*4882a593Smuzhiyun .read_page = marvell_read_page,
3023*4882a593Smuzhiyun .write_page = marvell_write_page,
3024*4882a593Smuzhiyun .get_sset_count = marvell_get_sset_count,
3025*4882a593Smuzhiyun .get_strings = marvell_get_strings,
3026*4882a593Smuzhiyun .get_stats = marvell_get_stats,
3027*4882a593Smuzhiyun .get_tunable = m88e1540_get_tunable,
3028*4882a593Smuzhiyun .set_tunable = m88e1540_set_tunable,
3029*4882a593Smuzhiyun },
3030*4882a593Smuzhiyun };
3031*4882a593Smuzhiyun
3032*4882a593Smuzhiyun module_phy_driver(marvell_drivers);
3033*4882a593Smuzhiyun
3034*4882a593Smuzhiyun static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3035*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3036*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3037*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3038*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3039*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3040*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3041*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3042*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3043*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3044*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3045*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3046*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3047*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3048*4882a593Smuzhiyun { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3049*4882a593Smuzhiyun { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3050*4882a593Smuzhiyun { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3051*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3052*4882a593Smuzhiyun { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3053*4882a593Smuzhiyun { }
3054*4882a593Smuzhiyun };
3055*4882a593Smuzhiyun
3056*4882a593Smuzhiyun MODULE_DEVICE_TABLE(mdio, marvell_tbl);
3057