xref: /OK3568_Linux_fs/kernel/drivers/net/phy/lxt.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * drivers/net/phy/lxt.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Driver for Intel LXT PHYs
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Andy Fleming
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (c) 2004 Freescale Semiconductor, Inc.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/string.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/unistd.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/netdevice.h>
19*4882a593Smuzhiyun #include <linux/etherdevice.h>
20*4882a593Smuzhiyun #include <linux/skbuff.h>
21*4882a593Smuzhiyun #include <linux/spinlock.h>
22*4882a593Smuzhiyun #include <linux/mm.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/mii.h>
25*4882a593Smuzhiyun #include <linux/ethtool.h>
26*4882a593Smuzhiyun #include <linux/phy.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include <asm/io.h>
29*4882a593Smuzhiyun #include <asm/irq.h>
30*4882a593Smuzhiyun #include <linux/uaccess.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* The Level one LXT970 is used by many boards				     */
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define MII_LXT970_IER       17  /* Interrupt Enable Register */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MII_LXT970_IER_IEN	0x0002
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define MII_LXT970_ISR       18  /* Interrupt Status Register */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define MII_LXT970_CONFIG    19  /* Configuration Register    */
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */
43*4882a593Smuzhiyun /* The Level one LXT971 is used on some of my custom boards                  */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* register definitions for the 971 */
46*4882a593Smuzhiyun #define MII_LXT971_IER		18  /* Interrupt Enable Register */
47*4882a593Smuzhiyun #define MII_LXT971_IER_IEN	0x00f2
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define MII_LXT971_ISR		19  /* Interrupt Status Register */
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* register definitions for the 973 */
52*4882a593Smuzhiyun #define MII_LXT973_PCR 16 /* Port Configuration Register */
53*4882a593Smuzhiyun #define PCR_FIBER_SELECT 1
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel LXT PHY driver");
56*4882a593Smuzhiyun MODULE_AUTHOR("Andy Fleming");
57*4882a593Smuzhiyun MODULE_LICENSE("GPL");
58*4882a593Smuzhiyun 
lxt970_ack_interrupt(struct phy_device * phydev)59*4882a593Smuzhiyun static int lxt970_ack_interrupt(struct phy_device *phydev)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	int err;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	err = phy_read(phydev, MII_BMSR);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	if (err < 0)
66*4882a593Smuzhiyun 		return err;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	err = phy_read(phydev, MII_LXT970_ISR);
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	if (err < 0)
71*4882a593Smuzhiyun 		return err;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
lxt970_config_intr(struct phy_device * phydev)76*4882a593Smuzhiyun static int lxt970_config_intr(struct phy_device *phydev)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
79*4882a593Smuzhiyun 		return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
80*4882a593Smuzhiyun 	else
81*4882a593Smuzhiyun 		return phy_write(phydev, MII_LXT970_IER, 0);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
lxt970_config_init(struct phy_device * phydev)84*4882a593Smuzhiyun static int lxt970_config_init(struct phy_device *phydev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	return phy_write(phydev, MII_LXT970_CONFIG, 0);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 
lxt971_ack_interrupt(struct phy_device * phydev)90*4882a593Smuzhiyun static int lxt971_ack_interrupt(struct phy_device *phydev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	int err = phy_read(phydev, MII_LXT971_ISR);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (err < 0)
95*4882a593Smuzhiyun 		return err;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
lxt971_config_intr(struct phy_device * phydev)100*4882a593Smuzhiyun static int lxt971_config_intr(struct phy_device *phydev)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
103*4882a593Smuzhiyun 		return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
104*4882a593Smuzhiyun 	else
105*4882a593Smuzhiyun 		return phy_write(phydev, MII_LXT971_IER, 0);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun  * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
110*4882a593Smuzhiyun  * of the previous even register when you read a odd register regularly
111*4882a593Smuzhiyun  */
112*4882a593Smuzhiyun 
lxt973a2_update_link(struct phy_device * phydev)113*4882a593Smuzhiyun static int lxt973a2_update_link(struct phy_device *phydev)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	int status;
116*4882a593Smuzhiyun 	int control;
117*4882a593Smuzhiyun 	int retry = 8; /* we try 8 times */
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	/* Do a fake read */
120*4882a593Smuzhiyun 	status = phy_read(phydev, MII_BMSR);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	if (status < 0)
123*4882a593Smuzhiyun 		return status;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	control = phy_read(phydev, MII_BMCR);
126*4882a593Smuzhiyun 	if (control < 0)
127*4882a593Smuzhiyun 		return control;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	do {
130*4882a593Smuzhiyun 		/* Read link and autonegotiation status */
131*4882a593Smuzhiyun 		status = phy_read(phydev, MII_BMSR);
132*4882a593Smuzhiyun 	} while (status >= 0 && retry-- && status == control);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	if (status < 0)
135*4882a593Smuzhiyun 		return status;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if ((status & BMSR_LSTATUS) == 0)
138*4882a593Smuzhiyun 		phydev->link = 0;
139*4882a593Smuzhiyun 	else
140*4882a593Smuzhiyun 		phydev->link = 1;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun 
lxt973a2_read_status(struct phy_device * phydev)145*4882a593Smuzhiyun static int lxt973a2_read_status(struct phy_device *phydev)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	int adv;
148*4882a593Smuzhiyun 	int err;
149*4882a593Smuzhiyun 	int lpa;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* Update the link, but return if there was an error */
152*4882a593Smuzhiyun 	err = lxt973a2_update_link(phydev);
153*4882a593Smuzhiyun 	if (err)
154*4882a593Smuzhiyun 		return err;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	if (AUTONEG_ENABLE == phydev->autoneg) {
157*4882a593Smuzhiyun 		int retry = 1;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 		adv = phy_read(phydev, MII_ADVERTISE);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 		if (adv < 0)
162*4882a593Smuzhiyun 			return adv;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 		do {
165*4882a593Smuzhiyun 			lpa = phy_read(phydev, MII_LPA);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 			if (lpa < 0)
168*4882a593Smuzhiyun 				return lpa;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 			/* If both registers are equal, it is suspect but not
171*4882a593Smuzhiyun 			* impossible, hence a new try
172*4882a593Smuzhiyun 			*/
173*4882a593Smuzhiyun 		} while (lpa == adv && retry--);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 		mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 		lpa &= adv;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 		phydev->speed = SPEED_10;
180*4882a593Smuzhiyun 		phydev->duplex = DUPLEX_HALF;
181*4882a593Smuzhiyun 		phydev->pause = phydev->asym_pause = 0;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 		if (lpa & (LPA_100FULL | LPA_100HALF)) {
184*4882a593Smuzhiyun 			phydev->speed = SPEED_100;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 			if (lpa & LPA_100FULL)
187*4882a593Smuzhiyun 				phydev->duplex = DUPLEX_FULL;
188*4882a593Smuzhiyun 		} else {
189*4882a593Smuzhiyun 			if (lpa & LPA_10FULL)
190*4882a593Smuzhiyun 				phydev->duplex = DUPLEX_FULL;
191*4882a593Smuzhiyun 		}
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 		phy_resolve_aneg_pause(phydev);
194*4882a593Smuzhiyun 	} else {
195*4882a593Smuzhiyun 		err = genphy_read_status_fixed(phydev);
196*4882a593Smuzhiyun 		if (err < 0)
197*4882a593Smuzhiyun 			return err;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 		phydev->pause = phydev->asym_pause = 0;
200*4882a593Smuzhiyun 		linkmode_zero(phydev->lp_advertising);
201*4882a593Smuzhiyun 	}
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	return 0;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
lxt973_probe(struct phy_device * phydev)206*4882a593Smuzhiyun static int lxt973_probe(struct phy_device *phydev)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	int val = phy_read(phydev, MII_LXT973_PCR);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	if (val & PCR_FIBER_SELECT) {
211*4882a593Smuzhiyun 		/*
212*4882a593Smuzhiyun 		 * If fiber is selected, then the only correct setting
213*4882a593Smuzhiyun 		 * is 100Mbps, full duplex, and auto negotiation off.
214*4882a593Smuzhiyun 		 */
215*4882a593Smuzhiyun 		val = phy_read(phydev, MII_BMCR);
216*4882a593Smuzhiyun 		val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
217*4882a593Smuzhiyun 		val &= ~BMCR_ANENABLE;
218*4882a593Smuzhiyun 		phy_write(phydev, MII_BMCR, val);
219*4882a593Smuzhiyun 		/* Remember that the port is in fiber mode. */
220*4882a593Smuzhiyun 		phydev->priv = lxt973_probe;
221*4882a593Smuzhiyun 		phydev->port = PORT_FIBRE;
222*4882a593Smuzhiyun 	} else {
223*4882a593Smuzhiyun 		phydev->priv = NULL;
224*4882a593Smuzhiyun 	}
225*4882a593Smuzhiyun 	return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
lxt973_config_aneg(struct phy_device * phydev)228*4882a593Smuzhiyun static int lxt973_config_aneg(struct phy_device *phydev)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	/* Do nothing if port is in fiber mode. */
231*4882a593Smuzhiyun 	return phydev->priv ? 0 : genphy_config_aneg(phydev);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun static struct phy_driver lxt97x_driver[] = {
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun 	.phy_id		= 0x78100000,
237*4882a593Smuzhiyun 	.name		= "LXT970",
238*4882a593Smuzhiyun 	.phy_id_mask	= 0xfffffff0,
239*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
240*4882a593Smuzhiyun 	.config_init	= lxt970_config_init,
241*4882a593Smuzhiyun 	.ack_interrupt	= lxt970_ack_interrupt,
242*4882a593Smuzhiyun 	.config_intr	= lxt970_config_intr,
243*4882a593Smuzhiyun }, {
244*4882a593Smuzhiyun 	.phy_id		= 0x001378e0,
245*4882a593Smuzhiyun 	.name		= "LXT971",
246*4882a593Smuzhiyun 	.phy_id_mask	= 0xfffffff0,
247*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
248*4882a593Smuzhiyun 	.ack_interrupt	= lxt971_ack_interrupt,
249*4882a593Smuzhiyun 	.config_intr	= lxt971_config_intr,
250*4882a593Smuzhiyun 	.suspend	= genphy_suspend,
251*4882a593Smuzhiyun 	.resume		= genphy_resume,
252*4882a593Smuzhiyun }, {
253*4882a593Smuzhiyun 	.phy_id		= 0x00137a10,
254*4882a593Smuzhiyun 	.name		= "LXT973-A2",
255*4882a593Smuzhiyun 	.phy_id_mask	= 0xffffffff,
256*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
257*4882a593Smuzhiyun 	.flags		= 0,
258*4882a593Smuzhiyun 	.probe		= lxt973_probe,
259*4882a593Smuzhiyun 	.config_aneg	= lxt973_config_aneg,
260*4882a593Smuzhiyun 	.read_status	= lxt973a2_read_status,
261*4882a593Smuzhiyun 	.suspend	= genphy_suspend,
262*4882a593Smuzhiyun 	.resume		= genphy_resume,
263*4882a593Smuzhiyun }, {
264*4882a593Smuzhiyun 	.phy_id		= 0x00137a10,
265*4882a593Smuzhiyun 	.name		= "LXT973",
266*4882a593Smuzhiyun 	.phy_id_mask	= 0xfffffff0,
267*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
268*4882a593Smuzhiyun 	.flags		= 0,
269*4882a593Smuzhiyun 	.probe		= lxt973_probe,
270*4882a593Smuzhiyun 	.config_aneg	= lxt973_config_aneg,
271*4882a593Smuzhiyun 	.suspend	= genphy_suspend,
272*4882a593Smuzhiyun 	.resume		= genphy_resume,
273*4882a593Smuzhiyun } };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun module_phy_driver(lxt97x_driver);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun static struct mdio_device_id __maybe_unused lxt_tbl[] = {
278*4882a593Smuzhiyun 	{ 0x78100000, 0xfffffff0 },
279*4882a593Smuzhiyun 	{ 0x001378e0, 0xfffffff0 },
280*4882a593Smuzhiyun 	{ 0x00137a10, 0xfffffff0 },
281*4882a593Smuzhiyun 	{ }
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun MODULE_DEVICE_TABLE(mdio, lxt_tbl);
285