1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/kernel.h>
9 #include <linux/mii.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/delay.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/bitfield.h>
17
18 #include <dt-bindings/net/ti-dp83867.h>
19
20 #define DP83867_PHY_ID 0x2000a231
21 #define DP83867_DEVADDR 0x1f
22
23 #define MII_DP83867_PHYCTRL 0x10
24 #define MII_DP83867_PHYSTS 0x11
25 #define MII_DP83867_MICR 0x12
26 #define MII_DP83867_ISR 0x13
27 #define DP83867_CFG2 0x14
28 #define DP83867_CFG3 0x1e
29 #define DP83867_CTRL 0x1f
30
31 /* Extended Registers */
32 #define DP83867_FLD_THR_CFG 0x002e
33 #define DP83867_CFG4 0x0031
34 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
35 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
36 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
37 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
38 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
39
40 #define DP83867_RGMIICTL 0x0032
41 #define DP83867_STRAP_STS1 0x006E
42 #define DP83867_STRAP_STS2 0x006f
43 #define DP83867_RGMIIDCTL 0x0086
44 #define DP83867_RXFCFG 0x0134
45 #define DP83867_RXFPMD1 0x0136
46 #define DP83867_RXFPMD2 0x0137
47 #define DP83867_RXFPMD3 0x0138
48 #define DP83867_RXFSOP1 0x0139
49 #define DP83867_RXFSOP2 0x013A
50 #define DP83867_RXFSOP3 0x013B
51 #define DP83867_IO_MUX_CFG 0x0170
52 #define DP83867_SGMIICTL 0x00D3
53 #define DP83867_10M_SGMII_CFG 0x016F
54 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
55
56 #define DP83867_SW_RESET BIT(15)
57 #define DP83867_SW_RESTART BIT(14)
58
59 /* MICR Interrupt bits */
60 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
61 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
62 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
63 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
64 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
65 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
66 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
67 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
68 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
69 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
70 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
71 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
72
73 /* RGMIICTL bits */
74 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
75 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
76
77 /* SGMIICTL bits */
78 #define DP83867_SGMII_TYPE BIT(14)
79
80 /* RXFCFG bits*/
81 #define DP83867_WOL_MAGIC_EN BIT(0)
82 #define DP83867_WOL_BCAST_EN BIT(2)
83 #define DP83867_WOL_UCAST_EN BIT(4)
84 #define DP83867_WOL_SEC_EN BIT(5)
85 #define DP83867_WOL_ENH_MAC BIT(7)
86
87 /* STRAP_STS1 bits */
88 #define DP83867_STRAP_STS1_RESERVED BIT(11)
89
90 /* STRAP_STS2 bits */
91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
95 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
96 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
97
98 /* PHY CTRL bits */
99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
101 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
104 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
105 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
106
107 /* RGMIIDCTL bits */
108 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
109 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
110 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
111 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
112 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
113 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
114
115 /* IO_MUX_CFG bits */
116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
122
123 /* PHY STS bits */
124 #define DP83867_PHYSTS_1000 BIT(15)
125 #define DP83867_PHYSTS_100 BIT(14)
126 #define DP83867_PHYSTS_DUPLEX BIT(13)
127 #define DP83867_PHYSTS_LINK BIT(10)
128
129 /* CFG2 bits */
130 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
131 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
132 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0
133 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1
134 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2
135 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3
136 #define DP83867_DOWNSHIFT_1_COUNT 1
137 #define DP83867_DOWNSHIFT_2_COUNT 2
138 #define DP83867_DOWNSHIFT_4_COUNT 4
139 #define DP83867_DOWNSHIFT_8_COUNT 8
140 #define DP83867_SGMII_AUTONEG_EN BIT(7)
141
142 /* CFG3 bits */
143 #define DP83867_CFG3_INT_OE BIT(7)
144 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
145
146 /* CFG4 bits */
147 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
148
149 /* FLD_THR_CFG */
150 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
151
152 enum {
153 DP83867_PORT_MIRROING_KEEP,
154 DP83867_PORT_MIRROING_EN,
155 DP83867_PORT_MIRROING_DIS,
156 };
157
158 struct dp83867_private {
159 u32 rx_id_delay;
160 u32 tx_id_delay;
161 u32 tx_fifo_depth;
162 u32 rx_fifo_depth;
163 int io_impedance;
164 int port_mirroring;
165 bool rxctrl_strap_quirk;
166 bool set_clk_output;
167 u32 clk_output_sel;
168 bool sgmii_ref_clk_en;
169 };
170
dp83867_ack_interrupt(struct phy_device * phydev)171 static int dp83867_ack_interrupt(struct phy_device *phydev)
172 {
173 int err = phy_read(phydev, MII_DP83867_ISR);
174
175 if (err < 0)
176 return err;
177
178 return 0;
179 }
180
dp83867_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)181 static int dp83867_set_wol(struct phy_device *phydev,
182 struct ethtool_wolinfo *wol)
183 {
184 struct net_device *ndev = phydev->attached_dev;
185 u16 val_rxcfg, val_micr;
186 u8 *mac;
187
188 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
189 val_micr = phy_read(phydev, MII_DP83867_MICR);
190
191 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
192 WAKE_BCAST)) {
193 val_rxcfg |= DP83867_WOL_ENH_MAC;
194 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
195
196 if (wol->wolopts & WAKE_MAGIC) {
197 mac = (u8 *)ndev->dev_addr;
198
199 if (!is_valid_ether_addr(mac))
200 return -EINVAL;
201
202 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
203 (mac[1] << 8 | mac[0]));
204 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
205 (mac[3] << 8 | mac[2]));
206 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
207 (mac[5] << 8 | mac[4]));
208
209 val_rxcfg |= DP83867_WOL_MAGIC_EN;
210 } else {
211 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
212 }
213
214 if (wol->wolopts & WAKE_MAGICSECURE) {
215 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
216 (wol->sopass[1] << 8) | wol->sopass[0]);
217 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
218 (wol->sopass[3] << 8) | wol->sopass[2]);
219 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
220 (wol->sopass[5] << 8) | wol->sopass[4]);
221
222 val_rxcfg |= DP83867_WOL_SEC_EN;
223 } else {
224 val_rxcfg &= ~DP83867_WOL_SEC_EN;
225 }
226
227 if (wol->wolopts & WAKE_UCAST)
228 val_rxcfg |= DP83867_WOL_UCAST_EN;
229 else
230 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
231
232 if (wol->wolopts & WAKE_BCAST)
233 val_rxcfg |= DP83867_WOL_BCAST_EN;
234 else
235 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
236 } else {
237 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
238 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
239 }
240
241 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
242 phy_write(phydev, MII_DP83867_MICR, val_micr);
243
244 return 0;
245 }
246
dp83867_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)247 static void dp83867_get_wol(struct phy_device *phydev,
248 struct ethtool_wolinfo *wol)
249 {
250 u16 value, sopass_val;
251
252 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
253 WAKE_MAGICSECURE);
254 wol->wolopts = 0;
255
256 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
257
258 if (value & DP83867_WOL_UCAST_EN)
259 wol->wolopts |= WAKE_UCAST;
260
261 if (value & DP83867_WOL_BCAST_EN)
262 wol->wolopts |= WAKE_BCAST;
263
264 if (value & DP83867_WOL_MAGIC_EN)
265 wol->wolopts |= WAKE_MAGIC;
266
267 if (value & DP83867_WOL_SEC_EN) {
268 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
269 DP83867_RXFSOP1);
270 wol->sopass[0] = (sopass_val & 0xff);
271 wol->sopass[1] = (sopass_val >> 8);
272
273 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
274 DP83867_RXFSOP2);
275 wol->sopass[2] = (sopass_val & 0xff);
276 wol->sopass[3] = (sopass_val >> 8);
277
278 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
279 DP83867_RXFSOP3);
280 wol->sopass[4] = (sopass_val & 0xff);
281 wol->sopass[5] = (sopass_val >> 8);
282
283 wol->wolopts |= WAKE_MAGICSECURE;
284 }
285
286 if (!(value & DP83867_WOL_ENH_MAC))
287 wol->wolopts = 0;
288 }
289
dp83867_config_intr(struct phy_device * phydev)290 static int dp83867_config_intr(struct phy_device *phydev)
291 {
292 int micr_status;
293
294 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
295 micr_status = phy_read(phydev, MII_DP83867_MICR);
296 if (micr_status < 0)
297 return micr_status;
298
299 micr_status |=
300 (MII_DP83867_MICR_AN_ERR_INT_EN |
301 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
302 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
303 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
304 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
305 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
306
307 return phy_write(phydev, MII_DP83867_MICR, micr_status);
308 }
309
310 micr_status = 0x0;
311 return phy_write(phydev, MII_DP83867_MICR, micr_status);
312 }
313
dp83867_read_status(struct phy_device * phydev)314 static int dp83867_read_status(struct phy_device *phydev)
315 {
316 int status = phy_read(phydev, MII_DP83867_PHYSTS);
317 int ret;
318
319 ret = genphy_read_status(phydev);
320 if (ret)
321 return ret;
322
323 if (status < 0)
324 return status;
325
326 if (status & DP83867_PHYSTS_DUPLEX)
327 phydev->duplex = DUPLEX_FULL;
328 else
329 phydev->duplex = DUPLEX_HALF;
330
331 if (status & DP83867_PHYSTS_1000)
332 phydev->speed = SPEED_1000;
333 else if (status & DP83867_PHYSTS_100)
334 phydev->speed = SPEED_100;
335 else
336 phydev->speed = SPEED_10;
337
338 return 0;
339 }
340
dp83867_get_downshift(struct phy_device * phydev,u8 * data)341 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
342 {
343 int val, cnt, enable, count;
344
345 val = phy_read(phydev, DP83867_CFG2);
346 if (val < 0)
347 return val;
348
349 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
350 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
351
352 switch (cnt) {
353 case DP83867_DOWNSHIFT_1_COUNT_VAL:
354 count = DP83867_DOWNSHIFT_1_COUNT;
355 break;
356 case DP83867_DOWNSHIFT_2_COUNT_VAL:
357 count = DP83867_DOWNSHIFT_2_COUNT;
358 break;
359 case DP83867_DOWNSHIFT_4_COUNT_VAL:
360 count = DP83867_DOWNSHIFT_4_COUNT;
361 break;
362 case DP83867_DOWNSHIFT_8_COUNT_VAL:
363 count = DP83867_DOWNSHIFT_8_COUNT;
364 break;
365 default:
366 return -EINVAL;
367 }
368
369 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
370
371 return 0;
372 }
373
dp83867_set_downshift(struct phy_device * phydev,u8 cnt)374 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
375 {
376 int val, count;
377
378 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
379 return -E2BIG;
380
381 if (!cnt)
382 return phy_clear_bits(phydev, DP83867_CFG2,
383 DP83867_DOWNSHIFT_EN);
384
385 switch (cnt) {
386 case DP83867_DOWNSHIFT_1_COUNT:
387 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
388 break;
389 case DP83867_DOWNSHIFT_2_COUNT:
390 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
391 break;
392 case DP83867_DOWNSHIFT_4_COUNT:
393 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
394 break;
395 case DP83867_DOWNSHIFT_8_COUNT:
396 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
397 break;
398 default:
399 phydev_err(phydev,
400 "Downshift count must be 1, 2, 4 or 8\n");
401 return -EINVAL;
402 }
403
404 val = DP83867_DOWNSHIFT_EN;
405 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
406
407 return phy_modify(phydev, DP83867_CFG2,
408 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
409 val);
410 }
411
dp83867_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)412 static int dp83867_get_tunable(struct phy_device *phydev,
413 struct ethtool_tunable *tuna, void *data)
414 {
415 switch (tuna->id) {
416 case ETHTOOL_PHY_DOWNSHIFT:
417 return dp83867_get_downshift(phydev, data);
418 default:
419 return -EOPNOTSUPP;
420 }
421 }
422
dp83867_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)423 static int dp83867_set_tunable(struct phy_device *phydev,
424 struct ethtool_tunable *tuna, const void *data)
425 {
426 switch (tuna->id) {
427 case ETHTOOL_PHY_DOWNSHIFT:
428 return dp83867_set_downshift(phydev, *(const u8 *)data);
429 default:
430 return -EOPNOTSUPP;
431 }
432 }
433
dp83867_config_port_mirroring(struct phy_device * phydev)434 static int dp83867_config_port_mirroring(struct phy_device *phydev)
435 {
436 struct dp83867_private *dp83867 =
437 (struct dp83867_private *)phydev->priv;
438
439 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
440 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
441 DP83867_CFG4_PORT_MIRROR_EN);
442 else
443 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
444 DP83867_CFG4_PORT_MIRROR_EN);
445 return 0;
446 }
447
dp83867_verify_rgmii_cfg(struct phy_device * phydev)448 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
449 {
450 struct dp83867_private *dp83867 = phydev->priv;
451
452 /* Existing behavior was to use default pin strapping delay in rgmii
453 * mode, but rgmii should have meant no delay. Warn existing users.
454 */
455 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
456 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
457 DP83867_STRAP_STS2);
458 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
459 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
460 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
461 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
462
463 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
464 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
465 phydev_warn(phydev,
466 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
467 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
468 txskew, rxskew);
469 }
470
471 /* RX delay *must* be specified if internal delay of RX is used. */
472 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
473 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
474 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
475 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
476 return -EINVAL;
477 }
478
479 /* TX delay *must* be specified if internal delay of TX is used. */
480 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
481 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
482 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
483 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
484 return -EINVAL;
485 }
486
487 return 0;
488 }
489
490 #if IS_ENABLED(CONFIG_OF_MDIO)
dp83867_of_init(struct phy_device * phydev)491 static int dp83867_of_init(struct phy_device *phydev)
492 {
493 struct dp83867_private *dp83867 = phydev->priv;
494 struct device *dev = &phydev->mdio.dev;
495 struct device_node *of_node = dev->of_node;
496 int ret;
497
498 if (!of_node)
499 return -ENODEV;
500
501 /* Optional configuration */
502 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
503 &dp83867->clk_output_sel);
504 /* If not set, keep default */
505 if (!ret) {
506 dp83867->set_clk_output = true;
507 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
508 * DP83867_CLK_O_SEL_OFF.
509 */
510 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
511 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
512 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
513 dp83867->clk_output_sel);
514 return -EINVAL;
515 }
516 }
517
518 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
519 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
520 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
521 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
522 else
523 dp83867->io_impedance = -1; /* leave at default */
524
525 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
526 "ti,dp83867-rxctrl-strap-quirk");
527
528 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
529 "ti,sgmii-ref-clock-output-enable");
530
531 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
532 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
533 &dp83867->rx_id_delay);
534 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
535 phydev_err(phydev,
536 "ti,rx-internal-delay value of %u out of range\n",
537 dp83867->rx_id_delay);
538 return -EINVAL;
539 }
540
541 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
542 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
543 &dp83867->tx_id_delay);
544 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
545 phydev_err(phydev,
546 "ti,tx-internal-delay value of %u out of range\n",
547 dp83867->tx_id_delay);
548 return -EINVAL;
549 }
550
551 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
552 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
553
554 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
555 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
556
557 ret = of_property_read_u32(of_node, "ti,fifo-depth",
558 &dp83867->tx_fifo_depth);
559 if (ret) {
560 ret = of_property_read_u32(of_node, "tx-fifo-depth",
561 &dp83867->tx_fifo_depth);
562 if (ret)
563 dp83867->tx_fifo_depth =
564 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
565 }
566
567 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
568 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
569 dp83867->tx_fifo_depth);
570 return -EINVAL;
571 }
572
573 ret = of_property_read_u32(of_node, "rx-fifo-depth",
574 &dp83867->rx_fifo_depth);
575 if (ret)
576 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
577
578 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
579 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
580 dp83867->rx_fifo_depth);
581 return -EINVAL;
582 }
583
584 return 0;
585 }
586 #else
dp83867_of_init(struct phy_device * phydev)587 static int dp83867_of_init(struct phy_device *phydev)
588 {
589 return 0;
590 }
591 #endif /* CONFIG_OF_MDIO */
592
dp83867_probe(struct phy_device * phydev)593 static int dp83867_probe(struct phy_device *phydev)
594 {
595 struct dp83867_private *dp83867;
596
597 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
598 GFP_KERNEL);
599 if (!dp83867)
600 return -ENOMEM;
601
602 phydev->priv = dp83867;
603
604 return dp83867_of_init(phydev);
605 }
606
dp83867_config_init(struct phy_device * phydev)607 static int dp83867_config_init(struct phy_device *phydev)
608 {
609 struct dp83867_private *dp83867 = phydev->priv;
610 int ret, val, bs;
611 u16 delay;
612
613 /* Force speed optimization for the PHY even if it strapped */
614 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
615 DP83867_DOWNSHIFT_EN);
616 if (ret)
617 return ret;
618
619 ret = dp83867_verify_rgmii_cfg(phydev);
620 if (ret)
621 return ret;
622
623 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
624 if (dp83867->rxctrl_strap_quirk)
625 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
626 BIT(7));
627
628 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
629 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
630 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
631 * be set to 0x2. This may causes the PHY link to be unstable -
632 * the default value 0x1 need to be restored.
633 */
634 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
635 DP83867_FLD_THR_CFG,
636 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
637 0x1);
638 if (ret)
639 return ret;
640 }
641
642 if (phy_interface_is_rgmii(phydev) ||
643 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
644 val = phy_read(phydev, MII_DP83867_PHYCTRL);
645 if (val < 0)
646 return val;
647
648 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
649 val |= (dp83867->tx_fifo_depth <<
650 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
651
652 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
653 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
654 val |= (dp83867->rx_fifo_depth <<
655 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
656 }
657
658 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
659 if (ret)
660 return ret;
661 }
662
663 if (phy_interface_is_rgmii(phydev)) {
664 val = phy_read(phydev, MII_DP83867_PHYCTRL);
665 if (val < 0)
666 return val;
667
668 /* The code below checks if "port mirroring" N/A MODE4 has been
669 * enabled during power on bootstrap.
670 *
671 * Such N/A mode enabled by mistake can put PHY IC in some
672 * internal testing mode and disable RGMII transmission.
673 *
674 * In this particular case one needs to check STRAP_STS1
675 * register's bit 11 (marked as RESERVED).
676 */
677
678 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
679 if (bs & DP83867_STRAP_STS1_RESERVED)
680 val &= ~DP83867_PHYCR_RESERVED_MASK;
681
682 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
683 if (ret)
684 return ret;
685
686 /* If rgmii mode with no internal delay is selected, we do NOT use
687 * aligned mode as one might expect. Instead we use the PHY's default
688 * based on pin strapping. And the "mode 0" default is to *use*
689 * internal delay with a value of 7 (2.00 ns).
690 *
691 * Set up RGMII delays
692 */
693 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
694
695 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
696 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
697 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
698
699 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
700 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
701
702 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
703 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
704
705 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
706
707 delay = 0;
708 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
709 delay |= dp83867->rx_id_delay;
710 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
711 delay |= dp83867->tx_id_delay <<
712 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
713
714 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
715 delay);
716 }
717
718 /* If specified, set io impedance */
719 if (dp83867->io_impedance >= 0)
720 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
721 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
722 dp83867->io_impedance);
723
724 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
725 /* For support SPEED_10 in SGMII mode
726 * DP83867_10M_SGMII_RATE_ADAPT bit
727 * has to be cleared by software. That
728 * does not affect SPEED_100 and
729 * SPEED_1000.
730 */
731 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
732 DP83867_10M_SGMII_CFG,
733 DP83867_10M_SGMII_RATE_ADAPT_MASK,
734 0);
735 if (ret)
736 return ret;
737
738 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
739 * are 01). That is not enough to finalize autoneg on some
740 * devices. Increase this timer duration to maximum 16ms.
741 */
742 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
743 DP83867_CFG4,
744 DP83867_CFG4_SGMII_ANEG_MASK,
745 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
746
747 if (ret)
748 return ret;
749
750 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
751 /* SGMII type is set to 4-wire mode by default.
752 * If we place appropriate property in dts (see above)
753 * switch on 6-wire mode.
754 */
755 if (dp83867->sgmii_ref_clk_en)
756 val |= DP83867_SGMII_TYPE;
757 else
758 val &= ~DP83867_SGMII_TYPE;
759 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
760
761 /* This is a SW workaround for link instability if RX_CTRL is
762 * not strapped to mode 3 or 4 in HW. This is required for SGMII
763 * in addition to clearing bit 7, handled above.
764 */
765 if (dp83867->rxctrl_strap_quirk)
766 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
767 BIT(8));
768 }
769
770 val = phy_read(phydev, DP83867_CFG3);
771 /* Enable Interrupt output INT_OE in CFG3 register */
772 if (phy_interrupt_is_valid(phydev))
773 val |= DP83867_CFG3_INT_OE;
774
775 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
776 phy_write(phydev, DP83867_CFG3, val);
777
778 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
779 dp83867_config_port_mirroring(phydev);
780
781 /* Clock output selection if muxing property is set */
782 if (dp83867->set_clk_output) {
783 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
784
785 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
786 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
787 } else {
788 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
789 val = dp83867->clk_output_sel <<
790 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
791 }
792
793 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
794 mask, val);
795 }
796
797 return 0;
798 }
799
dp83867_phy_reset(struct phy_device * phydev)800 static int dp83867_phy_reset(struct phy_device *phydev)
801 {
802 int err;
803
804 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
805 if (err < 0)
806 return err;
807
808 usleep_range(10, 20);
809
810 return phy_modify(phydev, MII_DP83867_PHYCTRL,
811 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
812 }
813
dp83867_link_change_notify(struct phy_device * phydev)814 static void dp83867_link_change_notify(struct phy_device *phydev)
815 {
816 /* There is a limitation in DP83867 PHY device where SGMII AN is
817 * only triggered once after the device is booted up. Even after the
818 * PHY TPI is down and up again, SGMII AN is not triggered and
819 * hence no new in-band message from PHY to MAC side SGMII.
820 * This could cause an issue during power up, when PHY is up prior
821 * to MAC. At this condition, once MAC side SGMII is up, MAC side
822 * SGMII wouldn`t receive new in-band message from TI PHY with
823 * correct link status, speed and duplex info.
824 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
825 * whenever there is a link change.
826 */
827 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
828 int val = 0;
829
830 val = phy_clear_bits(phydev, DP83867_CFG2,
831 DP83867_SGMII_AUTONEG_EN);
832 if (val < 0)
833 return;
834
835 phy_set_bits(phydev, DP83867_CFG2,
836 DP83867_SGMII_AUTONEG_EN);
837 }
838 }
839
840 static struct phy_driver dp83867_driver[] = {
841 {
842 .phy_id = DP83867_PHY_ID,
843 .phy_id_mask = 0xfffffff0,
844 .name = "TI DP83867",
845 /* PHY_GBIT_FEATURES */
846
847 .probe = dp83867_probe,
848 .config_init = dp83867_config_init,
849 .soft_reset = dp83867_phy_reset,
850
851 .read_status = dp83867_read_status,
852 .get_tunable = dp83867_get_tunable,
853 .set_tunable = dp83867_set_tunable,
854
855 .get_wol = dp83867_get_wol,
856 .set_wol = dp83867_set_wol,
857
858 /* IRQ related */
859 .ack_interrupt = dp83867_ack_interrupt,
860 .config_intr = dp83867_config_intr,
861
862 .suspend = genphy_suspend,
863 .resume = genphy_resume,
864
865 .link_change_notify = dp83867_link_change_notify,
866 },
867 };
868 module_phy_driver(dp83867_driver);
869
870 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
871 { DP83867_PHY_ID, 0xfffffff0 },
872 { }
873 };
874
875 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
876
877 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
878 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
879 MODULE_LICENSE("GPL v2");
880