1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Texas Instruments DP83848 PHY
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/phy.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define TI_DP83848C_PHY_ID 0x20005ca0
12*4882a593Smuzhiyun #define TI_DP83620_PHY_ID 0x20005ce0
13*4882a593Smuzhiyun #define NS_DP83848C_PHY_ID 0x20005c90
14*4882a593Smuzhiyun #define TLK10X_PHY_ID 0x2000a210
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Registers */
17*4882a593Smuzhiyun #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
18*4882a593Smuzhiyun #define DP83848_MISR 0x12 /* MII Interrupt Status Register */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* MICR Register Fields */
21*4882a593Smuzhiyun #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
22*4882a593Smuzhiyun #define DP83848_MICR_INTEN BIT(1) /* Interrupt Enable */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* MISR Register Fields */
25*4882a593Smuzhiyun #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
26*4882a593Smuzhiyun #define DP83848_MISR_FHF_INT_EN BIT(1) /* False Carrier Counter */
27*4882a593Smuzhiyun #define DP83848_MISR_ANC_INT_EN BIT(2) /* Auto-negotiation complete */
28*4882a593Smuzhiyun #define DP83848_MISR_DUP_INT_EN BIT(3) /* Duplex Status */
29*4882a593Smuzhiyun #define DP83848_MISR_SPD_INT_EN BIT(4) /* Speed status */
30*4882a593Smuzhiyun #define DP83848_MISR_LINK_INT_EN BIT(5) /* Link status */
31*4882a593Smuzhiyun #define DP83848_MISR_ED_INT_EN BIT(6) /* Energy detect */
32*4882a593Smuzhiyun #define DP83848_MISR_LQM_INT_EN BIT(7) /* Link Quality Monitor */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define DP83848_INT_EN_MASK \
35*4882a593Smuzhiyun (DP83848_MISR_ANC_INT_EN | \
36*4882a593Smuzhiyun DP83848_MISR_DUP_INT_EN | \
37*4882a593Smuzhiyun DP83848_MISR_SPD_INT_EN | \
38*4882a593Smuzhiyun DP83848_MISR_LINK_INT_EN)
39*4882a593Smuzhiyun
dp83848_ack_interrupt(struct phy_device * phydev)40*4882a593Smuzhiyun static int dp83848_ack_interrupt(struct phy_device *phydev)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun int err = phy_read(phydev, DP83848_MISR);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return err < 0 ? err : 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
dp83848_config_intr(struct phy_device * phydev)47*4882a593Smuzhiyun static int dp83848_config_intr(struct phy_device *phydev)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun int control, ret;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun control = phy_read(phydev, DP83848_MICR);
52*4882a593Smuzhiyun if (control < 0)
53*4882a593Smuzhiyun return control;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
56*4882a593Smuzhiyun control |= DP83848_MICR_INT_OE;
57*4882a593Smuzhiyun control |= DP83848_MICR_INTEN;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK);
60*4882a593Smuzhiyun if (ret < 0)
61*4882a593Smuzhiyun return ret;
62*4882a593Smuzhiyun } else {
63*4882a593Smuzhiyun control &= ~DP83848_MICR_INTEN;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return phy_write(phydev, DP83848_MICR, control);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
dp83848_config_init(struct phy_device * phydev)69*4882a593Smuzhiyun static int dp83848_config_init(struct phy_device *phydev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int val;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* DP83620 always reports Auto Negotiation Ability on BMSR. Instead,
74*4882a593Smuzhiyun * we check initial value of BMCR Auto negotiation enable bit
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun val = phy_read(phydev, MII_BMCR);
77*4882a593Smuzhiyun if (!(val & BMCR_ANENABLE))
78*4882a593Smuzhiyun phydev->autoneg = AUTONEG_DISABLE;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static struct mdio_device_id __maybe_unused dp83848_tbl[] = {
84*4882a593Smuzhiyun { TI_DP83848C_PHY_ID, 0xfffffff0 },
85*4882a593Smuzhiyun { NS_DP83848C_PHY_ID, 0xfffffff0 },
86*4882a593Smuzhiyun { TI_DP83620_PHY_ID, 0xfffffff0 },
87*4882a593Smuzhiyun { TLK10X_PHY_ID, 0xfffffff0 },
88*4882a593Smuzhiyun { }
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun MODULE_DEVICE_TABLE(mdio, dp83848_tbl);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define DP83848_PHY_DRIVER(_id, _name, _config_init) \
93*4882a593Smuzhiyun { \
94*4882a593Smuzhiyun .phy_id = _id, \
95*4882a593Smuzhiyun .phy_id_mask = 0xfffffff0, \
96*4882a593Smuzhiyun .name = _name, \
97*4882a593Smuzhiyun /* PHY_BASIC_FEATURES */ \
98*4882a593Smuzhiyun \
99*4882a593Smuzhiyun .soft_reset = genphy_soft_reset, \
100*4882a593Smuzhiyun .config_init = _config_init, \
101*4882a593Smuzhiyun .suspend = genphy_suspend, \
102*4882a593Smuzhiyun .resume = genphy_resume, \
103*4882a593Smuzhiyun \
104*4882a593Smuzhiyun /* IRQ related */ \
105*4882a593Smuzhiyun .ack_interrupt = dp83848_ack_interrupt, \
106*4882a593Smuzhiyun .config_intr = dp83848_config_intr, \
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun static struct phy_driver dp83848_driver[] = {
110*4882a593Smuzhiyun DP83848_PHY_DRIVER(TI_DP83848C_PHY_ID, "TI DP83848C 10/100 Mbps PHY",
111*4882a593Smuzhiyun NULL),
112*4882a593Smuzhiyun DP83848_PHY_DRIVER(NS_DP83848C_PHY_ID, "NS DP83848C 10/100 Mbps PHY",
113*4882a593Smuzhiyun NULL),
114*4882a593Smuzhiyun DP83848_PHY_DRIVER(TI_DP83620_PHY_ID, "TI DP83620 10/100 Mbps PHY",
115*4882a593Smuzhiyun dp83848_config_init),
116*4882a593Smuzhiyun DP83848_PHY_DRIVER(TLK10X_PHY_ID, "TI TLK10X 10/100 Mbps PHY",
117*4882a593Smuzhiyun NULL),
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun module_phy_driver(dp83848_driver);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments DP83848 PHY driver");
122*4882a593Smuzhiyun MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
123*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
124