1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* dp83640_reg.h 3*4882a593Smuzhiyun * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef HAVE_DP83640_REGISTERS 6*4882a593Smuzhiyun #define HAVE_DP83640_REGISTERS 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* #define PAGE0 0x0000 */ 9*4882a593Smuzhiyun #define PHYCR2 0x001c /* PHY Control Register 2 */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PAGE4 0x0004 12*4882a593Smuzhiyun #define PTP_CTL 0x0014 /* PTP Control Register */ 13*4882a593Smuzhiyun #define PTP_TDR 0x0015 /* PTP Time Data Register */ 14*4882a593Smuzhiyun #define PTP_STS 0x0016 /* PTP Status Register */ 15*4882a593Smuzhiyun #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */ 16*4882a593Smuzhiyun #define PTP_RATEL 0x0018 /* PTP Rate Low Register */ 17*4882a593Smuzhiyun #define PTP_RATEH 0x0019 /* PTP Rate High Register */ 18*4882a593Smuzhiyun #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */ 19*4882a593Smuzhiyun #define PTP_WRCKSUM 0x001b /* PTP Write Checksum */ 20*4882a593Smuzhiyun #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */ 21*4882a593Smuzhiyun #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */ 22*4882a593Smuzhiyun #define PTP_ESTS 0x001e /* PTP Event Status Register */ 23*4882a593Smuzhiyun #define PTP_EDATA 0x001f /* PTP Event Data Register */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PAGE5 0x0005 26*4882a593Smuzhiyun #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */ 27*4882a593Smuzhiyun #define PTP_EVNT 0x0015 /* PTP Event Configuration Register */ 28*4882a593Smuzhiyun #define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */ 29*4882a593Smuzhiyun #define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */ 30*4882a593Smuzhiyun #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */ 31*4882a593Smuzhiyun #define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */ 32*4882a593Smuzhiyun #define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */ 33*4882a593Smuzhiyun #define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */ 34*4882a593Smuzhiyun #define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */ 35*4882a593Smuzhiyun #define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */ 36*4882a593Smuzhiyun #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */ 37*4882a593Smuzhiyun #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PAGE6 0x0006 40*4882a593Smuzhiyun #define PTP_COC 0x0014 /* PTP Clock Output Control Register */ 41*4882a593Smuzhiyun #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */ 42*4882a593Smuzhiyun #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */ 43*4882a593Smuzhiyun #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */ 44*4882a593Smuzhiyun #define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */ 45*4882a593Smuzhiyun #define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */ 46*4882a593Smuzhiyun #define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */ 47*4882a593Smuzhiyun #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */ 48*4882a593Smuzhiyun #define PTP_ETR 0x001c /* PTP Ethernet Type Register */ 49*4882a593Smuzhiyun #define PTP_OFF 0x001d /* PTP Offset Register */ 50*4882a593Smuzhiyun #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */ 51*4882a593Smuzhiyun #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Bit definitions for the PHYCR2 register */ 54*4882a593Smuzhiyun #define BC_WRITE (1<<11) /* Broadcast Write Enable */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Bit definitions for the PTP_CTL register */ 57*4882a593Smuzhiyun #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */ 58*4882a593Smuzhiyun #define TRIG_SEL_MASK (0x7) 59*4882a593Smuzhiyun #define TRIG_DIS (1<<9) /* Disable PTP Trigger */ 60*4882a593Smuzhiyun #define TRIG_EN (1<<8) /* Enable PTP Trigger */ 61*4882a593Smuzhiyun #define TRIG_READ (1<<7) /* Read PTP Trigger */ 62*4882a593Smuzhiyun #define TRIG_LOAD (1<<6) /* Load PTP Trigger */ 63*4882a593Smuzhiyun #define PTP_RD_CLK (1<<5) /* Read PTP Clock */ 64*4882a593Smuzhiyun #define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */ 65*4882a593Smuzhiyun #define PTP_STEP_CLK (1<<3) /* Step PTP Clock */ 66*4882a593Smuzhiyun #define PTP_ENABLE (1<<2) /* Enable PTP Clock */ 67*4882a593Smuzhiyun #define PTP_DISABLE (1<<1) /* Disable PTP Clock */ 68*4882a593Smuzhiyun #define PTP_RESET (1<<0) /* Reset PTP Clock */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Bit definitions for the PTP_STS register */ 71*4882a593Smuzhiyun #define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */ 72*4882a593Smuzhiyun #define RXTS_RDY (1<<10) /* Receive Timestamp Ready */ 73*4882a593Smuzhiyun #define TRIG_DONE (1<<9) /* PTP Trigger Done */ 74*4882a593Smuzhiyun #define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */ 75*4882a593Smuzhiyun #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */ 76*4882a593Smuzhiyun #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */ 77*4882a593Smuzhiyun #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */ 78*4882a593Smuzhiyun #define EVENT_IE (1<<0) /* Event Interrupt Enable */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Bit definitions for the PTP_TSTS register */ 81*4882a593Smuzhiyun #define TRIG7_ERROR (1<<15) /* Trigger 7 Error */ 82*4882a593Smuzhiyun #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */ 83*4882a593Smuzhiyun #define TRIG6_ERROR (1<<13) /* Trigger 6 Error */ 84*4882a593Smuzhiyun #define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */ 85*4882a593Smuzhiyun #define TRIG5_ERROR (1<<11) /* Trigger 5 Error */ 86*4882a593Smuzhiyun #define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */ 87*4882a593Smuzhiyun #define TRIG4_ERROR (1<<9) /* Trigger 4 Error */ 88*4882a593Smuzhiyun #define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */ 89*4882a593Smuzhiyun #define TRIG3_ERROR (1<<7) /* Trigger 3 Error */ 90*4882a593Smuzhiyun #define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */ 91*4882a593Smuzhiyun #define TRIG2_ERROR (1<<5) /* Trigger 2 Error */ 92*4882a593Smuzhiyun #define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */ 93*4882a593Smuzhiyun #define TRIG1_ERROR (1<<3) /* Trigger 1 Error */ 94*4882a593Smuzhiyun #define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */ 95*4882a593Smuzhiyun #define TRIG0_ERROR (1<<1) /* Trigger 0 Error */ 96*4882a593Smuzhiyun #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Bit definitions for the PTP_RATEH register */ 99*4882a593Smuzhiyun #define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */ 100*4882a593Smuzhiyun #define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */ 101*4882a593Smuzhiyun #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */ 102*4882a593Smuzhiyun #define PTP_RATE_HI_MASK (0x3ff) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Bit definitions for the PTP_ESTS register */ 105*4882a593Smuzhiyun #define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */ 106*4882a593Smuzhiyun #define EVNTS_MISSED_MASK (0x7) 107*4882a593Smuzhiyun #define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */ 108*4882a593Smuzhiyun #define EVNT_TS_LEN_MASK (0x3) 109*4882a593Smuzhiyun #define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */ 110*4882a593Smuzhiyun #define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */ 111*4882a593Smuzhiyun #define EVNT_NUM_MASK (0x7) 112*4882a593Smuzhiyun #define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */ 113*4882a593Smuzhiyun #define EVENT_DET (1<<0) /* PTP Event Detected */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Bit definitions for the PTP_EDATA register */ 116*4882a593Smuzhiyun #define E7_RISE (1<<15) /* Indicates direction of Event 7 */ 117*4882a593Smuzhiyun #define E7_DET (1<<14) /* Indicates Event 7 detected */ 118*4882a593Smuzhiyun #define E6_RISE (1<<13) /* Indicates direction of Event 6 */ 119*4882a593Smuzhiyun #define E6_DET (1<<12) /* Indicates Event 6 detected */ 120*4882a593Smuzhiyun #define E5_RISE (1<<11) /* Indicates direction of Event 5 */ 121*4882a593Smuzhiyun #define E5_DET (1<<10) /* Indicates Event 5 detected */ 122*4882a593Smuzhiyun #define E4_RISE (1<<9) /* Indicates direction of Event 4 */ 123*4882a593Smuzhiyun #define E4_DET (1<<8) /* Indicates Event 4 detected */ 124*4882a593Smuzhiyun #define E3_RISE (1<<7) /* Indicates direction of Event 3 */ 125*4882a593Smuzhiyun #define E3_DET (1<<6) /* Indicates Event 3 detected */ 126*4882a593Smuzhiyun #define E2_RISE (1<<5) /* Indicates direction of Event 2 */ 127*4882a593Smuzhiyun #define E2_DET (1<<4) /* Indicates Event 2 detected */ 128*4882a593Smuzhiyun #define E1_RISE (1<<3) /* Indicates direction of Event 1 */ 129*4882a593Smuzhiyun #define E1_DET (1<<2) /* Indicates Event 1 detected */ 130*4882a593Smuzhiyun #define E0_RISE (1<<1) /* Indicates direction of Event 0 */ 131*4882a593Smuzhiyun #define E0_DET (1<<0) /* Indicates Event 0 detected */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* Bit definitions for the PTP_TRIG register */ 134*4882a593Smuzhiyun #define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */ 135*4882a593Smuzhiyun #define TRIG_PER (1<<14) /* generate a periodic signal */ 136*4882a593Smuzhiyun #define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */ 137*4882a593Smuzhiyun #define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */ 138*4882a593Smuzhiyun #define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */ 139*4882a593Smuzhiyun #define TRIG_GPIO_MASK (0xf) 140*4882a593Smuzhiyun #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */ 141*4882a593Smuzhiyun #define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */ 142*4882a593Smuzhiyun #define TRIG_CSEL_MASK (0x7) 143*4882a593Smuzhiyun #define TRIG_WR (1<<0) /* Trigger Configuration Write */ 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Bit definitions for the PTP_EVNT register */ 146*4882a593Smuzhiyun #define EVNT_RISE (1<<14) /* Event Rise Detect Enable */ 147*4882a593Smuzhiyun #define EVNT_FALL (1<<13) /* Event Fall Detect Enable */ 148*4882a593Smuzhiyun #define EVNT_SINGLE (1<<12) /* enable single event capture operation */ 149*4882a593Smuzhiyun #define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */ 150*4882a593Smuzhiyun #define EVNT_GPIO_MASK (0xf) 151*4882a593Smuzhiyun #define EVNT_SEL_SHIFT (1) /* Event Select */ 152*4882a593Smuzhiyun #define EVNT_SEL_MASK (0x7) 153*4882a593Smuzhiyun #define EVNT_WR (1<<0) /* Event Configuration Write */ 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* Bit definitions for the PTP_TXCFG0 register */ 156*4882a593Smuzhiyun #define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */ 157*4882a593Smuzhiyun #define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */ 158*4882a593Smuzhiyun #define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */ 159*4882a593Smuzhiyun #define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */ 160*4882a593Smuzhiyun #define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */ 161*4882a593Smuzhiyun #define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */ 162*4882a593Smuzhiyun #define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */ 163*4882a593Smuzhiyun #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */ 164*4882a593Smuzhiyun #define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */ 165*4882a593Smuzhiyun #define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */ 166*4882a593Smuzhiyun #define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */ 167*4882a593Smuzhiyun #define TX_PTP_VER_MASK (0xf) 168*4882a593Smuzhiyun #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* Bit definitions for the PTP_TXCFG1 register */ 171*4882a593Smuzhiyun #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */ 172*4882a593Smuzhiyun #define BYTE0_MASK_MASK (0xff) 173*4882a593Smuzhiyun #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */ 174*4882a593Smuzhiyun #define BYTE0_DATA_MASK (0xff) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* Bit definitions for the PSF_CFG0 register */ 177*4882a593Smuzhiyun #define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */ 178*4882a593Smuzhiyun #define MAC_SRC_ADD_MASK (0x3) 179*4882a593Smuzhiyun #define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */ 180*4882a593Smuzhiyun #define MIN_PRE_MASK (0x7) 181*4882a593Smuzhiyun #define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */ 182*4882a593Smuzhiyun #define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */ 183*4882a593Smuzhiyun #define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */ 184*4882a593Smuzhiyun #define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */ 185*4882a593Smuzhiyun #define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */ 186*4882a593Smuzhiyun #define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */ 187*4882a593Smuzhiyun #define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */ 188*4882a593Smuzhiyun #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */ 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* Bit definitions for the PTP_RXCFG0 register */ 191*4882a593Smuzhiyun #define DOMAIN_EN (1<<15) /* Domain Match Enable */ 192*4882a593Smuzhiyun #define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */ 193*4882a593Smuzhiyun #define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */ 194*4882a593Smuzhiyun #define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */ 195*4882a593Smuzhiyun #define RX_SLAVE (1<<11) /* Receive Slave Only */ 196*4882a593Smuzhiyun #define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */ 197*4882a593Smuzhiyun #define IP1588_EN_MASK (0xf) 198*4882a593Smuzhiyun #define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */ 199*4882a593Smuzhiyun #define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */ 200*4882a593Smuzhiyun #define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */ 201*4882a593Smuzhiyun #define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */ 202*4882a593Smuzhiyun #define RX_PTP_VER_MASK (0xf) 203*4882a593Smuzhiyun #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* Bit definitions for the PTP_RXCFG1 register */ 206*4882a593Smuzhiyun #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */ 207*4882a593Smuzhiyun #define BYTE0_MASK_MASK (0xff) 208*4882a593Smuzhiyun #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */ 209*4882a593Smuzhiyun #define BYTE0_DATA_MASK (0xff) 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* Bit definitions for the PTP_RXCFG3 register */ 212*4882a593Smuzhiyun #define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */ 213*4882a593Smuzhiyun #define TS_MIN_IFG_MASK (0xf) 214*4882a593Smuzhiyun #define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */ 215*4882a593Smuzhiyun #define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */ 216*4882a593Smuzhiyun #define TS_APPEND (1<<9) /* Append Timestamp for L2 */ 217*4882a593Smuzhiyun #define TS_INSERT (1<<8) /* Enable Timestamp Insertion */ 218*4882a593Smuzhiyun #define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */ 219*4882a593Smuzhiyun #define PTP_DOMAIN_MASK (0xff) 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* Bit definitions for the PTP_RXCFG4 register */ 222*4882a593Smuzhiyun #define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */ 223*4882a593Smuzhiyun #define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */ 224*4882a593Smuzhiyun #define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */ 225*4882a593Smuzhiyun #define TS_SEC_LEN_MASK (0x3) 226*4882a593Smuzhiyun #define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */ 227*4882a593Smuzhiyun #define RXTS_NS_OFF_MASK (0x3f) 228*4882a593Smuzhiyun #define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */ 229*4882a593Smuzhiyun #define RXTS_SEC_OFF_MASK (0x3f) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* Bit definitions for the PTP_COC register */ 232*4882a593Smuzhiyun #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */ 233*4882a593Smuzhiyun #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */ 234*4882a593Smuzhiyun #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */ 235*4882a593Smuzhiyun #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */ 236*4882a593Smuzhiyun #define PTP_CLKDIV_MASK (0xff) 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /* Bit definitions for the PSF_CFG1 register */ 239*4882a593Smuzhiyun #define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */ 240*4882a593Smuzhiyun #define PTPRESERVED_MASK (0xf) 241*4882a593Smuzhiyun #define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */ 242*4882a593Smuzhiyun #define VERSIONPTP_MASK (0xf) 243*4882a593Smuzhiyun #define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */ 244*4882a593Smuzhiyun #define TRANSPORT_SPECIFIC_MASK (0xf) 245*4882a593Smuzhiyun #define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */ 246*4882a593Smuzhiyun #define MESSAGETYPE_MASK (0xf) 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun /* Bit definitions for the PTP_SFDCFG register */ 249*4882a593Smuzhiyun #define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */ 250*4882a593Smuzhiyun #define TX_SFD_GPIO_MASK (0xf) 251*4882a593Smuzhiyun #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */ 252*4882a593Smuzhiyun #define RX_SFD_GPIO_MASK (0xf) 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* Bit definitions for the PTP_INTCTL register */ 255*4882a593Smuzhiyun #define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */ 256*4882a593Smuzhiyun #define PTP_INT_GPIO_MASK (0xf) 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /* Bit definitions for the PTP_CLKSRC register */ 259*4882a593Smuzhiyun #define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */ 260*4882a593Smuzhiyun #define CLK_SRC_MASK (0x3) 261*4882a593Smuzhiyun #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */ 262*4882a593Smuzhiyun #define CLK_SRC_PER_MASK (0x7f) 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* Bit definitions for the PTP_OFF register */ 265*4882a593Smuzhiyun #define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */ 266*4882a593Smuzhiyun #define PTP_OFFSET_MASK (0xff) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #endif 269