xref: /OK3568_Linux_fs/kernel/drivers/net/phy/davicom.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * drivers/net/phy/davicom.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Driver for Davicom PHYs
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Andy Fleming
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (c) 2004 Freescale Semiconductor, Inc.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/string.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/unistd.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/netdevice.h>
19*4882a593Smuzhiyun #include <linux/etherdevice.h>
20*4882a593Smuzhiyun #include <linux/skbuff.h>
21*4882a593Smuzhiyun #include <linux/spinlock.h>
22*4882a593Smuzhiyun #include <linux/mm.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/mii.h>
25*4882a593Smuzhiyun #include <linux/ethtool.h>
26*4882a593Smuzhiyun #include <linux/phy.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include <asm/io.h>
29*4882a593Smuzhiyun #include <asm/irq.h>
30*4882a593Smuzhiyun #include <linux/uaccess.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define MII_DM9161_SCR		0x10
33*4882a593Smuzhiyun #define MII_DM9161_SCR_INIT	0x0610
34*4882a593Smuzhiyun #define MII_DM9161_SCR_RMII	0x0100
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* DM9161 Interrupt Register */
37*4882a593Smuzhiyun #define MII_DM9161_INTR	0x15
38*4882a593Smuzhiyun #define MII_DM9161_INTR_PEND		0x8000
39*4882a593Smuzhiyun #define MII_DM9161_INTR_DPLX_MASK	0x0800
40*4882a593Smuzhiyun #define MII_DM9161_INTR_SPD_MASK	0x0400
41*4882a593Smuzhiyun #define MII_DM9161_INTR_LINK_MASK	0x0200
42*4882a593Smuzhiyun #define MII_DM9161_INTR_MASK		0x0100
43*4882a593Smuzhiyun #define MII_DM9161_INTR_DPLX_CHANGE	0x0010
44*4882a593Smuzhiyun #define MII_DM9161_INTR_SPD_CHANGE	0x0008
45*4882a593Smuzhiyun #define MII_DM9161_INTR_LINK_CHANGE	0x0004
46*4882a593Smuzhiyun #define MII_DM9161_INTR_INIT 		0x0000
47*4882a593Smuzhiyun #define MII_DM9161_INTR_STOP	\
48*4882a593Smuzhiyun (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
49*4882a593Smuzhiyun  | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* DM9161 10BT Configuration/Status */
52*4882a593Smuzhiyun #define MII_DM9161_10BTCSR	0x12
53*4882a593Smuzhiyun #define MII_DM9161_10BTCSR_INIT	0x7800
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun MODULE_DESCRIPTION("Davicom PHY driver");
56*4882a593Smuzhiyun MODULE_AUTHOR("Andy Fleming");
57*4882a593Smuzhiyun MODULE_LICENSE("GPL");
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define DM9161_DELAY 1
dm9161_config_intr(struct phy_device * phydev)61*4882a593Smuzhiyun static int dm9161_config_intr(struct phy_device *phydev)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	int temp;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	temp = phy_read(phydev, MII_DM9161_INTR);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	if (temp < 0)
68*4882a593Smuzhiyun 		return temp;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	if (PHY_INTERRUPT_ENABLED == phydev->interrupts)
71*4882a593Smuzhiyun 		temp &= ~(MII_DM9161_INTR_STOP);
72*4882a593Smuzhiyun 	else
73*4882a593Smuzhiyun 		temp |= MII_DM9161_INTR_STOP;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	temp = phy_write(phydev, MII_DM9161_INTR, temp);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	return temp;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
dm9161_config_aneg(struct phy_device * phydev)80*4882a593Smuzhiyun static int dm9161_config_aneg(struct phy_device *phydev)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	int err;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	/* Isolate the PHY */
85*4882a593Smuzhiyun 	err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	if (err < 0)
88*4882a593Smuzhiyun 		return err;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/* Configure the new settings */
91*4882a593Smuzhiyun 	err = genphy_config_aneg(phydev);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	if (err < 0)
94*4882a593Smuzhiyun 		return err;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
dm9161_config_init(struct phy_device * phydev)99*4882a593Smuzhiyun static int dm9161_config_init(struct phy_device *phydev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	int err, temp;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	/* Isolate the PHY */
104*4882a593Smuzhiyun 	err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	if (err < 0)
107*4882a593Smuzhiyun 		return err;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	switch (phydev->interface) {
110*4882a593Smuzhiyun 	case PHY_INTERFACE_MODE_MII:
111*4882a593Smuzhiyun 		temp = MII_DM9161_SCR_INIT;
112*4882a593Smuzhiyun 		break;
113*4882a593Smuzhiyun 	case PHY_INTERFACE_MODE_RMII:
114*4882a593Smuzhiyun 		temp =  MII_DM9161_SCR_INIT | MII_DM9161_SCR_RMII;
115*4882a593Smuzhiyun 		break;
116*4882a593Smuzhiyun 	default:
117*4882a593Smuzhiyun 		return -EINVAL;
118*4882a593Smuzhiyun 	}
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* Do not bypass the scrambler/descrambler */
121*4882a593Smuzhiyun 	err = phy_write(phydev, MII_DM9161_SCR, temp);
122*4882a593Smuzhiyun 	if (err < 0)
123*4882a593Smuzhiyun 		return err;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* Clear 10BTCSR to default */
126*4882a593Smuzhiyun 	err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (err < 0)
129*4882a593Smuzhiyun 		return err;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* Reconnect the PHY, and enable Autonegotiation */
132*4882a593Smuzhiyun 	return phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
dm9161_ack_interrupt(struct phy_device * phydev)135*4882a593Smuzhiyun static int dm9161_ack_interrupt(struct phy_device *phydev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	int err = phy_read(phydev, MII_DM9161_INTR);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return (err < 0) ? err : 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static struct phy_driver dm91xx_driver[] = {
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	.phy_id		= 0x0181b880,
145*4882a593Smuzhiyun 	.name		= "Davicom DM9161E",
146*4882a593Smuzhiyun 	.phy_id_mask	= 0x0ffffff0,
147*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
148*4882a593Smuzhiyun 	.config_init	= dm9161_config_init,
149*4882a593Smuzhiyun 	.config_aneg	= dm9161_config_aneg,
150*4882a593Smuzhiyun 	.ack_interrupt	= dm9161_ack_interrupt,
151*4882a593Smuzhiyun 	.config_intr	= dm9161_config_intr,
152*4882a593Smuzhiyun }, {
153*4882a593Smuzhiyun 	.phy_id		= 0x0181b8b0,
154*4882a593Smuzhiyun 	.name		= "Davicom DM9161B/C",
155*4882a593Smuzhiyun 	.phy_id_mask	= 0x0ffffff0,
156*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
157*4882a593Smuzhiyun 	.config_init	= dm9161_config_init,
158*4882a593Smuzhiyun 	.config_aneg	= dm9161_config_aneg,
159*4882a593Smuzhiyun 	.ack_interrupt	= dm9161_ack_interrupt,
160*4882a593Smuzhiyun 	.config_intr	= dm9161_config_intr,
161*4882a593Smuzhiyun }, {
162*4882a593Smuzhiyun 	.phy_id		= 0x0181b8a0,
163*4882a593Smuzhiyun 	.name		= "Davicom DM9161A",
164*4882a593Smuzhiyun 	.phy_id_mask	= 0x0ffffff0,
165*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
166*4882a593Smuzhiyun 	.config_init	= dm9161_config_init,
167*4882a593Smuzhiyun 	.config_aneg	= dm9161_config_aneg,
168*4882a593Smuzhiyun 	.ack_interrupt	= dm9161_ack_interrupt,
169*4882a593Smuzhiyun 	.config_intr	= dm9161_config_intr,
170*4882a593Smuzhiyun }, {
171*4882a593Smuzhiyun 	.phy_id		= 0x00181b80,
172*4882a593Smuzhiyun 	.name		= "Davicom DM9131",
173*4882a593Smuzhiyun 	.phy_id_mask	= 0x0ffffff0,
174*4882a593Smuzhiyun 	/* PHY_BASIC_FEATURES */
175*4882a593Smuzhiyun 	.ack_interrupt	= dm9161_ack_interrupt,
176*4882a593Smuzhiyun 	.config_intr	= dm9161_config_intr,
177*4882a593Smuzhiyun } };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun module_phy_driver(dm91xx_driver);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static struct mdio_device_id __maybe_unused davicom_tbl[] = {
182*4882a593Smuzhiyun 	{ 0x0181b880, 0x0ffffff0 },
183*4882a593Smuzhiyun 	{ 0x0181b8b0, 0x0ffffff0 },
184*4882a593Smuzhiyun 	{ 0x0181b8a0, 0x0ffffff0 },
185*4882a593Smuzhiyun 	{ 0x00181b80, 0x0ffffff0 },
186*4882a593Smuzhiyun 	{ }
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun MODULE_DEVICE_TABLE(mdio, davicom_tbl);
190