1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/net/phy/cicada.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for Cicada PHYs
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Andy Fleming
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (c) 2004 Freescale Semiconductor, Inc.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/string.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/unistd.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/netdevice.h>
19*4882a593Smuzhiyun #include <linux/etherdevice.h>
20*4882a593Smuzhiyun #include <linux/skbuff.h>
21*4882a593Smuzhiyun #include <linux/spinlock.h>
22*4882a593Smuzhiyun #include <linux/mm.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/mii.h>
25*4882a593Smuzhiyun #include <linux/ethtool.h>
26*4882a593Smuzhiyun #include <linux/phy.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <linux/io.h>
29*4882a593Smuzhiyun #include <asm/irq.h>
30*4882a593Smuzhiyun #include <linux/uaccess.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Cicada Extended Control Register 1 */
33*4882a593Smuzhiyun #define MII_CIS8201_EXT_CON1 0x17
34*4882a593Smuzhiyun #define MII_CIS8201_EXTCON1_INIT 0x0000
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Cicada Interrupt Mask Register */
37*4882a593Smuzhiyun #define MII_CIS8201_IMASK 0x19
38*4882a593Smuzhiyun #define MII_CIS8201_IMASK_IEN 0x8000
39*4882a593Smuzhiyun #define MII_CIS8201_IMASK_SPEED 0x4000
40*4882a593Smuzhiyun #define MII_CIS8201_IMASK_LINK 0x2000
41*4882a593Smuzhiyun #define MII_CIS8201_IMASK_DUPLEX 0x1000
42*4882a593Smuzhiyun #define MII_CIS8201_IMASK_MASK 0xf000
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Cicada Interrupt Status Register */
45*4882a593Smuzhiyun #define MII_CIS8201_ISTAT 0x1a
46*4882a593Smuzhiyun #define MII_CIS8201_ISTAT_STATUS 0x8000
47*4882a593Smuzhiyun #define MII_CIS8201_ISTAT_SPEED 0x4000
48*4882a593Smuzhiyun #define MII_CIS8201_ISTAT_LINK 0x2000
49*4882a593Smuzhiyun #define MII_CIS8201_ISTAT_DUPLEX 0x1000
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Cicada Auxiliary Control/Status Register */
52*4882a593Smuzhiyun #define MII_CIS8201_AUX_CONSTAT 0x1c
53*4882a593Smuzhiyun #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
54*4882a593Smuzhiyun #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
55*4882a593Smuzhiyun #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
56*4882a593Smuzhiyun #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
57*4882a593Smuzhiyun #define MII_CIS8201_AUXCONSTAT_100 0x0008
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun MODULE_DESCRIPTION("Cicadia PHY driver");
60*4882a593Smuzhiyun MODULE_AUTHOR("Andy Fleming");
61*4882a593Smuzhiyun MODULE_LICENSE("GPL");
62*4882a593Smuzhiyun
cis820x_config_init(struct phy_device * phydev)63*4882a593Smuzhiyun static int cis820x_config_init(struct phy_device *phydev)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun int err;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT,
68*4882a593Smuzhiyun MII_CIS8201_AUXCONSTAT_INIT);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (err < 0)
71*4882a593Smuzhiyun return err;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun err = phy_write(phydev, MII_CIS8201_EXT_CON1,
74*4882a593Smuzhiyun MII_CIS8201_EXTCON1_INIT);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return err;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
cis820x_ack_interrupt(struct phy_device * phydev)79*4882a593Smuzhiyun static int cis820x_ack_interrupt(struct phy_device *phydev)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun int err = phy_read(phydev, MII_CIS8201_ISTAT);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return (err < 0) ? err : 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
cis820x_config_intr(struct phy_device * phydev)86*4882a593Smuzhiyun static int cis820x_config_intr(struct phy_device *phydev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun int err;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
91*4882a593Smuzhiyun err = phy_write(phydev, MII_CIS8201_IMASK,
92*4882a593Smuzhiyun MII_CIS8201_IMASK_MASK);
93*4882a593Smuzhiyun else
94*4882a593Smuzhiyun err = phy_write(phydev, MII_CIS8201_IMASK, 0);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return err;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Cicada 8201, a.k.a Vitesse VSC8201 */
100*4882a593Smuzhiyun static struct phy_driver cis820x_driver[] = {
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun .phy_id = 0x000fc410,
103*4882a593Smuzhiyun .name = "Cicada Cis8201",
104*4882a593Smuzhiyun .phy_id_mask = 0x000ffff0,
105*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
106*4882a593Smuzhiyun .config_init = &cis820x_config_init,
107*4882a593Smuzhiyun .ack_interrupt = &cis820x_ack_interrupt,
108*4882a593Smuzhiyun .config_intr = &cis820x_config_intr,
109*4882a593Smuzhiyun }, {
110*4882a593Smuzhiyun .phy_id = 0x000fc440,
111*4882a593Smuzhiyun .name = "Cicada Cis8204",
112*4882a593Smuzhiyun .phy_id_mask = 0x000fffc0,
113*4882a593Smuzhiyun /* PHY_GBIT_FEATURES */
114*4882a593Smuzhiyun .config_init = &cis820x_config_init,
115*4882a593Smuzhiyun .ack_interrupt = &cis820x_ack_interrupt,
116*4882a593Smuzhiyun .config_intr = &cis820x_config_intr,
117*4882a593Smuzhiyun } };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun module_phy_driver(cis820x_driver);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static struct mdio_device_id __maybe_unused cicada_tbl[] = {
122*4882a593Smuzhiyun { 0x000fc410, 0x000ffff0 },
123*4882a593Smuzhiyun { 0x000fc440, 0x000fffc0 },
124*4882a593Smuzhiyun { }
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun MODULE_DEVICE_TABLE(mdio, cicada_tbl);
128