xref: /OK3568_Linux_fs/kernel/drivers/net/phy/bcm87xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2011 - 2012 Cavium, Inc.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/phy.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define PHY_ID_BCM8706	0x0143bdc1
11*4882a593Smuzhiyun #define PHY_ID_BCM8727	0x0143bff0
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define BCM87XX_PMD_RX_SIGNAL_DETECT	(MII_ADDR_C45 | 0x1000a)
14*4882a593Smuzhiyun #define BCM87XX_10GBASER_PCS_STATUS	(MII_ADDR_C45 | 0x30020)
15*4882a593Smuzhiyun #define BCM87XX_XGXS_LANE_STATUS	(MII_ADDR_C45 | 0x40018)
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define BCM87XX_LASI_CONTROL (MII_ADDR_C45 | 0x39002)
18*4882a593Smuzhiyun #define BCM87XX_LASI_STATUS (MII_ADDR_C45 | 0x39005)
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF_MDIO)
21*4882a593Smuzhiyun /* Set and/or override some configuration registers based on the
22*4882a593Smuzhiyun  * broadcom,c45-reg-init property stored in the of_node for the phydev.
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  * broadcom,c45-reg-init = <devid reg mask value>,...;
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * There may be one or more sets of <devid reg mask value>:
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  * devid: which sub-device to use.
29*4882a593Smuzhiyun  * reg: the register.
30*4882a593Smuzhiyun  * mask: if non-zero, ANDed with existing register value.
31*4882a593Smuzhiyun  * value: ORed with the masked value and written to the regiser.
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  */
bcm87xx_of_reg_init(struct phy_device * phydev)34*4882a593Smuzhiyun static int bcm87xx_of_reg_init(struct phy_device *phydev)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	const __be32 *paddr;
37*4882a593Smuzhiyun 	const __be32 *paddr_end;
38*4882a593Smuzhiyun 	int len, ret;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	if (!phydev->mdio.dev.of_node)
41*4882a593Smuzhiyun 		return 0;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	paddr = of_get_property(phydev->mdio.dev.of_node,
44*4882a593Smuzhiyun 				"broadcom,c45-reg-init", &len);
45*4882a593Smuzhiyun 	if (!paddr)
46*4882a593Smuzhiyun 		return 0;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	paddr_end = paddr + (len /= sizeof(*paddr));
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	ret = 0;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	while (paddr + 3 < paddr_end) {
53*4882a593Smuzhiyun 		u16 devid	= be32_to_cpup(paddr++);
54*4882a593Smuzhiyun 		u16 reg		= be32_to_cpup(paddr++);
55*4882a593Smuzhiyun 		u16 mask	= be32_to_cpup(paddr++);
56*4882a593Smuzhiyun 		u16 val_bits	= be32_to_cpup(paddr++);
57*4882a593Smuzhiyun 		int val;
58*4882a593Smuzhiyun 		u32 regnum = mdiobus_c45_addr(devid, reg);
59*4882a593Smuzhiyun 		val = 0;
60*4882a593Smuzhiyun 		if (mask) {
61*4882a593Smuzhiyun 			val = phy_read(phydev, regnum);
62*4882a593Smuzhiyun 			if (val < 0) {
63*4882a593Smuzhiyun 				ret = val;
64*4882a593Smuzhiyun 				goto err;
65*4882a593Smuzhiyun 			}
66*4882a593Smuzhiyun 			val &= mask;
67*4882a593Smuzhiyun 		}
68*4882a593Smuzhiyun 		val |= val_bits;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 		ret = phy_write(phydev, regnum, val);
71*4882a593Smuzhiyun 		if (ret < 0)
72*4882a593Smuzhiyun 			goto err;
73*4882a593Smuzhiyun 	}
74*4882a593Smuzhiyun err:
75*4882a593Smuzhiyun 	return ret;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun #else
bcm87xx_of_reg_init(struct phy_device * phydev)78*4882a593Smuzhiyun static int bcm87xx_of_reg_init(struct phy_device *phydev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun #endif /* CONFIG_OF_MDIO */
83*4882a593Smuzhiyun 
bcm87xx_get_features(struct phy_device * phydev)84*4882a593Smuzhiyun static int bcm87xx_get_features(struct phy_device *phydev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
87*4882a593Smuzhiyun 			 phydev->supported);
88*4882a593Smuzhiyun 	return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
bcm87xx_config_init(struct phy_device * phydev)91*4882a593Smuzhiyun static int bcm87xx_config_init(struct phy_device *phydev)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	return bcm87xx_of_reg_init(phydev);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
bcm87xx_config_aneg(struct phy_device * phydev)96*4882a593Smuzhiyun static int bcm87xx_config_aneg(struct phy_device *phydev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	return -EINVAL;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
bcm87xx_read_status(struct phy_device * phydev)101*4882a593Smuzhiyun static int bcm87xx_read_status(struct phy_device *phydev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	int rx_signal_detect;
104*4882a593Smuzhiyun 	int pcs_status;
105*4882a593Smuzhiyun 	int xgxs_lane_status;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	rx_signal_detect = phy_read(phydev, BCM87XX_PMD_RX_SIGNAL_DETECT);
108*4882a593Smuzhiyun 	if (rx_signal_detect < 0)
109*4882a593Smuzhiyun 		return rx_signal_detect;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	if ((rx_signal_detect & 1) == 0)
112*4882a593Smuzhiyun 		goto no_link;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	pcs_status = phy_read(phydev, BCM87XX_10GBASER_PCS_STATUS);
115*4882a593Smuzhiyun 	if (pcs_status < 0)
116*4882a593Smuzhiyun 		return pcs_status;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if ((pcs_status & 1) == 0)
119*4882a593Smuzhiyun 		goto no_link;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	xgxs_lane_status = phy_read(phydev, BCM87XX_XGXS_LANE_STATUS);
122*4882a593Smuzhiyun 	if (xgxs_lane_status < 0)
123*4882a593Smuzhiyun 		return xgxs_lane_status;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if ((xgxs_lane_status & 0x1000) == 0)
126*4882a593Smuzhiyun 		goto no_link;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	phydev->speed = 10000;
129*4882a593Smuzhiyun 	phydev->link = 1;
130*4882a593Smuzhiyun 	phydev->duplex = 1;
131*4882a593Smuzhiyun 	return 0;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun no_link:
134*4882a593Smuzhiyun 	phydev->link = 0;
135*4882a593Smuzhiyun 	return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
bcm87xx_config_intr(struct phy_device * phydev)138*4882a593Smuzhiyun static int bcm87xx_config_intr(struct phy_device *phydev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	int reg, err;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	reg = phy_read(phydev, BCM87XX_LASI_CONTROL);
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	if (reg < 0)
145*4882a593Smuzhiyun 		return reg;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
148*4882a593Smuzhiyun 		reg |= 1;
149*4882a593Smuzhiyun 	else
150*4882a593Smuzhiyun 		reg &= ~1;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg);
153*4882a593Smuzhiyun 	return err;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
bcm87xx_did_interrupt(struct phy_device * phydev)156*4882a593Smuzhiyun static int bcm87xx_did_interrupt(struct phy_device *phydev)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	int reg;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	reg = phy_read(phydev, BCM87XX_LASI_STATUS);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	if (reg < 0) {
163*4882a593Smuzhiyun 		phydev_err(phydev,
164*4882a593Smuzhiyun 			   "Error: Read of BCM87XX_LASI_STATUS failed: %d\n",
165*4882a593Smuzhiyun 			   reg);
166*4882a593Smuzhiyun 		return 0;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 	return (reg & 1) != 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
bcm87xx_ack_interrupt(struct phy_device * phydev)171*4882a593Smuzhiyun static int bcm87xx_ack_interrupt(struct phy_device *phydev)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	/* Reading the LASI status clears it. */
174*4882a593Smuzhiyun 	bcm87xx_did_interrupt(phydev);
175*4882a593Smuzhiyun 	return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
bcm8706_match_phy_device(struct phy_device * phydev)178*4882a593Smuzhiyun static int bcm8706_match_phy_device(struct phy_device *phydev)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
bcm8727_match_phy_device(struct phy_device * phydev)183*4882a593Smuzhiyun static int bcm8727_match_phy_device(struct phy_device *phydev)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static struct phy_driver bcm87xx_driver[] = {
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	.phy_id		= PHY_ID_BCM8706,
191*4882a593Smuzhiyun 	.phy_id_mask	= 0xffffffff,
192*4882a593Smuzhiyun 	.name		= "Broadcom BCM8706",
193*4882a593Smuzhiyun 	.get_features	= bcm87xx_get_features,
194*4882a593Smuzhiyun 	.config_init	= bcm87xx_config_init,
195*4882a593Smuzhiyun 	.config_aneg	= bcm87xx_config_aneg,
196*4882a593Smuzhiyun 	.read_status	= bcm87xx_read_status,
197*4882a593Smuzhiyun 	.ack_interrupt	= bcm87xx_ack_interrupt,
198*4882a593Smuzhiyun 	.config_intr	= bcm87xx_config_intr,
199*4882a593Smuzhiyun 	.did_interrupt	= bcm87xx_did_interrupt,
200*4882a593Smuzhiyun 	.match_phy_device = bcm8706_match_phy_device,
201*4882a593Smuzhiyun }, {
202*4882a593Smuzhiyun 	.phy_id		= PHY_ID_BCM8727,
203*4882a593Smuzhiyun 	.phy_id_mask	= 0xffffffff,
204*4882a593Smuzhiyun 	.name		= "Broadcom BCM8727",
205*4882a593Smuzhiyun 	.get_features	= bcm87xx_get_features,
206*4882a593Smuzhiyun 	.config_init	= bcm87xx_config_init,
207*4882a593Smuzhiyun 	.config_aneg	= bcm87xx_config_aneg,
208*4882a593Smuzhiyun 	.read_status	= bcm87xx_read_status,
209*4882a593Smuzhiyun 	.ack_interrupt	= bcm87xx_ack_interrupt,
210*4882a593Smuzhiyun 	.config_intr	= bcm87xx_config_intr,
211*4882a593Smuzhiyun 	.did_interrupt	= bcm87xx_did_interrupt,
212*4882a593Smuzhiyun 	.match_phy_device = bcm8727_match_phy_device,
213*4882a593Smuzhiyun } };
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun module_phy_driver(bcm87xx_driver);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
218