1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015 Broadcom Corporation
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _LINUX_BCM_PHY_LIB_H
7*4882a593Smuzhiyun #define _LINUX_BCM_PHY_LIB_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/brcmphy.h>
10*4882a593Smuzhiyun #include <linux/phy.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* 28nm only register definitions */
13*4882a593Smuzhiyun #define MISC_ADDR(base, channel) base, channel
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define DSP_TAP10 MISC_ADDR(0x0a, 0)
16*4882a593Smuzhiyun #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
17*4882a593Smuzhiyun #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
18*4882a593Smuzhiyun #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
21*4882a593Smuzhiyun #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
22*4882a593Smuzhiyun #define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
23*4882a593Smuzhiyun #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
24*4882a593Smuzhiyun #define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
25*4882a593Smuzhiyun #define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
26*4882a593Smuzhiyun #define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
27*4882a593Smuzhiyun #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
31*4882a593Smuzhiyun int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
32*4882a593Smuzhiyun int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
33*4882a593Smuzhiyun int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
34*4882a593Smuzhiyun int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
35*4882a593Smuzhiyun int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
36*4882a593Smuzhiyun
bcm_phy_write_exp_sel(struct phy_device * phydev,u16 reg,u16 val)37*4882a593Smuzhiyun static inline int bcm_phy_write_exp_sel(struct phy_device *phydev,
38*4882a593Smuzhiyun u16 reg, u16 val)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
44*4882a593Smuzhiyun int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun int bcm_phy_write_misc(struct phy_device *phydev,
47*4882a593Smuzhiyun u16 reg, u16 chl, u16 value);
48*4882a593Smuzhiyun int bcm_phy_read_misc(struct phy_device *phydev,
49*4882a593Smuzhiyun u16 reg, u16 chl);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
52*4882a593Smuzhiyun u16 val);
53*4882a593Smuzhiyun int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
56*4882a593Smuzhiyun int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
57*4882a593Smuzhiyun int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
58*4882a593Smuzhiyun int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
59*4882a593Smuzhiyun int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
60*4882a593Smuzhiyun u16 set);
61*4882a593Smuzhiyun int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
62*4882a593Smuzhiyun u16 set);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun int bcm_phy_ack_intr(struct phy_device *phydev);
65*4882a593Smuzhiyun int bcm_phy_config_intr(struct phy_device *phydev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun int bcm_phy_set_eee(struct phy_device *phydev, bool enable);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun int bcm_phy_downshift_set(struct phy_device *phydev, u8 count);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun int bcm_phy_get_sset_count(struct phy_device *phydev);
76*4882a593Smuzhiyun void bcm_phy_get_strings(struct phy_device *phydev, u8 *data);
77*4882a593Smuzhiyun void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
78*4882a593Smuzhiyun struct ethtool_stats *stats, u64 *data);
79*4882a593Smuzhiyun void bcm_phy_r_rc_cal_reset(struct phy_device *phydev);
80*4882a593Smuzhiyun int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev);
81*4882a593Smuzhiyun int bcm_phy_enable_jumbo(struct phy_device *phydev);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
84*4882a593Smuzhiyun bool *finished);
85*4882a593Smuzhiyun int bcm_phy_cable_test_start_rdb(struct phy_device *phydev);
86*4882a593Smuzhiyun int bcm_phy_cable_test_start(struct phy_device *phydev);
87*4882a593Smuzhiyun int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #endif /* _LINUX_BCM_PHY_LIB_H */
90