xref: /OK3568_Linux_fs/kernel/drivers/net/phy/aquantia_hwmon.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* HWMON driver for Aquantia PHY
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
5*4882a593Smuzhiyun  * Author: Andrew Lunn <andrew@lunn.ch>
6*4882a593Smuzhiyun  * Author: Heiner Kallweit <hkallweit1@gmail.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/phy.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/ctype.h>
12*4882a593Smuzhiyun #include <linux/hwmon.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include "aquantia.h"
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* Vendor specific 1, MDIO_MMD_VEND2 */
17*4882a593Smuzhiyun #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
18*4882a593Smuzhiyun #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
19*4882a593Smuzhiyun #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
20*4882a593Smuzhiyun #define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
21*4882a593Smuzhiyun #define VEND1_THERMAL_STAT1			0xc820
22*4882a593Smuzhiyun #define VEND1_THERMAL_STAT2			0xc821
23*4882a593Smuzhiyun #define VEND1_THERMAL_STAT2_VALID		BIT(0)
24*4882a593Smuzhiyun #define VEND1_GENERAL_STAT1			0xc830
25*4882a593Smuzhiyun #define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)
26*4882a593Smuzhiyun #define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)
27*4882a593Smuzhiyun #define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)
28*4882a593Smuzhiyun #define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_HWMON)
31*4882a593Smuzhiyun 
aqr_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)32*4882a593Smuzhiyun static umode_t aqr_hwmon_is_visible(const void *data,
33*4882a593Smuzhiyun 				    enum hwmon_sensor_types type,
34*4882a593Smuzhiyun 				    u32 attr, int channel)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	if (type != hwmon_temp)
37*4882a593Smuzhiyun 		return 0;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	switch (attr) {
40*4882a593Smuzhiyun 	case hwmon_temp_input:
41*4882a593Smuzhiyun 	case hwmon_temp_min_alarm:
42*4882a593Smuzhiyun 	case hwmon_temp_max_alarm:
43*4882a593Smuzhiyun 	case hwmon_temp_lcrit_alarm:
44*4882a593Smuzhiyun 	case hwmon_temp_crit_alarm:
45*4882a593Smuzhiyun 		return 0444;
46*4882a593Smuzhiyun 	case hwmon_temp_min:
47*4882a593Smuzhiyun 	case hwmon_temp_max:
48*4882a593Smuzhiyun 	case hwmon_temp_lcrit:
49*4882a593Smuzhiyun 	case hwmon_temp_crit:
50*4882a593Smuzhiyun 		return 0644;
51*4882a593Smuzhiyun 	default:
52*4882a593Smuzhiyun 		return 0;
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
aqr_hwmon_get(struct phy_device * phydev,int reg,long * value)56*4882a593Smuzhiyun static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	if (temp < 0)
61*4882a593Smuzhiyun 		return temp;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	/* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
64*4882a593Smuzhiyun 	*value = (s16)temp * 1000 / 256;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
aqr_hwmon_set(struct phy_device * phydev,int reg,long value)69*4882a593Smuzhiyun static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	int temp;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (value >= 128000 || value < -128000)
74*4882a593Smuzhiyun 		return -ERANGE;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	temp = value * 256 / 1000;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	/* temp is in s16 range and we're interested in lower 16 bits only */
79*4882a593Smuzhiyun 	return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
aqr_hwmon_test_bit(struct phy_device * phydev,int reg,int bit)82*4882a593Smuzhiyun static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	if (val < 0)
87*4882a593Smuzhiyun 		return val;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	return !!(val & bit);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
aqr_hwmon_status1(struct phy_device * phydev,int bit,long * value)92*4882a593Smuzhiyun static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	if (val < 0)
97*4882a593Smuzhiyun 		return val;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	*value = val;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
aqr_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)104*4882a593Smuzhiyun static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
105*4882a593Smuzhiyun 			  u32 attr, int channel, long *value)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	struct phy_device *phydev = dev_get_drvdata(dev);
108*4882a593Smuzhiyun 	int reg;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (type != hwmon_temp)
111*4882a593Smuzhiyun 		return -EOPNOTSUPP;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	switch (attr) {
114*4882a593Smuzhiyun 	case hwmon_temp_input:
115*4882a593Smuzhiyun 		reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
116*4882a593Smuzhiyun 					 VEND1_THERMAL_STAT2_VALID);
117*4882a593Smuzhiyun 		if (reg < 0)
118*4882a593Smuzhiyun 			return reg;
119*4882a593Smuzhiyun 		if (!reg)
120*4882a593Smuzhiyun 			return -EBUSY;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 		return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	case hwmon_temp_lcrit:
125*4882a593Smuzhiyun 		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
126*4882a593Smuzhiyun 				     value);
127*4882a593Smuzhiyun 	case hwmon_temp_min:
128*4882a593Smuzhiyun 		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
129*4882a593Smuzhiyun 				     value);
130*4882a593Smuzhiyun 	case hwmon_temp_max:
131*4882a593Smuzhiyun 		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
132*4882a593Smuzhiyun 				     value);
133*4882a593Smuzhiyun 	case hwmon_temp_crit:
134*4882a593Smuzhiyun 		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
135*4882a593Smuzhiyun 				     value);
136*4882a593Smuzhiyun 	case hwmon_temp_lcrit_alarm:
137*4882a593Smuzhiyun 		return aqr_hwmon_status1(phydev,
138*4882a593Smuzhiyun 					 VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
139*4882a593Smuzhiyun 					 value);
140*4882a593Smuzhiyun 	case hwmon_temp_min_alarm:
141*4882a593Smuzhiyun 		return aqr_hwmon_status1(phydev,
142*4882a593Smuzhiyun 					 VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
143*4882a593Smuzhiyun 					 value);
144*4882a593Smuzhiyun 	case hwmon_temp_max_alarm:
145*4882a593Smuzhiyun 		return aqr_hwmon_status1(phydev,
146*4882a593Smuzhiyun 					 VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
147*4882a593Smuzhiyun 					 value);
148*4882a593Smuzhiyun 	case hwmon_temp_crit_alarm:
149*4882a593Smuzhiyun 		return aqr_hwmon_status1(phydev,
150*4882a593Smuzhiyun 					 VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
151*4882a593Smuzhiyun 					 value);
152*4882a593Smuzhiyun 	default:
153*4882a593Smuzhiyun 		return -EOPNOTSUPP;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
aqr_hwmon_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long value)157*4882a593Smuzhiyun static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
158*4882a593Smuzhiyun 			   u32 attr, int channel, long value)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	struct phy_device *phydev = dev_get_drvdata(dev);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	if (type != hwmon_temp)
163*4882a593Smuzhiyun 		return -EOPNOTSUPP;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	switch (attr) {
166*4882a593Smuzhiyun 	case hwmon_temp_lcrit:
167*4882a593Smuzhiyun 		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
168*4882a593Smuzhiyun 				     value);
169*4882a593Smuzhiyun 	case hwmon_temp_min:
170*4882a593Smuzhiyun 		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
171*4882a593Smuzhiyun 				     value);
172*4882a593Smuzhiyun 	case hwmon_temp_max:
173*4882a593Smuzhiyun 		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
174*4882a593Smuzhiyun 				     value);
175*4882a593Smuzhiyun 	case hwmon_temp_crit:
176*4882a593Smuzhiyun 		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
177*4882a593Smuzhiyun 				     value);
178*4882a593Smuzhiyun 	default:
179*4882a593Smuzhiyun 		return -EOPNOTSUPP;
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun static const struct hwmon_ops aqr_hwmon_ops = {
184*4882a593Smuzhiyun 	.is_visible = aqr_hwmon_is_visible,
185*4882a593Smuzhiyun 	.read = aqr_hwmon_read,
186*4882a593Smuzhiyun 	.write = aqr_hwmon_write,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static u32 aqr_hwmon_chip_config[] = {
190*4882a593Smuzhiyun 	HWMON_C_REGISTER_TZ,
191*4882a593Smuzhiyun 	0,
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun static const struct hwmon_channel_info aqr_hwmon_chip = {
195*4882a593Smuzhiyun 	.type = hwmon_chip,
196*4882a593Smuzhiyun 	.config = aqr_hwmon_chip_config,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun static u32 aqr_hwmon_temp_config[] = {
200*4882a593Smuzhiyun 	HWMON_T_INPUT |
201*4882a593Smuzhiyun 	HWMON_T_MAX | HWMON_T_MIN |
202*4882a593Smuzhiyun 	HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
203*4882a593Smuzhiyun 	HWMON_T_CRIT | HWMON_T_LCRIT |
204*4882a593Smuzhiyun 	HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
205*4882a593Smuzhiyun 	0,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct hwmon_channel_info aqr_hwmon_temp = {
209*4882a593Smuzhiyun 	.type = hwmon_temp,
210*4882a593Smuzhiyun 	.config = aqr_hwmon_temp_config,
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun static const struct hwmon_channel_info *aqr_hwmon_info[] = {
214*4882a593Smuzhiyun 	&aqr_hwmon_chip,
215*4882a593Smuzhiyun 	&aqr_hwmon_temp,
216*4882a593Smuzhiyun 	NULL,
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun static const struct hwmon_chip_info aqr_hwmon_chip_info = {
220*4882a593Smuzhiyun 	.ops = &aqr_hwmon_ops,
221*4882a593Smuzhiyun 	.info = aqr_hwmon_info,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
aqr_hwmon_probe(struct phy_device * phydev)224*4882a593Smuzhiyun int aqr_hwmon_probe(struct phy_device *phydev)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun 	struct device *dev = &phydev->mdio.dev;
227*4882a593Smuzhiyun 	struct device *hwmon_dev;
228*4882a593Smuzhiyun 	char *hwmon_name;
229*4882a593Smuzhiyun 	int i, j;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
232*4882a593Smuzhiyun 	if (!hwmon_name)
233*4882a593Smuzhiyun 		return -ENOMEM;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	for (i = j = 0; hwmon_name[i]; i++) {
236*4882a593Smuzhiyun 		if (isalnum(hwmon_name[i])) {
237*4882a593Smuzhiyun 			if (i != j)
238*4882a593Smuzhiyun 				hwmon_name[j] = hwmon_name[i];
239*4882a593Smuzhiyun 			j++;
240*4882a593Smuzhiyun 		}
241*4882a593Smuzhiyun 	}
242*4882a593Smuzhiyun 	hwmon_name[j] = '\0';
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
245*4882a593Smuzhiyun 					phydev, &aqr_hwmon_chip_info, NULL);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return PTR_ERR_OR_ZERO(hwmon_dev);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun #endif
251