1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Simple memory-mapped device MDIO MUX driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Timur Tabi <timur@freescale.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/mdio-mux.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/of_mdio.h>
15*4882a593Smuzhiyun #include <linux/phy.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct mdio_mux_mmioreg_state {
19*4882a593Smuzhiyun void *mux_handle;
20*4882a593Smuzhiyun phys_addr_t phys;
21*4882a593Smuzhiyun unsigned int iosize;
22*4882a593Smuzhiyun unsigned int mask;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * MDIO multiplexing switch function
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * This function is called by the mdio-mux layer when it thinks the mdio bus
29*4882a593Smuzhiyun * multiplexer needs to switch.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * 'current_child' is the current value of the mux register (masked via
32*4882a593Smuzhiyun * s->mask).
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * 'desired_child' is the value of the 'reg' property of the target child MDIO
35*4882a593Smuzhiyun * node.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * The first time this function is called, current_child == -1.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * If current_child == desired_child, then the mux is already set to the
40*4882a593Smuzhiyun * correct bus.
41*4882a593Smuzhiyun */
mdio_mux_mmioreg_switch_fn(int current_child,int desired_child,void * data)42*4882a593Smuzhiyun static int mdio_mux_mmioreg_switch_fn(int current_child, int desired_child,
43*4882a593Smuzhiyun void *data)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct mdio_mux_mmioreg_state *s = data;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (current_child ^ desired_child) {
48*4882a593Smuzhiyun void __iomem *p = ioremap(s->phys, s->iosize);
49*4882a593Smuzhiyun if (!p)
50*4882a593Smuzhiyun return -ENOMEM;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun switch (s->iosize) {
53*4882a593Smuzhiyun case sizeof(uint8_t): {
54*4882a593Smuzhiyun uint8_t x, y;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun x = ioread8(p);
57*4882a593Smuzhiyun y = (x & ~s->mask) | desired_child;
58*4882a593Smuzhiyun if (x != y) {
59*4882a593Smuzhiyun iowrite8((x & ~s->mask) | desired_child, p);
60*4882a593Smuzhiyun pr_debug("%s: %02x -> %02x\n", __func__, x, y);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun case sizeof(uint16_t): {
66*4882a593Smuzhiyun uint16_t x, y;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun x = ioread16(p);
69*4882a593Smuzhiyun y = (x & ~s->mask) | desired_child;
70*4882a593Smuzhiyun if (x != y) {
71*4882a593Smuzhiyun iowrite16((x & ~s->mask) | desired_child, p);
72*4882a593Smuzhiyun pr_debug("%s: %04x -> %04x\n", __func__, x, y);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun break;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun case sizeof(uint32_t): {
78*4882a593Smuzhiyun uint32_t x, y;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun x = ioread32(p);
81*4882a593Smuzhiyun y = (x & ~s->mask) | desired_child;
82*4882a593Smuzhiyun if (x != y) {
83*4882a593Smuzhiyun iowrite32((x & ~s->mask) | desired_child, p);
84*4882a593Smuzhiyun pr_debug("%s: %08x -> %08x\n", __func__, x, y);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun iounmap(p);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
mdio_mux_mmioreg_probe(struct platform_device * pdev)97*4882a593Smuzhiyun static int mdio_mux_mmioreg_probe(struct platform_device *pdev)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct device_node *np2, *np = pdev->dev.of_node;
100*4882a593Smuzhiyun struct mdio_mux_mmioreg_state *s;
101*4882a593Smuzhiyun struct resource res;
102*4882a593Smuzhiyun const __be32 *iprop;
103*4882a593Smuzhiyun int len, ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun dev_dbg(&pdev->dev, "probing node %pOF\n", np);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
108*4882a593Smuzhiyun if (!s)
109*4882a593Smuzhiyun return -ENOMEM;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun ret = of_address_to_resource(np, 0, &res);
112*4882a593Smuzhiyun if (ret) {
113*4882a593Smuzhiyun dev_err(&pdev->dev, "could not obtain memory map for node %pOF\n",
114*4882a593Smuzhiyun np);
115*4882a593Smuzhiyun return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun s->phys = res.start;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun s->iosize = resource_size(&res);
120*4882a593Smuzhiyun if (s->iosize != sizeof(uint8_t) &&
121*4882a593Smuzhiyun s->iosize != sizeof(uint16_t) &&
122*4882a593Smuzhiyun s->iosize != sizeof(uint32_t)) {
123*4882a593Smuzhiyun dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n");
124*4882a593Smuzhiyun return -EINVAL;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun iprop = of_get_property(np, "mux-mask", &len);
128*4882a593Smuzhiyun if (!iprop || len != sizeof(uint32_t)) {
129*4882a593Smuzhiyun dev_err(&pdev->dev, "missing or invalid mux-mask property\n");
130*4882a593Smuzhiyun return -ENODEV;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun if (be32_to_cpup(iprop) >= BIT(s->iosize * 8)) {
133*4882a593Smuzhiyun dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n");
134*4882a593Smuzhiyun return -EINVAL;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun s->mask = be32_to_cpup(iprop);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun * Verify that the 'reg' property of each child MDIO bus does not
140*4882a593Smuzhiyun * set any bits outside of the 'mask'.
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun for_each_available_child_of_node(np, np2) {
143*4882a593Smuzhiyun iprop = of_get_property(np2, "reg", &len);
144*4882a593Smuzhiyun if (!iprop || len != sizeof(uint32_t)) {
145*4882a593Smuzhiyun dev_err(&pdev->dev, "mdio-mux child node %pOF is "
146*4882a593Smuzhiyun "missing a 'reg' property\n", np2);
147*4882a593Smuzhiyun of_node_put(np2);
148*4882a593Smuzhiyun return -ENODEV;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun if (be32_to_cpup(iprop) & ~s->mask) {
151*4882a593Smuzhiyun dev_err(&pdev->dev, "mdio-mux child node %pOF has "
152*4882a593Smuzhiyun "a 'reg' value with unmasked bits\n",
153*4882a593Smuzhiyun np2);
154*4882a593Smuzhiyun of_node_put(np2);
155*4882a593Smuzhiyun return -ENODEV;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun ret = mdio_mux_init(&pdev->dev, pdev->dev.of_node,
160*4882a593Smuzhiyun mdio_mux_mmioreg_switch_fn,
161*4882a593Smuzhiyun &s->mux_handle, s, NULL);
162*4882a593Smuzhiyun if (ret) {
163*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
164*4882a593Smuzhiyun dev_err(&pdev->dev,
165*4882a593Smuzhiyun "failed to register mdio-mux bus %pOF\n", np);
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun pdev->dev.platform_data = s;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
mdio_mux_mmioreg_remove(struct platform_device * pdev)174*4882a593Smuzhiyun static int mdio_mux_mmioreg_remove(struct platform_device *pdev)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun struct mdio_mux_mmioreg_state *s = dev_get_platdata(&pdev->dev);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun mdio_mux_uninit(s->mux_handle);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static const struct of_device_id mdio_mux_mmioreg_match[] = {
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun .compatible = "mdio-mux-mmioreg",
186*4882a593Smuzhiyun },
187*4882a593Smuzhiyun {},
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mdio_mux_mmioreg_match);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static struct platform_driver mdio_mux_mmioreg_driver = {
192*4882a593Smuzhiyun .driver = {
193*4882a593Smuzhiyun .name = "mdio-mux-mmioreg",
194*4882a593Smuzhiyun .of_match_table = mdio_mux_mmioreg_match,
195*4882a593Smuzhiyun },
196*4882a593Smuzhiyun .probe = mdio_mux_mmioreg_probe,
197*4882a593Smuzhiyun .remove = mdio_mux_mmioreg_remove,
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun module_platform_driver(mdio_mux_mmioreg_driver);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
203*4882a593Smuzhiyun MODULE_DESCRIPTION("Memory-mapped device MDIO MUX driver");
204*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
205