1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Qualcomm IPQ8064 MDIO interface driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
5*4882a593Smuzhiyun * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_mdio.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* MII address register definitions */
18*4882a593Smuzhiyun #define MII_ADDR_REG_ADDR 0x10
19*4882a593Smuzhiyun #define MII_BUSY BIT(0)
20*4882a593Smuzhiyun #define MII_WRITE BIT(1)
21*4882a593Smuzhiyun #define MII_CLKRANGE_60_100M (0 << 2)
22*4882a593Smuzhiyun #define MII_CLKRANGE_100_150M (1 << 2)
23*4882a593Smuzhiyun #define MII_CLKRANGE_20_35M (2 << 2)
24*4882a593Smuzhiyun #define MII_CLKRANGE_35_60M (3 << 2)
25*4882a593Smuzhiyun #define MII_CLKRANGE_150_250M (4 << 2)
26*4882a593Smuzhiyun #define MII_CLKRANGE_250_300M (5 << 2)
27*4882a593Smuzhiyun #define MII_CLKRANGE_MASK GENMASK(4, 2)
28*4882a593Smuzhiyun #define MII_REG_SHIFT 6
29*4882a593Smuzhiyun #define MII_REG_MASK GENMASK(10, 6)
30*4882a593Smuzhiyun #define MII_ADDR_SHIFT 11
31*4882a593Smuzhiyun #define MII_ADDR_MASK GENMASK(15, 11)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define MII_DATA_REG_ADDR 0x14
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define MII_MDIO_DELAY_USEC (1000)
36*4882a593Smuzhiyun #define MII_MDIO_RETRY_MSEC (10)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct ipq8064_mdio {
39*4882a593Smuzhiyun struct regmap *base; /* NSS_GMAC0_BASE */
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static int
ipq8064_mdio_wait_busy(struct ipq8064_mdio * priv)43*4882a593Smuzhiyun ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun u32 busy;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
48*4882a593Smuzhiyun !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
49*4882a593Smuzhiyun MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static int
ipq8064_mdio_read(struct mii_bus * bus,int phy_addr,int reg_offset)53*4882a593Smuzhiyun ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
56*4882a593Smuzhiyun struct ipq8064_mdio *priv = bus->priv;
57*4882a593Smuzhiyun u32 ret_val;
58*4882a593Smuzhiyun int err;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Reject clause 45 */
61*4882a593Smuzhiyun if (reg_offset & MII_ADDR_C45)
62*4882a593Smuzhiyun return -EOPNOTSUPP;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
65*4882a593Smuzhiyun ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
68*4882a593Smuzhiyun usleep_range(8, 10);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun err = ipq8064_mdio_wait_busy(priv);
71*4882a593Smuzhiyun if (err)
72*4882a593Smuzhiyun return err;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
75*4882a593Smuzhiyun return (int)ret_val;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static int
ipq8064_mdio_write(struct mii_bus * bus,int phy_addr,int reg_offset,u16 data)79*4882a593Smuzhiyun ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
82*4882a593Smuzhiyun struct ipq8064_mdio *priv = bus->priv;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Reject clause 45 */
85*4882a593Smuzhiyun if (reg_offset & MII_ADDR_C45)
86*4882a593Smuzhiyun return -EOPNOTSUPP;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun regmap_write(priv->base, MII_DATA_REG_ADDR, data);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
91*4882a593Smuzhiyun ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
94*4882a593Smuzhiyun usleep_range(8, 10);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return ipq8064_mdio_wait_busy(priv);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct regmap_config ipq8064_mdio_regmap_config = {
100*4882a593Smuzhiyun .reg_bits = 32,
101*4882a593Smuzhiyun .reg_stride = 4,
102*4882a593Smuzhiyun .val_bits = 32,
103*4882a593Smuzhiyun .can_multi_write = false,
104*4882a593Smuzhiyun /* the mdio lock is used by any user of this mdio driver */
105*4882a593Smuzhiyun .disable_locking = true,
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun .cache_type = REGCACHE_NONE,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static int
ipq8064_mdio_probe(struct platform_device * pdev)111*4882a593Smuzhiyun ipq8064_mdio_probe(struct platform_device *pdev)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
114*4882a593Smuzhiyun struct ipq8064_mdio *priv;
115*4882a593Smuzhiyun struct resource res;
116*4882a593Smuzhiyun struct mii_bus *bus;
117*4882a593Smuzhiyun void __iomem *base;
118*4882a593Smuzhiyun int ret;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (of_address_to_resource(np, 0, &res))
121*4882a593Smuzhiyun return -ENOMEM;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun base = ioremap(res.start, resource_size(&res));
124*4882a593Smuzhiyun if (!base)
125*4882a593Smuzhiyun return -ENOMEM;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
128*4882a593Smuzhiyun if (!bus)
129*4882a593Smuzhiyun return -ENOMEM;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun bus->name = "ipq8064_mdio_bus";
132*4882a593Smuzhiyun bus->read = ipq8064_mdio_read;
133*4882a593Smuzhiyun bus->write = ipq8064_mdio_write;
134*4882a593Smuzhiyun snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
135*4882a593Smuzhiyun bus->parent = &pdev->dev;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun priv = bus->priv;
138*4882a593Smuzhiyun priv->base = devm_regmap_init_mmio(&pdev->dev, base,
139*4882a593Smuzhiyun &ipq8064_mdio_regmap_config);
140*4882a593Smuzhiyun if (IS_ERR(priv->base))
141*4882a593Smuzhiyun return PTR_ERR(priv->base);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun ret = of_mdiobus_register(bus, np);
144*4882a593Smuzhiyun if (ret)
145*4882a593Smuzhiyun return ret;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun platform_set_drvdata(pdev, bus);
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static int
ipq8064_mdio_remove(struct platform_device * pdev)152*4882a593Smuzhiyun ipq8064_mdio_remove(struct platform_device *pdev)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct mii_bus *bus = platform_get_drvdata(pdev);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun mdiobus_unregister(bus);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static const struct of_device_id ipq8064_mdio_dt_ids[] = {
162*4882a593Smuzhiyun { .compatible = "qcom,ipq8064-mdio" },
163*4882a593Smuzhiyun { }
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static struct platform_driver ipq8064_mdio_driver = {
168*4882a593Smuzhiyun .probe = ipq8064_mdio_probe,
169*4882a593Smuzhiyun .remove = ipq8064_mdio_remove,
170*4882a593Smuzhiyun .driver = {
171*4882a593Smuzhiyun .name = "ipq8064-mdio",
172*4882a593Smuzhiyun .of_match_table = ipq8064_mdio_dt_ids,
173*4882a593Smuzhiyun },
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun module_platform_driver(ipq8064_mdio_driver);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
179*4882a593Smuzhiyun MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
180*4882a593Smuzhiyun MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
181*4882a593Smuzhiyun MODULE_LICENSE("GPL");
182