xref: /OK3568_Linux_fs/kernel/drivers/net/mdio/mdio-hisi-femac.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Hisilicon Fast Ethernet MDIO Bus Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/iopoll.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/of_mdio.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define MDIO_RWCTRL		0x00
17*4882a593Smuzhiyun #define MDIO_RO_DATA		0x04
18*4882a593Smuzhiyun #define MDIO_WRITE		BIT(13)
19*4882a593Smuzhiyun #define MDIO_RW_FINISH		BIT(15)
20*4882a593Smuzhiyun #define BIT_PHY_ADDR_OFFSET	8
21*4882a593Smuzhiyun #define BIT_WR_DATA_OFFSET	16
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct hisi_femac_mdio_data {
24*4882a593Smuzhiyun 	struct clk *clk;
25*4882a593Smuzhiyun 	void __iomem *membase;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data * data)28*4882a593Smuzhiyun static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	u32 val;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	return readl_poll_timeout(data->membase + MDIO_RWCTRL,
33*4882a593Smuzhiyun 				  val, val & MDIO_RW_FINISH, 20, 10000);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun 
hisi_femac_mdio_read(struct mii_bus * bus,int mii_id,int regnum)36*4882a593Smuzhiyun static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	struct hisi_femac_mdio_data *data = bus->priv;
39*4882a593Smuzhiyun 	int ret;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	ret = hisi_femac_mdio_wait_ready(data);
42*4882a593Smuzhiyun 	if (ret)
43*4882a593Smuzhiyun 		return ret;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
46*4882a593Smuzhiyun 	       data->membase + MDIO_RWCTRL);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	ret = hisi_femac_mdio_wait_ready(data);
49*4882a593Smuzhiyun 	if (ret)
50*4882a593Smuzhiyun 		return ret;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
hisi_femac_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)55*4882a593Smuzhiyun static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
56*4882a593Smuzhiyun 				 u16 value)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	struct hisi_femac_mdio_data *data = bus->priv;
59*4882a593Smuzhiyun 	int ret;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	ret = hisi_femac_mdio_wait_ready(data);
62*4882a593Smuzhiyun 	if (ret)
63*4882a593Smuzhiyun 		return ret;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) |
66*4882a593Smuzhiyun 	       (mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
67*4882a593Smuzhiyun 	       data->membase + MDIO_RWCTRL);
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	return hisi_femac_mdio_wait_ready(data);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
hisi_femac_mdio_probe(struct platform_device * pdev)72*4882a593Smuzhiyun static int hisi_femac_mdio_probe(struct platform_device *pdev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
75*4882a593Smuzhiyun 	struct mii_bus *bus;
76*4882a593Smuzhiyun 	struct hisi_femac_mdio_data *data;
77*4882a593Smuzhiyun 	int ret;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	bus = mdiobus_alloc_size(sizeof(*data));
80*4882a593Smuzhiyun 	if (!bus)
81*4882a593Smuzhiyun 		return -ENOMEM;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	bus->name = "hisi_femac_mii_bus";
84*4882a593Smuzhiyun 	bus->read = &hisi_femac_mdio_read;
85*4882a593Smuzhiyun 	bus->write = &hisi_femac_mdio_write;
86*4882a593Smuzhiyun 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
87*4882a593Smuzhiyun 	bus->parent = &pdev->dev;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	data = bus->priv;
90*4882a593Smuzhiyun 	data->membase = devm_platform_ioremap_resource(pdev, 0);
91*4882a593Smuzhiyun 	if (IS_ERR(data->membase)) {
92*4882a593Smuzhiyun 		ret = PTR_ERR(data->membase);
93*4882a593Smuzhiyun 		goto err_out_free_mdiobus;
94*4882a593Smuzhiyun 	}
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	data->clk = devm_clk_get(&pdev->dev, NULL);
97*4882a593Smuzhiyun 	if (IS_ERR(data->clk)) {
98*4882a593Smuzhiyun 		ret = PTR_ERR(data->clk);
99*4882a593Smuzhiyun 		goto err_out_free_mdiobus;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	ret = clk_prepare_enable(data->clk);
103*4882a593Smuzhiyun 	if (ret)
104*4882a593Smuzhiyun 		goto err_out_free_mdiobus;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	ret = of_mdiobus_register(bus, np);
107*4882a593Smuzhiyun 	if (ret)
108*4882a593Smuzhiyun 		goto err_out_disable_clk;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	platform_set_drvdata(pdev, bus);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return 0;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun err_out_disable_clk:
115*4882a593Smuzhiyun 	clk_disable_unprepare(data->clk);
116*4882a593Smuzhiyun err_out_free_mdiobus:
117*4882a593Smuzhiyun 	mdiobus_free(bus);
118*4882a593Smuzhiyun 	return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
hisi_femac_mdio_remove(struct platform_device * pdev)121*4882a593Smuzhiyun static int hisi_femac_mdio_remove(struct platform_device *pdev)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	struct mii_bus *bus = platform_get_drvdata(pdev);
124*4882a593Smuzhiyun 	struct hisi_femac_mdio_data *data = bus->priv;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	mdiobus_unregister(bus);
127*4882a593Smuzhiyun 	clk_disable_unprepare(data->clk);
128*4882a593Smuzhiyun 	mdiobus_free(bus);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static const struct of_device_id hisi_femac_mdio_dt_ids[] = {
134*4882a593Smuzhiyun 	{ .compatible = "hisilicon,hisi-femac-mdio" },
135*4882a593Smuzhiyun 	{ }
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hisi_femac_mdio_dt_ids);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun static struct platform_driver hisi_femac_mdio_driver = {
140*4882a593Smuzhiyun 	.probe = hisi_femac_mdio_probe,
141*4882a593Smuzhiyun 	.remove = hisi_femac_mdio_remove,
142*4882a593Smuzhiyun 	.driver = {
143*4882a593Smuzhiyun 		.name = "hisi-femac-mdio",
144*4882a593Smuzhiyun 		.of_match_table = hisi_femac_mdio_dt_ids,
145*4882a593Smuzhiyun 	},
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun module_platform_driver(hisi_femac_mdio_driver);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC MDIO interface driver");
151*4882a593Smuzhiyun MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
152*4882a593Smuzhiyun MODULE_LICENSE("GPL");
153