1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2009-2016 Cavium, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun enum cavium_mdiobus_mode {
7*4882a593Smuzhiyun UNINIT = 0,
8*4882a593Smuzhiyun C22,
9*4882a593Smuzhiyun C45
10*4882a593Smuzhiyun };
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define SMI_CMD 0x0
13*4882a593Smuzhiyun #define SMI_WR_DAT 0x8
14*4882a593Smuzhiyun #define SMI_RD_DAT 0x10
15*4882a593Smuzhiyun #define SMI_CLK 0x18
16*4882a593Smuzhiyun #define SMI_EN 0x20
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifdef __BIG_ENDIAN_BITFIELD
19*4882a593Smuzhiyun #define OCT_MDIO_BITFIELD_FIELD(field, more) \
20*4882a593Smuzhiyun field; \
21*4882a593Smuzhiyun more
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #else
24*4882a593Smuzhiyun #define OCT_MDIO_BITFIELD_FIELD(field, more) \
25*4882a593Smuzhiyun more \
26*4882a593Smuzhiyun field;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #endif
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun union cvmx_smix_clk {
31*4882a593Smuzhiyun u64 u64;
32*4882a593Smuzhiyun struct cvmx_smix_clk_s {
33*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
34*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
35*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
36*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
37*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
38*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
39*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
40*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
41*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
42*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
43*4882a593Smuzhiyun ;))))))))))
44*4882a593Smuzhiyun } s;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun union cvmx_smix_cmd {
48*4882a593Smuzhiyun u64 u64;
49*4882a593Smuzhiyun struct cvmx_smix_cmd_s {
50*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
51*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
52*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
53*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
54*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
55*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
56*4882a593Smuzhiyun ;))))))
57*4882a593Smuzhiyun } s;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun union cvmx_smix_en {
61*4882a593Smuzhiyun u64 u64;
62*4882a593Smuzhiyun struct cvmx_smix_en_s {
63*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
64*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 en:1,
65*4882a593Smuzhiyun ;))
66*4882a593Smuzhiyun } s;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun union cvmx_smix_rd_dat {
70*4882a593Smuzhiyun u64 u64;
71*4882a593Smuzhiyun struct cvmx_smix_rd_dat_s {
72*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
73*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
74*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 val:1,
75*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
76*4882a593Smuzhiyun ;))))
77*4882a593Smuzhiyun } s;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun union cvmx_smix_wr_dat {
81*4882a593Smuzhiyun u64 u64;
82*4882a593Smuzhiyun struct cvmx_smix_wr_dat_s {
83*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
84*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
85*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 val:1,
86*4882a593Smuzhiyun OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
87*4882a593Smuzhiyun ;))))
88*4882a593Smuzhiyun } s;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct cavium_mdiobus {
92*4882a593Smuzhiyun struct mii_bus *mii_bus;
93*4882a593Smuzhiyun void __iomem *register_base;
94*4882a593Smuzhiyun enum cavium_mdiobus_mode mode;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #ifdef CONFIG_CAVIUM_OCTEON_SOC
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
100*4882a593Smuzhiyun
oct_mdio_writeq(u64 val,void __iomem * addr)101*4882a593Smuzhiyun static inline void oct_mdio_writeq(u64 val, void __iomem *addr)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun cvmx_write_csr((u64 __force)addr, val);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
oct_mdio_readq(void __iomem * addr)106*4882a593Smuzhiyun static inline u64 oct_mdio_readq(void __iomem *addr)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun return cvmx_read_csr((u64 __force)addr);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun #else
111*4882a593Smuzhiyun #include <linux/io-64-nonatomic-lo-hi.h>
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define oct_mdio_writeq(val, addr) writeq(val, addr)
114*4882a593Smuzhiyun #define oct_mdio_readq(addr) readq(addr)
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum);
118*4882a593Smuzhiyun int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
119