1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2009-2016 Cavium, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/phy.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "mdio-cavium.h"
12*4882a593Smuzhiyun
cavium_mdiobus_set_mode(struct cavium_mdiobus * p,enum cavium_mdiobus_mode m)13*4882a593Smuzhiyun static void cavium_mdiobus_set_mode(struct cavium_mdiobus *p,
14*4882a593Smuzhiyun enum cavium_mdiobus_mode m)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun union cvmx_smix_clk smi_clk;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun if (m == p->mode)
19*4882a593Smuzhiyun return;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
22*4882a593Smuzhiyun smi_clk.s.mode = (m == C45) ? 1 : 0;
23*4882a593Smuzhiyun smi_clk.s.preamble = 1;
24*4882a593Smuzhiyun oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
25*4882a593Smuzhiyun p->mode = m;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
cavium_mdiobus_c45_addr(struct cavium_mdiobus * p,int phy_id,int regnum)28*4882a593Smuzhiyun static int cavium_mdiobus_c45_addr(struct cavium_mdiobus *p,
29*4882a593Smuzhiyun int phy_id, int regnum)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun union cvmx_smix_cmd smi_cmd;
32*4882a593Smuzhiyun union cvmx_smix_wr_dat smi_wr;
33*4882a593Smuzhiyun int timeout = 1000;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun cavium_mdiobus_set_mode(p, C45);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun smi_wr.u64 = 0;
38*4882a593Smuzhiyun smi_wr.s.dat = regnum & 0xffff;
39*4882a593Smuzhiyun oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun regnum = (regnum >> 16) & 0x1f;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun smi_cmd.u64 = 0;
44*4882a593Smuzhiyun smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
45*4882a593Smuzhiyun smi_cmd.s.phy_adr = phy_id;
46*4882a593Smuzhiyun smi_cmd.s.reg_adr = regnum;
47*4882a593Smuzhiyun oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun do {
50*4882a593Smuzhiyun /* Wait 1000 clocks so we don't saturate the RSL bus
51*4882a593Smuzhiyun * doing reads.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun __delay(1000);
54*4882a593Smuzhiyun smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
55*4882a593Smuzhiyun } while (smi_wr.s.pending && --timeout);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (timeout <= 0)
58*4882a593Smuzhiyun return -EIO;
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
cavium_mdiobus_read(struct mii_bus * bus,int phy_id,int regnum)62*4882a593Smuzhiyun int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct cavium_mdiobus *p = bus->priv;
65*4882a593Smuzhiyun union cvmx_smix_cmd smi_cmd;
66*4882a593Smuzhiyun union cvmx_smix_rd_dat smi_rd;
67*4882a593Smuzhiyun unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
68*4882a593Smuzhiyun int timeout = 1000;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (regnum & MII_ADDR_C45) {
71*4882a593Smuzhiyun int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (r < 0)
74*4882a593Smuzhiyun return r;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun regnum = (regnum >> 16) & 0x1f;
77*4882a593Smuzhiyun op = 3; /* MDIO_CLAUSE_45_READ */
78*4882a593Smuzhiyun } else {
79*4882a593Smuzhiyun cavium_mdiobus_set_mode(p, C22);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun smi_cmd.u64 = 0;
83*4882a593Smuzhiyun smi_cmd.s.phy_op = op;
84*4882a593Smuzhiyun smi_cmd.s.phy_adr = phy_id;
85*4882a593Smuzhiyun smi_cmd.s.reg_adr = regnum;
86*4882a593Smuzhiyun oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun do {
89*4882a593Smuzhiyun /* Wait 1000 clocks so we don't saturate the RSL bus
90*4882a593Smuzhiyun * doing reads.
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun __delay(1000);
93*4882a593Smuzhiyun smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
94*4882a593Smuzhiyun } while (smi_rd.s.pending && --timeout);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (smi_rd.s.val)
97*4882a593Smuzhiyun return smi_rd.s.dat;
98*4882a593Smuzhiyun else
99*4882a593Smuzhiyun return -EIO;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun EXPORT_SYMBOL(cavium_mdiobus_read);
102*4882a593Smuzhiyun
cavium_mdiobus_write(struct mii_bus * bus,int phy_id,int regnum,u16 val)103*4882a593Smuzhiyun int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct cavium_mdiobus *p = bus->priv;
106*4882a593Smuzhiyun union cvmx_smix_cmd smi_cmd;
107*4882a593Smuzhiyun union cvmx_smix_wr_dat smi_wr;
108*4882a593Smuzhiyun unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
109*4882a593Smuzhiyun int timeout = 1000;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun if (regnum & MII_ADDR_C45) {
112*4882a593Smuzhiyun int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (r < 0)
115*4882a593Smuzhiyun return r;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun regnum = (regnum >> 16) & 0x1f;
118*4882a593Smuzhiyun op = 1; /* MDIO_CLAUSE_45_WRITE */
119*4882a593Smuzhiyun } else {
120*4882a593Smuzhiyun cavium_mdiobus_set_mode(p, C22);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun smi_wr.u64 = 0;
124*4882a593Smuzhiyun smi_wr.s.dat = val;
125*4882a593Smuzhiyun oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun smi_cmd.u64 = 0;
128*4882a593Smuzhiyun smi_cmd.s.phy_op = op;
129*4882a593Smuzhiyun smi_cmd.s.phy_adr = phy_id;
130*4882a593Smuzhiyun smi_cmd.s.reg_adr = regnum;
131*4882a593Smuzhiyun oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun do {
134*4882a593Smuzhiyun /* Wait 1000 clocks so we don't saturate the RSL bus
135*4882a593Smuzhiyun * doing reads.
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun __delay(1000);
138*4882a593Smuzhiyun smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
139*4882a593Smuzhiyun } while (smi_wr.s.pending && --timeout);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if (timeout <= 0)
142*4882a593Smuzhiyun return -EIO;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun EXPORT_SYMBOL(cavium_mdiobus_write);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun MODULE_DESCRIPTION("Common code for OCTEON and Thunder MDIO bus drivers");
149*4882a593Smuzhiyun MODULE_AUTHOR("David Daney");
150*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
151