1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /* Copyright (C) 2019 IBM Corp. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/bitfield.h>
5*4882a593Smuzhiyun #include <linux/delay.h>
6*4882a593Smuzhiyun #include <linux/iopoll.h>
7*4882a593Smuzhiyun #include <linux/mdio.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/of_mdio.h>
11*4882a593Smuzhiyun #include <linux/phy.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define DRV_NAME "mdio-aspeed"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL 0x0
17*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_FIRE BIT(31)
18*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_ST BIT(28)
19*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_ST_C45 0
20*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_ST_C22 1
21*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_OP GENMASK(27, 26)
22*4882a593Smuzhiyun #define MDIO_C22_OP_WRITE 0b01
23*4882a593Smuzhiyun #define MDIO_C22_OP_READ 0b10
24*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21)
25*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16)
26*4882a593Smuzhiyun #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define ASPEED_MDIO_DATA 0x4
29*4882a593Smuzhiyun #define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24)
30*4882a593Smuzhiyun #define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23)
31*4882a593Smuzhiyun #define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20)
32*4882a593Smuzhiyun #define ASPEED_MDIO_DATA_IDLE BIT(16)
33*4882a593Smuzhiyun #define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0)
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define ASPEED_MDIO_INTERVAL_US 100
36*4882a593Smuzhiyun #define ASPEED_MDIO_TIMEOUT_US (ASPEED_MDIO_INTERVAL_US * 10)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct aspeed_mdio {
39*4882a593Smuzhiyun void __iomem *base;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
aspeed_mdio_read(struct mii_bus * bus,int addr,int regnum)42*4882a593Smuzhiyun static int aspeed_mdio_read(struct mii_bus *bus, int addr, int regnum)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct aspeed_mdio *ctx = bus->priv;
45*4882a593Smuzhiyun u32 ctrl;
46*4882a593Smuzhiyun u32 data;
47*4882a593Smuzhiyun int rc;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d\n", __func__, addr,
50*4882a593Smuzhiyun regnum);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Just clause 22 for the moment */
53*4882a593Smuzhiyun if (regnum & MII_ADDR_C45)
54*4882a593Smuzhiyun return -EOPNOTSUPP;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun ctrl = ASPEED_MDIO_CTRL_FIRE
57*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22)
58*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ)
59*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr)
60*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regnum);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun rc = readl_poll_timeout(ctx->base + ASPEED_MDIO_CTRL, ctrl,
65*4882a593Smuzhiyun !(ctrl & ASPEED_MDIO_CTRL_FIRE),
66*4882a593Smuzhiyun ASPEED_MDIO_INTERVAL_US,
67*4882a593Smuzhiyun ASPEED_MDIO_TIMEOUT_US);
68*4882a593Smuzhiyun if (rc < 0)
69*4882a593Smuzhiyun return rc;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun rc = readl_poll_timeout(ctx->base + ASPEED_MDIO_DATA, data,
72*4882a593Smuzhiyun data & ASPEED_MDIO_DATA_IDLE,
73*4882a593Smuzhiyun ASPEED_MDIO_INTERVAL_US,
74*4882a593Smuzhiyun ASPEED_MDIO_TIMEOUT_US);
75*4882a593Smuzhiyun if (rc < 0)
76*4882a593Smuzhiyun return rc;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
aspeed_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)81*4882a593Smuzhiyun static int aspeed_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct aspeed_mdio *ctx = bus->priv;
84*4882a593Smuzhiyun u32 ctrl;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d, val: 0x%x\n",
87*4882a593Smuzhiyun __func__, addr, regnum, val);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Just clause 22 for the moment */
90*4882a593Smuzhiyun if (regnum & MII_ADDR_C45)
91*4882a593Smuzhiyun return -EOPNOTSUPP;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun ctrl = ASPEED_MDIO_CTRL_FIRE
94*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22)
95*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_WRITE)
96*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr)
97*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regnum)
98*4882a593Smuzhiyun | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return readl_poll_timeout(ctx->base + ASPEED_MDIO_CTRL, ctrl,
103*4882a593Smuzhiyun !(ctrl & ASPEED_MDIO_CTRL_FIRE),
104*4882a593Smuzhiyun ASPEED_MDIO_INTERVAL_US,
105*4882a593Smuzhiyun ASPEED_MDIO_TIMEOUT_US);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
aspeed_mdio_probe(struct platform_device * pdev)108*4882a593Smuzhiyun static int aspeed_mdio_probe(struct platform_device *pdev)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun struct aspeed_mdio *ctx;
111*4882a593Smuzhiyun struct mii_bus *bus;
112*4882a593Smuzhiyun int rc;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*ctx));
115*4882a593Smuzhiyun if (!bus)
116*4882a593Smuzhiyun return -ENOMEM;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun ctx = bus->priv;
119*4882a593Smuzhiyun ctx->base = devm_platform_ioremap_resource(pdev, 0);
120*4882a593Smuzhiyun if (IS_ERR(ctx->base))
121*4882a593Smuzhiyun return PTR_ERR(ctx->base);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun bus->name = DRV_NAME;
124*4882a593Smuzhiyun snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
125*4882a593Smuzhiyun bus->parent = &pdev->dev;
126*4882a593Smuzhiyun bus->read = aspeed_mdio_read;
127*4882a593Smuzhiyun bus->write = aspeed_mdio_write;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun rc = of_mdiobus_register(bus, pdev->dev.of_node);
130*4882a593Smuzhiyun if (rc) {
131*4882a593Smuzhiyun dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
132*4882a593Smuzhiyun return rc;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun platform_set_drvdata(pdev, bus);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
aspeed_mdio_remove(struct platform_device * pdev)140*4882a593Smuzhiyun static int aspeed_mdio_remove(struct platform_device *pdev)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun mdiobus_unregister(platform_get_drvdata(pdev));
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct of_device_id aspeed_mdio_of_match[] = {
148*4882a593Smuzhiyun { .compatible = "aspeed,ast2600-mdio", },
149*4882a593Smuzhiyun { },
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, aspeed_mdio_of_match);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static struct platform_driver aspeed_mdio_driver = {
154*4882a593Smuzhiyun .driver = {
155*4882a593Smuzhiyun .name = DRV_NAME,
156*4882a593Smuzhiyun .of_match_table = aspeed_mdio_of_match,
157*4882a593Smuzhiyun },
158*4882a593Smuzhiyun .probe = aspeed_mdio_probe,
159*4882a593Smuzhiyun .remove = aspeed_mdio_remove,
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun module_platform_driver(aspeed_mdio_driver);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
165*4882a593Smuzhiyun MODULE_LICENSE("GPL");
166