1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * mdio.c: Generic support for MDIO-compatible transceivers
4*4882a593Smuzhiyun * Copyright 2006-2009 Solarflare Communications Inc.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/capability.h>
9*4882a593Smuzhiyun #include <linux/errno.h>
10*4882a593Smuzhiyun #include <linux/ethtool.h>
11*4882a593Smuzhiyun #include <linux/mdio.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers");
15*4882a593Smuzhiyun MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc.");
16*4882a593Smuzhiyun MODULE_LICENSE("GPL");
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /**
19*4882a593Smuzhiyun * mdio45_probe - probe for an MDIO (clause 45) device
20*4882a593Smuzhiyun * @mdio: MDIO interface
21*4882a593Smuzhiyun * @prtad: Expected PHY address
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * This sets @prtad and @mmds in the MDIO interface if successful.
24*4882a593Smuzhiyun * Returns 0 on success, negative on error.
25*4882a593Smuzhiyun */
mdio45_probe(struct mdio_if_info * mdio,int prtad)26*4882a593Smuzhiyun int mdio45_probe(struct mdio_if_info *mdio, int prtad)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun int mmd, stat2, devs1, devs2;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Assume PHY must have at least one of PMA/PMD, WIS, PCS, PHY
31*4882a593Smuzhiyun * XS or DTE XS; give up if none is present. */
32*4882a593Smuzhiyun for (mmd = 1; mmd <= 5; mmd++) {
33*4882a593Smuzhiyun /* Is this MMD present? */
34*4882a593Smuzhiyun stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2);
35*4882a593Smuzhiyun if (stat2 < 0 ||
36*4882a593Smuzhiyun (stat2 & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL)
37*4882a593Smuzhiyun continue;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* It should tell us about all the other MMDs */
40*4882a593Smuzhiyun devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1);
41*4882a593Smuzhiyun devs2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS2);
42*4882a593Smuzhiyun if (devs1 < 0 || devs2 < 0)
43*4882a593Smuzhiyun continue;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun mdio->prtad = prtad;
46*4882a593Smuzhiyun mdio->mmds = devs1 | (devs2 << 16);
47*4882a593Smuzhiyun return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return -ENODEV;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun EXPORT_SYMBOL(mdio45_probe);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /**
55*4882a593Smuzhiyun * mdio_set_flag - set or clear flag in an MDIO register
56*4882a593Smuzhiyun * @mdio: MDIO interface
57*4882a593Smuzhiyun * @prtad: PHY address
58*4882a593Smuzhiyun * @devad: MMD address
59*4882a593Smuzhiyun * @addr: Register address
60*4882a593Smuzhiyun * @mask: Mask for flag (single bit set)
61*4882a593Smuzhiyun * @sense: New value of flag
62*4882a593Smuzhiyun *
63*4882a593Smuzhiyun * This debounces changes: it does not write the register if the flag
64*4882a593Smuzhiyun * already has the proper value. Returns 0 on success, negative on error.
65*4882a593Smuzhiyun */
mdio_set_flag(const struct mdio_if_info * mdio,int prtad,int devad,u16 addr,int mask,bool sense)66*4882a593Smuzhiyun int mdio_set_flag(const struct mdio_if_info *mdio,
67*4882a593Smuzhiyun int prtad, int devad, u16 addr, int mask,
68*4882a593Smuzhiyun bool sense)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun int old_val = mdio->mdio_read(mdio->dev, prtad, devad, addr);
71*4882a593Smuzhiyun int new_val;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (old_val < 0)
74*4882a593Smuzhiyun return old_val;
75*4882a593Smuzhiyun if (sense)
76*4882a593Smuzhiyun new_val = old_val | mask;
77*4882a593Smuzhiyun else
78*4882a593Smuzhiyun new_val = old_val & ~mask;
79*4882a593Smuzhiyun if (old_val == new_val)
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun return mdio->mdio_write(mdio->dev, prtad, devad, addr, new_val);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun EXPORT_SYMBOL(mdio_set_flag);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /**
86*4882a593Smuzhiyun * mdio_link_ok - is link status up/OK
87*4882a593Smuzhiyun * @mdio: MDIO interface
88*4882a593Smuzhiyun * @mmd_mask: Mask for MMDs to check
89*4882a593Smuzhiyun *
90*4882a593Smuzhiyun * Returns 1 if the PHY reports link status up/OK, 0 otherwise.
91*4882a593Smuzhiyun * @mmd_mask is normally @mdio->mmds, but if loopback is enabled
92*4882a593Smuzhiyun * the MMDs being bypassed should be excluded from the mask.
93*4882a593Smuzhiyun */
mdio45_links_ok(const struct mdio_if_info * mdio,u32 mmd_mask)94*4882a593Smuzhiyun int mdio45_links_ok(const struct mdio_if_info *mdio, u32 mmd_mask)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun int devad, reg;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (!mmd_mask) {
99*4882a593Smuzhiyun /* Use absence of XGMII faults in lieu of link state */
100*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad,
101*4882a593Smuzhiyun MDIO_MMD_PHYXS, MDIO_STAT2);
102*4882a593Smuzhiyun return reg >= 0 && !(reg & MDIO_STAT2_RXFAULT);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun for (devad = 0; mmd_mask; devad++) {
106*4882a593Smuzhiyun if (mmd_mask & (1 << devad)) {
107*4882a593Smuzhiyun mmd_mask &= ~(1 << devad);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Reset the latched status and fault flags */
110*4882a593Smuzhiyun mdio->mdio_read(mdio->dev, mdio->prtad,
111*4882a593Smuzhiyun devad, MDIO_STAT1);
112*4882a593Smuzhiyun if (devad == MDIO_MMD_PMAPMD || devad == MDIO_MMD_PCS ||
113*4882a593Smuzhiyun devad == MDIO_MMD_PHYXS || devad == MDIO_MMD_DTEXS)
114*4882a593Smuzhiyun mdio->mdio_read(mdio->dev, mdio->prtad,
115*4882a593Smuzhiyun devad, MDIO_STAT2);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Check the current status and fault flags */
118*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad,
119*4882a593Smuzhiyun devad, MDIO_STAT1);
120*4882a593Smuzhiyun if (reg < 0 ||
121*4882a593Smuzhiyun (reg & (MDIO_STAT1_FAULT | MDIO_STAT1_LSTATUS)) !=
122*4882a593Smuzhiyun MDIO_STAT1_LSTATUS)
123*4882a593Smuzhiyun return false;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return true;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun EXPORT_SYMBOL(mdio45_links_ok);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /**
132*4882a593Smuzhiyun * mdio45_nway_restart - restart auto-negotiation for this interface
133*4882a593Smuzhiyun * @mdio: MDIO interface
134*4882a593Smuzhiyun *
135*4882a593Smuzhiyun * Returns 0 on success, negative on error.
136*4882a593Smuzhiyun */
mdio45_nway_restart(const struct mdio_if_info * mdio)137*4882a593Smuzhiyun int mdio45_nway_restart(const struct mdio_if_info *mdio)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun if (!(mdio->mmds & MDIO_DEVS_AN))
140*4882a593Smuzhiyun return -EOPNOTSUPP;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1,
143*4882a593Smuzhiyun MDIO_AN_CTRL1_RESTART, true);
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun EXPORT_SYMBOL(mdio45_nway_restart);
147*4882a593Smuzhiyun
mdio45_get_an(const struct mdio_if_info * mdio,u16 addr)148*4882a593Smuzhiyun static u32 mdio45_get_an(const struct mdio_if_info *mdio, u16 addr)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun u32 result = 0;
151*4882a593Smuzhiyun int reg;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr);
154*4882a593Smuzhiyun if (reg & ADVERTISE_10HALF)
155*4882a593Smuzhiyun result |= ADVERTISED_10baseT_Half;
156*4882a593Smuzhiyun if (reg & ADVERTISE_10FULL)
157*4882a593Smuzhiyun result |= ADVERTISED_10baseT_Full;
158*4882a593Smuzhiyun if (reg & ADVERTISE_100HALF)
159*4882a593Smuzhiyun result |= ADVERTISED_100baseT_Half;
160*4882a593Smuzhiyun if (reg & ADVERTISE_100FULL)
161*4882a593Smuzhiyun result |= ADVERTISED_100baseT_Full;
162*4882a593Smuzhiyun if (reg & ADVERTISE_PAUSE_CAP)
163*4882a593Smuzhiyun result |= ADVERTISED_Pause;
164*4882a593Smuzhiyun if (reg & ADVERTISE_PAUSE_ASYM)
165*4882a593Smuzhiyun result |= ADVERTISED_Asym_Pause;
166*4882a593Smuzhiyun return result;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /**
170*4882a593Smuzhiyun * mdio45_ethtool_gset_npage - get settings for ETHTOOL_GSET
171*4882a593Smuzhiyun * @mdio: MDIO interface
172*4882a593Smuzhiyun * @ecmd: Ethtool request structure
173*4882a593Smuzhiyun * @npage_adv: Modes currently advertised on next pages
174*4882a593Smuzhiyun * @npage_lpa: Modes advertised by link partner on next pages
175*4882a593Smuzhiyun *
176*4882a593Smuzhiyun * The @ecmd parameter is expected to have been cleared before calling
177*4882a593Smuzhiyun * mdio45_ethtool_gset_npage().
178*4882a593Smuzhiyun *
179*4882a593Smuzhiyun * Since the CSRs for auto-negotiation using next pages are not fully
180*4882a593Smuzhiyun * standardised, this function does not attempt to decode them. The
181*4882a593Smuzhiyun * caller must pass them in.
182*4882a593Smuzhiyun */
mdio45_ethtool_gset_npage(const struct mdio_if_info * mdio,struct ethtool_cmd * ecmd,u32 npage_adv,u32 npage_lpa)183*4882a593Smuzhiyun void mdio45_ethtool_gset_npage(const struct mdio_if_info *mdio,
184*4882a593Smuzhiyun struct ethtool_cmd *ecmd,
185*4882a593Smuzhiyun u32 npage_adv, u32 npage_lpa)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun int reg;
188*4882a593Smuzhiyun u32 speed;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun BUILD_BUG_ON(MDIO_SUPPORTS_C22 != ETH_MDIO_SUPPORTS_C22);
191*4882a593Smuzhiyun BUILD_BUG_ON(MDIO_SUPPORTS_C45 != ETH_MDIO_SUPPORTS_C45);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun ecmd->transceiver = XCVR_INTERNAL;
194*4882a593Smuzhiyun ecmd->phy_address = mdio->prtad;
195*4882a593Smuzhiyun ecmd->mdio_support =
196*4882a593Smuzhiyun mdio->mode_support & (MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
199*4882a593Smuzhiyun MDIO_CTRL2);
200*4882a593Smuzhiyun switch (reg & MDIO_PMA_CTRL2_TYPE) {
201*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBT:
202*4882a593Smuzhiyun case MDIO_PMA_CTRL2_1000BT:
203*4882a593Smuzhiyun case MDIO_PMA_CTRL2_100BTX:
204*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10BT:
205*4882a593Smuzhiyun ecmd->port = PORT_TP;
206*4882a593Smuzhiyun ecmd->supported = SUPPORTED_TP;
207*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
208*4882a593Smuzhiyun MDIO_SPEED);
209*4882a593Smuzhiyun if (reg & MDIO_SPEED_10G)
210*4882a593Smuzhiyun ecmd->supported |= SUPPORTED_10000baseT_Full;
211*4882a593Smuzhiyun if (reg & MDIO_PMA_SPEED_1000)
212*4882a593Smuzhiyun ecmd->supported |= (SUPPORTED_1000baseT_Full |
213*4882a593Smuzhiyun SUPPORTED_1000baseT_Half);
214*4882a593Smuzhiyun if (reg & MDIO_PMA_SPEED_100)
215*4882a593Smuzhiyun ecmd->supported |= (SUPPORTED_100baseT_Full |
216*4882a593Smuzhiyun SUPPORTED_100baseT_Half);
217*4882a593Smuzhiyun if (reg & MDIO_PMA_SPEED_10)
218*4882a593Smuzhiyun ecmd->supported |= (SUPPORTED_10baseT_Full |
219*4882a593Smuzhiyun SUPPORTED_10baseT_Half);
220*4882a593Smuzhiyun ecmd->advertising = ADVERTISED_TP;
221*4882a593Smuzhiyun break;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBCX4:
224*4882a593Smuzhiyun ecmd->port = PORT_OTHER;
225*4882a593Smuzhiyun ecmd->supported = 0;
226*4882a593Smuzhiyun ecmd->advertising = 0;
227*4882a593Smuzhiyun break;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBKX4:
230*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBKR:
231*4882a593Smuzhiyun case MDIO_PMA_CTRL2_1000BKX:
232*4882a593Smuzhiyun ecmd->port = PORT_OTHER;
233*4882a593Smuzhiyun ecmd->supported = SUPPORTED_Backplane;
234*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
235*4882a593Smuzhiyun MDIO_PMA_EXTABLE);
236*4882a593Smuzhiyun if (reg & MDIO_PMA_EXTABLE_10GBKX4)
237*4882a593Smuzhiyun ecmd->supported |= SUPPORTED_10000baseKX4_Full;
238*4882a593Smuzhiyun if (reg & MDIO_PMA_EXTABLE_10GBKR)
239*4882a593Smuzhiyun ecmd->supported |= SUPPORTED_10000baseKR_Full;
240*4882a593Smuzhiyun if (reg & MDIO_PMA_EXTABLE_1000BKX)
241*4882a593Smuzhiyun ecmd->supported |= SUPPORTED_1000baseKX_Full;
242*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
243*4882a593Smuzhiyun MDIO_PMA_10GBR_FECABLE);
244*4882a593Smuzhiyun if (reg & MDIO_PMA_10GBR_FECABLE_ABLE)
245*4882a593Smuzhiyun ecmd->supported |= SUPPORTED_10000baseR_FEC;
246*4882a593Smuzhiyun ecmd->advertising = ADVERTISED_Backplane;
247*4882a593Smuzhiyun break;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* All the other defined modes are flavours of optical */
250*4882a593Smuzhiyun default:
251*4882a593Smuzhiyun ecmd->port = PORT_FIBRE;
252*4882a593Smuzhiyun ecmd->supported = SUPPORTED_FIBRE;
253*4882a593Smuzhiyun ecmd->advertising = ADVERTISED_FIBRE;
254*4882a593Smuzhiyun break;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun if (mdio->mmds & MDIO_DEVS_AN) {
258*4882a593Smuzhiyun ecmd->supported |= SUPPORTED_Autoneg;
259*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN,
260*4882a593Smuzhiyun MDIO_CTRL1);
261*4882a593Smuzhiyun if (reg & MDIO_AN_CTRL1_ENABLE) {
262*4882a593Smuzhiyun ecmd->autoneg = AUTONEG_ENABLE;
263*4882a593Smuzhiyun ecmd->advertising |=
264*4882a593Smuzhiyun ADVERTISED_Autoneg |
265*4882a593Smuzhiyun mdio45_get_an(mdio, MDIO_AN_ADVERTISE) |
266*4882a593Smuzhiyun npage_adv;
267*4882a593Smuzhiyun } else {
268*4882a593Smuzhiyun ecmd->autoneg = AUTONEG_DISABLE;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun } else {
271*4882a593Smuzhiyun ecmd->autoneg = AUTONEG_DISABLE;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (ecmd->autoneg) {
275*4882a593Smuzhiyun u32 modes = 0;
276*4882a593Smuzhiyun int an_stat = mdio->mdio_read(mdio->dev, mdio->prtad,
277*4882a593Smuzhiyun MDIO_MMD_AN, MDIO_STAT1);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun /* If AN is complete and successful, report best common
280*4882a593Smuzhiyun * mode, otherwise report best advertised mode. */
281*4882a593Smuzhiyun if (an_stat & MDIO_AN_STAT1_COMPLETE) {
282*4882a593Smuzhiyun ecmd->lp_advertising =
283*4882a593Smuzhiyun mdio45_get_an(mdio, MDIO_AN_LPA) | npage_lpa;
284*4882a593Smuzhiyun if (an_stat & MDIO_AN_STAT1_LPABLE)
285*4882a593Smuzhiyun ecmd->lp_advertising |= ADVERTISED_Autoneg;
286*4882a593Smuzhiyun modes = ecmd->advertising & ecmd->lp_advertising;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun if ((modes & ~ADVERTISED_Autoneg) == 0)
289*4882a593Smuzhiyun modes = ecmd->advertising;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if (modes & (ADVERTISED_10000baseT_Full |
292*4882a593Smuzhiyun ADVERTISED_10000baseKX4_Full |
293*4882a593Smuzhiyun ADVERTISED_10000baseKR_Full)) {
294*4882a593Smuzhiyun speed = SPEED_10000;
295*4882a593Smuzhiyun ecmd->duplex = DUPLEX_FULL;
296*4882a593Smuzhiyun } else if (modes & (ADVERTISED_1000baseT_Full |
297*4882a593Smuzhiyun ADVERTISED_1000baseT_Half |
298*4882a593Smuzhiyun ADVERTISED_1000baseKX_Full)) {
299*4882a593Smuzhiyun speed = SPEED_1000;
300*4882a593Smuzhiyun ecmd->duplex = !(modes & ADVERTISED_1000baseT_Half);
301*4882a593Smuzhiyun } else if (modes & (ADVERTISED_100baseT_Full |
302*4882a593Smuzhiyun ADVERTISED_100baseT_Half)) {
303*4882a593Smuzhiyun speed = SPEED_100;
304*4882a593Smuzhiyun ecmd->duplex = !!(modes & ADVERTISED_100baseT_Full);
305*4882a593Smuzhiyun } else {
306*4882a593Smuzhiyun speed = SPEED_10;
307*4882a593Smuzhiyun ecmd->duplex = !!(modes & ADVERTISED_10baseT_Full);
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun } else {
310*4882a593Smuzhiyun /* Report forced settings */
311*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
312*4882a593Smuzhiyun MDIO_CTRL1);
313*4882a593Smuzhiyun speed = (((reg & MDIO_PMA_CTRL1_SPEED1000) ? 100 : 1)
314*4882a593Smuzhiyun * ((reg & MDIO_PMA_CTRL1_SPEED100) ? 100 : 10));
315*4882a593Smuzhiyun ecmd->duplex = (reg & MDIO_CTRL1_FULLDPLX ||
316*4882a593Smuzhiyun speed == SPEED_10000);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun ethtool_cmd_speed_set(ecmd, speed);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* 10GBASE-T MDI/MDI-X */
322*4882a593Smuzhiyun if (ecmd->port == PORT_TP
323*4882a593Smuzhiyun && (ethtool_cmd_speed(ecmd) == SPEED_10000)) {
324*4882a593Smuzhiyun switch (mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
325*4882a593Smuzhiyun MDIO_PMA_10GBT_SWAPPOL)) {
326*4882a593Smuzhiyun case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
327*4882a593Smuzhiyun ecmd->eth_tp_mdix = ETH_TP_MDI;
328*4882a593Smuzhiyun break;
329*4882a593Smuzhiyun case 0:
330*4882a593Smuzhiyun ecmd->eth_tp_mdix = ETH_TP_MDI_X;
331*4882a593Smuzhiyun break;
332*4882a593Smuzhiyun default:
333*4882a593Smuzhiyun /* It's complicated... */
334*4882a593Smuzhiyun ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
335*4882a593Smuzhiyun break;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun EXPORT_SYMBOL(mdio45_ethtool_gset_npage);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /**
342*4882a593Smuzhiyun * mdio45_ethtool_ksettings_get_npage - get settings for ETHTOOL_GLINKSETTINGS
343*4882a593Smuzhiyun * @mdio: MDIO interface
344*4882a593Smuzhiyun * @cmd: Ethtool request structure
345*4882a593Smuzhiyun * @npage_adv: Modes currently advertised on next pages
346*4882a593Smuzhiyun * @npage_lpa: Modes advertised by link partner on next pages
347*4882a593Smuzhiyun *
348*4882a593Smuzhiyun * The @cmd parameter is expected to have been cleared before calling
349*4882a593Smuzhiyun * mdio45_ethtool_ksettings_get_npage().
350*4882a593Smuzhiyun *
351*4882a593Smuzhiyun * Since the CSRs for auto-negotiation using next pages are not fully
352*4882a593Smuzhiyun * standardised, this function does not attempt to decode them. The
353*4882a593Smuzhiyun * caller must pass them in.
354*4882a593Smuzhiyun */
mdio45_ethtool_ksettings_get_npage(const struct mdio_if_info * mdio,struct ethtool_link_ksettings * cmd,u32 npage_adv,u32 npage_lpa)355*4882a593Smuzhiyun void mdio45_ethtool_ksettings_get_npage(const struct mdio_if_info *mdio,
356*4882a593Smuzhiyun struct ethtool_link_ksettings *cmd,
357*4882a593Smuzhiyun u32 npage_adv, u32 npage_lpa)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun int reg;
360*4882a593Smuzhiyun u32 speed, supported = 0, advertising = 0, lp_advertising = 0;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun BUILD_BUG_ON(MDIO_SUPPORTS_C22 != ETH_MDIO_SUPPORTS_C22);
363*4882a593Smuzhiyun BUILD_BUG_ON(MDIO_SUPPORTS_C45 != ETH_MDIO_SUPPORTS_C45);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun cmd->base.phy_address = mdio->prtad;
366*4882a593Smuzhiyun cmd->base.mdio_support =
367*4882a593Smuzhiyun mdio->mode_support & (MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
370*4882a593Smuzhiyun MDIO_CTRL2);
371*4882a593Smuzhiyun switch (reg & MDIO_PMA_CTRL2_TYPE) {
372*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBT:
373*4882a593Smuzhiyun case MDIO_PMA_CTRL2_1000BT:
374*4882a593Smuzhiyun case MDIO_PMA_CTRL2_100BTX:
375*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10BT:
376*4882a593Smuzhiyun cmd->base.port = PORT_TP;
377*4882a593Smuzhiyun supported = SUPPORTED_TP;
378*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
379*4882a593Smuzhiyun MDIO_SPEED);
380*4882a593Smuzhiyun if (reg & MDIO_SPEED_10G)
381*4882a593Smuzhiyun supported |= SUPPORTED_10000baseT_Full;
382*4882a593Smuzhiyun if (reg & MDIO_PMA_SPEED_1000)
383*4882a593Smuzhiyun supported |= (SUPPORTED_1000baseT_Full |
384*4882a593Smuzhiyun SUPPORTED_1000baseT_Half);
385*4882a593Smuzhiyun if (reg & MDIO_PMA_SPEED_100)
386*4882a593Smuzhiyun supported |= (SUPPORTED_100baseT_Full |
387*4882a593Smuzhiyun SUPPORTED_100baseT_Half);
388*4882a593Smuzhiyun if (reg & MDIO_PMA_SPEED_10)
389*4882a593Smuzhiyun supported |= (SUPPORTED_10baseT_Full |
390*4882a593Smuzhiyun SUPPORTED_10baseT_Half);
391*4882a593Smuzhiyun advertising = ADVERTISED_TP;
392*4882a593Smuzhiyun break;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBCX4:
395*4882a593Smuzhiyun cmd->base.port = PORT_OTHER;
396*4882a593Smuzhiyun supported = 0;
397*4882a593Smuzhiyun advertising = 0;
398*4882a593Smuzhiyun break;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBKX4:
401*4882a593Smuzhiyun case MDIO_PMA_CTRL2_10GBKR:
402*4882a593Smuzhiyun case MDIO_PMA_CTRL2_1000BKX:
403*4882a593Smuzhiyun cmd->base.port = PORT_OTHER;
404*4882a593Smuzhiyun supported = SUPPORTED_Backplane;
405*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
406*4882a593Smuzhiyun MDIO_PMA_EXTABLE);
407*4882a593Smuzhiyun if (reg & MDIO_PMA_EXTABLE_10GBKX4)
408*4882a593Smuzhiyun supported |= SUPPORTED_10000baseKX4_Full;
409*4882a593Smuzhiyun if (reg & MDIO_PMA_EXTABLE_10GBKR)
410*4882a593Smuzhiyun supported |= SUPPORTED_10000baseKR_Full;
411*4882a593Smuzhiyun if (reg & MDIO_PMA_EXTABLE_1000BKX)
412*4882a593Smuzhiyun supported |= SUPPORTED_1000baseKX_Full;
413*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
414*4882a593Smuzhiyun MDIO_PMA_10GBR_FECABLE);
415*4882a593Smuzhiyun if (reg & MDIO_PMA_10GBR_FECABLE_ABLE)
416*4882a593Smuzhiyun supported |= SUPPORTED_10000baseR_FEC;
417*4882a593Smuzhiyun advertising = ADVERTISED_Backplane;
418*4882a593Smuzhiyun break;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /* All the other defined modes are flavours of optical */
421*4882a593Smuzhiyun default:
422*4882a593Smuzhiyun cmd->base.port = PORT_FIBRE;
423*4882a593Smuzhiyun supported = SUPPORTED_FIBRE;
424*4882a593Smuzhiyun advertising = ADVERTISED_FIBRE;
425*4882a593Smuzhiyun break;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (mdio->mmds & MDIO_DEVS_AN) {
429*4882a593Smuzhiyun supported |= SUPPORTED_Autoneg;
430*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN,
431*4882a593Smuzhiyun MDIO_CTRL1);
432*4882a593Smuzhiyun if (reg & MDIO_AN_CTRL1_ENABLE) {
433*4882a593Smuzhiyun cmd->base.autoneg = AUTONEG_ENABLE;
434*4882a593Smuzhiyun advertising |=
435*4882a593Smuzhiyun ADVERTISED_Autoneg |
436*4882a593Smuzhiyun mdio45_get_an(mdio, MDIO_AN_ADVERTISE) |
437*4882a593Smuzhiyun npage_adv;
438*4882a593Smuzhiyun } else {
439*4882a593Smuzhiyun cmd->base.autoneg = AUTONEG_DISABLE;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun } else {
442*4882a593Smuzhiyun cmd->base.autoneg = AUTONEG_DISABLE;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun if (cmd->base.autoneg) {
446*4882a593Smuzhiyun u32 modes = 0;
447*4882a593Smuzhiyun int an_stat = mdio->mdio_read(mdio->dev, mdio->prtad,
448*4882a593Smuzhiyun MDIO_MMD_AN, MDIO_STAT1);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /* If AN is complete and successful, report best common
451*4882a593Smuzhiyun * mode, otherwise report best advertised mode.
452*4882a593Smuzhiyun */
453*4882a593Smuzhiyun if (an_stat & MDIO_AN_STAT1_COMPLETE) {
454*4882a593Smuzhiyun lp_advertising =
455*4882a593Smuzhiyun mdio45_get_an(mdio, MDIO_AN_LPA) | npage_lpa;
456*4882a593Smuzhiyun if (an_stat & MDIO_AN_STAT1_LPABLE)
457*4882a593Smuzhiyun lp_advertising |= ADVERTISED_Autoneg;
458*4882a593Smuzhiyun modes = advertising & lp_advertising;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun if ((modes & ~ADVERTISED_Autoneg) == 0)
461*4882a593Smuzhiyun modes = advertising;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun if (modes & (ADVERTISED_10000baseT_Full |
464*4882a593Smuzhiyun ADVERTISED_10000baseKX4_Full |
465*4882a593Smuzhiyun ADVERTISED_10000baseKR_Full)) {
466*4882a593Smuzhiyun speed = SPEED_10000;
467*4882a593Smuzhiyun cmd->base.duplex = DUPLEX_FULL;
468*4882a593Smuzhiyun } else if (modes & (ADVERTISED_1000baseT_Full |
469*4882a593Smuzhiyun ADVERTISED_1000baseT_Half |
470*4882a593Smuzhiyun ADVERTISED_1000baseKX_Full)) {
471*4882a593Smuzhiyun speed = SPEED_1000;
472*4882a593Smuzhiyun cmd->base.duplex = !(modes & ADVERTISED_1000baseT_Half);
473*4882a593Smuzhiyun } else if (modes & (ADVERTISED_100baseT_Full |
474*4882a593Smuzhiyun ADVERTISED_100baseT_Half)) {
475*4882a593Smuzhiyun speed = SPEED_100;
476*4882a593Smuzhiyun cmd->base.duplex = !!(modes & ADVERTISED_100baseT_Full);
477*4882a593Smuzhiyun } else {
478*4882a593Smuzhiyun speed = SPEED_10;
479*4882a593Smuzhiyun cmd->base.duplex = !!(modes & ADVERTISED_10baseT_Full);
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun } else {
482*4882a593Smuzhiyun /* Report forced settings */
483*4882a593Smuzhiyun reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
484*4882a593Smuzhiyun MDIO_CTRL1);
485*4882a593Smuzhiyun speed = (((reg & MDIO_PMA_CTRL1_SPEED1000) ? 100 : 1)
486*4882a593Smuzhiyun * ((reg & MDIO_PMA_CTRL1_SPEED100) ? 100 : 10));
487*4882a593Smuzhiyun cmd->base.duplex = (reg & MDIO_CTRL1_FULLDPLX ||
488*4882a593Smuzhiyun speed == SPEED_10000);
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun cmd->base.speed = speed;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
494*4882a593Smuzhiyun supported);
495*4882a593Smuzhiyun ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
496*4882a593Smuzhiyun advertising);
497*4882a593Smuzhiyun ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
498*4882a593Smuzhiyun lp_advertising);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /* 10GBASE-T MDI/MDI-X */
501*4882a593Smuzhiyun if (cmd->base.port == PORT_TP && (cmd->base.speed == SPEED_10000)) {
502*4882a593Smuzhiyun switch (mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD,
503*4882a593Smuzhiyun MDIO_PMA_10GBT_SWAPPOL)) {
504*4882a593Smuzhiyun case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
505*4882a593Smuzhiyun cmd->base.eth_tp_mdix = ETH_TP_MDI;
506*4882a593Smuzhiyun break;
507*4882a593Smuzhiyun case 0:
508*4882a593Smuzhiyun cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
509*4882a593Smuzhiyun break;
510*4882a593Smuzhiyun default:
511*4882a593Smuzhiyun /* It's complicated... */
512*4882a593Smuzhiyun cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
513*4882a593Smuzhiyun break;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun EXPORT_SYMBOL(mdio45_ethtool_ksettings_get_npage);
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun /**
520*4882a593Smuzhiyun * mdio_mii_ioctl - MII ioctl interface for MDIO (clause 22 or 45) PHYs
521*4882a593Smuzhiyun * @mdio: MDIO interface
522*4882a593Smuzhiyun * @mii_data: MII ioctl data structure
523*4882a593Smuzhiyun * @cmd: MII ioctl command
524*4882a593Smuzhiyun *
525*4882a593Smuzhiyun * Returns 0 on success, negative on error.
526*4882a593Smuzhiyun */
mdio_mii_ioctl(const struct mdio_if_info * mdio,struct mii_ioctl_data * mii_data,int cmd)527*4882a593Smuzhiyun int mdio_mii_ioctl(const struct mdio_if_info *mdio,
528*4882a593Smuzhiyun struct mii_ioctl_data *mii_data, int cmd)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun int prtad, devad;
531*4882a593Smuzhiyun u16 addr = mii_data->reg_num;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun /* Validate/convert cmd to one of SIOC{G,S}MIIREG */
534*4882a593Smuzhiyun switch (cmd) {
535*4882a593Smuzhiyun case SIOCGMIIPHY:
536*4882a593Smuzhiyun if (mdio->prtad == MDIO_PRTAD_NONE)
537*4882a593Smuzhiyun return -EOPNOTSUPP;
538*4882a593Smuzhiyun mii_data->phy_id = mdio->prtad;
539*4882a593Smuzhiyun cmd = SIOCGMIIREG;
540*4882a593Smuzhiyun break;
541*4882a593Smuzhiyun case SIOCGMIIREG:
542*4882a593Smuzhiyun case SIOCSMIIREG:
543*4882a593Smuzhiyun break;
544*4882a593Smuzhiyun default:
545*4882a593Smuzhiyun return -EOPNOTSUPP;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun /* Validate/convert phy_id */
549*4882a593Smuzhiyun if ((mdio->mode_support & MDIO_SUPPORTS_C45) &&
550*4882a593Smuzhiyun mdio_phy_id_is_c45(mii_data->phy_id)) {
551*4882a593Smuzhiyun prtad = mdio_phy_id_prtad(mii_data->phy_id);
552*4882a593Smuzhiyun devad = mdio_phy_id_devad(mii_data->phy_id);
553*4882a593Smuzhiyun } else if ((mdio->mode_support & MDIO_SUPPORTS_C22) &&
554*4882a593Smuzhiyun mii_data->phy_id < 0x20) {
555*4882a593Smuzhiyun prtad = mii_data->phy_id;
556*4882a593Smuzhiyun devad = MDIO_DEVAD_NONE;
557*4882a593Smuzhiyun addr &= 0x1f;
558*4882a593Smuzhiyun } else if ((mdio->mode_support & MDIO_EMULATE_C22) &&
559*4882a593Smuzhiyun mdio->prtad != MDIO_PRTAD_NONE &&
560*4882a593Smuzhiyun mii_data->phy_id == mdio->prtad) {
561*4882a593Smuzhiyun /* Remap commonly-used MII registers. */
562*4882a593Smuzhiyun prtad = mdio->prtad;
563*4882a593Smuzhiyun switch (addr) {
564*4882a593Smuzhiyun case MII_BMCR:
565*4882a593Smuzhiyun case MII_BMSR:
566*4882a593Smuzhiyun case MII_PHYSID1:
567*4882a593Smuzhiyun case MII_PHYSID2:
568*4882a593Smuzhiyun devad = __ffs(mdio->mmds);
569*4882a593Smuzhiyun break;
570*4882a593Smuzhiyun case MII_ADVERTISE:
571*4882a593Smuzhiyun case MII_LPA:
572*4882a593Smuzhiyun if (!(mdio->mmds & MDIO_DEVS_AN))
573*4882a593Smuzhiyun return -EINVAL;
574*4882a593Smuzhiyun devad = MDIO_MMD_AN;
575*4882a593Smuzhiyun if (addr == MII_ADVERTISE)
576*4882a593Smuzhiyun addr = MDIO_AN_ADVERTISE;
577*4882a593Smuzhiyun else
578*4882a593Smuzhiyun addr = MDIO_AN_LPA;
579*4882a593Smuzhiyun break;
580*4882a593Smuzhiyun default:
581*4882a593Smuzhiyun return -EINVAL;
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun } else {
584*4882a593Smuzhiyun return -EINVAL;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (cmd == SIOCGMIIREG) {
588*4882a593Smuzhiyun int rc = mdio->mdio_read(mdio->dev, prtad, devad, addr);
589*4882a593Smuzhiyun if (rc < 0)
590*4882a593Smuzhiyun return rc;
591*4882a593Smuzhiyun mii_data->val_out = rc;
592*4882a593Smuzhiyun return 0;
593*4882a593Smuzhiyun } else {
594*4882a593Smuzhiyun return mdio->mdio_write(mdio->dev, prtad, devad, addr,
595*4882a593Smuzhiyun mii_data->val_in);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun EXPORT_SYMBOL(mdio_mii_ioctl);
599