xref: /OK3568_Linux_fs/kernel/drivers/net/ipa/ipa_interrupt.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  * Copyright (C) 2018-2020 Linaro Ltd.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun /* DOC: IPA Interrupts
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * The IPA has an interrupt line distinct from the interrupt used by the GSI
10*4882a593Smuzhiyun  * code.  Whereas GSI interrupts are generally related to channel events (like
11*4882a593Smuzhiyun  * transfer completions), IPA interrupts are related to other events related
12*4882a593Smuzhiyun  * to the IPA.  Some of the IPA interrupts come from a microcontroller
13*4882a593Smuzhiyun  * embedded in the IPA.  Each IPA interrupt type can be both masked and
14*4882a593Smuzhiyun  * acknowledged independent of the others.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * Two of the IPA interrupts are initiated by the microcontroller.  A third
17*4882a593Smuzhiyun  * can be generated to signal the need for a wakeup/resume when an IPA
18*4882a593Smuzhiyun  * endpoint has been suspended.  There are other IPA events, but at this
19*4882a593Smuzhiyun  * time only these three are supported.
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun #include <linux/interrupt.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include "ipa.h"
26*4882a593Smuzhiyun #include "ipa_clock.h"
27*4882a593Smuzhiyun #include "ipa_reg.h"
28*4882a593Smuzhiyun #include "ipa_endpoint.h"
29*4882a593Smuzhiyun #include "ipa_interrupt.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /**
32*4882a593Smuzhiyun  * struct ipa_interrupt - IPA interrupt information
33*4882a593Smuzhiyun  * @ipa:		IPA pointer
34*4882a593Smuzhiyun  * @irq:		Linux IRQ number used for IPA interrupts
35*4882a593Smuzhiyun  * @enabled:		Mask indicating which interrupts are enabled
36*4882a593Smuzhiyun  * @handler:		Array of handlers indexed by IPA interrupt ID
37*4882a593Smuzhiyun  */
38*4882a593Smuzhiyun struct ipa_interrupt {
39*4882a593Smuzhiyun 	struct ipa *ipa;
40*4882a593Smuzhiyun 	u32 irq;
41*4882a593Smuzhiyun 	u32 enabled;
42*4882a593Smuzhiyun 	ipa_irq_handler_t handler[IPA_IRQ_COUNT];
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* Returns true if the interrupt type is associated with the microcontroller */
ipa_interrupt_uc(struct ipa_interrupt * interrupt,u32 irq_id)46*4882a593Smuzhiyun static bool ipa_interrupt_uc(struct ipa_interrupt *interrupt, u32 irq_id)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	return irq_id == IPA_IRQ_UC_0 || irq_id == IPA_IRQ_UC_1;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* Process a particular interrupt type that has been received */
ipa_interrupt_process(struct ipa_interrupt * interrupt,u32 irq_id)52*4882a593Smuzhiyun static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	bool uc_irq = ipa_interrupt_uc(interrupt, irq_id);
55*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
56*4882a593Smuzhiyun 	u32 mask = BIT(irq_id);
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	/* For microcontroller interrupts, clear the interrupt right away,
59*4882a593Smuzhiyun 	 * "to avoid clearing unhandled interrupts."
60*4882a593Smuzhiyun 	 */
61*4882a593Smuzhiyun 	if (uc_irq)
62*4882a593Smuzhiyun 		iowrite32(mask, ipa->reg_virt + IPA_REG_IRQ_CLR_OFFSET);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	if (irq_id < IPA_IRQ_COUNT && interrupt->handler[irq_id])
65*4882a593Smuzhiyun 		interrupt->handler[irq_id](interrupt->ipa, irq_id);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* Clearing the SUSPEND_TX interrupt also clears the register
68*4882a593Smuzhiyun 	 * that tells us which suspended endpoint(s) caused the interrupt,
69*4882a593Smuzhiyun 	 * so defer clearing until after the handler has been called.
70*4882a593Smuzhiyun 	 */
71*4882a593Smuzhiyun 	if (!uc_irq)
72*4882a593Smuzhiyun 		iowrite32(mask, ipa->reg_virt + IPA_REG_IRQ_CLR_OFFSET);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* Process all IPA interrupt types that have been signaled */
ipa_interrupt_process_all(struct ipa_interrupt * interrupt)76*4882a593Smuzhiyun static void ipa_interrupt_process_all(struct ipa_interrupt *interrupt)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
79*4882a593Smuzhiyun 	u32 enabled = interrupt->enabled;
80*4882a593Smuzhiyun 	u32 mask;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/* The status register indicates which conditions are present,
83*4882a593Smuzhiyun 	 * including conditions whose interrupt is not enabled.  Handle
84*4882a593Smuzhiyun 	 * only the enabled ones.
85*4882a593Smuzhiyun 	 */
86*4882a593Smuzhiyun 	mask = ioread32(ipa->reg_virt + IPA_REG_IRQ_STTS_OFFSET);
87*4882a593Smuzhiyun 	while ((mask &= enabled)) {
88*4882a593Smuzhiyun 		do {
89*4882a593Smuzhiyun 			u32 irq_id = __ffs(mask);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 			mask ^= BIT(irq_id);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 			ipa_interrupt_process(interrupt, irq_id);
94*4882a593Smuzhiyun 		} while (mask);
95*4882a593Smuzhiyun 		mask = ioread32(ipa->reg_virt + IPA_REG_IRQ_STTS_OFFSET);
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /* Threaded part of the IPA IRQ handler */
ipa_isr_thread(int irq,void * dev_id)100*4882a593Smuzhiyun static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct ipa_interrupt *interrupt = dev_id;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ipa_clock_get(interrupt->ipa);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	ipa_interrupt_process_all(interrupt);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	ipa_clock_put(interrupt->ipa);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	return IRQ_HANDLED;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* Hard part (i.e., "real" IRQ handler) of the IRQ handler */
ipa_isr(int irq,void * dev_id)114*4882a593Smuzhiyun static irqreturn_t ipa_isr(int irq, void *dev_id)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	struct ipa_interrupt *interrupt = dev_id;
117*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
118*4882a593Smuzhiyun 	u32 mask;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	mask = ioread32(ipa->reg_virt + IPA_REG_IRQ_STTS_OFFSET);
121*4882a593Smuzhiyun 	if (mask & interrupt->enabled)
122*4882a593Smuzhiyun 		return IRQ_WAKE_THREAD;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* Nothing in the mask was supposed to cause an interrupt */
125*4882a593Smuzhiyun 	iowrite32(mask, ipa->reg_virt + IPA_REG_IRQ_CLR_OFFSET);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	dev_err(&ipa->pdev->dev, "%s: unexpected interrupt, mask 0x%08x\n",
128*4882a593Smuzhiyun 		__func__, mask);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return IRQ_HANDLED;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun /* Common function used to enable/disable TX_SUSPEND for an endpoint */
ipa_interrupt_suspend_control(struct ipa_interrupt * interrupt,u32 endpoint_id,bool enable)134*4882a593Smuzhiyun static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
135*4882a593Smuzhiyun 					  u32 endpoint_id, bool enable)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
138*4882a593Smuzhiyun 	u32 mask = BIT(endpoint_id);
139*4882a593Smuzhiyun 	u32 val;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* assert(mask & ipa->available); */
142*4882a593Smuzhiyun 	val = ioread32(ipa->reg_virt + IPA_REG_SUSPEND_IRQ_EN_OFFSET);
143*4882a593Smuzhiyun 	if (enable)
144*4882a593Smuzhiyun 		val |= mask;
145*4882a593Smuzhiyun 	else
146*4882a593Smuzhiyun 		val &= ~mask;
147*4882a593Smuzhiyun 	iowrite32(val, ipa->reg_virt + IPA_REG_SUSPEND_IRQ_EN_OFFSET);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /* Enable TX_SUSPEND for an endpoint */
151*4882a593Smuzhiyun void
ipa_interrupt_suspend_enable(struct ipa_interrupt * interrupt,u32 endpoint_id)152*4882a593Smuzhiyun ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	ipa_interrupt_suspend_control(interrupt, endpoint_id, true);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun /* Disable TX_SUSPEND for an endpoint */
158*4882a593Smuzhiyun void
ipa_interrupt_suspend_disable(struct ipa_interrupt * interrupt,u32 endpoint_id)159*4882a593Smuzhiyun ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	ipa_interrupt_suspend_control(interrupt, endpoint_id, false);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /* Clear the suspend interrupt for all endpoints that signaled it */
ipa_interrupt_suspend_clear_all(struct ipa_interrupt * interrupt)165*4882a593Smuzhiyun void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
168*4882a593Smuzhiyun 	u32 val;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	val = ioread32(ipa->reg_virt + IPA_REG_IRQ_SUSPEND_INFO_OFFSET);
171*4882a593Smuzhiyun 	iowrite32(val, ipa->reg_virt + IPA_REG_SUSPEND_IRQ_CLR_OFFSET);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun /* Simulate arrival of an IPA TX_SUSPEND interrupt */
ipa_interrupt_simulate_suspend(struct ipa_interrupt * interrupt)175*4882a593Smuzhiyun void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /* Add a handler for an IPA interrupt */
ipa_interrupt_add(struct ipa_interrupt * interrupt,enum ipa_irq_id ipa_irq,ipa_irq_handler_t handler)181*4882a593Smuzhiyun void ipa_interrupt_add(struct ipa_interrupt *interrupt,
182*4882a593Smuzhiyun 		       enum ipa_irq_id ipa_irq, ipa_irq_handler_t handler)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	/* assert(ipa_irq < IPA_IRQ_COUNT); */
187*4882a593Smuzhiyun 	interrupt->handler[ipa_irq] = handler;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	/* Update the IPA interrupt mask to enable it */
190*4882a593Smuzhiyun 	interrupt->enabled |= BIT(ipa_irq);
191*4882a593Smuzhiyun 	iowrite32(interrupt->enabled, ipa->reg_virt + IPA_REG_IRQ_EN_OFFSET);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun /* Remove the handler for an IPA interrupt type */
195*4882a593Smuzhiyun void
ipa_interrupt_remove(struct ipa_interrupt * interrupt,enum ipa_irq_id ipa_irq)196*4882a593Smuzhiyun ipa_interrupt_remove(struct ipa_interrupt *interrupt, enum ipa_irq_id ipa_irq)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun 	struct ipa *ipa = interrupt->ipa;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* assert(ipa_irq < IPA_IRQ_COUNT); */
201*4882a593Smuzhiyun 	/* Update the IPA interrupt mask to disable it */
202*4882a593Smuzhiyun 	interrupt->enabled &= ~BIT(ipa_irq);
203*4882a593Smuzhiyun 	iowrite32(interrupt->enabled, ipa->reg_virt + IPA_REG_IRQ_EN_OFFSET);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	interrupt->handler[ipa_irq] = NULL;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun /* Set up the IPA interrupt framework */
ipa_interrupt_setup(struct ipa * ipa)209*4882a593Smuzhiyun struct ipa_interrupt *ipa_interrupt_setup(struct ipa *ipa)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	struct device *dev = &ipa->pdev->dev;
212*4882a593Smuzhiyun 	struct ipa_interrupt *interrupt;
213*4882a593Smuzhiyun 	unsigned int irq;
214*4882a593Smuzhiyun 	int ret;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	ret = platform_get_irq_byname(ipa->pdev, "ipa");
217*4882a593Smuzhiyun 	if (ret <= 0) {
218*4882a593Smuzhiyun 		dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n",
219*4882a593Smuzhiyun 			ret);
220*4882a593Smuzhiyun 		return ERR_PTR(ret ? : -EINVAL);
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 	irq = ret;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL);
225*4882a593Smuzhiyun 	if (!interrupt)
226*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
227*4882a593Smuzhiyun 	interrupt->ipa = ipa;
228*4882a593Smuzhiyun 	interrupt->irq = irq;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	/* Start with all IPA interrupts disabled */
231*4882a593Smuzhiyun 	iowrite32(0, ipa->reg_virt + IPA_REG_IRQ_EN_OFFSET);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	ret = request_threaded_irq(irq, ipa_isr, ipa_isr_thread, IRQF_ONESHOT,
234*4882a593Smuzhiyun 				   "ipa", interrupt);
235*4882a593Smuzhiyun 	if (ret) {
236*4882a593Smuzhiyun 		dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret);
237*4882a593Smuzhiyun 		goto err_kfree;
238*4882a593Smuzhiyun 	}
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	ret = enable_irq_wake(irq);
241*4882a593Smuzhiyun 	if (ret) {
242*4882a593Smuzhiyun 		dev_err(dev, "error %d enabling wakeup for \"ipa\" IRQ\n", ret);
243*4882a593Smuzhiyun 		goto err_free_irq;
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	return interrupt;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun err_free_irq:
249*4882a593Smuzhiyun 	free_irq(interrupt->irq, interrupt);
250*4882a593Smuzhiyun err_kfree:
251*4882a593Smuzhiyun 	kfree(interrupt);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	return ERR_PTR(ret);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun /* Tear down the IPA interrupt framework */
ipa_interrupt_teardown(struct ipa_interrupt * interrupt)257*4882a593Smuzhiyun void ipa_interrupt_teardown(struct ipa_interrupt *interrupt)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	struct device *dev = &interrupt->ipa->pdev->dev;
260*4882a593Smuzhiyun 	int ret;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	ret = disable_irq_wake(interrupt->irq);
263*4882a593Smuzhiyun 	if (ret)
264*4882a593Smuzhiyun 		dev_err(dev, "error %d disabling \"ipa\" IRQ wakeup\n", ret);
265*4882a593Smuzhiyun 	free_irq(interrupt->irq, interrupt);
266*4882a593Smuzhiyun 	kfree(interrupt);
267*4882a593Smuzhiyun }
268