1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _MCR20A_H 8*4882a593Smuzhiyun #define _MCR20A_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Direct Accress Register */ 11*4882a593Smuzhiyun #define DAR_IRQ_STS1 0x00 12*4882a593Smuzhiyun #define DAR_IRQ_STS2 0x01 13*4882a593Smuzhiyun #define DAR_IRQ_STS3 0x02 14*4882a593Smuzhiyun #define DAR_PHY_CTRL1 0x03 15*4882a593Smuzhiyun #define DAR_PHY_CTRL2 0x04 16*4882a593Smuzhiyun #define DAR_PHY_CTRL3 0x05 17*4882a593Smuzhiyun #define DAR_RX_FRM_LEN 0x06 18*4882a593Smuzhiyun #define DAR_PHY_CTRL4 0x07 19*4882a593Smuzhiyun #define DAR_SRC_CTRL 0x08 20*4882a593Smuzhiyun #define DAR_SRC_ADDRS_SUM_LSB 0x09 21*4882a593Smuzhiyun #define DAR_SRC_ADDRS_SUM_MSB 0x0A 22*4882a593Smuzhiyun #define DAR_CCA1_ED_FNL 0x0B 23*4882a593Smuzhiyun #define DAR_EVENT_TMR_LSB 0x0C 24*4882a593Smuzhiyun #define DAR_EVENT_TMR_MSB 0x0D 25*4882a593Smuzhiyun #define DAR_EVENT_TMR_USB 0x0E 26*4882a593Smuzhiyun #define DAR_TIMESTAMP_LSB 0x0F 27*4882a593Smuzhiyun #define DAR_TIMESTAMP_MSB 0x10 28*4882a593Smuzhiyun #define DAR_TIMESTAMP_USB 0x11 29*4882a593Smuzhiyun #define DAR_T3CMP_LSB 0x12 30*4882a593Smuzhiyun #define DAR_T3CMP_MSB 0x13 31*4882a593Smuzhiyun #define DAR_T3CMP_USB 0x14 32*4882a593Smuzhiyun #define DAR_T2PRIMECMP_LSB 0x15 33*4882a593Smuzhiyun #define DAR_T2PRIMECMP_MSB 0x16 34*4882a593Smuzhiyun #define DAR_T1CMP_LSB 0x17 35*4882a593Smuzhiyun #define DAR_T1CMP_MSB 0x18 36*4882a593Smuzhiyun #define DAR_T1CMP_USB 0x19 37*4882a593Smuzhiyun #define DAR_T2CMP_LSB 0x1A 38*4882a593Smuzhiyun #define DAR_T2CMP_MSB 0x1B 39*4882a593Smuzhiyun #define DAR_T2CMP_USB 0x1C 40*4882a593Smuzhiyun #define DAR_T4CMP_LSB 0x1D 41*4882a593Smuzhiyun #define DAR_T4CMP_MSB 0x1E 42*4882a593Smuzhiyun #define DAR_T4CMP_USB 0x1F 43*4882a593Smuzhiyun #define DAR_PLL_INT0 0x20 44*4882a593Smuzhiyun #define DAR_PLL_FRAC0_LSB 0x21 45*4882a593Smuzhiyun #define DAR_PLL_FRAC0_MSB 0x22 46*4882a593Smuzhiyun #define DAR_PA_PWR 0x23 47*4882a593Smuzhiyun #define DAR_SEQ_STATE 0x24 48*4882a593Smuzhiyun #define DAR_LQI_VALUE 0x25 49*4882a593Smuzhiyun #define DAR_RSSI_CCA_CONT 0x26 50*4882a593Smuzhiyun /*------------------ 0x27 */ 51*4882a593Smuzhiyun #define DAR_ASM_CTRL1 0x28 52*4882a593Smuzhiyun #define DAR_ASM_CTRL2 0x29 53*4882a593Smuzhiyun #define DAR_ASM_DATA_0 0x2A 54*4882a593Smuzhiyun #define DAR_ASM_DATA_1 0x2B 55*4882a593Smuzhiyun #define DAR_ASM_DATA_2 0x2C 56*4882a593Smuzhiyun #define DAR_ASM_DATA_3 0x2D 57*4882a593Smuzhiyun #define DAR_ASM_DATA_4 0x2E 58*4882a593Smuzhiyun #define DAR_ASM_DATA_5 0x2F 59*4882a593Smuzhiyun #define DAR_ASM_DATA_6 0x30 60*4882a593Smuzhiyun #define DAR_ASM_DATA_7 0x31 61*4882a593Smuzhiyun #define DAR_ASM_DATA_8 0x32 62*4882a593Smuzhiyun #define DAR_ASM_DATA_9 0x33 63*4882a593Smuzhiyun #define DAR_ASM_DATA_A 0x34 64*4882a593Smuzhiyun #define DAR_ASM_DATA_B 0x35 65*4882a593Smuzhiyun #define DAR_ASM_DATA_C 0x36 66*4882a593Smuzhiyun #define DAR_ASM_DATA_D 0x37 67*4882a593Smuzhiyun #define DAR_ASM_DATA_E 0x38 68*4882a593Smuzhiyun #define DAR_ASM_DATA_F 0x39 69*4882a593Smuzhiyun /*----------------------- 0x3A */ 70*4882a593Smuzhiyun #define DAR_OVERWRITE_VER 0x3B 71*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL 0x3C 72*4882a593Smuzhiyun #define DAR_PWR_MODES 0x3D 73*4882a593Smuzhiyun #define IAR_INDEX 0x3E 74*4882a593Smuzhiyun #define IAR_DATA 0x3F 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Indirect Resgister Memory */ 77*4882a593Smuzhiyun #define IAR_PART_ID 0x00 78*4882a593Smuzhiyun #define IAR_XTAL_TRIM 0x01 79*4882a593Smuzhiyun #define IAR_PMC_LP_TRIM 0x02 80*4882a593Smuzhiyun #define IAR_MACPANID0_LSB 0x03 81*4882a593Smuzhiyun #define IAR_MACPANID0_MSB 0x04 82*4882a593Smuzhiyun #define IAR_MACSHORTADDRS0_LSB 0x05 83*4882a593Smuzhiyun #define IAR_MACSHORTADDRS0_MSB 0x06 84*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_0 0x07 85*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_8 0x08 86*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_16 0x09 87*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_24 0x0A 88*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_32 0x0B 89*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_40 0x0C 90*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_48 0x0D 91*4882a593Smuzhiyun #define IAR_MACLONGADDRS0_56 0x0E 92*4882a593Smuzhiyun #define IAR_RX_FRAME_FILTER 0x0F 93*4882a593Smuzhiyun #define IAR_PLL_INT1 0x10 94*4882a593Smuzhiyun #define IAR_PLL_FRAC1_LSB 0x11 95*4882a593Smuzhiyun #define IAR_PLL_FRAC1_MSB 0x12 96*4882a593Smuzhiyun #define IAR_MACPANID1_LSB 0x13 97*4882a593Smuzhiyun #define IAR_MACPANID1_MSB 0x14 98*4882a593Smuzhiyun #define IAR_MACSHORTADDRS1_LSB 0x15 99*4882a593Smuzhiyun #define IAR_MACSHORTADDRS1_MSB 0x16 100*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_0 0x17 101*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_8 0x18 102*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_16 0x19 103*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_24 0x1A 104*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_32 0x1B 105*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_40 0x1C 106*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_48 0x1D 107*4882a593Smuzhiyun #define IAR_MACLONGADDRS1_56 0x1E 108*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL 0x1F 109*4882a593Smuzhiyun #define IAR_DUAL_PAN_DWELL 0x20 110*4882a593Smuzhiyun #define IAR_DUAL_PAN_STS 0x21 111*4882a593Smuzhiyun #define IAR_CCA1_THRESH 0x22 112*4882a593Smuzhiyun #define IAR_CCA1_ED_OFFSET_COMP 0x23 113*4882a593Smuzhiyun #define IAR_LQI_OFFSET_COMP 0x24 114*4882a593Smuzhiyun #define IAR_CCA_CTRL 0x25 115*4882a593Smuzhiyun #define IAR_CCA2_CORR_PEAKS 0x26 116*4882a593Smuzhiyun #define IAR_CCA2_CORR_THRESH 0x27 117*4882a593Smuzhiyun #define IAR_TMR_PRESCALE 0x28 118*4882a593Smuzhiyun /*-------------------- 0x29 */ 119*4882a593Smuzhiyun #define IAR_GPIO_DATA 0x2A 120*4882a593Smuzhiyun #define IAR_GPIO_DIR 0x2B 121*4882a593Smuzhiyun #define IAR_GPIO_PUL_EN 0x2C 122*4882a593Smuzhiyun #define IAR_GPIO_PUL_SEL 0x2D 123*4882a593Smuzhiyun #define IAR_GPIO_DS 0x2E 124*4882a593Smuzhiyun /*------------------ 0x2F */ 125*4882a593Smuzhiyun #define IAR_ANT_PAD_CTRL 0x30 126*4882a593Smuzhiyun #define IAR_MISC_PAD_CTRL 0x31 127*4882a593Smuzhiyun #define IAR_BSM_CTRL 0x32 128*4882a593Smuzhiyun /*------------------- 0x33 */ 129*4882a593Smuzhiyun #define IAR_RNG 0x34 130*4882a593Smuzhiyun #define IAR_RX_BYTE_COUNT 0x35 131*4882a593Smuzhiyun #define IAR_RX_WTR_MARK 0x36 132*4882a593Smuzhiyun #define IAR_SOFT_RESET 0x37 133*4882a593Smuzhiyun #define IAR_TXDELAY 0x38 134*4882a593Smuzhiyun #define IAR_ACKDELAY 0x39 135*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL 0x3A 136*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS 0x3B 137*4882a593Smuzhiyun #define IAR_SEQ_T_STS 0x3C 138*4882a593Smuzhiyun #define IAR_ABORT_STS 0x3D 139*4882a593Smuzhiyun #define IAR_CCCA_BUSY_CNT 0x3E 140*4882a593Smuzhiyun #define IAR_SRC_ADDR_CHECKSUM1 0x3F 141*4882a593Smuzhiyun #define IAR_SRC_ADDR_CHECKSUM2 0x40 142*4882a593Smuzhiyun #define IAR_SRC_TBL_VALID1 0x41 143*4882a593Smuzhiyun #define IAR_SRC_TBL_VALID2 0x42 144*4882a593Smuzhiyun #define IAR_FILTERFAIL_CODE1 0x43 145*4882a593Smuzhiyun #define IAR_FILTERFAIL_CODE2 0x44 146*4882a593Smuzhiyun #define IAR_SLOT_PRELOAD 0x45 147*4882a593Smuzhiyun /*-------------------- 0x46 */ 148*4882a593Smuzhiyun #define IAR_CORR_VT 0x47 149*4882a593Smuzhiyun #define IAR_SYNC_CTRL 0x48 150*4882a593Smuzhiyun #define IAR_PN_LSB_0 0x49 151*4882a593Smuzhiyun #define IAR_PN_LSB_1 0x4A 152*4882a593Smuzhiyun #define IAR_PN_MSB_0 0x4B 153*4882a593Smuzhiyun #define IAR_PN_MSB_1 0x4C 154*4882a593Smuzhiyun #define IAR_CORR_NVAL 0x4D 155*4882a593Smuzhiyun #define IAR_TX_MODE_CTRL 0x4E 156*4882a593Smuzhiyun #define IAR_SNF_THR 0x4F 157*4882a593Smuzhiyun #define IAR_FAD_THR 0x50 158*4882a593Smuzhiyun #define IAR_ANT_AGC_CTRL 0x51 159*4882a593Smuzhiyun #define IAR_AGC_THR1 0x52 160*4882a593Smuzhiyun #define IAR_AGC_THR2 0x53 161*4882a593Smuzhiyun #define IAR_AGC_HYS 0x54 162*4882a593Smuzhiyun #define IAR_AFC 0x55 163*4882a593Smuzhiyun /*------------------- 0x56 */ 164*4882a593Smuzhiyun /*------------------- 0x57 */ 165*4882a593Smuzhiyun #define IAR_PHY_STS 0x58 166*4882a593Smuzhiyun #define IAR_RX_MAX_CORR 0x59 167*4882a593Smuzhiyun #define IAR_RX_MAX_PREAMBLE 0x5A 168*4882a593Smuzhiyun #define IAR_RSSI 0x5B 169*4882a593Smuzhiyun /*------------------- 0x5C */ 170*4882a593Smuzhiyun /*------------------- 0x5D */ 171*4882a593Smuzhiyun #define IAR_PLL_DIG_CTRL 0x5E 172*4882a593Smuzhiyun #define IAR_VCO_CAL 0x5F 173*4882a593Smuzhiyun #define IAR_VCO_BEST_DIFF 0x60 174*4882a593Smuzhiyun #define IAR_VCO_BIAS 0x61 175*4882a593Smuzhiyun #define IAR_KMOD_CTRL 0x62 176*4882a593Smuzhiyun #define IAR_KMOD_CAL 0x63 177*4882a593Smuzhiyun #define IAR_PA_CAL 0x64 178*4882a593Smuzhiyun #define IAR_PA_PWRCAL 0x65 179*4882a593Smuzhiyun #define IAR_ATT_RSSI1 0x66 180*4882a593Smuzhiyun #define IAR_ATT_RSSI2 0x67 181*4882a593Smuzhiyun #define IAR_RSSI_OFFSET 0x68 182*4882a593Smuzhiyun #define IAR_RSSI_SLOPE 0x69 183*4882a593Smuzhiyun #define IAR_RSSI_CAL1 0x6A 184*4882a593Smuzhiyun #define IAR_RSSI_CAL2 0x6B 185*4882a593Smuzhiyun /*------------------- 0x6C */ 186*4882a593Smuzhiyun /*------------------- 0x6D */ 187*4882a593Smuzhiyun #define IAR_XTAL_CTRL 0x6E 188*4882a593Smuzhiyun #define IAR_XTAL_COMP_MIN 0x6F 189*4882a593Smuzhiyun #define IAR_XTAL_COMP_MAX 0x70 190*4882a593Smuzhiyun #define IAR_XTAL_GM 0x71 191*4882a593Smuzhiyun /*------------------- 0x72 */ 192*4882a593Smuzhiyun /*------------------- 0x73 */ 193*4882a593Smuzhiyun #define IAR_LNA_TUNE 0x74 194*4882a593Smuzhiyun #define IAR_LNA_AGCGAIN 0x75 195*4882a593Smuzhiyun /*------------------- 0x76 */ 196*4882a593Smuzhiyun /*------------------- 0x77 */ 197*4882a593Smuzhiyun #define IAR_CHF_PMA_GAIN 0x78 198*4882a593Smuzhiyun #define IAR_CHF_IBUF 0x79 199*4882a593Smuzhiyun #define IAR_CHF_QBUF 0x7A 200*4882a593Smuzhiyun #define IAR_CHF_IRIN 0x7B 201*4882a593Smuzhiyun #define IAR_CHF_QRIN 0x7C 202*4882a593Smuzhiyun #define IAR_CHF_IL 0x7D 203*4882a593Smuzhiyun #define IAR_CHF_QL 0x7E 204*4882a593Smuzhiyun #define IAR_CHF_CC1 0x7F 205*4882a593Smuzhiyun #define IAR_CHF_CCL 0x80 206*4882a593Smuzhiyun #define IAR_CHF_CC2 0x81 207*4882a593Smuzhiyun #define IAR_CHF_IROUT 0x82 208*4882a593Smuzhiyun #define IAR_CHF_QROUT 0x83 209*4882a593Smuzhiyun /*------------------- 0x84 */ 210*4882a593Smuzhiyun /*------------------- 0x85 */ 211*4882a593Smuzhiyun #define IAR_RSSI_CTRL 0x86 212*4882a593Smuzhiyun /*------------------- 0x87 */ 213*4882a593Smuzhiyun /*------------------- 0x88 */ 214*4882a593Smuzhiyun #define IAR_PA_BIAS 0x89 215*4882a593Smuzhiyun #define IAR_PA_TUNING 0x8A 216*4882a593Smuzhiyun /*------------------- 0x8B */ 217*4882a593Smuzhiyun /*------------------- 0x8C */ 218*4882a593Smuzhiyun #define IAR_PMC_HP_TRIM 0x8D 219*4882a593Smuzhiyun #define IAR_VREGA_TRIM 0x8E 220*4882a593Smuzhiyun /*------------------- 0x8F */ 221*4882a593Smuzhiyun /*------------------- 0x90 */ 222*4882a593Smuzhiyun #define IAR_VCO_CTRL1 0x91 223*4882a593Smuzhiyun #define IAR_VCO_CTRL2 0x92 224*4882a593Smuzhiyun /*------------------- 0x93 */ 225*4882a593Smuzhiyun /*------------------- 0x94 */ 226*4882a593Smuzhiyun #define IAR_ANA_SPARE_OUT1 0x95 227*4882a593Smuzhiyun #define IAR_ANA_SPARE_OUT2 0x96 228*4882a593Smuzhiyun #define IAR_ANA_SPARE_IN 0x97 229*4882a593Smuzhiyun #define IAR_MISCELLANEOUS 0x98 230*4882a593Smuzhiyun /*------------------- 0x99 */ 231*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD0 0x9A 232*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD1 0x9B 233*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD2 0x9C 234*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD3 0x9D 235*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD4 0x9E 236*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD5 0x9F 237*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD6 0xA0 238*4882a593Smuzhiyun #define IAR_SEQ_MGR_OVRD7 0xA1 239*4882a593Smuzhiyun /*------------------- 0xA2 */ 240*4882a593Smuzhiyun #define IAR_TESTMODE_CTRL 0xA3 241*4882a593Smuzhiyun #define IAR_DTM_CTRL1 0xA4 242*4882a593Smuzhiyun #define IAR_DTM_CTRL2 0xA5 243*4882a593Smuzhiyun #define IAR_ATM_CTRL1 0xA6 244*4882a593Smuzhiyun #define IAR_ATM_CTRL2 0xA7 245*4882a593Smuzhiyun #define IAR_ATM_CTRL3 0xA8 246*4882a593Smuzhiyun /*------------------- 0xA9 */ 247*4882a593Smuzhiyun #define IAR_LIM_FE_TEST_CTRL 0xAA 248*4882a593Smuzhiyun #define IAR_CHF_TEST_CTRL 0xAB 249*4882a593Smuzhiyun #define IAR_VCO_TEST_CTRL 0xAC 250*4882a593Smuzhiyun #define IAR_PLL_TEST_CTRL 0xAD 251*4882a593Smuzhiyun #define IAR_PA_TEST_CTRL 0xAE 252*4882a593Smuzhiyun #define IAR_PMC_TEST_CTRL 0xAF 253*4882a593Smuzhiyun #define IAR_SCAN_DTM_PROTECT_1 0xFE 254*4882a593Smuzhiyun #define IAR_SCAN_DTM_PROTECT_0 0xFF 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun /* IRQSTS1 bits */ 257*4882a593Smuzhiyun #define DAR_IRQSTS1_RX_FRM_PEND BIT(7) 258*4882a593Smuzhiyun #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6) 259*4882a593Smuzhiyun #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5) 260*4882a593Smuzhiyun #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4) 261*4882a593Smuzhiyun #define DAR_IRQSTS1_CCAIRQ BIT(3) 262*4882a593Smuzhiyun #define DAR_IRQSTS1_RXIRQ BIT(2) 263*4882a593Smuzhiyun #define DAR_IRQSTS1_TXIRQ BIT(1) 264*4882a593Smuzhiyun #define DAR_IRQSTS1_SEQIRQ BIT(0) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* IRQSTS2 bits */ 267*4882a593Smuzhiyun #define DAR_IRQSTS2_CRCVALID BIT(7) 268*4882a593Smuzhiyun #define DAR_IRQSTS2_CCA BIT(6) 269*4882a593Smuzhiyun #define DAR_IRQSTS2_SRCADDR BIT(5) 270*4882a593Smuzhiyun #define DAR_IRQSTS2_PI BIT(4) 271*4882a593Smuzhiyun #define DAR_IRQSTS2_TMRSTATUS BIT(3) 272*4882a593Smuzhiyun #define DAR_IRQSTS2_ASM_IRQ BIT(2) 273*4882a593Smuzhiyun #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1) 274*4882a593Smuzhiyun #define DAR_IRQSTS2_WAKE_IRQ BIT(0) 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun /* IRQSTS3 bits */ 277*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR4MSK BIT(7) 278*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR3MSK BIT(6) 279*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR2MSK BIT(5) 280*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR1MSK BIT(4) 281*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR4IRQ BIT(3) 282*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR3IRQ BIT(2) 283*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR2IRQ BIT(1) 284*4882a593Smuzhiyun #define DAR_IRQSTS3_TMR1IRQ BIT(0) 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /* PHY_CTRL1 bits */ 287*4882a593Smuzhiyun #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7) 288*4882a593Smuzhiyun #define DAR_PHY_CTRL1_SLOTTED BIT(6) 289*4882a593Smuzhiyun #define DAR_PHY_CTRL1_CCABFRTX BIT(5) 290*4882a593Smuzhiyun #define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5 291*4882a593Smuzhiyun #define DAR_PHY_CTRL1_RXACKRQD BIT(4) 292*4882a593Smuzhiyun #define DAR_PHY_CTRL1_AUTOACK BIT(3) 293*4882a593Smuzhiyun #define DAR_PHY_CTRL1_XCVSEQ_MASK 0x07 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* PHY_CTRL2 bits */ 296*4882a593Smuzhiyun #define DAR_PHY_CTRL2_CRC_MSK BIT(7) 297*4882a593Smuzhiyun #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6) 298*4882a593Smuzhiyun #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5) 299*4882a593Smuzhiyun #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4) 300*4882a593Smuzhiyun #define DAR_PHY_CTRL2_CCAMSK BIT(3) 301*4882a593Smuzhiyun #define DAR_PHY_CTRL2_RXMSK BIT(2) 302*4882a593Smuzhiyun #define DAR_PHY_CTRL2_TXMSK BIT(1) 303*4882a593Smuzhiyun #define DAR_PHY_CTRL2_SEQMSK BIT(0) 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun /* PHY_CTRL3 bits */ 306*4882a593Smuzhiyun #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7) 307*4882a593Smuzhiyun #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6) 308*4882a593Smuzhiyun #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5) 309*4882a593Smuzhiyun #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4) 310*4882a593Smuzhiyun #define DAR_PHY_CTRL3_ASM_MSK BIT(2) 311*4882a593Smuzhiyun #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1) 312*4882a593Smuzhiyun #define DAR_PHY_CTRL3_WAKE_MSK BIT(0) 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* RX_FRM_LEN bits */ 315*4882a593Smuzhiyun #define DAR_RX_FRAME_LENGTH_MASK (0x7F) 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* PHY_CTRL4 bits */ 318*4882a593Smuzhiyun #define DAR_PHY_CTRL4_TRCV_MSK BIT(7) 319*4882a593Smuzhiyun #define DAR_PHY_CTRL4_TC3TMOUT BIT(6) 320*4882a593Smuzhiyun #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5) 321*4882a593Smuzhiyun #define DAR_PHY_CTRL4_CCATYPE (3) 322*4882a593Smuzhiyun #define DAR_PHY_CTRL4_CCATYPE_SHIFT (3) 323*4882a593Smuzhiyun #define DAR_PHY_CTRL4_CCATYPE_MASK (0x18) 324*4882a593Smuzhiyun #define DAR_PHY_CTRL4_TMRLOAD BIT(2) 325*4882a593Smuzhiyun #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1) 326*4882a593Smuzhiyun #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0) 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* SRC_CTRL bits */ 329*4882a593Smuzhiyun #define DAR_SRC_CTRL_INDEX (0x0F) 330*4882a593Smuzhiyun #define DAR_SRC_CTRL_INDEX_SHIFT (4) 331*4882a593Smuzhiyun #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3) 332*4882a593Smuzhiyun #define DAR_SRC_CTRL_SRCADDR_EN BIT(2) 333*4882a593Smuzhiyun #define DAR_SRC_CTRL_INDEX_EN BIT(1) 334*4882a593Smuzhiyun #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0) 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun /* DAR_ASM_CTRL1 bits */ 337*4882a593Smuzhiyun #define DAR_ASM_CTRL1_CLEAR BIT(7) 338*4882a593Smuzhiyun #define DAR_ASM_CTRL1_START BIT(6) 339*4882a593Smuzhiyun #define DAR_ASM_CTRL1_SELFTST BIT(5) 340*4882a593Smuzhiyun #define DAR_ASM_CTRL1_CTR BIT(4) 341*4882a593Smuzhiyun #define DAR_ASM_CTRL1_CBC BIT(3) 342*4882a593Smuzhiyun #define DAR_ASM_CTRL1_AES BIT(2) 343*4882a593Smuzhiyun #define DAR_ASM_CTRL1_LOAD_MAC BIT(1) 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun /* DAR_ASM_CTRL2 bits */ 346*4882a593Smuzhiyun #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL (7) 347*4882a593Smuzhiyun #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5) 348*4882a593Smuzhiyun #define DAR_ASM_CTRL2_TSTPAS BIT(1) 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* DAR_CLK_OUT_CTRL bits */ 351*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL_EXTEND BIT(7) 352*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL_HIZ BIT(6) 353*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL_SR BIT(5) 354*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL_DS BIT(4) 355*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL_EN BIT(3) 356*4882a593Smuzhiyun #define DAR_CLK_OUT_CTRL_DIV (7) 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun /* DAR_PWR_MODES bits */ 359*4882a593Smuzhiyun #define DAR_PWR_MODES_XTAL_READY BIT(5) 360*4882a593Smuzhiyun #define DAR_PWR_MODES_XTALEN BIT(4) 361*4882a593Smuzhiyun #define DAR_PWR_MODES_ASM_CLK_EN BIT(3) 362*4882a593Smuzhiyun #define DAR_PWR_MODES_AUTODOZE BIT(1) 363*4882a593Smuzhiyun #define DAR_PWR_MODES_PMC_MODE BIT(0) 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /* RX_FRAME_FILTER bits */ 366*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_FRM_VER (0xC0) 367*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_FRM_VER_SHIFT (6) 368*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5) 369*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_NS_FT BIT(4) 370*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_CMD_FT BIT(3) 371*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_ACK_FT BIT(2) 372*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_DATA_FT BIT(1) 373*4882a593Smuzhiyun #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0) 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun /* DUAL_PAN_CTRL bits */ 376*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0) 377*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4) 378*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3) 379*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2) 380*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1) 381*4882a593Smuzhiyun #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0) 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun /* DUAL_PAN_STS bits */ 384*4882a593Smuzhiyun #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7) 385*4882a593Smuzhiyun #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6) 386*4882a593Smuzhiyun #define IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F) 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* CCA_CTRL bits */ 389*4882a593Smuzhiyun #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6) 390*4882a593Smuzhiyun #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5) 391*4882a593Smuzhiyun #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4) 392*4882a593Smuzhiyun #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3) 393*4882a593Smuzhiyun #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2) 394*4882a593Smuzhiyun #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1) 395*4882a593Smuzhiyun #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0) 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun /* ANT_PAD_CTRL bits */ 398*4882a593Smuzhiyun #define IAR_ANT_PAD_CTRL_ANTX_POL (0x0F) 399*4882a593Smuzhiyun #define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4) 400*4882a593Smuzhiyun #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3) 401*4882a593Smuzhiyun #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2) 402*4882a593Smuzhiyun #define IAR_ANT_PAD_CTRL_ANTX_EN (3) 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun /* MISC_PAD_CTRL bits */ 405*4882a593Smuzhiyun #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3) 406*4882a593Smuzhiyun #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2) 407*4882a593Smuzhiyun #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1) 408*4882a593Smuzhiyun #define IAR_MISC_PAD_CTRL_ANTX_CURR (1) 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun /* ANT_AGC_CTRL bits */ 411*4882a593Smuzhiyun #define IAR_ANT_AGC_CTRL_FAD_EN_SHIFT (0) 412*4882a593Smuzhiyun #define IAR_ANT_AGC_CTRL_FAD_EN_MASK (1) 413*4882a593Smuzhiyun #define IAR_ANT_AGC_CTRL_ANTX_SHIFT (1) 414*4882a593Smuzhiyun #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT) 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun /* BSM_CTRL bits */ 417*4882a593Smuzhiyun #define BSM_CTRL_BSM_EN (1) 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun /* SOFT_RESET bits */ 420*4882a593Smuzhiyun #define IAR_SOFT_RESET_SOG_RST BIT(7) 421*4882a593Smuzhiyun #define IAR_SOFT_RESET_REGS_RST BIT(4) 422*4882a593Smuzhiyun #define IAR_SOFT_RESET_PLL_RST BIT(3) 423*4882a593Smuzhiyun #define IAR_SOFT_RESET_TX_RST BIT(2) 424*4882a593Smuzhiyun #define IAR_SOFT_RESET_RX_RST BIT(1) 425*4882a593Smuzhiyun #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0) 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun /* SEQ_MGR_CTRL bits */ 428*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL (3) 429*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6) 430*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5) 431*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4) 432*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3) 433*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2) 434*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1) 435*4882a593Smuzhiyun #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0) 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun /* SEQ_MGR_STS bits */ 438*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7) 439*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS_RX_MODE BIT(6) 440*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5) 441*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4) 442*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3) 443*4882a593Smuzhiyun #define IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL (7) 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun /* ABORT_STS bits */ 446*4882a593Smuzhiyun #define IAR_ABORT_STS_PLL_ABORTED BIT(2) 447*4882a593Smuzhiyun #define IAR_ABORT_STS_TC3_ABORTED BIT(1) 448*4882a593Smuzhiyun #define IAR_ABORT_STS_SW_ABORTED BIT(0) 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun /* IAR_FILTERFAIL_CODE2 bits */ 451*4882a593Smuzhiyun #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7) 452*4882a593Smuzhiyun #define IAR_FILTERFAIL_CODE2_9_8 (3) 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun /* PHY_STS bits */ 455*4882a593Smuzhiyun #define IAR_PHY_STS_PLL_UNLOCK BIT(7) 456*4882a593Smuzhiyun #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6) 457*4882a593Smuzhiyun #define IAR_PHY_STS_PLL_LOCK BIT(5) 458*4882a593Smuzhiyun #define IAR_PHY_STS_CRCVALID BIT(3) 459*4882a593Smuzhiyun #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2) 460*4882a593Smuzhiyun #define IAR_PHY_STS_SFD_DET BIT(1) 461*4882a593Smuzhiyun #define IAR_PHY_STS_PREAMBLE_DET BIT(0) 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun /* TESTMODE_CTRL bits */ 464*4882a593Smuzhiyun #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4) 465*4882a593Smuzhiyun #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3) 466*4882a593Smuzhiyun #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2) 467*4882a593Smuzhiyun #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1) 468*4882a593Smuzhiyun #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0) 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun /* DTM_CTRL1 bits */ 471*4882a593Smuzhiyun #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7) 472*4882a593Smuzhiyun #define IAR_DTM_CTRL1_DTM_EN BIT(6) 473*4882a593Smuzhiyun #define IAR_DTM_CTRL1_PAGE5 BIT(5) 474*4882a593Smuzhiyun #define IAR_DTM_CTRL1_PAGE4 BIT(4) 475*4882a593Smuzhiyun #define IAR_DTM_CTRL1_PAGE3 BIT(3) 476*4882a593Smuzhiyun #define IAR_DTM_CTRL1_PAGE2 BIT(2) 477*4882a593Smuzhiyun #define IAR_DTM_CTRL1_PAGE1 BIT(1) 478*4882a593Smuzhiyun #define IAR_DTM_CTRL1_PAGE0 BIT(0) 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun /* TX_MODE_CTRL */ 481*4882a593Smuzhiyun #define IAR_TX_MODE_CTRL_TX_INV BIT(4) 482*4882a593Smuzhiyun #define IAR_TX_MODE_CTRL_BT_EN BIT(3) 483*4882a593Smuzhiyun #define IAR_TX_MODE_CTRL_DTS2 BIT(2) 484*4882a593Smuzhiyun #define IAR_TX_MODE_CTRL_DTS1 BIT(1) 485*4882a593Smuzhiyun #define IAR_TX_MODE_CTRL_DTS0 BIT(0) 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun #define TX_MODE_CTRL_DTS_MASK (7) 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun #endif /* _MCR20A_H */ 490