1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * http://www.cascoda.com/products/ca-821x/
3*4882a593Smuzhiyun * Copyright (c) 2016, Cascoda, Ltd.
4*4882a593Smuzhiyun * All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This code is dual-licensed under both GPLv2 and 3-clause BSD. What follows is
7*4882a593Smuzhiyun * the license notice for both respectively.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *******************************************************************************
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
12*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License
13*4882a593Smuzhiyun * as published by the Free Software Foundation; either version 2
14*4882a593Smuzhiyun * of the License, or (at your option) any later version.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful,
17*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of
18*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19*4882a593Smuzhiyun * GNU General Public License for more details.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun *******************************************************************************
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
24*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met:
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright notice,
27*4882a593Smuzhiyun * this list of conditions and the following disclaimer.
28*4882a593Smuzhiyun *
29*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce the above copyright notice,
30*4882a593Smuzhiyun * this list of conditions and the following disclaimer in the documentation
31*4882a593Smuzhiyun * and/or other materials provided with the distribution.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * 3. Neither the name of the copyright holder nor the names of its contributors
34*4882a593Smuzhiyun * may be used to endorse or promote products derived from this software without
35*4882a593Smuzhiyun * specific prior written permission.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
38*4882a593Smuzhiyun * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39*4882a593Smuzhiyun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40*4882a593Smuzhiyun * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
41*4882a593Smuzhiyun * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
42*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
43*4882a593Smuzhiyun * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
44*4882a593Smuzhiyun * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
45*4882a593Smuzhiyun * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
46*4882a593Smuzhiyun * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
47*4882a593Smuzhiyun * POSSIBILITY OF SUCH DAMAGE.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #include <linux/cdev.h>
51*4882a593Smuzhiyun #include <linux/clk-provider.h>
52*4882a593Smuzhiyun #include <linux/debugfs.h>
53*4882a593Smuzhiyun #include <linux/delay.h>
54*4882a593Smuzhiyun #include <linux/gpio.h>
55*4882a593Smuzhiyun #include <linux/ieee802154.h>
56*4882a593Smuzhiyun #include <linux/io.h>
57*4882a593Smuzhiyun #include <linux/kfifo.h>
58*4882a593Smuzhiyun #include <linux/of.h>
59*4882a593Smuzhiyun #include <linux/of_device.h>
60*4882a593Smuzhiyun #include <linux/of_gpio.h>
61*4882a593Smuzhiyun #include <linux/module.h>
62*4882a593Smuzhiyun #include <linux/mutex.h>
63*4882a593Smuzhiyun #include <linux/poll.h>
64*4882a593Smuzhiyun #include <linux/skbuff.h>
65*4882a593Smuzhiyun #include <linux/slab.h>
66*4882a593Smuzhiyun #include <linux/spi/spi.h>
67*4882a593Smuzhiyun #include <linux/spinlock.h>
68*4882a593Smuzhiyun #include <linux/string.h>
69*4882a593Smuzhiyun #include <linux/workqueue.h>
70*4882a593Smuzhiyun #include <linux/interrupt.h>
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #include <net/ieee802154_netdev.h>
73*4882a593Smuzhiyun #include <net/mac802154.h>
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define DRIVER_NAME "ca8210"
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* external clock frequencies */
78*4882a593Smuzhiyun #define ONE_MHZ 1000000
79*4882a593Smuzhiyun #define TWO_MHZ (2 * ONE_MHZ)
80*4882a593Smuzhiyun #define FOUR_MHZ (4 * ONE_MHZ)
81*4882a593Smuzhiyun #define EIGHT_MHZ (8 * ONE_MHZ)
82*4882a593Smuzhiyun #define SIXTEEN_MHZ (16 * ONE_MHZ)
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* spi constants */
85*4882a593Smuzhiyun #define CA8210_SPI_BUF_SIZE 256
86*4882a593Smuzhiyun #define CA8210_SYNC_TIMEOUT 1000 /* Timeout for synchronous commands [ms] */
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* test interface constants */
89*4882a593Smuzhiyun #define CA8210_TEST_INT_FILE_NAME "ca8210_test"
90*4882a593Smuzhiyun #define CA8210_TEST_INT_FIFO_SIZE 256
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* MAC status enumerations */
93*4882a593Smuzhiyun #define MAC_SUCCESS (0x00)
94*4882a593Smuzhiyun #define MAC_ERROR (0x01)
95*4882a593Smuzhiyun #define MAC_CANCELLED (0x02)
96*4882a593Smuzhiyun #define MAC_READY_FOR_POLL (0x03)
97*4882a593Smuzhiyun #define MAC_COUNTER_ERROR (0xDB)
98*4882a593Smuzhiyun #define MAC_IMPROPER_KEY_TYPE (0xDC)
99*4882a593Smuzhiyun #define MAC_IMPROPER_SECURITY_LEVEL (0xDD)
100*4882a593Smuzhiyun #define MAC_UNSUPPORTED_LEGACY (0xDE)
101*4882a593Smuzhiyun #define MAC_UNSUPPORTED_SECURITY (0xDF)
102*4882a593Smuzhiyun #define MAC_BEACON_LOST (0xE0)
103*4882a593Smuzhiyun #define MAC_CHANNEL_ACCESS_FAILURE (0xE1)
104*4882a593Smuzhiyun #define MAC_DENIED (0xE2)
105*4882a593Smuzhiyun #define MAC_DISABLE_TRX_FAILURE (0xE3)
106*4882a593Smuzhiyun #define MAC_SECURITY_ERROR (0xE4)
107*4882a593Smuzhiyun #define MAC_FRAME_TOO_LONG (0xE5)
108*4882a593Smuzhiyun #define MAC_INVALID_GTS (0xE6)
109*4882a593Smuzhiyun #define MAC_INVALID_HANDLE (0xE7)
110*4882a593Smuzhiyun #define MAC_INVALID_PARAMETER (0xE8)
111*4882a593Smuzhiyun #define MAC_NO_ACK (0xE9)
112*4882a593Smuzhiyun #define MAC_NO_BEACON (0xEA)
113*4882a593Smuzhiyun #define MAC_NO_DATA (0xEB)
114*4882a593Smuzhiyun #define MAC_NO_SHORT_ADDRESS (0xEC)
115*4882a593Smuzhiyun #define MAC_OUT_OF_CAP (0xED)
116*4882a593Smuzhiyun #define MAC_PAN_ID_CONFLICT (0xEE)
117*4882a593Smuzhiyun #define MAC_REALIGNMENT (0xEF)
118*4882a593Smuzhiyun #define MAC_TRANSACTION_EXPIRED (0xF0)
119*4882a593Smuzhiyun #define MAC_TRANSACTION_OVERFLOW (0xF1)
120*4882a593Smuzhiyun #define MAC_TX_ACTIVE (0xF2)
121*4882a593Smuzhiyun #define MAC_UNAVAILABLE_KEY (0xF3)
122*4882a593Smuzhiyun #define MAC_UNSUPPORTED_ATTRIBUTE (0xF4)
123*4882a593Smuzhiyun #define MAC_INVALID_ADDRESS (0xF5)
124*4882a593Smuzhiyun #define MAC_ON_TIME_TOO_LONG (0xF6)
125*4882a593Smuzhiyun #define MAC_PAST_TIME (0xF7)
126*4882a593Smuzhiyun #define MAC_TRACKING_OFF (0xF8)
127*4882a593Smuzhiyun #define MAC_INVALID_INDEX (0xF9)
128*4882a593Smuzhiyun #define MAC_LIMIT_REACHED (0xFA)
129*4882a593Smuzhiyun #define MAC_READ_ONLY (0xFB)
130*4882a593Smuzhiyun #define MAC_SCAN_IN_PROGRESS (0xFC)
131*4882a593Smuzhiyun #define MAC_SUPERFRAME_OVERLAP (0xFD)
132*4882a593Smuzhiyun #define MAC_SYSTEM_ERROR (0xFF)
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* HWME attribute IDs */
135*4882a593Smuzhiyun #define HWME_EDTHRESHOLD (0x04)
136*4882a593Smuzhiyun #define HWME_EDVALUE (0x06)
137*4882a593Smuzhiyun #define HWME_SYSCLKOUT (0x0F)
138*4882a593Smuzhiyun #define HWME_LQILIMIT (0x11)
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* TDME attribute IDs */
141*4882a593Smuzhiyun #define TDME_CHANNEL (0x00)
142*4882a593Smuzhiyun #define TDME_ATM_CONFIG (0x06)
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #define MAX_HWME_ATTRIBUTE_SIZE 16
145*4882a593Smuzhiyun #define MAX_TDME_ATTRIBUTE_SIZE 2
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* PHY/MAC PIB Attribute Enumerations */
148*4882a593Smuzhiyun #define PHY_CURRENT_CHANNEL (0x00)
149*4882a593Smuzhiyun #define PHY_TRANSMIT_POWER (0x02)
150*4882a593Smuzhiyun #define PHY_CCA_MODE (0x03)
151*4882a593Smuzhiyun #define MAC_ASSOCIATION_PERMIT (0x41)
152*4882a593Smuzhiyun #define MAC_AUTO_REQUEST (0x42)
153*4882a593Smuzhiyun #define MAC_BATT_LIFE_EXT (0x43)
154*4882a593Smuzhiyun #define MAC_BATT_LIFE_EXT_PERIODS (0x44)
155*4882a593Smuzhiyun #define MAC_BEACON_PAYLOAD (0x45)
156*4882a593Smuzhiyun #define MAC_BEACON_PAYLOAD_LENGTH (0x46)
157*4882a593Smuzhiyun #define MAC_BEACON_ORDER (0x47)
158*4882a593Smuzhiyun #define MAC_GTS_PERMIT (0x4d)
159*4882a593Smuzhiyun #define MAC_MAX_CSMA_BACKOFFS (0x4e)
160*4882a593Smuzhiyun #define MAC_MIN_BE (0x4f)
161*4882a593Smuzhiyun #define MAC_PAN_ID (0x50)
162*4882a593Smuzhiyun #define MAC_PROMISCUOUS_MODE (0x51)
163*4882a593Smuzhiyun #define MAC_RX_ON_WHEN_IDLE (0x52)
164*4882a593Smuzhiyun #define MAC_SHORT_ADDRESS (0x53)
165*4882a593Smuzhiyun #define MAC_SUPERFRAME_ORDER (0x54)
166*4882a593Smuzhiyun #define MAC_ASSOCIATED_PAN_COORD (0x56)
167*4882a593Smuzhiyun #define MAC_MAX_BE (0x57)
168*4882a593Smuzhiyun #define MAC_MAX_FRAME_RETRIES (0x59)
169*4882a593Smuzhiyun #define MAC_RESPONSE_WAIT_TIME (0x5A)
170*4882a593Smuzhiyun #define MAC_SECURITY_ENABLED (0x5D)
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun #define MAC_AUTO_REQUEST_SECURITY_LEVEL (0x78)
173*4882a593Smuzhiyun #define MAC_AUTO_REQUEST_KEY_ID_MODE (0x79)
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun #define NS_IEEE_ADDRESS (0xFF) /* Non-standard IEEE address */
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* MAC Address Mode Definitions */
178*4882a593Smuzhiyun #define MAC_MODE_NO_ADDR (0x00)
179*4882a593Smuzhiyun #define MAC_MODE_SHORT_ADDR (0x02)
180*4882a593Smuzhiyun #define MAC_MODE_LONG_ADDR (0x03)
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* MAC constants */
183*4882a593Smuzhiyun #define MAX_BEACON_OVERHEAD (75)
184*4882a593Smuzhiyun #define MAX_BEACON_PAYLOAD_LENGTH (IEEE802154_MTU - MAX_BEACON_OVERHEAD)
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun #define MAX_ATTRIBUTE_SIZE (122)
187*4882a593Smuzhiyun #define MAX_DATA_SIZE (114)
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun #define CA8210_VALID_CHANNELS (0x07FFF800)
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* MAC workarounds for V1.1 and MPW silicon (V0.x) */
192*4882a593Smuzhiyun #define CA8210_MAC_WORKAROUNDS (0)
193*4882a593Smuzhiyun #define CA8210_MAC_MPW (0)
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* memory manipulation macros */
196*4882a593Smuzhiyun #define LS_BYTE(x) ((u8)((x) & 0xFF))
197*4882a593Smuzhiyun #define MS_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* message ID codes in SPI commands */
200*4882a593Smuzhiyun /* downstream */
201*4882a593Smuzhiyun #define MCPS_DATA_REQUEST (0x00)
202*4882a593Smuzhiyun #define MLME_ASSOCIATE_REQUEST (0x02)
203*4882a593Smuzhiyun #define MLME_ASSOCIATE_RESPONSE (0x03)
204*4882a593Smuzhiyun #define MLME_DISASSOCIATE_REQUEST (0x04)
205*4882a593Smuzhiyun #define MLME_GET_REQUEST (0x05)
206*4882a593Smuzhiyun #define MLME_ORPHAN_RESPONSE (0x06)
207*4882a593Smuzhiyun #define MLME_RESET_REQUEST (0x07)
208*4882a593Smuzhiyun #define MLME_RX_ENABLE_REQUEST (0x08)
209*4882a593Smuzhiyun #define MLME_SCAN_REQUEST (0x09)
210*4882a593Smuzhiyun #define MLME_SET_REQUEST (0x0A)
211*4882a593Smuzhiyun #define MLME_START_REQUEST (0x0B)
212*4882a593Smuzhiyun #define MLME_POLL_REQUEST (0x0D)
213*4882a593Smuzhiyun #define HWME_SET_REQUEST (0x0E)
214*4882a593Smuzhiyun #define HWME_GET_REQUEST (0x0F)
215*4882a593Smuzhiyun #define TDME_SETSFR_REQUEST (0x11)
216*4882a593Smuzhiyun #define TDME_GETSFR_REQUEST (0x12)
217*4882a593Smuzhiyun #define TDME_SET_REQUEST (0x14)
218*4882a593Smuzhiyun /* upstream */
219*4882a593Smuzhiyun #define MCPS_DATA_INDICATION (0x00)
220*4882a593Smuzhiyun #define MCPS_DATA_CONFIRM (0x01)
221*4882a593Smuzhiyun #define MLME_RESET_CONFIRM (0x0A)
222*4882a593Smuzhiyun #define MLME_SET_CONFIRM (0x0E)
223*4882a593Smuzhiyun #define MLME_START_CONFIRM (0x0F)
224*4882a593Smuzhiyun #define HWME_SET_CONFIRM (0x12)
225*4882a593Smuzhiyun #define HWME_GET_CONFIRM (0x13)
226*4882a593Smuzhiyun #define HWME_WAKEUP_INDICATION (0x15)
227*4882a593Smuzhiyun #define TDME_SETSFR_CONFIRM (0x17)
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /* SPI command IDs */
230*4882a593Smuzhiyun /* bit indicating a confirm or indication from slave to master */
231*4882a593Smuzhiyun #define SPI_S2M (0x20)
232*4882a593Smuzhiyun /* bit indicating a synchronous message */
233*4882a593Smuzhiyun #define SPI_SYN (0x40)
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /* SPI command definitions */
236*4882a593Smuzhiyun #define SPI_IDLE (0xFF)
237*4882a593Smuzhiyun #define SPI_NACK (0xF0)
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun #define SPI_MCPS_DATA_REQUEST (MCPS_DATA_REQUEST)
240*4882a593Smuzhiyun #define SPI_MCPS_DATA_INDICATION (MCPS_DATA_INDICATION + SPI_S2M)
241*4882a593Smuzhiyun #define SPI_MCPS_DATA_CONFIRM (MCPS_DATA_CONFIRM + SPI_S2M)
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun #define SPI_MLME_ASSOCIATE_REQUEST (MLME_ASSOCIATE_REQUEST)
244*4882a593Smuzhiyun #define SPI_MLME_RESET_REQUEST (MLME_RESET_REQUEST + SPI_SYN)
245*4882a593Smuzhiyun #define SPI_MLME_SET_REQUEST (MLME_SET_REQUEST + SPI_SYN)
246*4882a593Smuzhiyun #define SPI_MLME_START_REQUEST (MLME_START_REQUEST + SPI_SYN)
247*4882a593Smuzhiyun #define SPI_MLME_RESET_CONFIRM (MLME_RESET_CONFIRM + SPI_S2M + SPI_SYN)
248*4882a593Smuzhiyun #define SPI_MLME_SET_CONFIRM (MLME_SET_CONFIRM + SPI_S2M + SPI_SYN)
249*4882a593Smuzhiyun #define SPI_MLME_START_CONFIRM (MLME_START_CONFIRM + SPI_S2M + SPI_SYN)
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun #define SPI_HWME_SET_REQUEST (HWME_SET_REQUEST + SPI_SYN)
252*4882a593Smuzhiyun #define SPI_HWME_GET_REQUEST (HWME_GET_REQUEST + SPI_SYN)
253*4882a593Smuzhiyun #define SPI_HWME_SET_CONFIRM (HWME_SET_CONFIRM + SPI_S2M + SPI_SYN)
254*4882a593Smuzhiyun #define SPI_HWME_GET_CONFIRM (HWME_GET_CONFIRM + SPI_S2M + SPI_SYN)
255*4882a593Smuzhiyun #define SPI_HWME_WAKEUP_INDICATION (HWME_WAKEUP_INDICATION + SPI_S2M)
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun #define SPI_TDME_SETSFR_REQUEST (TDME_SETSFR_REQUEST + SPI_SYN)
258*4882a593Smuzhiyun #define SPI_TDME_SET_REQUEST (TDME_SET_REQUEST + SPI_SYN)
259*4882a593Smuzhiyun #define SPI_TDME_SETSFR_CONFIRM (TDME_SETSFR_CONFIRM + SPI_S2M + SPI_SYN)
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* TDME SFR addresses */
262*4882a593Smuzhiyun /* Page 0 */
263*4882a593Smuzhiyun #define CA8210_SFR_PACFG (0xB1)
264*4882a593Smuzhiyun #define CA8210_SFR_MACCON (0xD8)
265*4882a593Smuzhiyun #define CA8210_SFR_PACFGIB (0xFE)
266*4882a593Smuzhiyun /* Page 1 */
267*4882a593Smuzhiyun #define CA8210_SFR_LOTXCAL (0xBF)
268*4882a593Smuzhiyun #define CA8210_SFR_PTHRH (0xD1)
269*4882a593Smuzhiyun #define CA8210_SFR_PRECFG (0xD3)
270*4882a593Smuzhiyun #define CA8210_SFR_LNAGX40 (0xE1)
271*4882a593Smuzhiyun #define CA8210_SFR_LNAGX41 (0xE2)
272*4882a593Smuzhiyun #define CA8210_SFR_LNAGX42 (0xE3)
273*4882a593Smuzhiyun #define CA8210_SFR_LNAGX43 (0xE4)
274*4882a593Smuzhiyun #define CA8210_SFR_LNAGX44 (0xE5)
275*4882a593Smuzhiyun #define CA8210_SFR_LNAGX45 (0xE6)
276*4882a593Smuzhiyun #define CA8210_SFR_LNAGX46 (0xE7)
277*4882a593Smuzhiyun #define CA8210_SFR_LNAGX47 (0xE9)
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun #define PACFGIB_DEFAULT_CURRENT (0x3F)
280*4882a593Smuzhiyun #define PTHRH_DEFAULT_THRESHOLD (0x5A)
281*4882a593Smuzhiyun #define LNAGX40_DEFAULT_GAIN (0x29) /* 10dB */
282*4882a593Smuzhiyun #define LNAGX41_DEFAULT_GAIN (0x54) /* 21dB */
283*4882a593Smuzhiyun #define LNAGX42_DEFAULT_GAIN (0x6C) /* 27dB */
284*4882a593Smuzhiyun #define LNAGX43_DEFAULT_GAIN (0x7A) /* 30dB */
285*4882a593Smuzhiyun #define LNAGX44_DEFAULT_GAIN (0x84) /* 33dB */
286*4882a593Smuzhiyun #define LNAGX45_DEFAULT_GAIN (0x8B) /* 34dB */
287*4882a593Smuzhiyun #define LNAGX46_DEFAULT_GAIN (0x92) /* 36dB */
288*4882a593Smuzhiyun #define LNAGX47_DEFAULT_GAIN (0x96) /* 37dB */
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun #define CA8210_IOCTL_HARD_RESET (0x00)
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun /* Structs/Enums */
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /**
295*4882a593Smuzhiyun * struct cas_control - spi transfer structure
296*4882a593Smuzhiyun * @msg: spi_message for each exchange
297*4882a593Smuzhiyun * @transfer: spi_transfer for each exchange
298*4882a593Smuzhiyun * @tx_buf: source array for transmission
299*4882a593Smuzhiyun * @tx_in_buf: array storing bytes received during transmission
300*4882a593Smuzhiyun * @priv: pointer to private data
301*4882a593Smuzhiyun *
302*4882a593Smuzhiyun * This structure stores all the necessary data passed around during a single
303*4882a593Smuzhiyun * spi exchange.
304*4882a593Smuzhiyun */
305*4882a593Smuzhiyun struct cas_control {
306*4882a593Smuzhiyun struct spi_message msg;
307*4882a593Smuzhiyun struct spi_transfer transfer;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun u8 tx_buf[CA8210_SPI_BUF_SIZE];
310*4882a593Smuzhiyun u8 tx_in_buf[CA8210_SPI_BUF_SIZE];
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun struct ca8210_priv *priv;
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /**
316*4882a593Smuzhiyun * struct ca8210_test - ca8210 test interface structure
317*4882a593Smuzhiyun * @ca8210_dfs_spi_int: pointer to the entry in the debug fs for this device
318*4882a593Smuzhiyun * @up_fifo: fifo for upstream messages
319*4882a593Smuzhiyun *
320*4882a593Smuzhiyun * This structure stores all the data pertaining to the debug interface
321*4882a593Smuzhiyun */
322*4882a593Smuzhiyun struct ca8210_test {
323*4882a593Smuzhiyun struct dentry *ca8210_dfs_spi_int;
324*4882a593Smuzhiyun struct kfifo up_fifo;
325*4882a593Smuzhiyun wait_queue_head_t readq;
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /**
329*4882a593Smuzhiyun * struct ca8210_priv - ca8210 private data structure
330*4882a593Smuzhiyun * @spi: pointer to the ca8210 spi device object
331*4882a593Smuzhiyun * @hw: pointer to the ca8210 ieee802154_hw object
332*4882a593Smuzhiyun * @hw_registered: true if hw has been registered with ieee802154
333*4882a593Smuzhiyun * @lock: spinlock protecting the private data area
334*4882a593Smuzhiyun * @mlme_workqueue: workqueue for triggering MLME Reset
335*4882a593Smuzhiyun * @irq_workqueue: workqueue for irq processing
336*4882a593Smuzhiyun * @tx_skb: current socket buffer to transmit
337*4882a593Smuzhiyun * @nextmsduhandle: msdu handle to pass to the 15.4 MAC layer for the
338*4882a593Smuzhiyun * next transmission
339*4882a593Smuzhiyun * @clk: external clock provided by the ca8210
340*4882a593Smuzhiyun * @last_dsn: sequence number of last data packet received, for
341*4882a593Smuzhiyun * resend detection
342*4882a593Smuzhiyun * @test: test interface data section for this instance
343*4882a593Smuzhiyun * @async_tx_pending: true if an asynchronous transmission was started and
344*4882a593Smuzhiyun * is not complete
345*4882a593Smuzhiyun * @sync_command_response: pointer to buffer to fill with sync response
346*4882a593Smuzhiyun * @ca8210_is_awake: nonzero if ca8210 is initialised, ready for comms
347*4882a593Smuzhiyun * @sync_down: counts number of downstream synchronous commands
348*4882a593Smuzhiyun * @sync_up: counts number of upstream synchronous commands
349*4882a593Smuzhiyun * @spi_transfer_complete completion object for a single spi_transfer
350*4882a593Smuzhiyun * @sync_exchange_complete completion object for a complete synchronous API
351*4882a593Smuzhiyun * exchange
352*4882a593Smuzhiyun * @promiscuous whether the ca8210 is in promiscuous mode or not
353*4882a593Smuzhiyun * @retries: records how many times the current pending spi
354*4882a593Smuzhiyun * transfer has been retried
355*4882a593Smuzhiyun */
356*4882a593Smuzhiyun struct ca8210_priv {
357*4882a593Smuzhiyun struct spi_device *spi;
358*4882a593Smuzhiyun struct ieee802154_hw *hw;
359*4882a593Smuzhiyun bool hw_registered;
360*4882a593Smuzhiyun spinlock_t lock;
361*4882a593Smuzhiyun struct workqueue_struct *mlme_workqueue;
362*4882a593Smuzhiyun struct workqueue_struct *irq_workqueue;
363*4882a593Smuzhiyun struct sk_buff *tx_skb;
364*4882a593Smuzhiyun u8 nextmsduhandle;
365*4882a593Smuzhiyun struct clk *clk;
366*4882a593Smuzhiyun int last_dsn;
367*4882a593Smuzhiyun struct ca8210_test test;
368*4882a593Smuzhiyun bool async_tx_pending;
369*4882a593Smuzhiyun u8 *sync_command_response;
370*4882a593Smuzhiyun struct completion ca8210_is_awake;
371*4882a593Smuzhiyun int sync_down, sync_up;
372*4882a593Smuzhiyun struct completion spi_transfer_complete, sync_exchange_complete;
373*4882a593Smuzhiyun bool promiscuous;
374*4882a593Smuzhiyun int retries;
375*4882a593Smuzhiyun };
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /**
378*4882a593Smuzhiyun * struct work_priv_container - link between a work object and the relevant
379*4882a593Smuzhiyun * device's private data
380*4882a593Smuzhiyun * @work: work object being executed
381*4882a593Smuzhiyun * @priv: device's private data section
382*4882a593Smuzhiyun *
383*4882a593Smuzhiyun */
384*4882a593Smuzhiyun struct work_priv_container {
385*4882a593Smuzhiyun struct work_struct work;
386*4882a593Smuzhiyun struct ca8210_priv *priv;
387*4882a593Smuzhiyun };
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun /**
390*4882a593Smuzhiyun * struct ca8210_platform_data - ca8210 platform data structure
391*4882a593Smuzhiyun * @extclockenable: true if the external clock is to be enabled
392*4882a593Smuzhiyun * @extclockfreq: frequency of the external clock
393*4882a593Smuzhiyun * @extclockgpio: ca8210 output gpio of the external clock
394*4882a593Smuzhiyun * @gpio_reset: gpio number of ca8210 reset line
395*4882a593Smuzhiyun * @gpio_irq: gpio number of ca8210 interrupt line
396*4882a593Smuzhiyun * @irq_id: identifier for the ca8210 irq
397*4882a593Smuzhiyun *
398*4882a593Smuzhiyun */
399*4882a593Smuzhiyun struct ca8210_platform_data {
400*4882a593Smuzhiyun bool extclockenable;
401*4882a593Smuzhiyun unsigned int extclockfreq;
402*4882a593Smuzhiyun unsigned int extclockgpio;
403*4882a593Smuzhiyun int gpio_reset;
404*4882a593Smuzhiyun int gpio_irq;
405*4882a593Smuzhiyun int irq_id;
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /**
409*4882a593Smuzhiyun * struct fulladdr - full MAC addressing information structure
410*4882a593Smuzhiyun * @mode: address mode (none, short, extended)
411*4882a593Smuzhiyun * @pan_id: 16-bit LE pan id
412*4882a593Smuzhiyun * @address: LE address, variable length as specified by mode
413*4882a593Smuzhiyun *
414*4882a593Smuzhiyun */
415*4882a593Smuzhiyun struct fulladdr {
416*4882a593Smuzhiyun u8 mode;
417*4882a593Smuzhiyun u8 pan_id[2];
418*4882a593Smuzhiyun u8 address[8];
419*4882a593Smuzhiyun };
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun /**
422*4882a593Smuzhiyun * union macaddr: generic MAC address container
423*4882a593Smuzhiyun * @short_addr: 16-bit short address
424*4882a593Smuzhiyun * @ieee_address: 64-bit extended address as LE byte array
425*4882a593Smuzhiyun *
426*4882a593Smuzhiyun */
427*4882a593Smuzhiyun union macaddr {
428*4882a593Smuzhiyun u16 short_address;
429*4882a593Smuzhiyun u8 ieee_address[8];
430*4882a593Smuzhiyun };
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /**
433*4882a593Smuzhiyun * struct secspec: security specification for SAP commands
434*4882a593Smuzhiyun * @security_level: 0-7, controls level of authentication & encryption
435*4882a593Smuzhiyun * @key_id_mode: 0-3, specifies how to obtain key
436*4882a593Smuzhiyun * @key_source: extended key retrieval data
437*4882a593Smuzhiyun * @key_index: single-byte key identifier
438*4882a593Smuzhiyun *
439*4882a593Smuzhiyun */
440*4882a593Smuzhiyun struct secspec {
441*4882a593Smuzhiyun u8 security_level;
442*4882a593Smuzhiyun u8 key_id_mode;
443*4882a593Smuzhiyun u8 key_source[8];
444*4882a593Smuzhiyun u8 key_index;
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun /* downlink functions parameter set definitions */
448*4882a593Smuzhiyun struct mcps_data_request_pset {
449*4882a593Smuzhiyun u8 src_addr_mode;
450*4882a593Smuzhiyun struct fulladdr dst;
451*4882a593Smuzhiyun u8 msdu_length;
452*4882a593Smuzhiyun u8 msdu_handle;
453*4882a593Smuzhiyun u8 tx_options;
454*4882a593Smuzhiyun u8 msdu[MAX_DATA_SIZE];
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun struct mlme_set_request_pset {
458*4882a593Smuzhiyun u8 pib_attribute;
459*4882a593Smuzhiyun u8 pib_attribute_index;
460*4882a593Smuzhiyun u8 pib_attribute_length;
461*4882a593Smuzhiyun u8 pib_attribute_value[MAX_ATTRIBUTE_SIZE];
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun struct hwme_set_request_pset {
465*4882a593Smuzhiyun u8 hw_attribute;
466*4882a593Smuzhiyun u8 hw_attribute_length;
467*4882a593Smuzhiyun u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun struct hwme_get_request_pset {
471*4882a593Smuzhiyun u8 hw_attribute;
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun struct tdme_setsfr_request_pset {
475*4882a593Smuzhiyun u8 sfr_page;
476*4882a593Smuzhiyun u8 sfr_address;
477*4882a593Smuzhiyun u8 sfr_value;
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun /* uplink functions parameter set definitions */
481*4882a593Smuzhiyun struct hwme_set_confirm_pset {
482*4882a593Smuzhiyun u8 status;
483*4882a593Smuzhiyun u8 hw_attribute;
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun struct hwme_get_confirm_pset {
487*4882a593Smuzhiyun u8 status;
488*4882a593Smuzhiyun u8 hw_attribute;
489*4882a593Smuzhiyun u8 hw_attribute_length;
490*4882a593Smuzhiyun u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun struct tdme_setsfr_confirm_pset {
494*4882a593Smuzhiyun u8 status;
495*4882a593Smuzhiyun u8 sfr_page;
496*4882a593Smuzhiyun u8 sfr_address;
497*4882a593Smuzhiyun };
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun struct mac_message {
500*4882a593Smuzhiyun u8 command_id;
501*4882a593Smuzhiyun u8 length;
502*4882a593Smuzhiyun union {
503*4882a593Smuzhiyun struct mcps_data_request_pset data_req;
504*4882a593Smuzhiyun struct mlme_set_request_pset set_req;
505*4882a593Smuzhiyun struct hwme_set_request_pset hwme_set_req;
506*4882a593Smuzhiyun struct hwme_get_request_pset hwme_get_req;
507*4882a593Smuzhiyun struct tdme_setsfr_request_pset tdme_set_sfr_req;
508*4882a593Smuzhiyun struct hwme_set_confirm_pset hwme_set_cnf;
509*4882a593Smuzhiyun struct hwme_get_confirm_pset hwme_get_cnf;
510*4882a593Smuzhiyun struct tdme_setsfr_confirm_pset tdme_set_sfr_cnf;
511*4882a593Smuzhiyun u8 u8param;
512*4882a593Smuzhiyun u8 status;
513*4882a593Smuzhiyun u8 payload[148];
514*4882a593Smuzhiyun } pdata;
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun union pa_cfg_sfr {
518*4882a593Smuzhiyun struct {
519*4882a593Smuzhiyun u8 bias_current_trim : 3;
520*4882a593Smuzhiyun u8 /* reserved */ : 1;
521*4882a593Smuzhiyun u8 buffer_capacitor_trim : 3;
522*4882a593Smuzhiyun u8 boost : 1;
523*4882a593Smuzhiyun };
524*4882a593Smuzhiyun u8 paib;
525*4882a593Smuzhiyun };
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun struct preamble_cfg_sfr {
528*4882a593Smuzhiyun u8 timeout_symbols : 3;
529*4882a593Smuzhiyun u8 acquisition_symbols : 3;
530*4882a593Smuzhiyun u8 search_symbols : 2;
531*4882a593Smuzhiyun };
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun static int (*cascoda_api_upstream)(
534*4882a593Smuzhiyun const u8 *buf,
535*4882a593Smuzhiyun size_t len,
536*4882a593Smuzhiyun void *device_ref
537*4882a593Smuzhiyun );
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun /**
540*4882a593Smuzhiyun * link_to_linux_err() - Translates an 802.15.4 return code into the closest
541*4882a593Smuzhiyun * linux error
542*4882a593Smuzhiyun * @link_status: 802.15.4 status code
543*4882a593Smuzhiyun *
544*4882a593Smuzhiyun * Return: 0 or Linux error code
545*4882a593Smuzhiyun */
link_to_linux_err(int link_status)546*4882a593Smuzhiyun static int link_to_linux_err(int link_status)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun if (link_status < 0) {
549*4882a593Smuzhiyun /* status is already a Linux code */
550*4882a593Smuzhiyun return link_status;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun switch (link_status) {
553*4882a593Smuzhiyun case MAC_SUCCESS:
554*4882a593Smuzhiyun case MAC_REALIGNMENT:
555*4882a593Smuzhiyun return 0;
556*4882a593Smuzhiyun case MAC_IMPROPER_KEY_TYPE:
557*4882a593Smuzhiyun return -EKEYREJECTED;
558*4882a593Smuzhiyun case MAC_IMPROPER_SECURITY_LEVEL:
559*4882a593Smuzhiyun case MAC_UNSUPPORTED_LEGACY:
560*4882a593Smuzhiyun case MAC_DENIED:
561*4882a593Smuzhiyun return -EACCES;
562*4882a593Smuzhiyun case MAC_BEACON_LOST:
563*4882a593Smuzhiyun case MAC_NO_ACK:
564*4882a593Smuzhiyun case MAC_NO_BEACON:
565*4882a593Smuzhiyun return -ENETUNREACH;
566*4882a593Smuzhiyun case MAC_CHANNEL_ACCESS_FAILURE:
567*4882a593Smuzhiyun case MAC_TX_ACTIVE:
568*4882a593Smuzhiyun case MAC_SCAN_IN_PROGRESS:
569*4882a593Smuzhiyun return -EBUSY;
570*4882a593Smuzhiyun case MAC_DISABLE_TRX_FAILURE:
571*4882a593Smuzhiyun case MAC_OUT_OF_CAP:
572*4882a593Smuzhiyun return -EAGAIN;
573*4882a593Smuzhiyun case MAC_FRAME_TOO_LONG:
574*4882a593Smuzhiyun return -EMSGSIZE;
575*4882a593Smuzhiyun case MAC_INVALID_GTS:
576*4882a593Smuzhiyun case MAC_PAST_TIME:
577*4882a593Smuzhiyun return -EBADSLT;
578*4882a593Smuzhiyun case MAC_INVALID_HANDLE:
579*4882a593Smuzhiyun return -EBADMSG;
580*4882a593Smuzhiyun case MAC_INVALID_PARAMETER:
581*4882a593Smuzhiyun case MAC_UNSUPPORTED_ATTRIBUTE:
582*4882a593Smuzhiyun case MAC_ON_TIME_TOO_LONG:
583*4882a593Smuzhiyun case MAC_INVALID_INDEX:
584*4882a593Smuzhiyun return -EINVAL;
585*4882a593Smuzhiyun case MAC_NO_DATA:
586*4882a593Smuzhiyun return -ENODATA;
587*4882a593Smuzhiyun case MAC_NO_SHORT_ADDRESS:
588*4882a593Smuzhiyun return -EFAULT;
589*4882a593Smuzhiyun case MAC_PAN_ID_CONFLICT:
590*4882a593Smuzhiyun return -EADDRINUSE;
591*4882a593Smuzhiyun case MAC_TRANSACTION_EXPIRED:
592*4882a593Smuzhiyun return -ETIME;
593*4882a593Smuzhiyun case MAC_TRANSACTION_OVERFLOW:
594*4882a593Smuzhiyun return -ENOBUFS;
595*4882a593Smuzhiyun case MAC_UNAVAILABLE_KEY:
596*4882a593Smuzhiyun return -ENOKEY;
597*4882a593Smuzhiyun case MAC_INVALID_ADDRESS:
598*4882a593Smuzhiyun return -ENXIO;
599*4882a593Smuzhiyun case MAC_TRACKING_OFF:
600*4882a593Smuzhiyun case MAC_SUPERFRAME_OVERLAP:
601*4882a593Smuzhiyun return -EREMOTEIO;
602*4882a593Smuzhiyun case MAC_LIMIT_REACHED:
603*4882a593Smuzhiyun return -EDQUOT;
604*4882a593Smuzhiyun case MAC_READ_ONLY:
605*4882a593Smuzhiyun return -EROFS;
606*4882a593Smuzhiyun default:
607*4882a593Smuzhiyun return -EPROTO;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun /**
612*4882a593Smuzhiyun * ca8210_test_int_driver_write() - Writes a message to the test interface to be
613*4882a593Smuzhiyun * read by the userspace
614*4882a593Smuzhiyun * @buf: Buffer containing upstream message
615*4882a593Smuzhiyun * @len: length of message to write
616*4882a593Smuzhiyun * @spi: SPI device of message originator
617*4882a593Smuzhiyun *
618*4882a593Smuzhiyun * Return: 0 or linux error code
619*4882a593Smuzhiyun */
ca8210_test_int_driver_write(const u8 * buf,size_t len,void * spi)620*4882a593Smuzhiyun static int ca8210_test_int_driver_write(
621*4882a593Smuzhiyun const u8 *buf,
622*4882a593Smuzhiyun size_t len,
623*4882a593Smuzhiyun void *spi
624*4882a593Smuzhiyun )
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun struct ca8210_priv *priv = spi_get_drvdata(spi);
627*4882a593Smuzhiyun struct ca8210_test *test = &priv->test;
628*4882a593Smuzhiyun char *fifo_buffer;
629*4882a593Smuzhiyun int i;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun dev_dbg(
632*4882a593Smuzhiyun &priv->spi->dev,
633*4882a593Smuzhiyun "test_interface: Buffering upstream message:\n"
634*4882a593Smuzhiyun );
635*4882a593Smuzhiyun for (i = 0; i < len; i++)
636*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "%#03x\n", buf[i]);
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun fifo_buffer = kmemdup(buf, len, GFP_KERNEL);
639*4882a593Smuzhiyun if (!fifo_buffer)
640*4882a593Smuzhiyun return -ENOMEM;
641*4882a593Smuzhiyun kfifo_in(&test->up_fifo, &fifo_buffer, 4);
642*4882a593Smuzhiyun wake_up_interruptible(&priv->test.readq);
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun return 0;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /* SPI Operation */
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun static int ca8210_net_rx(
650*4882a593Smuzhiyun struct ieee802154_hw *hw,
651*4882a593Smuzhiyun u8 *command,
652*4882a593Smuzhiyun size_t len
653*4882a593Smuzhiyun );
654*4882a593Smuzhiyun static u8 mlme_reset_request_sync(
655*4882a593Smuzhiyun u8 set_default_pib,
656*4882a593Smuzhiyun void *device_ref
657*4882a593Smuzhiyun );
658*4882a593Smuzhiyun static int ca8210_spi_transfer(
659*4882a593Smuzhiyun struct spi_device *spi,
660*4882a593Smuzhiyun const u8 *buf,
661*4882a593Smuzhiyun size_t len
662*4882a593Smuzhiyun );
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun /**
665*4882a593Smuzhiyun * ca8210_reset_send() - Hard resets the ca8210 for a given time
666*4882a593Smuzhiyun * @spi: Pointer to target ca8210 spi device
667*4882a593Smuzhiyun * @ms: Milliseconds to hold the reset line low for
668*4882a593Smuzhiyun */
ca8210_reset_send(struct spi_device * spi,unsigned int ms)669*4882a593Smuzhiyun static void ca8210_reset_send(struct spi_device *spi, unsigned int ms)
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun struct ca8210_platform_data *pdata = spi->dev.platform_data;
672*4882a593Smuzhiyun struct ca8210_priv *priv = spi_get_drvdata(spi);
673*4882a593Smuzhiyun long status;
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun gpio_set_value(pdata->gpio_reset, 0);
676*4882a593Smuzhiyun reinit_completion(&priv->ca8210_is_awake);
677*4882a593Smuzhiyun msleep(ms);
678*4882a593Smuzhiyun gpio_set_value(pdata->gpio_reset, 1);
679*4882a593Smuzhiyun priv->promiscuous = false;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun /* Wait until wakeup indication seen */
682*4882a593Smuzhiyun status = wait_for_completion_interruptible_timeout(
683*4882a593Smuzhiyun &priv->ca8210_is_awake,
684*4882a593Smuzhiyun msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
685*4882a593Smuzhiyun );
686*4882a593Smuzhiyun if (status == 0) {
687*4882a593Smuzhiyun dev_crit(
688*4882a593Smuzhiyun &spi->dev,
689*4882a593Smuzhiyun "Fatal: No wakeup from ca8210 after reset!\n"
690*4882a593Smuzhiyun );
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun dev_dbg(&spi->dev, "Reset the device\n");
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun /**
697*4882a593Smuzhiyun * ca8210_mlme_reset_worker() - Resets the MLME, Called when the MAC OVERFLOW
698*4882a593Smuzhiyun * condition happens.
699*4882a593Smuzhiyun * @work: Pointer to work being executed
700*4882a593Smuzhiyun */
ca8210_mlme_reset_worker(struct work_struct * work)701*4882a593Smuzhiyun static void ca8210_mlme_reset_worker(struct work_struct *work)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun struct work_priv_container *wpc = container_of(
704*4882a593Smuzhiyun work,
705*4882a593Smuzhiyun struct work_priv_container,
706*4882a593Smuzhiyun work
707*4882a593Smuzhiyun );
708*4882a593Smuzhiyun struct ca8210_priv *priv = wpc->priv;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun mlme_reset_request_sync(0, priv->spi);
711*4882a593Smuzhiyun kfree(wpc);
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun /**
715*4882a593Smuzhiyun * ca8210_rx_done() - Calls various message dispatches responding to a received
716*4882a593Smuzhiyun * command
717*4882a593Smuzhiyun * @arg: Pointer to the cas_control object for the relevant spi transfer
718*4882a593Smuzhiyun *
719*4882a593Smuzhiyun * Presents a received SAP command from the ca8210 to the Cascoda EVBME, test
720*4882a593Smuzhiyun * interface and network driver.
721*4882a593Smuzhiyun */
ca8210_rx_done(struct cas_control * cas_ctl)722*4882a593Smuzhiyun static void ca8210_rx_done(struct cas_control *cas_ctl)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun u8 *buf;
725*4882a593Smuzhiyun unsigned int len;
726*4882a593Smuzhiyun struct work_priv_container *mlme_reset_wpc;
727*4882a593Smuzhiyun struct ca8210_priv *priv = cas_ctl->priv;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun buf = cas_ctl->tx_in_buf;
730*4882a593Smuzhiyun len = buf[1] + 2;
731*4882a593Smuzhiyun if (len > CA8210_SPI_BUF_SIZE) {
732*4882a593Smuzhiyun dev_crit(
733*4882a593Smuzhiyun &priv->spi->dev,
734*4882a593Smuzhiyun "Received packet len (%u) erroneously long\n",
735*4882a593Smuzhiyun len
736*4882a593Smuzhiyun );
737*4882a593Smuzhiyun goto finish;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun if (buf[0] & SPI_SYN) {
741*4882a593Smuzhiyun if (priv->sync_command_response) {
742*4882a593Smuzhiyun memcpy(priv->sync_command_response, buf, len);
743*4882a593Smuzhiyun complete(&priv->sync_exchange_complete);
744*4882a593Smuzhiyun } else {
745*4882a593Smuzhiyun if (cascoda_api_upstream)
746*4882a593Smuzhiyun cascoda_api_upstream(buf, len, priv->spi);
747*4882a593Smuzhiyun priv->sync_up++;
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun } else {
750*4882a593Smuzhiyun if (cascoda_api_upstream)
751*4882a593Smuzhiyun cascoda_api_upstream(buf, len, priv->spi);
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun ca8210_net_rx(priv->hw, buf, len);
755*4882a593Smuzhiyun if (buf[0] == SPI_MCPS_DATA_CONFIRM) {
756*4882a593Smuzhiyun if (buf[3] == MAC_TRANSACTION_OVERFLOW) {
757*4882a593Smuzhiyun dev_info(
758*4882a593Smuzhiyun &priv->spi->dev,
759*4882a593Smuzhiyun "Waiting for transaction overflow to stabilise...\n");
760*4882a593Smuzhiyun msleep(2000);
761*4882a593Smuzhiyun dev_info(
762*4882a593Smuzhiyun &priv->spi->dev,
763*4882a593Smuzhiyun "Resetting MAC...\n");
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun mlme_reset_wpc = kmalloc(sizeof(*mlme_reset_wpc),
766*4882a593Smuzhiyun GFP_KERNEL);
767*4882a593Smuzhiyun if (!mlme_reset_wpc)
768*4882a593Smuzhiyun goto finish;
769*4882a593Smuzhiyun INIT_WORK(
770*4882a593Smuzhiyun &mlme_reset_wpc->work,
771*4882a593Smuzhiyun ca8210_mlme_reset_worker
772*4882a593Smuzhiyun );
773*4882a593Smuzhiyun mlme_reset_wpc->priv = priv;
774*4882a593Smuzhiyun queue_work(priv->mlme_workqueue, &mlme_reset_wpc->work);
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun } else if (buf[0] == SPI_HWME_WAKEUP_INDICATION) {
777*4882a593Smuzhiyun dev_notice(
778*4882a593Smuzhiyun &priv->spi->dev,
779*4882a593Smuzhiyun "Wakeup indication received, reason:\n"
780*4882a593Smuzhiyun );
781*4882a593Smuzhiyun switch (buf[2]) {
782*4882a593Smuzhiyun case 0:
783*4882a593Smuzhiyun dev_notice(
784*4882a593Smuzhiyun &priv->spi->dev,
785*4882a593Smuzhiyun "Transceiver woken up from Power Up / System Reset\n"
786*4882a593Smuzhiyun );
787*4882a593Smuzhiyun break;
788*4882a593Smuzhiyun case 1:
789*4882a593Smuzhiyun dev_notice(
790*4882a593Smuzhiyun &priv->spi->dev,
791*4882a593Smuzhiyun "Watchdog Timer Time-Out\n"
792*4882a593Smuzhiyun );
793*4882a593Smuzhiyun break;
794*4882a593Smuzhiyun case 2:
795*4882a593Smuzhiyun dev_notice(
796*4882a593Smuzhiyun &priv->spi->dev,
797*4882a593Smuzhiyun "Transceiver woken up from Power-Off by Sleep Timer Time-Out\n");
798*4882a593Smuzhiyun break;
799*4882a593Smuzhiyun case 3:
800*4882a593Smuzhiyun dev_notice(
801*4882a593Smuzhiyun &priv->spi->dev,
802*4882a593Smuzhiyun "Transceiver woken up from Power-Off by GPIO Activity\n"
803*4882a593Smuzhiyun );
804*4882a593Smuzhiyun break;
805*4882a593Smuzhiyun case 4:
806*4882a593Smuzhiyun dev_notice(
807*4882a593Smuzhiyun &priv->spi->dev,
808*4882a593Smuzhiyun "Transceiver woken up from Standby by Sleep Timer Time-Out\n"
809*4882a593Smuzhiyun );
810*4882a593Smuzhiyun break;
811*4882a593Smuzhiyun case 5:
812*4882a593Smuzhiyun dev_notice(
813*4882a593Smuzhiyun &priv->spi->dev,
814*4882a593Smuzhiyun "Transceiver woken up from Standby by GPIO Activity\n"
815*4882a593Smuzhiyun );
816*4882a593Smuzhiyun break;
817*4882a593Smuzhiyun case 6:
818*4882a593Smuzhiyun dev_notice(
819*4882a593Smuzhiyun &priv->spi->dev,
820*4882a593Smuzhiyun "Sleep-Timer Time-Out in Active Mode\n"
821*4882a593Smuzhiyun );
822*4882a593Smuzhiyun break;
823*4882a593Smuzhiyun default:
824*4882a593Smuzhiyun dev_warn(&priv->spi->dev, "Wakeup reason unknown\n");
825*4882a593Smuzhiyun break;
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun complete(&priv->ca8210_is_awake);
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun finish:;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun static int ca8210_remove(struct spi_device *spi_device);
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun /**
836*4882a593Smuzhiyun * ca8210_spi_transfer_complete() - Called when a single spi transfer has
837*4882a593Smuzhiyun * completed
838*4882a593Smuzhiyun * @context: Pointer to the cas_control object for the finished transfer
839*4882a593Smuzhiyun */
ca8210_spi_transfer_complete(void * context)840*4882a593Smuzhiyun static void ca8210_spi_transfer_complete(void *context)
841*4882a593Smuzhiyun {
842*4882a593Smuzhiyun struct cas_control *cas_ctl = context;
843*4882a593Smuzhiyun struct ca8210_priv *priv = cas_ctl->priv;
844*4882a593Smuzhiyun bool duplex_rx = false;
845*4882a593Smuzhiyun int i;
846*4882a593Smuzhiyun u8 retry_buffer[CA8210_SPI_BUF_SIZE];
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun if (
849*4882a593Smuzhiyun cas_ctl->tx_in_buf[0] == SPI_NACK ||
850*4882a593Smuzhiyun (cas_ctl->tx_in_buf[0] == SPI_IDLE &&
851*4882a593Smuzhiyun cas_ctl->tx_in_buf[1] == SPI_NACK)
852*4882a593Smuzhiyun ) {
853*4882a593Smuzhiyun /* ca8210 is busy */
854*4882a593Smuzhiyun dev_info(&priv->spi->dev, "ca8210 was busy during attempted write\n");
855*4882a593Smuzhiyun if (cas_ctl->tx_buf[0] == SPI_IDLE) {
856*4882a593Smuzhiyun dev_warn(
857*4882a593Smuzhiyun &priv->spi->dev,
858*4882a593Smuzhiyun "IRQ servicing NACKd, dropping transfer\n"
859*4882a593Smuzhiyun );
860*4882a593Smuzhiyun kfree(cas_ctl);
861*4882a593Smuzhiyun return;
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun if (priv->retries > 3) {
864*4882a593Smuzhiyun dev_err(&priv->spi->dev, "too many retries!\n");
865*4882a593Smuzhiyun kfree(cas_ctl);
866*4882a593Smuzhiyun ca8210_remove(priv->spi);
867*4882a593Smuzhiyun return;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun memcpy(retry_buffer, cas_ctl->tx_buf, CA8210_SPI_BUF_SIZE);
870*4882a593Smuzhiyun kfree(cas_ctl);
871*4882a593Smuzhiyun ca8210_spi_transfer(
872*4882a593Smuzhiyun priv->spi,
873*4882a593Smuzhiyun retry_buffer,
874*4882a593Smuzhiyun CA8210_SPI_BUF_SIZE
875*4882a593Smuzhiyun );
876*4882a593Smuzhiyun priv->retries++;
877*4882a593Smuzhiyun dev_info(&priv->spi->dev, "retried spi write\n");
878*4882a593Smuzhiyun return;
879*4882a593Smuzhiyun } else if (
880*4882a593Smuzhiyun cas_ctl->tx_in_buf[0] != SPI_IDLE &&
881*4882a593Smuzhiyun cas_ctl->tx_in_buf[0] != SPI_NACK
882*4882a593Smuzhiyun ) {
883*4882a593Smuzhiyun duplex_rx = true;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun if (duplex_rx) {
887*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "READ CMD DURING TX\n");
888*4882a593Smuzhiyun for (i = 0; i < cas_ctl->tx_in_buf[1] + 2; i++)
889*4882a593Smuzhiyun dev_dbg(
890*4882a593Smuzhiyun &priv->spi->dev,
891*4882a593Smuzhiyun "%#03x\n",
892*4882a593Smuzhiyun cas_ctl->tx_in_buf[i]
893*4882a593Smuzhiyun );
894*4882a593Smuzhiyun ca8210_rx_done(cas_ctl);
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun complete(&priv->spi_transfer_complete);
897*4882a593Smuzhiyun kfree(cas_ctl);
898*4882a593Smuzhiyun priv->retries = 0;
899*4882a593Smuzhiyun }
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun /**
902*4882a593Smuzhiyun * ca8210_spi_transfer() - Initiate duplex spi transfer with ca8210
903*4882a593Smuzhiyun * @spi: Pointer to spi device for transfer
904*4882a593Smuzhiyun * @buf: Octet array to send
905*4882a593Smuzhiyun * @len: length of the buffer being sent
906*4882a593Smuzhiyun *
907*4882a593Smuzhiyun * Return: 0 or linux error code
908*4882a593Smuzhiyun */
ca8210_spi_transfer(struct spi_device * spi,const u8 * buf,size_t len)909*4882a593Smuzhiyun static int ca8210_spi_transfer(
910*4882a593Smuzhiyun struct spi_device *spi,
911*4882a593Smuzhiyun const u8 *buf,
912*4882a593Smuzhiyun size_t len
913*4882a593Smuzhiyun )
914*4882a593Smuzhiyun {
915*4882a593Smuzhiyun int i, status = 0;
916*4882a593Smuzhiyun struct ca8210_priv *priv;
917*4882a593Smuzhiyun struct cas_control *cas_ctl;
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun if (!spi) {
920*4882a593Smuzhiyun pr_crit("NULL spi device passed to %s\n", __func__);
921*4882a593Smuzhiyun return -ENODEV;
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun priv = spi_get_drvdata(spi);
925*4882a593Smuzhiyun reinit_completion(&priv->spi_transfer_complete);
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun dev_dbg(&spi->dev, "%s called\n", __func__);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun cas_ctl = kzalloc(sizeof(*cas_ctl), GFP_ATOMIC);
930*4882a593Smuzhiyun if (!cas_ctl)
931*4882a593Smuzhiyun return -ENOMEM;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun cas_ctl->priv = priv;
934*4882a593Smuzhiyun memset(cas_ctl->tx_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
935*4882a593Smuzhiyun memset(cas_ctl->tx_in_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
936*4882a593Smuzhiyun memcpy(cas_ctl->tx_buf, buf, len);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun for (i = 0; i < len; i++)
939*4882a593Smuzhiyun dev_dbg(&spi->dev, "%#03x\n", cas_ctl->tx_buf[i]);
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun spi_message_init(&cas_ctl->msg);
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun cas_ctl->transfer.tx_nbits = 1; /* 1 MOSI line */
944*4882a593Smuzhiyun cas_ctl->transfer.rx_nbits = 1; /* 1 MISO line */
945*4882a593Smuzhiyun cas_ctl->transfer.speed_hz = 0; /* Use device setting */
946*4882a593Smuzhiyun cas_ctl->transfer.bits_per_word = 0; /* Use device setting */
947*4882a593Smuzhiyun cas_ctl->transfer.tx_buf = cas_ctl->tx_buf;
948*4882a593Smuzhiyun cas_ctl->transfer.rx_buf = cas_ctl->tx_in_buf;
949*4882a593Smuzhiyun cas_ctl->transfer.delay.value = 0;
950*4882a593Smuzhiyun cas_ctl->transfer.delay.unit = SPI_DELAY_UNIT_USECS;
951*4882a593Smuzhiyun cas_ctl->transfer.cs_change = 0;
952*4882a593Smuzhiyun cas_ctl->transfer.len = sizeof(struct mac_message);
953*4882a593Smuzhiyun cas_ctl->msg.complete = ca8210_spi_transfer_complete;
954*4882a593Smuzhiyun cas_ctl->msg.context = cas_ctl;
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun spi_message_add_tail(
957*4882a593Smuzhiyun &cas_ctl->transfer,
958*4882a593Smuzhiyun &cas_ctl->msg
959*4882a593Smuzhiyun );
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun status = spi_async(spi, &cas_ctl->msg);
962*4882a593Smuzhiyun if (status < 0) {
963*4882a593Smuzhiyun dev_crit(
964*4882a593Smuzhiyun &spi->dev,
965*4882a593Smuzhiyun "status %d from spi_sync in write\n",
966*4882a593Smuzhiyun status
967*4882a593Smuzhiyun );
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun return status;
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun /**
974*4882a593Smuzhiyun * ca8210_spi_exchange() - Exchange API/SAP commands with the radio
975*4882a593Smuzhiyun * @buf: Octet array of command being sent downstream
976*4882a593Smuzhiyun * @len: length of buf
977*4882a593Smuzhiyun * @response: buffer for storing synchronous response
978*4882a593Smuzhiyun * @device_ref: spi_device pointer for ca8210
979*4882a593Smuzhiyun *
980*4882a593Smuzhiyun * Effectively calls ca8210_spi_transfer to write buf[] to the spi, then for
981*4882a593Smuzhiyun * synchronous commands waits for the corresponding response to be read from
982*4882a593Smuzhiyun * the spi before returning. The response is written to the response parameter.
983*4882a593Smuzhiyun *
984*4882a593Smuzhiyun * Return: 0 or linux error code
985*4882a593Smuzhiyun */
ca8210_spi_exchange(const u8 * buf,size_t len,u8 * response,void * device_ref)986*4882a593Smuzhiyun static int ca8210_spi_exchange(
987*4882a593Smuzhiyun const u8 *buf,
988*4882a593Smuzhiyun size_t len,
989*4882a593Smuzhiyun u8 *response,
990*4882a593Smuzhiyun void *device_ref
991*4882a593Smuzhiyun )
992*4882a593Smuzhiyun {
993*4882a593Smuzhiyun int status = 0;
994*4882a593Smuzhiyun struct spi_device *spi = device_ref;
995*4882a593Smuzhiyun struct ca8210_priv *priv = spi->dev.driver_data;
996*4882a593Smuzhiyun long wait_remaining;
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun if ((buf[0] & SPI_SYN) && response) { /* if sync wait for confirm */
999*4882a593Smuzhiyun reinit_completion(&priv->sync_exchange_complete);
1000*4882a593Smuzhiyun priv->sync_command_response = response;
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun do {
1004*4882a593Smuzhiyun reinit_completion(&priv->spi_transfer_complete);
1005*4882a593Smuzhiyun status = ca8210_spi_transfer(priv->spi, buf, len);
1006*4882a593Smuzhiyun if (status) {
1007*4882a593Smuzhiyun dev_warn(
1008*4882a593Smuzhiyun &spi->dev,
1009*4882a593Smuzhiyun "spi write failed, returned %d\n",
1010*4882a593Smuzhiyun status
1011*4882a593Smuzhiyun );
1012*4882a593Smuzhiyun if (status == -EBUSY)
1013*4882a593Smuzhiyun continue;
1014*4882a593Smuzhiyun if (((buf[0] & SPI_SYN) && response))
1015*4882a593Smuzhiyun complete(&priv->sync_exchange_complete);
1016*4882a593Smuzhiyun goto cleanup;
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun wait_remaining = wait_for_completion_interruptible_timeout(
1020*4882a593Smuzhiyun &priv->spi_transfer_complete,
1021*4882a593Smuzhiyun msecs_to_jiffies(1000)
1022*4882a593Smuzhiyun );
1023*4882a593Smuzhiyun if (wait_remaining == -ERESTARTSYS) {
1024*4882a593Smuzhiyun status = -ERESTARTSYS;
1025*4882a593Smuzhiyun } else if (wait_remaining == 0) {
1026*4882a593Smuzhiyun dev_err(
1027*4882a593Smuzhiyun &spi->dev,
1028*4882a593Smuzhiyun "SPI downstream transfer timed out!\n"
1029*4882a593Smuzhiyun );
1030*4882a593Smuzhiyun status = -ETIME;
1031*4882a593Smuzhiyun goto cleanup;
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun } while (status < 0);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun if (!((buf[0] & SPI_SYN) && response))
1036*4882a593Smuzhiyun goto cleanup;
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun wait_remaining = wait_for_completion_interruptible_timeout(
1039*4882a593Smuzhiyun &priv->sync_exchange_complete,
1040*4882a593Smuzhiyun msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
1041*4882a593Smuzhiyun );
1042*4882a593Smuzhiyun if (wait_remaining == -ERESTARTSYS) {
1043*4882a593Smuzhiyun status = -ERESTARTSYS;
1044*4882a593Smuzhiyun } else if (wait_remaining == 0) {
1045*4882a593Smuzhiyun dev_err(
1046*4882a593Smuzhiyun &spi->dev,
1047*4882a593Smuzhiyun "Synchronous confirm timeout\n"
1048*4882a593Smuzhiyun );
1049*4882a593Smuzhiyun status = -ETIME;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun cleanup:
1053*4882a593Smuzhiyun priv->sync_command_response = NULL;
1054*4882a593Smuzhiyun return status;
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun /**
1058*4882a593Smuzhiyun * ca8210_interrupt_handler() - Called when an irq is received from the ca8210
1059*4882a593Smuzhiyun * @irq: Id of the irq being handled
1060*4882a593Smuzhiyun * @dev_id: Pointer passed by the system, pointing to the ca8210's private data
1061*4882a593Smuzhiyun *
1062*4882a593Smuzhiyun * This function is called when the irq line from the ca8210 is asserted,
1063*4882a593Smuzhiyun * signifying that the ca8210 has a message to send upstream to us. Starts the
1064*4882a593Smuzhiyun * asynchronous spi read.
1065*4882a593Smuzhiyun *
1066*4882a593Smuzhiyun * Return: irq return code
1067*4882a593Smuzhiyun */
ca8210_interrupt_handler(int irq,void * dev_id)1068*4882a593Smuzhiyun static irqreturn_t ca8210_interrupt_handler(int irq, void *dev_id)
1069*4882a593Smuzhiyun {
1070*4882a593Smuzhiyun struct ca8210_priv *priv = dev_id;
1071*4882a593Smuzhiyun int status;
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "irq: Interrupt occurred\n");
1074*4882a593Smuzhiyun do {
1075*4882a593Smuzhiyun status = ca8210_spi_transfer(priv->spi, NULL, 0);
1076*4882a593Smuzhiyun if (status && (status != -EBUSY)) {
1077*4882a593Smuzhiyun dev_warn(
1078*4882a593Smuzhiyun &priv->spi->dev,
1079*4882a593Smuzhiyun "spi read failed, returned %d\n",
1080*4882a593Smuzhiyun status
1081*4882a593Smuzhiyun );
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun } while (status == -EBUSY);
1084*4882a593Smuzhiyun return IRQ_HANDLED;
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun static int (*cascoda_api_downstream)(
1088*4882a593Smuzhiyun const u8 *buf,
1089*4882a593Smuzhiyun size_t len,
1090*4882a593Smuzhiyun u8 *response,
1091*4882a593Smuzhiyun void *device_ref
1092*4882a593Smuzhiyun ) = ca8210_spi_exchange;
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun /* Cascoda API / 15.4 SAP Primitives */
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun /**
1097*4882a593Smuzhiyun * tdme_setsfr_request_sync() - TDME_SETSFR_request/confirm according to API
1098*4882a593Smuzhiyun * @sfr_page: SFR Page
1099*4882a593Smuzhiyun * @sfr_address: SFR Address
1100*4882a593Smuzhiyun * @sfr_value: SFR Value
1101*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1102*4882a593Smuzhiyun *
1103*4882a593Smuzhiyun * Return: 802.15.4 status code of TDME-SETSFR.confirm
1104*4882a593Smuzhiyun */
tdme_setsfr_request_sync(u8 sfr_page,u8 sfr_address,u8 sfr_value,void * device_ref)1105*4882a593Smuzhiyun static u8 tdme_setsfr_request_sync(
1106*4882a593Smuzhiyun u8 sfr_page,
1107*4882a593Smuzhiyun u8 sfr_address,
1108*4882a593Smuzhiyun u8 sfr_value,
1109*4882a593Smuzhiyun void *device_ref
1110*4882a593Smuzhiyun )
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun int ret;
1113*4882a593Smuzhiyun struct mac_message command, response;
1114*4882a593Smuzhiyun struct spi_device *spi = device_ref;
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun command.command_id = SPI_TDME_SETSFR_REQUEST;
1117*4882a593Smuzhiyun command.length = 3;
1118*4882a593Smuzhiyun command.pdata.tdme_set_sfr_req.sfr_page = sfr_page;
1119*4882a593Smuzhiyun command.pdata.tdme_set_sfr_req.sfr_address = sfr_address;
1120*4882a593Smuzhiyun command.pdata.tdme_set_sfr_req.sfr_value = sfr_value;
1121*4882a593Smuzhiyun response.command_id = SPI_IDLE;
1122*4882a593Smuzhiyun ret = cascoda_api_downstream(
1123*4882a593Smuzhiyun &command.command_id,
1124*4882a593Smuzhiyun command.length + 2,
1125*4882a593Smuzhiyun &response.command_id,
1126*4882a593Smuzhiyun device_ref
1127*4882a593Smuzhiyun );
1128*4882a593Smuzhiyun if (ret) {
1129*4882a593Smuzhiyun dev_crit(&spi->dev, "cascoda_api_downstream returned %d", ret);
1130*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1131*4882a593Smuzhiyun }
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun if (response.command_id != SPI_TDME_SETSFR_CONFIRM) {
1134*4882a593Smuzhiyun dev_crit(
1135*4882a593Smuzhiyun &spi->dev,
1136*4882a593Smuzhiyun "sync response to SPI_TDME_SETSFR_REQUEST was not SPI_TDME_SETSFR_CONFIRM, it was %d\n",
1137*4882a593Smuzhiyun response.command_id
1138*4882a593Smuzhiyun );
1139*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun return response.pdata.tdme_set_sfr_cnf.status;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun /**
1146*4882a593Smuzhiyun * tdme_chipinit() - TDME Chip Register Default Initialisation Macro
1147*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1148*4882a593Smuzhiyun *
1149*4882a593Smuzhiyun * Return: 802.15.4 status code of API calls
1150*4882a593Smuzhiyun */
tdme_chipinit(void * device_ref)1151*4882a593Smuzhiyun static u8 tdme_chipinit(void *device_ref)
1152*4882a593Smuzhiyun {
1153*4882a593Smuzhiyun u8 status = MAC_SUCCESS;
1154*4882a593Smuzhiyun u8 sfr_address;
1155*4882a593Smuzhiyun struct spi_device *spi = device_ref;
1156*4882a593Smuzhiyun struct preamble_cfg_sfr pre_cfg_value = {
1157*4882a593Smuzhiyun .timeout_symbols = 3,
1158*4882a593Smuzhiyun .acquisition_symbols = 3,
1159*4882a593Smuzhiyun .search_symbols = 1,
1160*4882a593Smuzhiyun };
1161*4882a593Smuzhiyun /* LNA Gain Settings */
1162*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1163*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX40),
1164*4882a593Smuzhiyun LNAGX40_DEFAULT_GAIN, device_ref);
1165*4882a593Smuzhiyun if (status)
1166*4882a593Smuzhiyun goto finish;
1167*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1168*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX41),
1169*4882a593Smuzhiyun LNAGX41_DEFAULT_GAIN, device_ref);
1170*4882a593Smuzhiyun if (status)
1171*4882a593Smuzhiyun goto finish;
1172*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1173*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX42),
1174*4882a593Smuzhiyun LNAGX42_DEFAULT_GAIN, device_ref);
1175*4882a593Smuzhiyun if (status)
1176*4882a593Smuzhiyun goto finish;
1177*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1178*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX43),
1179*4882a593Smuzhiyun LNAGX43_DEFAULT_GAIN, device_ref);
1180*4882a593Smuzhiyun if (status)
1181*4882a593Smuzhiyun goto finish;
1182*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1183*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX44),
1184*4882a593Smuzhiyun LNAGX44_DEFAULT_GAIN, device_ref);
1185*4882a593Smuzhiyun if (status)
1186*4882a593Smuzhiyun goto finish;
1187*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1188*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX45),
1189*4882a593Smuzhiyun LNAGX45_DEFAULT_GAIN, device_ref);
1190*4882a593Smuzhiyun if (status)
1191*4882a593Smuzhiyun goto finish;
1192*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1193*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX46),
1194*4882a593Smuzhiyun LNAGX46_DEFAULT_GAIN, device_ref);
1195*4882a593Smuzhiyun if (status)
1196*4882a593Smuzhiyun goto finish;
1197*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1198*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_LNAGX47),
1199*4882a593Smuzhiyun LNAGX47_DEFAULT_GAIN, device_ref);
1200*4882a593Smuzhiyun if (status)
1201*4882a593Smuzhiyun goto finish;
1202*4882a593Smuzhiyun /* Preamble Timing Config */
1203*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1204*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_PRECFG),
1205*4882a593Smuzhiyun *((u8 *)&pre_cfg_value), device_ref);
1206*4882a593Smuzhiyun if (status)
1207*4882a593Smuzhiyun goto finish;
1208*4882a593Smuzhiyun /* Preamble Threshold High */
1209*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1210*4882a593Smuzhiyun 1, (sfr_address = CA8210_SFR_PTHRH),
1211*4882a593Smuzhiyun PTHRH_DEFAULT_THRESHOLD, device_ref);
1212*4882a593Smuzhiyun if (status)
1213*4882a593Smuzhiyun goto finish;
1214*4882a593Smuzhiyun /* Tx Output Power 8 dBm */
1215*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1216*4882a593Smuzhiyun 0, (sfr_address = CA8210_SFR_PACFGIB),
1217*4882a593Smuzhiyun PACFGIB_DEFAULT_CURRENT, device_ref);
1218*4882a593Smuzhiyun if (status)
1219*4882a593Smuzhiyun goto finish;
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun finish:
1222*4882a593Smuzhiyun if (status != MAC_SUCCESS) {
1223*4882a593Smuzhiyun dev_err(
1224*4882a593Smuzhiyun &spi->dev,
1225*4882a593Smuzhiyun "failed to set sfr at %#03x, status = %#03x\n",
1226*4882a593Smuzhiyun sfr_address,
1227*4882a593Smuzhiyun status
1228*4882a593Smuzhiyun );
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun return status;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun /**
1234*4882a593Smuzhiyun * tdme_channelinit() - TDME Channel Register Default Initialisation Macro (Tx)
1235*4882a593Smuzhiyun * @channel: 802.15.4 channel to initialise chip for
1236*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1237*4882a593Smuzhiyun *
1238*4882a593Smuzhiyun * Return: 802.15.4 status code of API calls
1239*4882a593Smuzhiyun */
tdme_channelinit(u8 channel,void * device_ref)1240*4882a593Smuzhiyun static u8 tdme_channelinit(u8 channel, void *device_ref)
1241*4882a593Smuzhiyun {
1242*4882a593Smuzhiyun /* Transceiver front-end local oscillator tx two-point calibration
1243*4882a593Smuzhiyun * value. Tuned for the hardware.
1244*4882a593Smuzhiyun */
1245*4882a593Smuzhiyun u8 txcalval;
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun if (channel >= 25)
1248*4882a593Smuzhiyun txcalval = 0xA7;
1249*4882a593Smuzhiyun else if (channel >= 23)
1250*4882a593Smuzhiyun txcalval = 0xA8;
1251*4882a593Smuzhiyun else if (channel >= 22)
1252*4882a593Smuzhiyun txcalval = 0xA9;
1253*4882a593Smuzhiyun else if (channel >= 20)
1254*4882a593Smuzhiyun txcalval = 0xAA;
1255*4882a593Smuzhiyun else if (channel >= 17)
1256*4882a593Smuzhiyun txcalval = 0xAB;
1257*4882a593Smuzhiyun else if (channel >= 16)
1258*4882a593Smuzhiyun txcalval = 0xAC;
1259*4882a593Smuzhiyun else if (channel >= 14)
1260*4882a593Smuzhiyun txcalval = 0xAD;
1261*4882a593Smuzhiyun else if (channel >= 12)
1262*4882a593Smuzhiyun txcalval = 0xAE;
1263*4882a593Smuzhiyun else
1264*4882a593Smuzhiyun txcalval = 0xAF;
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun return tdme_setsfr_request_sync(
1267*4882a593Smuzhiyun 1,
1268*4882a593Smuzhiyun CA8210_SFR_LOTXCAL,
1269*4882a593Smuzhiyun txcalval,
1270*4882a593Smuzhiyun device_ref
1271*4882a593Smuzhiyun ); /* LO Tx Cal */
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun /**
1275*4882a593Smuzhiyun * tdme_checkpibattribute() - Checks Attribute Values that are not checked in
1276*4882a593Smuzhiyun * MAC
1277*4882a593Smuzhiyun * @pib_attribute: Attribute Number
1278*4882a593Smuzhiyun * @pib_attribute_length: Attribute length
1279*4882a593Smuzhiyun * @pib_attribute_value: Pointer to Attribute Value
1280*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1281*4882a593Smuzhiyun *
1282*4882a593Smuzhiyun * Return: 802.15.4 status code of checks
1283*4882a593Smuzhiyun */
tdme_checkpibattribute(u8 pib_attribute,u8 pib_attribute_length,const void * pib_attribute_value)1284*4882a593Smuzhiyun static u8 tdme_checkpibattribute(
1285*4882a593Smuzhiyun u8 pib_attribute,
1286*4882a593Smuzhiyun u8 pib_attribute_length,
1287*4882a593Smuzhiyun const void *pib_attribute_value
1288*4882a593Smuzhiyun )
1289*4882a593Smuzhiyun {
1290*4882a593Smuzhiyun u8 status = MAC_SUCCESS;
1291*4882a593Smuzhiyun u8 value;
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun value = *((u8 *)pib_attribute_value);
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun switch (pib_attribute) {
1296*4882a593Smuzhiyun /* PHY */
1297*4882a593Smuzhiyun case PHY_TRANSMIT_POWER:
1298*4882a593Smuzhiyun if (value > 0x3F)
1299*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1300*4882a593Smuzhiyun break;
1301*4882a593Smuzhiyun case PHY_CCA_MODE:
1302*4882a593Smuzhiyun if (value > 0x03)
1303*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1304*4882a593Smuzhiyun break;
1305*4882a593Smuzhiyun /* MAC */
1306*4882a593Smuzhiyun case MAC_BATT_LIFE_EXT_PERIODS:
1307*4882a593Smuzhiyun if (value < 6 || value > 41)
1308*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1309*4882a593Smuzhiyun break;
1310*4882a593Smuzhiyun case MAC_BEACON_PAYLOAD:
1311*4882a593Smuzhiyun if (pib_attribute_length > MAX_BEACON_PAYLOAD_LENGTH)
1312*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1313*4882a593Smuzhiyun break;
1314*4882a593Smuzhiyun case MAC_BEACON_PAYLOAD_LENGTH:
1315*4882a593Smuzhiyun if (value > MAX_BEACON_PAYLOAD_LENGTH)
1316*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1317*4882a593Smuzhiyun break;
1318*4882a593Smuzhiyun case MAC_BEACON_ORDER:
1319*4882a593Smuzhiyun if (value > 15)
1320*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1321*4882a593Smuzhiyun break;
1322*4882a593Smuzhiyun case MAC_MAX_BE:
1323*4882a593Smuzhiyun if (value < 3 || value > 8)
1324*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1325*4882a593Smuzhiyun break;
1326*4882a593Smuzhiyun case MAC_MAX_CSMA_BACKOFFS:
1327*4882a593Smuzhiyun if (value > 5)
1328*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1329*4882a593Smuzhiyun break;
1330*4882a593Smuzhiyun case MAC_MAX_FRAME_RETRIES:
1331*4882a593Smuzhiyun if (value > 7)
1332*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1333*4882a593Smuzhiyun break;
1334*4882a593Smuzhiyun case MAC_MIN_BE:
1335*4882a593Smuzhiyun if (value > 8)
1336*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1337*4882a593Smuzhiyun break;
1338*4882a593Smuzhiyun case MAC_RESPONSE_WAIT_TIME:
1339*4882a593Smuzhiyun if (value < 2 || value > 64)
1340*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1341*4882a593Smuzhiyun break;
1342*4882a593Smuzhiyun case MAC_SUPERFRAME_ORDER:
1343*4882a593Smuzhiyun if (value > 15)
1344*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1345*4882a593Smuzhiyun break;
1346*4882a593Smuzhiyun /* boolean */
1347*4882a593Smuzhiyun case MAC_ASSOCIATED_PAN_COORD:
1348*4882a593Smuzhiyun case MAC_ASSOCIATION_PERMIT:
1349*4882a593Smuzhiyun case MAC_AUTO_REQUEST:
1350*4882a593Smuzhiyun case MAC_BATT_LIFE_EXT:
1351*4882a593Smuzhiyun case MAC_GTS_PERMIT:
1352*4882a593Smuzhiyun case MAC_PROMISCUOUS_MODE:
1353*4882a593Smuzhiyun case MAC_RX_ON_WHEN_IDLE:
1354*4882a593Smuzhiyun case MAC_SECURITY_ENABLED:
1355*4882a593Smuzhiyun if (value > 1)
1356*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1357*4882a593Smuzhiyun break;
1358*4882a593Smuzhiyun /* MAC SEC */
1359*4882a593Smuzhiyun case MAC_AUTO_REQUEST_SECURITY_LEVEL:
1360*4882a593Smuzhiyun if (value > 7)
1361*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1362*4882a593Smuzhiyun break;
1363*4882a593Smuzhiyun case MAC_AUTO_REQUEST_KEY_ID_MODE:
1364*4882a593Smuzhiyun if (value > 3)
1365*4882a593Smuzhiyun status = MAC_INVALID_PARAMETER;
1366*4882a593Smuzhiyun break;
1367*4882a593Smuzhiyun default:
1368*4882a593Smuzhiyun break;
1369*4882a593Smuzhiyun }
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun return status;
1372*4882a593Smuzhiyun }
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun /**
1375*4882a593Smuzhiyun * tdme_settxpower() - Sets the tx power for MLME_SET phyTransmitPower
1376*4882a593Smuzhiyun * @txp: Transmit Power
1377*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1378*4882a593Smuzhiyun *
1379*4882a593Smuzhiyun * Normalised to 802.15.4 Definition (6-bit, signed):
1380*4882a593Smuzhiyun * Bit 7-6: not used
1381*4882a593Smuzhiyun * Bit 5-0: tx power (-32 - +31 dB)
1382*4882a593Smuzhiyun *
1383*4882a593Smuzhiyun * Return: 802.15.4 status code of api calls
1384*4882a593Smuzhiyun */
tdme_settxpower(u8 txp,void * device_ref)1385*4882a593Smuzhiyun static u8 tdme_settxpower(u8 txp, void *device_ref)
1386*4882a593Smuzhiyun {
1387*4882a593Smuzhiyun u8 status;
1388*4882a593Smuzhiyun s8 txp_val;
1389*4882a593Smuzhiyun u8 txp_ext;
1390*4882a593Smuzhiyun union pa_cfg_sfr pa_cfg_val;
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun /* extend from 6 to 8 bit */
1393*4882a593Smuzhiyun txp_ext = 0x3F & txp;
1394*4882a593Smuzhiyun if (txp_ext & 0x20)
1395*4882a593Smuzhiyun txp_ext += 0xC0;
1396*4882a593Smuzhiyun txp_val = (s8)txp_ext;
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun if (CA8210_MAC_MPW) {
1399*4882a593Smuzhiyun if (txp_val > 0) {
1400*4882a593Smuzhiyun /* 8 dBm: ptrim = 5, itrim = +3 => +4 dBm */
1401*4882a593Smuzhiyun pa_cfg_val.bias_current_trim = 3;
1402*4882a593Smuzhiyun pa_cfg_val.buffer_capacitor_trim = 5;
1403*4882a593Smuzhiyun pa_cfg_val.boost = 1;
1404*4882a593Smuzhiyun } else {
1405*4882a593Smuzhiyun /* 0 dBm: ptrim = 7, itrim = +3 => -6 dBm */
1406*4882a593Smuzhiyun pa_cfg_val.bias_current_trim = 3;
1407*4882a593Smuzhiyun pa_cfg_val.buffer_capacitor_trim = 7;
1408*4882a593Smuzhiyun pa_cfg_val.boost = 0;
1409*4882a593Smuzhiyun }
1410*4882a593Smuzhiyun /* write PACFG */
1411*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1412*4882a593Smuzhiyun 0,
1413*4882a593Smuzhiyun CA8210_SFR_PACFG,
1414*4882a593Smuzhiyun pa_cfg_val.paib,
1415*4882a593Smuzhiyun device_ref
1416*4882a593Smuzhiyun );
1417*4882a593Smuzhiyun } else {
1418*4882a593Smuzhiyun /* Look-Up Table for Setting Current and Frequency Trim values
1419*4882a593Smuzhiyun * for desired Output Power
1420*4882a593Smuzhiyun */
1421*4882a593Smuzhiyun if (txp_val > 8) {
1422*4882a593Smuzhiyun pa_cfg_val.paib = 0x3F;
1423*4882a593Smuzhiyun } else if (txp_val == 8) {
1424*4882a593Smuzhiyun pa_cfg_val.paib = 0x32;
1425*4882a593Smuzhiyun } else if (txp_val == 7) {
1426*4882a593Smuzhiyun pa_cfg_val.paib = 0x22;
1427*4882a593Smuzhiyun } else if (txp_val == 6) {
1428*4882a593Smuzhiyun pa_cfg_val.paib = 0x18;
1429*4882a593Smuzhiyun } else if (txp_val == 5) {
1430*4882a593Smuzhiyun pa_cfg_val.paib = 0x10;
1431*4882a593Smuzhiyun } else if (txp_val == 4) {
1432*4882a593Smuzhiyun pa_cfg_val.paib = 0x0C;
1433*4882a593Smuzhiyun } else if (txp_val == 3) {
1434*4882a593Smuzhiyun pa_cfg_val.paib = 0x08;
1435*4882a593Smuzhiyun } else if (txp_val == 2) {
1436*4882a593Smuzhiyun pa_cfg_val.paib = 0x05;
1437*4882a593Smuzhiyun } else if (txp_val == 1) {
1438*4882a593Smuzhiyun pa_cfg_val.paib = 0x03;
1439*4882a593Smuzhiyun } else if (txp_val == 0) {
1440*4882a593Smuzhiyun pa_cfg_val.paib = 0x01;
1441*4882a593Smuzhiyun } else { /* < 0 */
1442*4882a593Smuzhiyun pa_cfg_val.paib = 0x00;
1443*4882a593Smuzhiyun }
1444*4882a593Smuzhiyun /* write PACFGIB */
1445*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1446*4882a593Smuzhiyun 0,
1447*4882a593Smuzhiyun CA8210_SFR_PACFGIB,
1448*4882a593Smuzhiyun pa_cfg_val.paib,
1449*4882a593Smuzhiyun device_ref
1450*4882a593Smuzhiyun );
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun
1453*4882a593Smuzhiyun return status;
1454*4882a593Smuzhiyun }
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun /**
1457*4882a593Smuzhiyun * mcps_data_request() - mcps_data_request (Send Data) according to API Spec
1458*4882a593Smuzhiyun * @src_addr_mode: Source Addressing Mode
1459*4882a593Smuzhiyun * @dst_address_mode: Destination Addressing Mode
1460*4882a593Smuzhiyun * @dst_pan_id: Destination PAN ID
1461*4882a593Smuzhiyun * @dst_addr: Pointer to Destination Address
1462*4882a593Smuzhiyun * @msdu_length: length of Data
1463*4882a593Smuzhiyun * @msdu: Pointer to Data
1464*4882a593Smuzhiyun * @msdu_handle: Handle of Data
1465*4882a593Smuzhiyun * @tx_options: Tx Options Bit Field
1466*4882a593Smuzhiyun * @security: Pointer to Security Structure or NULL
1467*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1468*4882a593Smuzhiyun *
1469*4882a593Smuzhiyun * Return: 802.15.4 status code of action
1470*4882a593Smuzhiyun */
mcps_data_request(u8 src_addr_mode,u8 dst_address_mode,u16 dst_pan_id,union macaddr * dst_addr,u8 msdu_length,u8 * msdu,u8 msdu_handle,u8 tx_options,struct secspec * security,void * device_ref)1471*4882a593Smuzhiyun static u8 mcps_data_request(
1472*4882a593Smuzhiyun u8 src_addr_mode,
1473*4882a593Smuzhiyun u8 dst_address_mode,
1474*4882a593Smuzhiyun u16 dst_pan_id,
1475*4882a593Smuzhiyun union macaddr *dst_addr,
1476*4882a593Smuzhiyun u8 msdu_length,
1477*4882a593Smuzhiyun u8 *msdu,
1478*4882a593Smuzhiyun u8 msdu_handle,
1479*4882a593Smuzhiyun u8 tx_options,
1480*4882a593Smuzhiyun struct secspec *security,
1481*4882a593Smuzhiyun void *device_ref
1482*4882a593Smuzhiyun )
1483*4882a593Smuzhiyun {
1484*4882a593Smuzhiyun struct secspec *psec;
1485*4882a593Smuzhiyun struct mac_message command;
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun command.command_id = SPI_MCPS_DATA_REQUEST;
1488*4882a593Smuzhiyun command.pdata.data_req.src_addr_mode = src_addr_mode;
1489*4882a593Smuzhiyun command.pdata.data_req.dst.mode = dst_address_mode;
1490*4882a593Smuzhiyun if (dst_address_mode != MAC_MODE_NO_ADDR) {
1491*4882a593Smuzhiyun command.pdata.data_req.dst.pan_id[0] = LS_BYTE(dst_pan_id);
1492*4882a593Smuzhiyun command.pdata.data_req.dst.pan_id[1] = MS_BYTE(dst_pan_id);
1493*4882a593Smuzhiyun if (dst_address_mode == MAC_MODE_SHORT_ADDR) {
1494*4882a593Smuzhiyun command.pdata.data_req.dst.address[0] = LS_BYTE(
1495*4882a593Smuzhiyun dst_addr->short_address
1496*4882a593Smuzhiyun );
1497*4882a593Smuzhiyun command.pdata.data_req.dst.address[1] = MS_BYTE(
1498*4882a593Smuzhiyun dst_addr->short_address
1499*4882a593Smuzhiyun );
1500*4882a593Smuzhiyun } else { /* MAC_MODE_LONG_ADDR*/
1501*4882a593Smuzhiyun memcpy(
1502*4882a593Smuzhiyun command.pdata.data_req.dst.address,
1503*4882a593Smuzhiyun dst_addr->ieee_address,
1504*4882a593Smuzhiyun 8
1505*4882a593Smuzhiyun );
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun }
1508*4882a593Smuzhiyun command.pdata.data_req.msdu_length = msdu_length;
1509*4882a593Smuzhiyun command.pdata.data_req.msdu_handle = msdu_handle;
1510*4882a593Smuzhiyun command.pdata.data_req.tx_options = tx_options;
1511*4882a593Smuzhiyun memcpy(command.pdata.data_req.msdu, msdu, msdu_length);
1512*4882a593Smuzhiyun psec = (struct secspec *)(command.pdata.data_req.msdu + msdu_length);
1513*4882a593Smuzhiyun command.length = sizeof(struct mcps_data_request_pset) -
1514*4882a593Smuzhiyun MAX_DATA_SIZE + msdu_length;
1515*4882a593Smuzhiyun if (!security || security->security_level == 0) {
1516*4882a593Smuzhiyun psec->security_level = 0;
1517*4882a593Smuzhiyun command.length += 1;
1518*4882a593Smuzhiyun } else {
1519*4882a593Smuzhiyun *psec = *security;
1520*4882a593Smuzhiyun command.length += sizeof(struct secspec);
1521*4882a593Smuzhiyun }
1522*4882a593Smuzhiyun
1523*4882a593Smuzhiyun if (ca8210_spi_transfer(device_ref, &command.command_id,
1524*4882a593Smuzhiyun command.length + 2))
1525*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun return MAC_SUCCESS;
1528*4882a593Smuzhiyun }
1529*4882a593Smuzhiyun
1530*4882a593Smuzhiyun /**
1531*4882a593Smuzhiyun * mlme_reset_request_sync() - MLME_RESET_request/confirm according to API Spec
1532*4882a593Smuzhiyun * @set_default_pib: Set defaults in PIB
1533*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1534*4882a593Smuzhiyun *
1535*4882a593Smuzhiyun * Return: 802.15.4 status code of MLME-RESET.confirm
1536*4882a593Smuzhiyun */
mlme_reset_request_sync(u8 set_default_pib,void * device_ref)1537*4882a593Smuzhiyun static u8 mlme_reset_request_sync(
1538*4882a593Smuzhiyun u8 set_default_pib,
1539*4882a593Smuzhiyun void *device_ref
1540*4882a593Smuzhiyun )
1541*4882a593Smuzhiyun {
1542*4882a593Smuzhiyun u8 status;
1543*4882a593Smuzhiyun struct mac_message command, response;
1544*4882a593Smuzhiyun struct spi_device *spi = device_ref;
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun command.command_id = SPI_MLME_RESET_REQUEST;
1547*4882a593Smuzhiyun command.length = 1;
1548*4882a593Smuzhiyun command.pdata.u8param = set_default_pib;
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun if (cascoda_api_downstream(
1551*4882a593Smuzhiyun &command.command_id,
1552*4882a593Smuzhiyun command.length + 2,
1553*4882a593Smuzhiyun &response.command_id,
1554*4882a593Smuzhiyun device_ref)) {
1555*4882a593Smuzhiyun dev_err(&spi->dev, "cascoda_api_downstream failed\n");
1556*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1557*4882a593Smuzhiyun }
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun if (response.command_id != SPI_MLME_RESET_CONFIRM)
1560*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1561*4882a593Smuzhiyun
1562*4882a593Smuzhiyun status = response.pdata.status;
1563*4882a593Smuzhiyun
1564*4882a593Smuzhiyun /* reset COORD Bit for Channel Filtering as Coordinator */
1565*4882a593Smuzhiyun if (CA8210_MAC_WORKAROUNDS && set_default_pib && !status) {
1566*4882a593Smuzhiyun status = tdme_setsfr_request_sync(
1567*4882a593Smuzhiyun 0,
1568*4882a593Smuzhiyun CA8210_SFR_MACCON,
1569*4882a593Smuzhiyun 0,
1570*4882a593Smuzhiyun device_ref
1571*4882a593Smuzhiyun );
1572*4882a593Smuzhiyun }
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun return status;
1575*4882a593Smuzhiyun }
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun /**
1578*4882a593Smuzhiyun * mlme_set_request_sync() - MLME_SET_request/confirm according to API Spec
1579*4882a593Smuzhiyun * @pib_attribute: Attribute Number
1580*4882a593Smuzhiyun * @pib_attribute_index: Index within Attribute if an Array
1581*4882a593Smuzhiyun * @pib_attribute_length: Attribute length
1582*4882a593Smuzhiyun * @pib_attribute_value: Pointer to Attribute Value
1583*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1584*4882a593Smuzhiyun *
1585*4882a593Smuzhiyun * Return: 802.15.4 status code of MLME-SET.confirm
1586*4882a593Smuzhiyun */
mlme_set_request_sync(u8 pib_attribute,u8 pib_attribute_index,u8 pib_attribute_length,const void * pib_attribute_value,void * device_ref)1587*4882a593Smuzhiyun static u8 mlme_set_request_sync(
1588*4882a593Smuzhiyun u8 pib_attribute,
1589*4882a593Smuzhiyun u8 pib_attribute_index,
1590*4882a593Smuzhiyun u8 pib_attribute_length,
1591*4882a593Smuzhiyun const void *pib_attribute_value,
1592*4882a593Smuzhiyun void *device_ref
1593*4882a593Smuzhiyun )
1594*4882a593Smuzhiyun {
1595*4882a593Smuzhiyun u8 status;
1596*4882a593Smuzhiyun struct mac_message command, response;
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun /* pre-check the validity of pib_attribute values that are not checked
1599*4882a593Smuzhiyun * in MAC
1600*4882a593Smuzhiyun */
1601*4882a593Smuzhiyun if (tdme_checkpibattribute(
1602*4882a593Smuzhiyun pib_attribute, pib_attribute_length, pib_attribute_value)) {
1603*4882a593Smuzhiyun return MAC_INVALID_PARAMETER;
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun if (pib_attribute == PHY_CURRENT_CHANNEL) {
1607*4882a593Smuzhiyun status = tdme_channelinit(
1608*4882a593Smuzhiyun *((u8 *)pib_attribute_value),
1609*4882a593Smuzhiyun device_ref
1610*4882a593Smuzhiyun );
1611*4882a593Smuzhiyun if (status)
1612*4882a593Smuzhiyun return status;
1613*4882a593Smuzhiyun }
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun if (pib_attribute == PHY_TRANSMIT_POWER) {
1616*4882a593Smuzhiyun return tdme_settxpower(
1617*4882a593Smuzhiyun *((u8 *)pib_attribute_value),
1618*4882a593Smuzhiyun device_ref
1619*4882a593Smuzhiyun );
1620*4882a593Smuzhiyun }
1621*4882a593Smuzhiyun
1622*4882a593Smuzhiyun command.command_id = SPI_MLME_SET_REQUEST;
1623*4882a593Smuzhiyun command.length = sizeof(struct mlme_set_request_pset) -
1624*4882a593Smuzhiyun MAX_ATTRIBUTE_SIZE + pib_attribute_length;
1625*4882a593Smuzhiyun command.pdata.set_req.pib_attribute = pib_attribute;
1626*4882a593Smuzhiyun command.pdata.set_req.pib_attribute_index = pib_attribute_index;
1627*4882a593Smuzhiyun command.pdata.set_req.pib_attribute_length = pib_attribute_length;
1628*4882a593Smuzhiyun memcpy(
1629*4882a593Smuzhiyun command.pdata.set_req.pib_attribute_value,
1630*4882a593Smuzhiyun pib_attribute_value,
1631*4882a593Smuzhiyun pib_attribute_length
1632*4882a593Smuzhiyun );
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun if (cascoda_api_downstream(
1635*4882a593Smuzhiyun &command.command_id,
1636*4882a593Smuzhiyun command.length + 2,
1637*4882a593Smuzhiyun &response.command_id,
1638*4882a593Smuzhiyun device_ref)) {
1639*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1640*4882a593Smuzhiyun }
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun if (response.command_id != SPI_MLME_SET_CONFIRM)
1643*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1644*4882a593Smuzhiyun
1645*4882a593Smuzhiyun return response.pdata.status;
1646*4882a593Smuzhiyun }
1647*4882a593Smuzhiyun
1648*4882a593Smuzhiyun /**
1649*4882a593Smuzhiyun * hwme_set_request_sync() - HWME_SET_request/confirm according to API Spec
1650*4882a593Smuzhiyun * @hw_attribute: Attribute Number
1651*4882a593Smuzhiyun * @hw_attribute_length: Attribute length
1652*4882a593Smuzhiyun * @hw_attribute_value: Pointer to Attribute Value
1653*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1654*4882a593Smuzhiyun *
1655*4882a593Smuzhiyun * Return: 802.15.4 status code of HWME-SET.confirm
1656*4882a593Smuzhiyun */
hwme_set_request_sync(u8 hw_attribute,u8 hw_attribute_length,u8 * hw_attribute_value,void * device_ref)1657*4882a593Smuzhiyun static u8 hwme_set_request_sync(
1658*4882a593Smuzhiyun u8 hw_attribute,
1659*4882a593Smuzhiyun u8 hw_attribute_length,
1660*4882a593Smuzhiyun u8 *hw_attribute_value,
1661*4882a593Smuzhiyun void *device_ref
1662*4882a593Smuzhiyun )
1663*4882a593Smuzhiyun {
1664*4882a593Smuzhiyun struct mac_message command, response;
1665*4882a593Smuzhiyun
1666*4882a593Smuzhiyun command.command_id = SPI_HWME_SET_REQUEST;
1667*4882a593Smuzhiyun command.length = 2 + hw_attribute_length;
1668*4882a593Smuzhiyun command.pdata.hwme_set_req.hw_attribute = hw_attribute;
1669*4882a593Smuzhiyun command.pdata.hwme_set_req.hw_attribute_length = hw_attribute_length;
1670*4882a593Smuzhiyun memcpy(
1671*4882a593Smuzhiyun command.pdata.hwme_set_req.hw_attribute_value,
1672*4882a593Smuzhiyun hw_attribute_value,
1673*4882a593Smuzhiyun hw_attribute_length
1674*4882a593Smuzhiyun );
1675*4882a593Smuzhiyun
1676*4882a593Smuzhiyun if (cascoda_api_downstream(
1677*4882a593Smuzhiyun &command.command_id,
1678*4882a593Smuzhiyun command.length + 2,
1679*4882a593Smuzhiyun &response.command_id,
1680*4882a593Smuzhiyun device_ref)) {
1681*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1682*4882a593Smuzhiyun }
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun if (response.command_id != SPI_HWME_SET_CONFIRM)
1685*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun return response.pdata.hwme_set_cnf.status;
1688*4882a593Smuzhiyun }
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun /**
1691*4882a593Smuzhiyun * hwme_get_request_sync() - HWME_GET_request/confirm according to API Spec
1692*4882a593Smuzhiyun * @hw_attribute: Attribute Number
1693*4882a593Smuzhiyun * @hw_attribute_length: Attribute length
1694*4882a593Smuzhiyun * @hw_attribute_value: Pointer to Attribute Value
1695*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
1696*4882a593Smuzhiyun *
1697*4882a593Smuzhiyun * Return: 802.15.4 status code of HWME-GET.confirm
1698*4882a593Smuzhiyun */
hwme_get_request_sync(u8 hw_attribute,u8 * hw_attribute_length,u8 * hw_attribute_value,void * device_ref)1699*4882a593Smuzhiyun static u8 hwme_get_request_sync(
1700*4882a593Smuzhiyun u8 hw_attribute,
1701*4882a593Smuzhiyun u8 *hw_attribute_length,
1702*4882a593Smuzhiyun u8 *hw_attribute_value,
1703*4882a593Smuzhiyun void *device_ref
1704*4882a593Smuzhiyun )
1705*4882a593Smuzhiyun {
1706*4882a593Smuzhiyun struct mac_message command, response;
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun command.command_id = SPI_HWME_GET_REQUEST;
1709*4882a593Smuzhiyun command.length = 1;
1710*4882a593Smuzhiyun command.pdata.hwme_get_req.hw_attribute = hw_attribute;
1711*4882a593Smuzhiyun
1712*4882a593Smuzhiyun if (cascoda_api_downstream(
1713*4882a593Smuzhiyun &command.command_id,
1714*4882a593Smuzhiyun command.length + 2,
1715*4882a593Smuzhiyun &response.command_id,
1716*4882a593Smuzhiyun device_ref)) {
1717*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1718*4882a593Smuzhiyun }
1719*4882a593Smuzhiyun
1720*4882a593Smuzhiyun if (response.command_id != SPI_HWME_GET_CONFIRM)
1721*4882a593Smuzhiyun return MAC_SYSTEM_ERROR;
1722*4882a593Smuzhiyun
1723*4882a593Smuzhiyun if (response.pdata.hwme_get_cnf.status == MAC_SUCCESS) {
1724*4882a593Smuzhiyun *hw_attribute_length =
1725*4882a593Smuzhiyun response.pdata.hwme_get_cnf.hw_attribute_length;
1726*4882a593Smuzhiyun memcpy(
1727*4882a593Smuzhiyun hw_attribute_value,
1728*4882a593Smuzhiyun response.pdata.hwme_get_cnf.hw_attribute_value,
1729*4882a593Smuzhiyun *hw_attribute_length
1730*4882a593Smuzhiyun );
1731*4882a593Smuzhiyun }
1732*4882a593Smuzhiyun
1733*4882a593Smuzhiyun return response.pdata.hwme_get_cnf.status;
1734*4882a593Smuzhiyun }
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun /* Network driver operation */
1737*4882a593Smuzhiyun
1738*4882a593Smuzhiyun /**
1739*4882a593Smuzhiyun * ca8210_async_xmit_complete() - Called to announce that an asynchronous
1740*4882a593Smuzhiyun * transmission has finished
1741*4882a593Smuzhiyun * @hw: ieee802154_hw of ca8210 that has finished exchange
1742*4882a593Smuzhiyun * @msduhandle: Identifier of transmission that has completed
1743*4882a593Smuzhiyun * @status: Returned 802.15.4 status code of the transmission
1744*4882a593Smuzhiyun *
1745*4882a593Smuzhiyun * Return: 0 or linux error code
1746*4882a593Smuzhiyun */
ca8210_async_xmit_complete(struct ieee802154_hw * hw,u8 msduhandle,u8 status)1747*4882a593Smuzhiyun static int ca8210_async_xmit_complete(
1748*4882a593Smuzhiyun struct ieee802154_hw *hw,
1749*4882a593Smuzhiyun u8 msduhandle,
1750*4882a593Smuzhiyun u8 status)
1751*4882a593Smuzhiyun {
1752*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
1753*4882a593Smuzhiyun
1754*4882a593Smuzhiyun if (priv->nextmsduhandle != msduhandle) {
1755*4882a593Smuzhiyun dev_err(
1756*4882a593Smuzhiyun &priv->spi->dev,
1757*4882a593Smuzhiyun "Unexpected msdu_handle on data confirm, Expected %d, got %d\n",
1758*4882a593Smuzhiyun priv->nextmsduhandle,
1759*4882a593Smuzhiyun msduhandle
1760*4882a593Smuzhiyun );
1761*4882a593Smuzhiyun return -EIO;
1762*4882a593Smuzhiyun }
1763*4882a593Smuzhiyun
1764*4882a593Smuzhiyun priv->async_tx_pending = false;
1765*4882a593Smuzhiyun priv->nextmsduhandle++;
1766*4882a593Smuzhiyun
1767*4882a593Smuzhiyun if (status) {
1768*4882a593Smuzhiyun dev_err(
1769*4882a593Smuzhiyun &priv->spi->dev,
1770*4882a593Smuzhiyun "Link transmission unsuccessful, status = %d\n",
1771*4882a593Smuzhiyun status
1772*4882a593Smuzhiyun );
1773*4882a593Smuzhiyun if (status != MAC_TRANSACTION_OVERFLOW) {
1774*4882a593Smuzhiyun dev_kfree_skb_any(priv->tx_skb);
1775*4882a593Smuzhiyun ieee802154_wake_queue(priv->hw);
1776*4882a593Smuzhiyun return 0;
1777*4882a593Smuzhiyun }
1778*4882a593Smuzhiyun }
1779*4882a593Smuzhiyun ieee802154_xmit_complete(priv->hw, priv->tx_skb, true);
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun return 0;
1782*4882a593Smuzhiyun }
1783*4882a593Smuzhiyun
1784*4882a593Smuzhiyun /**
1785*4882a593Smuzhiyun * ca8210_skb_rx() - Contructs a properly framed socket buffer from a received
1786*4882a593Smuzhiyun * MCPS_DATA_indication
1787*4882a593Smuzhiyun * @hw: ieee802154_hw that MCPS_DATA_indication was received by
1788*4882a593Smuzhiyun * @len: length of MCPS_DATA_indication
1789*4882a593Smuzhiyun * @data_ind: Octet array of MCPS_DATA_indication
1790*4882a593Smuzhiyun *
1791*4882a593Smuzhiyun * Called by the spi driver whenever a SAP command is received, this function
1792*4882a593Smuzhiyun * will ascertain whether the command is of interest to the network driver and
1793*4882a593Smuzhiyun * take necessary action.
1794*4882a593Smuzhiyun *
1795*4882a593Smuzhiyun * Return: 0 or linux error code
1796*4882a593Smuzhiyun */
ca8210_skb_rx(struct ieee802154_hw * hw,size_t len,u8 * data_ind)1797*4882a593Smuzhiyun static int ca8210_skb_rx(
1798*4882a593Smuzhiyun struct ieee802154_hw *hw,
1799*4882a593Smuzhiyun size_t len,
1800*4882a593Smuzhiyun u8 *data_ind
1801*4882a593Smuzhiyun )
1802*4882a593Smuzhiyun {
1803*4882a593Smuzhiyun struct ieee802154_hdr hdr;
1804*4882a593Smuzhiyun int msdulen;
1805*4882a593Smuzhiyun int hlen;
1806*4882a593Smuzhiyun u8 mpdulinkquality = data_ind[23];
1807*4882a593Smuzhiyun struct sk_buff *skb;
1808*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun /* Allocate mtu size buffer for every rx packet */
1811*4882a593Smuzhiyun skb = dev_alloc_skb(IEEE802154_MTU + sizeof(hdr));
1812*4882a593Smuzhiyun if (!skb)
1813*4882a593Smuzhiyun return -ENOMEM;
1814*4882a593Smuzhiyun
1815*4882a593Smuzhiyun skb_reserve(skb, sizeof(hdr));
1816*4882a593Smuzhiyun
1817*4882a593Smuzhiyun msdulen = data_ind[22]; /* msdu_length */
1818*4882a593Smuzhiyun if (msdulen > IEEE802154_MTU) {
1819*4882a593Smuzhiyun dev_err(
1820*4882a593Smuzhiyun &priv->spi->dev,
1821*4882a593Smuzhiyun "received erroneously large msdu length!\n"
1822*4882a593Smuzhiyun );
1823*4882a593Smuzhiyun kfree_skb(skb);
1824*4882a593Smuzhiyun return -EMSGSIZE;
1825*4882a593Smuzhiyun }
1826*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "skb buffer length = %d\n", msdulen);
1827*4882a593Smuzhiyun
1828*4882a593Smuzhiyun if (priv->promiscuous)
1829*4882a593Smuzhiyun goto copy_payload;
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun /* Populate hdr */
1832*4882a593Smuzhiyun hdr.sec.level = data_ind[29 + msdulen];
1833*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "security level: %#03x\n", hdr.sec.level);
1834*4882a593Smuzhiyun if (hdr.sec.level > 0) {
1835*4882a593Smuzhiyun hdr.sec.key_id_mode = data_ind[30 + msdulen];
1836*4882a593Smuzhiyun memcpy(&hdr.sec.extended_src, &data_ind[31 + msdulen], 8);
1837*4882a593Smuzhiyun hdr.sec.key_id = data_ind[39 + msdulen];
1838*4882a593Smuzhiyun }
1839*4882a593Smuzhiyun hdr.source.mode = data_ind[0];
1840*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "srcAddrMode: %#03x\n", hdr.source.mode);
1841*4882a593Smuzhiyun hdr.source.pan_id = *(u16 *)&data_ind[1];
1842*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "srcPanId: %#06x\n", hdr.source.pan_id);
1843*4882a593Smuzhiyun memcpy(&hdr.source.extended_addr, &data_ind[3], 8);
1844*4882a593Smuzhiyun hdr.dest.mode = data_ind[11];
1845*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "dstAddrMode: %#03x\n", hdr.dest.mode);
1846*4882a593Smuzhiyun hdr.dest.pan_id = *(u16 *)&data_ind[12];
1847*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "dstPanId: %#06x\n", hdr.dest.pan_id);
1848*4882a593Smuzhiyun memcpy(&hdr.dest.extended_addr, &data_ind[14], 8);
1849*4882a593Smuzhiyun
1850*4882a593Smuzhiyun /* Fill in FC implicitly */
1851*4882a593Smuzhiyun hdr.fc.type = 1; /* Data frame */
1852*4882a593Smuzhiyun if (hdr.sec.level)
1853*4882a593Smuzhiyun hdr.fc.security_enabled = 1;
1854*4882a593Smuzhiyun else
1855*4882a593Smuzhiyun hdr.fc.security_enabled = 0;
1856*4882a593Smuzhiyun if (data_ind[1] != data_ind[12] || data_ind[2] != data_ind[13])
1857*4882a593Smuzhiyun hdr.fc.intra_pan = 1;
1858*4882a593Smuzhiyun else
1859*4882a593Smuzhiyun hdr.fc.intra_pan = 0;
1860*4882a593Smuzhiyun hdr.fc.dest_addr_mode = hdr.dest.mode;
1861*4882a593Smuzhiyun hdr.fc.source_addr_mode = hdr.source.mode;
1862*4882a593Smuzhiyun
1863*4882a593Smuzhiyun /* Add hdr to front of buffer */
1864*4882a593Smuzhiyun hlen = ieee802154_hdr_push(skb, &hdr);
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun if (hlen < 0) {
1867*4882a593Smuzhiyun dev_crit(&priv->spi->dev, "failed to push mac hdr onto skb!\n");
1868*4882a593Smuzhiyun kfree_skb(skb);
1869*4882a593Smuzhiyun return hlen;
1870*4882a593Smuzhiyun }
1871*4882a593Smuzhiyun
1872*4882a593Smuzhiyun skb_reset_mac_header(skb);
1873*4882a593Smuzhiyun skb->mac_len = hlen;
1874*4882a593Smuzhiyun
1875*4882a593Smuzhiyun copy_payload:
1876*4882a593Smuzhiyun /* Add <msdulen> bytes of space to the back of the buffer */
1877*4882a593Smuzhiyun /* Copy msdu to skb */
1878*4882a593Smuzhiyun skb_put_data(skb, &data_ind[29], msdulen);
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun ieee802154_rx_irqsafe(hw, skb, mpdulinkquality);
1881*4882a593Smuzhiyun return 0;
1882*4882a593Smuzhiyun }
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun /**
1885*4882a593Smuzhiyun * ca8210_net_rx() - Acts upon received SAP commands relevant to the network
1886*4882a593Smuzhiyun * driver
1887*4882a593Smuzhiyun * @hw: ieee802154_hw that command was received by
1888*4882a593Smuzhiyun * @command: Octet array of received command
1889*4882a593Smuzhiyun * @len: length of the received command
1890*4882a593Smuzhiyun *
1891*4882a593Smuzhiyun * Called by the spi driver whenever a SAP command is received, this function
1892*4882a593Smuzhiyun * will ascertain whether the command is of interest to the network driver and
1893*4882a593Smuzhiyun * take necessary action.
1894*4882a593Smuzhiyun *
1895*4882a593Smuzhiyun * Return: 0 or linux error code
1896*4882a593Smuzhiyun */
ca8210_net_rx(struct ieee802154_hw * hw,u8 * command,size_t len)1897*4882a593Smuzhiyun static int ca8210_net_rx(struct ieee802154_hw *hw, u8 *command, size_t len)
1898*4882a593Smuzhiyun {
1899*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
1900*4882a593Smuzhiyun unsigned long flags;
1901*4882a593Smuzhiyun u8 status;
1902*4882a593Smuzhiyun
1903*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "%s: CmdID = %d\n", __func__, command[0]);
1904*4882a593Smuzhiyun
1905*4882a593Smuzhiyun if (command[0] == SPI_MCPS_DATA_INDICATION) {
1906*4882a593Smuzhiyun /* Received data */
1907*4882a593Smuzhiyun spin_lock_irqsave(&priv->lock, flags);
1908*4882a593Smuzhiyun if (command[26] == priv->last_dsn) {
1909*4882a593Smuzhiyun dev_dbg(
1910*4882a593Smuzhiyun &priv->spi->dev,
1911*4882a593Smuzhiyun "DSN %d resend received, ignoring...\n",
1912*4882a593Smuzhiyun command[26]
1913*4882a593Smuzhiyun );
1914*4882a593Smuzhiyun spin_unlock_irqrestore(&priv->lock, flags);
1915*4882a593Smuzhiyun return 0;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun priv->last_dsn = command[26];
1918*4882a593Smuzhiyun spin_unlock_irqrestore(&priv->lock, flags);
1919*4882a593Smuzhiyun return ca8210_skb_rx(hw, len - 2, command + 2);
1920*4882a593Smuzhiyun } else if (command[0] == SPI_MCPS_DATA_CONFIRM) {
1921*4882a593Smuzhiyun status = command[3];
1922*4882a593Smuzhiyun if (priv->async_tx_pending) {
1923*4882a593Smuzhiyun return ca8210_async_xmit_complete(
1924*4882a593Smuzhiyun hw,
1925*4882a593Smuzhiyun command[2],
1926*4882a593Smuzhiyun status
1927*4882a593Smuzhiyun );
1928*4882a593Smuzhiyun }
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun
1931*4882a593Smuzhiyun return 0;
1932*4882a593Smuzhiyun }
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun /**
1935*4882a593Smuzhiyun * ca8210_skb_tx() - Transmits a given socket buffer using the ca8210
1936*4882a593Smuzhiyun * @skb: Socket buffer to transmit
1937*4882a593Smuzhiyun * @msduhandle: Data identifier to pass to the 802.15.4 MAC
1938*4882a593Smuzhiyun * @priv: Pointer to private data section of target ca8210
1939*4882a593Smuzhiyun *
1940*4882a593Smuzhiyun * Return: 0 or linux error code
1941*4882a593Smuzhiyun */
ca8210_skb_tx(struct sk_buff * skb,u8 msduhandle,struct ca8210_priv * priv)1942*4882a593Smuzhiyun static int ca8210_skb_tx(
1943*4882a593Smuzhiyun struct sk_buff *skb,
1944*4882a593Smuzhiyun u8 msduhandle,
1945*4882a593Smuzhiyun struct ca8210_priv *priv
1946*4882a593Smuzhiyun )
1947*4882a593Smuzhiyun {
1948*4882a593Smuzhiyun int status;
1949*4882a593Smuzhiyun struct ieee802154_hdr header = { };
1950*4882a593Smuzhiyun struct secspec secspec;
1951*4882a593Smuzhiyun unsigned int mac_len;
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "%s called\n", __func__);
1954*4882a593Smuzhiyun
1955*4882a593Smuzhiyun /* Get addressing info from skb - ieee802154 layer creates a full
1956*4882a593Smuzhiyun * packet
1957*4882a593Smuzhiyun */
1958*4882a593Smuzhiyun mac_len = ieee802154_hdr_peek_addrs(skb, &header);
1959*4882a593Smuzhiyun
1960*4882a593Smuzhiyun secspec.security_level = header.sec.level;
1961*4882a593Smuzhiyun secspec.key_id_mode = header.sec.key_id_mode;
1962*4882a593Smuzhiyun if (secspec.key_id_mode == 2)
1963*4882a593Smuzhiyun memcpy(secspec.key_source, &header.sec.short_src, 4);
1964*4882a593Smuzhiyun else if (secspec.key_id_mode == 3)
1965*4882a593Smuzhiyun memcpy(secspec.key_source, &header.sec.extended_src, 8);
1966*4882a593Smuzhiyun secspec.key_index = header.sec.key_id;
1967*4882a593Smuzhiyun
1968*4882a593Smuzhiyun /* Pass to Cascoda API */
1969*4882a593Smuzhiyun status = mcps_data_request(
1970*4882a593Smuzhiyun header.source.mode,
1971*4882a593Smuzhiyun header.dest.mode,
1972*4882a593Smuzhiyun header.dest.pan_id,
1973*4882a593Smuzhiyun (union macaddr *)&header.dest.extended_addr,
1974*4882a593Smuzhiyun skb->len - mac_len,
1975*4882a593Smuzhiyun &skb->data[mac_len],
1976*4882a593Smuzhiyun msduhandle,
1977*4882a593Smuzhiyun header.fc.ack_request,
1978*4882a593Smuzhiyun &secspec,
1979*4882a593Smuzhiyun priv->spi
1980*4882a593Smuzhiyun );
1981*4882a593Smuzhiyun return link_to_linux_err(status);
1982*4882a593Smuzhiyun }
1983*4882a593Smuzhiyun
1984*4882a593Smuzhiyun /**
1985*4882a593Smuzhiyun * ca8210_start() - Starts the network driver
1986*4882a593Smuzhiyun * @hw: ieee802154_hw of ca8210 being started
1987*4882a593Smuzhiyun *
1988*4882a593Smuzhiyun * Return: 0 or linux error code
1989*4882a593Smuzhiyun */
ca8210_start(struct ieee802154_hw * hw)1990*4882a593Smuzhiyun static int ca8210_start(struct ieee802154_hw *hw)
1991*4882a593Smuzhiyun {
1992*4882a593Smuzhiyun int status;
1993*4882a593Smuzhiyun u8 rx_on_when_idle;
1994*4882a593Smuzhiyun u8 lqi_threshold = 0;
1995*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
1996*4882a593Smuzhiyun
1997*4882a593Smuzhiyun priv->last_dsn = -1;
1998*4882a593Smuzhiyun /* Turn receiver on when idle for now just to test rx */
1999*4882a593Smuzhiyun rx_on_when_idle = 1;
2000*4882a593Smuzhiyun status = mlme_set_request_sync(
2001*4882a593Smuzhiyun MAC_RX_ON_WHEN_IDLE,
2002*4882a593Smuzhiyun 0,
2003*4882a593Smuzhiyun 1,
2004*4882a593Smuzhiyun &rx_on_when_idle,
2005*4882a593Smuzhiyun priv->spi
2006*4882a593Smuzhiyun );
2007*4882a593Smuzhiyun if (status) {
2008*4882a593Smuzhiyun dev_crit(
2009*4882a593Smuzhiyun &priv->spi->dev,
2010*4882a593Smuzhiyun "Setting rx_on_when_idle failed, status = %d\n",
2011*4882a593Smuzhiyun status
2012*4882a593Smuzhiyun );
2013*4882a593Smuzhiyun return link_to_linux_err(status);
2014*4882a593Smuzhiyun }
2015*4882a593Smuzhiyun status = hwme_set_request_sync(
2016*4882a593Smuzhiyun HWME_LQILIMIT,
2017*4882a593Smuzhiyun 1,
2018*4882a593Smuzhiyun &lqi_threshold,
2019*4882a593Smuzhiyun priv->spi
2020*4882a593Smuzhiyun );
2021*4882a593Smuzhiyun if (status) {
2022*4882a593Smuzhiyun dev_crit(
2023*4882a593Smuzhiyun &priv->spi->dev,
2024*4882a593Smuzhiyun "Setting lqilimit failed, status = %d\n",
2025*4882a593Smuzhiyun status
2026*4882a593Smuzhiyun );
2027*4882a593Smuzhiyun return link_to_linux_err(status);
2028*4882a593Smuzhiyun }
2029*4882a593Smuzhiyun
2030*4882a593Smuzhiyun return 0;
2031*4882a593Smuzhiyun }
2032*4882a593Smuzhiyun
2033*4882a593Smuzhiyun /**
2034*4882a593Smuzhiyun * ca8210_stop() - Stops the network driver
2035*4882a593Smuzhiyun * @hw: ieee802154_hw of ca8210 being stopped
2036*4882a593Smuzhiyun *
2037*4882a593Smuzhiyun * Return: 0 or linux error code
2038*4882a593Smuzhiyun */
ca8210_stop(struct ieee802154_hw * hw)2039*4882a593Smuzhiyun static void ca8210_stop(struct ieee802154_hw *hw)
2040*4882a593Smuzhiyun {
2041*4882a593Smuzhiyun }
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun /**
2044*4882a593Smuzhiyun * ca8210_xmit_async() - Asynchronously transmits a given socket buffer using
2045*4882a593Smuzhiyun * the ca8210
2046*4882a593Smuzhiyun * @hw: ieee802154_hw of ca8210 to transmit from
2047*4882a593Smuzhiyun * @skb: Socket buffer to transmit
2048*4882a593Smuzhiyun *
2049*4882a593Smuzhiyun * Return: 0 or linux error code
2050*4882a593Smuzhiyun */
ca8210_xmit_async(struct ieee802154_hw * hw,struct sk_buff * skb)2051*4882a593Smuzhiyun static int ca8210_xmit_async(struct ieee802154_hw *hw, struct sk_buff *skb)
2052*4882a593Smuzhiyun {
2053*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2054*4882a593Smuzhiyun int status;
2055*4882a593Smuzhiyun
2056*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "calling %s\n", __func__);
2057*4882a593Smuzhiyun
2058*4882a593Smuzhiyun priv->tx_skb = skb;
2059*4882a593Smuzhiyun priv->async_tx_pending = true;
2060*4882a593Smuzhiyun status = ca8210_skb_tx(skb, priv->nextmsduhandle, priv);
2061*4882a593Smuzhiyun return status;
2062*4882a593Smuzhiyun }
2063*4882a593Smuzhiyun
2064*4882a593Smuzhiyun /**
2065*4882a593Smuzhiyun * ca8210_get_ed() - Returns the measured energy on the current channel at this
2066*4882a593Smuzhiyun * instant in time
2067*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2068*4882a593Smuzhiyun * @level: Measured Energy Detect level
2069*4882a593Smuzhiyun *
2070*4882a593Smuzhiyun * Return: 0 or linux error code
2071*4882a593Smuzhiyun */
ca8210_get_ed(struct ieee802154_hw * hw,u8 * level)2072*4882a593Smuzhiyun static int ca8210_get_ed(struct ieee802154_hw *hw, u8 *level)
2073*4882a593Smuzhiyun {
2074*4882a593Smuzhiyun u8 lenvar;
2075*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2076*4882a593Smuzhiyun
2077*4882a593Smuzhiyun return link_to_linux_err(
2078*4882a593Smuzhiyun hwme_get_request_sync(HWME_EDVALUE, &lenvar, level, priv->spi)
2079*4882a593Smuzhiyun );
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun
2082*4882a593Smuzhiyun /**
2083*4882a593Smuzhiyun * ca8210_set_channel() - Sets the current operating 802.15.4 channel of the
2084*4882a593Smuzhiyun * ca8210
2085*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2086*4882a593Smuzhiyun * @page: Channel page to set
2087*4882a593Smuzhiyun * @channel: Channel number to set
2088*4882a593Smuzhiyun *
2089*4882a593Smuzhiyun * Return: 0 or linux error code
2090*4882a593Smuzhiyun */
ca8210_set_channel(struct ieee802154_hw * hw,u8 page,u8 channel)2091*4882a593Smuzhiyun static int ca8210_set_channel(
2092*4882a593Smuzhiyun struct ieee802154_hw *hw,
2093*4882a593Smuzhiyun u8 page,
2094*4882a593Smuzhiyun u8 channel
2095*4882a593Smuzhiyun )
2096*4882a593Smuzhiyun {
2097*4882a593Smuzhiyun u8 status;
2098*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2099*4882a593Smuzhiyun
2100*4882a593Smuzhiyun status = mlme_set_request_sync(
2101*4882a593Smuzhiyun PHY_CURRENT_CHANNEL,
2102*4882a593Smuzhiyun 0,
2103*4882a593Smuzhiyun 1,
2104*4882a593Smuzhiyun &channel,
2105*4882a593Smuzhiyun priv->spi
2106*4882a593Smuzhiyun );
2107*4882a593Smuzhiyun if (status) {
2108*4882a593Smuzhiyun dev_err(
2109*4882a593Smuzhiyun &priv->spi->dev,
2110*4882a593Smuzhiyun "error setting channel, MLME-SET.confirm status = %d\n",
2111*4882a593Smuzhiyun status
2112*4882a593Smuzhiyun );
2113*4882a593Smuzhiyun }
2114*4882a593Smuzhiyun return link_to_linux_err(status);
2115*4882a593Smuzhiyun }
2116*4882a593Smuzhiyun
2117*4882a593Smuzhiyun /**
2118*4882a593Smuzhiyun * ca8210_set_hw_addr_filt() - Sets the address filtering parameters of the
2119*4882a593Smuzhiyun * ca8210
2120*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2121*4882a593Smuzhiyun * @filt: Filtering parameters
2122*4882a593Smuzhiyun * @changed: Bitmap representing which parameters to change
2123*4882a593Smuzhiyun *
2124*4882a593Smuzhiyun * Effectively just sets the actual addressing information identifying this node
2125*4882a593Smuzhiyun * as all filtering is performed by the ca8210 as detailed in the IEEE 802.15.4
2126*4882a593Smuzhiyun * 2006 specification.
2127*4882a593Smuzhiyun *
2128*4882a593Smuzhiyun * Return: 0 or linux error code
2129*4882a593Smuzhiyun */
ca8210_set_hw_addr_filt(struct ieee802154_hw * hw,struct ieee802154_hw_addr_filt * filt,unsigned long changed)2130*4882a593Smuzhiyun static int ca8210_set_hw_addr_filt(
2131*4882a593Smuzhiyun struct ieee802154_hw *hw,
2132*4882a593Smuzhiyun struct ieee802154_hw_addr_filt *filt,
2133*4882a593Smuzhiyun unsigned long changed
2134*4882a593Smuzhiyun )
2135*4882a593Smuzhiyun {
2136*4882a593Smuzhiyun u8 status = 0;
2137*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun if (changed & IEEE802154_AFILT_PANID_CHANGED) {
2140*4882a593Smuzhiyun status = mlme_set_request_sync(
2141*4882a593Smuzhiyun MAC_PAN_ID,
2142*4882a593Smuzhiyun 0,
2143*4882a593Smuzhiyun 2,
2144*4882a593Smuzhiyun &filt->pan_id, priv->spi
2145*4882a593Smuzhiyun );
2146*4882a593Smuzhiyun if (status) {
2147*4882a593Smuzhiyun dev_err(
2148*4882a593Smuzhiyun &priv->spi->dev,
2149*4882a593Smuzhiyun "error setting pan id, MLME-SET.confirm status = %d",
2150*4882a593Smuzhiyun status
2151*4882a593Smuzhiyun );
2152*4882a593Smuzhiyun return link_to_linux_err(status);
2153*4882a593Smuzhiyun }
2154*4882a593Smuzhiyun }
2155*4882a593Smuzhiyun if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
2156*4882a593Smuzhiyun status = mlme_set_request_sync(
2157*4882a593Smuzhiyun MAC_SHORT_ADDRESS,
2158*4882a593Smuzhiyun 0,
2159*4882a593Smuzhiyun 2,
2160*4882a593Smuzhiyun &filt->short_addr, priv->spi
2161*4882a593Smuzhiyun );
2162*4882a593Smuzhiyun if (status) {
2163*4882a593Smuzhiyun dev_err(
2164*4882a593Smuzhiyun &priv->spi->dev,
2165*4882a593Smuzhiyun "error setting short address, MLME-SET.confirm status = %d",
2166*4882a593Smuzhiyun status
2167*4882a593Smuzhiyun );
2168*4882a593Smuzhiyun return link_to_linux_err(status);
2169*4882a593Smuzhiyun }
2170*4882a593Smuzhiyun }
2171*4882a593Smuzhiyun if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
2172*4882a593Smuzhiyun status = mlme_set_request_sync(
2173*4882a593Smuzhiyun NS_IEEE_ADDRESS,
2174*4882a593Smuzhiyun 0,
2175*4882a593Smuzhiyun 8,
2176*4882a593Smuzhiyun &filt->ieee_addr,
2177*4882a593Smuzhiyun priv->spi
2178*4882a593Smuzhiyun );
2179*4882a593Smuzhiyun if (status) {
2180*4882a593Smuzhiyun dev_err(
2181*4882a593Smuzhiyun &priv->spi->dev,
2182*4882a593Smuzhiyun "error setting ieee address, MLME-SET.confirm status = %d",
2183*4882a593Smuzhiyun status
2184*4882a593Smuzhiyun );
2185*4882a593Smuzhiyun return link_to_linux_err(status);
2186*4882a593Smuzhiyun }
2187*4882a593Smuzhiyun }
2188*4882a593Smuzhiyun /* TODO: Should use MLME_START to set coord bit? */
2189*4882a593Smuzhiyun return 0;
2190*4882a593Smuzhiyun }
2191*4882a593Smuzhiyun
2192*4882a593Smuzhiyun /**
2193*4882a593Smuzhiyun * ca8210_set_tx_power() - Sets the transmit power of the ca8210
2194*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2195*4882a593Smuzhiyun * @mbm: Transmit power in mBm (dBm*100)
2196*4882a593Smuzhiyun *
2197*4882a593Smuzhiyun * Return: 0 or linux error code
2198*4882a593Smuzhiyun */
ca8210_set_tx_power(struct ieee802154_hw * hw,s32 mbm)2199*4882a593Smuzhiyun static int ca8210_set_tx_power(struct ieee802154_hw *hw, s32 mbm)
2200*4882a593Smuzhiyun {
2201*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2202*4882a593Smuzhiyun
2203*4882a593Smuzhiyun mbm /= 100;
2204*4882a593Smuzhiyun return link_to_linux_err(
2205*4882a593Smuzhiyun mlme_set_request_sync(PHY_TRANSMIT_POWER, 0, 1, &mbm, priv->spi)
2206*4882a593Smuzhiyun );
2207*4882a593Smuzhiyun }
2208*4882a593Smuzhiyun
2209*4882a593Smuzhiyun /**
2210*4882a593Smuzhiyun * ca8210_set_cca_mode() - Sets the clear channel assessment mode of the ca8210
2211*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2212*4882a593Smuzhiyun * @cca: CCA mode to set
2213*4882a593Smuzhiyun *
2214*4882a593Smuzhiyun * Return: 0 or linux error code
2215*4882a593Smuzhiyun */
ca8210_set_cca_mode(struct ieee802154_hw * hw,const struct wpan_phy_cca * cca)2216*4882a593Smuzhiyun static int ca8210_set_cca_mode(
2217*4882a593Smuzhiyun struct ieee802154_hw *hw,
2218*4882a593Smuzhiyun const struct wpan_phy_cca *cca
2219*4882a593Smuzhiyun )
2220*4882a593Smuzhiyun {
2221*4882a593Smuzhiyun u8 status;
2222*4882a593Smuzhiyun u8 cca_mode;
2223*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2224*4882a593Smuzhiyun
2225*4882a593Smuzhiyun cca_mode = cca->mode & 3;
2226*4882a593Smuzhiyun if (cca_mode == 3 && cca->opt == NL802154_CCA_OPT_ENERGY_CARRIER_OR) {
2227*4882a593Smuzhiyun /* cca_mode 0 == CS OR ED, 3 == CS AND ED */
2228*4882a593Smuzhiyun cca_mode = 0;
2229*4882a593Smuzhiyun }
2230*4882a593Smuzhiyun status = mlme_set_request_sync(
2231*4882a593Smuzhiyun PHY_CCA_MODE,
2232*4882a593Smuzhiyun 0,
2233*4882a593Smuzhiyun 1,
2234*4882a593Smuzhiyun &cca_mode,
2235*4882a593Smuzhiyun priv->spi
2236*4882a593Smuzhiyun );
2237*4882a593Smuzhiyun if (status) {
2238*4882a593Smuzhiyun dev_err(
2239*4882a593Smuzhiyun &priv->spi->dev,
2240*4882a593Smuzhiyun "error setting cca mode, MLME-SET.confirm status = %d",
2241*4882a593Smuzhiyun status
2242*4882a593Smuzhiyun );
2243*4882a593Smuzhiyun }
2244*4882a593Smuzhiyun return link_to_linux_err(status);
2245*4882a593Smuzhiyun }
2246*4882a593Smuzhiyun
2247*4882a593Smuzhiyun /**
2248*4882a593Smuzhiyun * ca8210_set_cca_ed_level() - Sets the CCA ED level of the ca8210
2249*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2250*4882a593Smuzhiyun * @level: ED level to set (in mbm)
2251*4882a593Smuzhiyun *
2252*4882a593Smuzhiyun * Sets the minimum threshold of measured energy above which the ca8210 will
2253*4882a593Smuzhiyun * back off and retry a transmission.
2254*4882a593Smuzhiyun *
2255*4882a593Smuzhiyun * Return: 0 or linux error code
2256*4882a593Smuzhiyun */
ca8210_set_cca_ed_level(struct ieee802154_hw * hw,s32 level)2257*4882a593Smuzhiyun static int ca8210_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
2258*4882a593Smuzhiyun {
2259*4882a593Smuzhiyun u8 status;
2260*4882a593Smuzhiyun u8 ed_threshold = (level / 100) * 2 + 256;
2261*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2262*4882a593Smuzhiyun
2263*4882a593Smuzhiyun status = hwme_set_request_sync(
2264*4882a593Smuzhiyun HWME_EDTHRESHOLD,
2265*4882a593Smuzhiyun 1,
2266*4882a593Smuzhiyun &ed_threshold,
2267*4882a593Smuzhiyun priv->spi
2268*4882a593Smuzhiyun );
2269*4882a593Smuzhiyun if (status) {
2270*4882a593Smuzhiyun dev_err(
2271*4882a593Smuzhiyun &priv->spi->dev,
2272*4882a593Smuzhiyun "error setting ed threshold, HWME-SET.confirm status = %d",
2273*4882a593Smuzhiyun status
2274*4882a593Smuzhiyun );
2275*4882a593Smuzhiyun }
2276*4882a593Smuzhiyun return link_to_linux_err(status);
2277*4882a593Smuzhiyun }
2278*4882a593Smuzhiyun
2279*4882a593Smuzhiyun /**
2280*4882a593Smuzhiyun * ca8210_set_csma_params() - Sets the CSMA parameters of the ca8210
2281*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2282*4882a593Smuzhiyun * @min_be: Minimum backoff exponent when backing off a transmission
2283*4882a593Smuzhiyun * @max_be: Maximum backoff exponent when backing off a transmission
2284*4882a593Smuzhiyun * @retries: Number of times to retry after backing off
2285*4882a593Smuzhiyun *
2286*4882a593Smuzhiyun * Return: 0 or linux error code
2287*4882a593Smuzhiyun */
ca8210_set_csma_params(struct ieee802154_hw * hw,u8 min_be,u8 max_be,u8 retries)2288*4882a593Smuzhiyun static int ca8210_set_csma_params(
2289*4882a593Smuzhiyun struct ieee802154_hw *hw,
2290*4882a593Smuzhiyun u8 min_be,
2291*4882a593Smuzhiyun u8 max_be,
2292*4882a593Smuzhiyun u8 retries
2293*4882a593Smuzhiyun )
2294*4882a593Smuzhiyun {
2295*4882a593Smuzhiyun u8 status;
2296*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2297*4882a593Smuzhiyun
2298*4882a593Smuzhiyun status = mlme_set_request_sync(MAC_MIN_BE, 0, 1, &min_be, priv->spi);
2299*4882a593Smuzhiyun if (status) {
2300*4882a593Smuzhiyun dev_err(
2301*4882a593Smuzhiyun &priv->spi->dev,
2302*4882a593Smuzhiyun "error setting min be, MLME-SET.confirm status = %d",
2303*4882a593Smuzhiyun status
2304*4882a593Smuzhiyun );
2305*4882a593Smuzhiyun return link_to_linux_err(status);
2306*4882a593Smuzhiyun }
2307*4882a593Smuzhiyun status = mlme_set_request_sync(MAC_MAX_BE, 0, 1, &max_be, priv->spi);
2308*4882a593Smuzhiyun if (status) {
2309*4882a593Smuzhiyun dev_err(
2310*4882a593Smuzhiyun &priv->spi->dev,
2311*4882a593Smuzhiyun "error setting max be, MLME-SET.confirm status = %d",
2312*4882a593Smuzhiyun status
2313*4882a593Smuzhiyun );
2314*4882a593Smuzhiyun return link_to_linux_err(status);
2315*4882a593Smuzhiyun }
2316*4882a593Smuzhiyun status = mlme_set_request_sync(
2317*4882a593Smuzhiyun MAC_MAX_CSMA_BACKOFFS,
2318*4882a593Smuzhiyun 0,
2319*4882a593Smuzhiyun 1,
2320*4882a593Smuzhiyun &retries,
2321*4882a593Smuzhiyun priv->spi
2322*4882a593Smuzhiyun );
2323*4882a593Smuzhiyun if (status) {
2324*4882a593Smuzhiyun dev_err(
2325*4882a593Smuzhiyun &priv->spi->dev,
2326*4882a593Smuzhiyun "error setting max csma backoffs, MLME-SET.confirm status = %d",
2327*4882a593Smuzhiyun status
2328*4882a593Smuzhiyun );
2329*4882a593Smuzhiyun }
2330*4882a593Smuzhiyun return link_to_linux_err(status);
2331*4882a593Smuzhiyun }
2332*4882a593Smuzhiyun
2333*4882a593Smuzhiyun /**
2334*4882a593Smuzhiyun * ca8210_set_frame_retries() - Sets the maximum frame retries of the ca8210
2335*4882a593Smuzhiyun * @hw: ieee802154_hw of target ca8210
2336*4882a593Smuzhiyun * @retries: Number of retries
2337*4882a593Smuzhiyun *
2338*4882a593Smuzhiyun * Sets the number of times to retry a transmission if no acknowledgment was
2339*4882a593Smuzhiyun * was received from the other end when one was requested.
2340*4882a593Smuzhiyun *
2341*4882a593Smuzhiyun * Return: 0 or linux error code
2342*4882a593Smuzhiyun */
ca8210_set_frame_retries(struct ieee802154_hw * hw,s8 retries)2343*4882a593Smuzhiyun static int ca8210_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
2344*4882a593Smuzhiyun {
2345*4882a593Smuzhiyun u8 status;
2346*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2347*4882a593Smuzhiyun
2348*4882a593Smuzhiyun status = mlme_set_request_sync(
2349*4882a593Smuzhiyun MAC_MAX_FRAME_RETRIES,
2350*4882a593Smuzhiyun 0,
2351*4882a593Smuzhiyun 1,
2352*4882a593Smuzhiyun &retries,
2353*4882a593Smuzhiyun priv->spi
2354*4882a593Smuzhiyun );
2355*4882a593Smuzhiyun if (status) {
2356*4882a593Smuzhiyun dev_err(
2357*4882a593Smuzhiyun &priv->spi->dev,
2358*4882a593Smuzhiyun "error setting frame retries, MLME-SET.confirm status = %d",
2359*4882a593Smuzhiyun status
2360*4882a593Smuzhiyun );
2361*4882a593Smuzhiyun }
2362*4882a593Smuzhiyun return link_to_linux_err(status);
2363*4882a593Smuzhiyun }
2364*4882a593Smuzhiyun
ca8210_set_promiscuous_mode(struct ieee802154_hw * hw,const bool on)2365*4882a593Smuzhiyun static int ca8210_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
2366*4882a593Smuzhiyun {
2367*4882a593Smuzhiyun u8 status;
2368*4882a593Smuzhiyun struct ca8210_priv *priv = hw->priv;
2369*4882a593Smuzhiyun
2370*4882a593Smuzhiyun status = mlme_set_request_sync(
2371*4882a593Smuzhiyun MAC_PROMISCUOUS_MODE,
2372*4882a593Smuzhiyun 0,
2373*4882a593Smuzhiyun 1,
2374*4882a593Smuzhiyun (const void *)&on,
2375*4882a593Smuzhiyun priv->spi
2376*4882a593Smuzhiyun );
2377*4882a593Smuzhiyun if (status) {
2378*4882a593Smuzhiyun dev_err(
2379*4882a593Smuzhiyun &priv->spi->dev,
2380*4882a593Smuzhiyun "error setting promiscuous mode, MLME-SET.confirm status = %d",
2381*4882a593Smuzhiyun status
2382*4882a593Smuzhiyun );
2383*4882a593Smuzhiyun } else {
2384*4882a593Smuzhiyun priv->promiscuous = on;
2385*4882a593Smuzhiyun }
2386*4882a593Smuzhiyun return link_to_linux_err(status);
2387*4882a593Smuzhiyun }
2388*4882a593Smuzhiyun
2389*4882a593Smuzhiyun static const struct ieee802154_ops ca8210_phy_ops = {
2390*4882a593Smuzhiyun .start = ca8210_start,
2391*4882a593Smuzhiyun .stop = ca8210_stop,
2392*4882a593Smuzhiyun .xmit_async = ca8210_xmit_async,
2393*4882a593Smuzhiyun .ed = ca8210_get_ed,
2394*4882a593Smuzhiyun .set_channel = ca8210_set_channel,
2395*4882a593Smuzhiyun .set_hw_addr_filt = ca8210_set_hw_addr_filt,
2396*4882a593Smuzhiyun .set_txpower = ca8210_set_tx_power,
2397*4882a593Smuzhiyun .set_cca_mode = ca8210_set_cca_mode,
2398*4882a593Smuzhiyun .set_cca_ed_level = ca8210_set_cca_ed_level,
2399*4882a593Smuzhiyun .set_csma_params = ca8210_set_csma_params,
2400*4882a593Smuzhiyun .set_frame_retries = ca8210_set_frame_retries,
2401*4882a593Smuzhiyun .set_promiscuous_mode = ca8210_set_promiscuous_mode
2402*4882a593Smuzhiyun };
2403*4882a593Smuzhiyun
2404*4882a593Smuzhiyun /* Test/EVBME Interface */
2405*4882a593Smuzhiyun
2406*4882a593Smuzhiyun /**
2407*4882a593Smuzhiyun * ca8210_test_int_open() - Opens the test interface to the userspace
2408*4882a593Smuzhiyun * @inodp: inode representation of file interface
2409*4882a593Smuzhiyun * @filp: file interface
2410*4882a593Smuzhiyun *
2411*4882a593Smuzhiyun * Return: 0 or linux error code
2412*4882a593Smuzhiyun */
ca8210_test_int_open(struct inode * inodp,struct file * filp)2413*4882a593Smuzhiyun static int ca8210_test_int_open(struct inode *inodp, struct file *filp)
2414*4882a593Smuzhiyun {
2415*4882a593Smuzhiyun struct ca8210_priv *priv = inodp->i_private;
2416*4882a593Smuzhiyun
2417*4882a593Smuzhiyun filp->private_data = priv;
2418*4882a593Smuzhiyun return 0;
2419*4882a593Smuzhiyun }
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun /**
2422*4882a593Smuzhiyun * ca8210_test_check_upstream() - Checks a command received from the upstream
2423*4882a593Smuzhiyun * testing interface for required action
2424*4882a593Smuzhiyun * @buf: Buffer containing command to check
2425*4882a593Smuzhiyun * @device_ref: Nondescript pointer to target device
2426*4882a593Smuzhiyun *
2427*4882a593Smuzhiyun * Return: 0 or linux error code
2428*4882a593Smuzhiyun */
ca8210_test_check_upstream(u8 * buf,void * device_ref)2429*4882a593Smuzhiyun static int ca8210_test_check_upstream(u8 *buf, void *device_ref)
2430*4882a593Smuzhiyun {
2431*4882a593Smuzhiyun int ret;
2432*4882a593Smuzhiyun u8 response[CA8210_SPI_BUF_SIZE];
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun if (buf[0] == SPI_MLME_SET_REQUEST) {
2435*4882a593Smuzhiyun ret = tdme_checkpibattribute(buf[2], buf[4], buf + 5);
2436*4882a593Smuzhiyun if (ret) {
2437*4882a593Smuzhiyun response[0] = SPI_MLME_SET_CONFIRM;
2438*4882a593Smuzhiyun response[1] = 3;
2439*4882a593Smuzhiyun response[2] = MAC_INVALID_PARAMETER;
2440*4882a593Smuzhiyun response[3] = buf[2];
2441*4882a593Smuzhiyun response[4] = buf[3];
2442*4882a593Smuzhiyun if (cascoda_api_upstream)
2443*4882a593Smuzhiyun cascoda_api_upstream(response, 5, device_ref);
2444*4882a593Smuzhiyun return ret;
2445*4882a593Smuzhiyun }
2446*4882a593Smuzhiyun }
2447*4882a593Smuzhiyun if (buf[0] == SPI_MLME_ASSOCIATE_REQUEST) {
2448*4882a593Smuzhiyun return tdme_channelinit(buf[2], device_ref);
2449*4882a593Smuzhiyun } else if (buf[0] == SPI_MLME_START_REQUEST) {
2450*4882a593Smuzhiyun return tdme_channelinit(buf[4], device_ref);
2451*4882a593Smuzhiyun } else if (
2452*4882a593Smuzhiyun (buf[0] == SPI_MLME_SET_REQUEST) &&
2453*4882a593Smuzhiyun (buf[2] == PHY_CURRENT_CHANNEL)
2454*4882a593Smuzhiyun ) {
2455*4882a593Smuzhiyun return tdme_channelinit(buf[5], device_ref);
2456*4882a593Smuzhiyun } else if (
2457*4882a593Smuzhiyun (buf[0] == SPI_TDME_SET_REQUEST) &&
2458*4882a593Smuzhiyun (buf[2] == TDME_CHANNEL)
2459*4882a593Smuzhiyun ) {
2460*4882a593Smuzhiyun return tdme_channelinit(buf[4], device_ref);
2461*4882a593Smuzhiyun } else if (
2462*4882a593Smuzhiyun (CA8210_MAC_WORKAROUNDS) &&
2463*4882a593Smuzhiyun (buf[0] == SPI_MLME_RESET_REQUEST) &&
2464*4882a593Smuzhiyun (buf[2] == 1)
2465*4882a593Smuzhiyun ) {
2466*4882a593Smuzhiyun /* reset COORD Bit for Channel Filtering as Coordinator */
2467*4882a593Smuzhiyun return tdme_setsfr_request_sync(
2468*4882a593Smuzhiyun 0,
2469*4882a593Smuzhiyun CA8210_SFR_MACCON,
2470*4882a593Smuzhiyun 0,
2471*4882a593Smuzhiyun device_ref
2472*4882a593Smuzhiyun );
2473*4882a593Smuzhiyun }
2474*4882a593Smuzhiyun return 0;
2475*4882a593Smuzhiyun } /* End of EVBMECheckSerialCommand() */
2476*4882a593Smuzhiyun
2477*4882a593Smuzhiyun /**
2478*4882a593Smuzhiyun * ca8210_test_int_user_write() - Called by a process in userspace to send a
2479*4882a593Smuzhiyun * message to the ca8210 drivers
2480*4882a593Smuzhiyun * @filp: file interface
2481*4882a593Smuzhiyun * @in_buf: Buffer containing message to write
2482*4882a593Smuzhiyun * @len: length of message
2483*4882a593Smuzhiyun * @off: file offset
2484*4882a593Smuzhiyun *
2485*4882a593Smuzhiyun * Return: 0 or linux error code
2486*4882a593Smuzhiyun */
ca8210_test_int_user_write(struct file * filp,const char __user * in_buf,size_t len,loff_t * off)2487*4882a593Smuzhiyun static ssize_t ca8210_test_int_user_write(
2488*4882a593Smuzhiyun struct file *filp,
2489*4882a593Smuzhiyun const char __user *in_buf,
2490*4882a593Smuzhiyun size_t len,
2491*4882a593Smuzhiyun loff_t *off
2492*4882a593Smuzhiyun )
2493*4882a593Smuzhiyun {
2494*4882a593Smuzhiyun int ret;
2495*4882a593Smuzhiyun struct ca8210_priv *priv = filp->private_data;
2496*4882a593Smuzhiyun u8 command[CA8210_SPI_BUF_SIZE];
2497*4882a593Smuzhiyun
2498*4882a593Smuzhiyun memset(command, SPI_IDLE, 6);
2499*4882a593Smuzhiyun if (len > CA8210_SPI_BUF_SIZE || len < 2) {
2500*4882a593Smuzhiyun dev_warn(
2501*4882a593Smuzhiyun &priv->spi->dev,
2502*4882a593Smuzhiyun "userspace requested erroneous write length (%zu)\n",
2503*4882a593Smuzhiyun len
2504*4882a593Smuzhiyun );
2505*4882a593Smuzhiyun return -EBADE;
2506*4882a593Smuzhiyun }
2507*4882a593Smuzhiyun
2508*4882a593Smuzhiyun ret = copy_from_user(command, in_buf, len);
2509*4882a593Smuzhiyun if (ret) {
2510*4882a593Smuzhiyun dev_err(
2511*4882a593Smuzhiyun &priv->spi->dev,
2512*4882a593Smuzhiyun "%d bytes could not be copied from userspace\n",
2513*4882a593Smuzhiyun ret
2514*4882a593Smuzhiyun );
2515*4882a593Smuzhiyun return -EIO;
2516*4882a593Smuzhiyun }
2517*4882a593Smuzhiyun if (len != command[1] + 2) {
2518*4882a593Smuzhiyun dev_err(
2519*4882a593Smuzhiyun &priv->spi->dev,
2520*4882a593Smuzhiyun "write len does not match packet length field\n"
2521*4882a593Smuzhiyun );
2522*4882a593Smuzhiyun return -EBADE;
2523*4882a593Smuzhiyun }
2524*4882a593Smuzhiyun
2525*4882a593Smuzhiyun ret = ca8210_test_check_upstream(command, priv->spi);
2526*4882a593Smuzhiyun if (ret == 0) {
2527*4882a593Smuzhiyun ret = ca8210_spi_exchange(
2528*4882a593Smuzhiyun command,
2529*4882a593Smuzhiyun command[1] + 2,
2530*4882a593Smuzhiyun NULL,
2531*4882a593Smuzhiyun priv->spi
2532*4882a593Smuzhiyun );
2533*4882a593Smuzhiyun if (ret < 0) {
2534*4882a593Smuzhiyun /* effectively 0 bytes were written successfully */
2535*4882a593Smuzhiyun dev_err(
2536*4882a593Smuzhiyun &priv->spi->dev,
2537*4882a593Smuzhiyun "spi exchange failed\n"
2538*4882a593Smuzhiyun );
2539*4882a593Smuzhiyun return ret;
2540*4882a593Smuzhiyun }
2541*4882a593Smuzhiyun if (command[0] & SPI_SYN)
2542*4882a593Smuzhiyun priv->sync_down++;
2543*4882a593Smuzhiyun }
2544*4882a593Smuzhiyun
2545*4882a593Smuzhiyun return len;
2546*4882a593Smuzhiyun }
2547*4882a593Smuzhiyun
2548*4882a593Smuzhiyun /**
2549*4882a593Smuzhiyun * ca8210_test_int_user_read() - Called by a process in userspace to read a
2550*4882a593Smuzhiyun * message from the ca8210 drivers
2551*4882a593Smuzhiyun * @filp: file interface
2552*4882a593Smuzhiyun * @buf: Buffer to write message to
2553*4882a593Smuzhiyun * @len: length of message to read (ignored)
2554*4882a593Smuzhiyun * @offp: file offset
2555*4882a593Smuzhiyun *
2556*4882a593Smuzhiyun * If the O_NONBLOCK flag was set when opening the file then this function will
2557*4882a593Smuzhiyun * not block, i.e. it will return if the fifo is empty. Otherwise the function
2558*4882a593Smuzhiyun * will block, i.e. wait until new data arrives.
2559*4882a593Smuzhiyun *
2560*4882a593Smuzhiyun * Return: number of bytes read
2561*4882a593Smuzhiyun */
ca8210_test_int_user_read(struct file * filp,char __user * buf,size_t len,loff_t * offp)2562*4882a593Smuzhiyun static ssize_t ca8210_test_int_user_read(
2563*4882a593Smuzhiyun struct file *filp,
2564*4882a593Smuzhiyun char __user *buf,
2565*4882a593Smuzhiyun size_t len,
2566*4882a593Smuzhiyun loff_t *offp
2567*4882a593Smuzhiyun )
2568*4882a593Smuzhiyun {
2569*4882a593Smuzhiyun int i, cmdlen;
2570*4882a593Smuzhiyun struct ca8210_priv *priv = filp->private_data;
2571*4882a593Smuzhiyun unsigned char *fifo_buffer;
2572*4882a593Smuzhiyun unsigned long bytes_not_copied;
2573*4882a593Smuzhiyun
2574*4882a593Smuzhiyun if (filp->f_flags & O_NONBLOCK) {
2575*4882a593Smuzhiyun /* Non-blocking mode */
2576*4882a593Smuzhiyun if (kfifo_is_empty(&priv->test.up_fifo))
2577*4882a593Smuzhiyun return 0;
2578*4882a593Smuzhiyun } else {
2579*4882a593Smuzhiyun /* Blocking mode */
2580*4882a593Smuzhiyun wait_event_interruptible(
2581*4882a593Smuzhiyun priv->test.readq,
2582*4882a593Smuzhiyun !kfifo_is_empty(&priv->test.up_fifo)
2583*4882a593Smuzhiyun );
2584*4882a593Smuzhiyun }
2585*4882a593Smuzhiyun
2586*4882a593Smuzhiyun if (kfifo_out(&priv->test.up_fifo, &fifo_buffer, 4) != 4) {
2587*4882a593Smuzhiyun dev_err(
2588*4882a593Smuzhiyun &priv->spi->dev,
2589*4882a593Smuzhiyun "test_interface: Wrong number of elements popped from upstream fifo\n"
2590*4882a593Smuzhiyun );
2591*4882a593Smuzhiyun return 0;
2592*4882a593Smuzhiyun }
2593*4882a593Smuzhiyun cmdlen = fifo_buffer[1];
2594*4882a593Smuzhiyun bytes_not_copied = cmdlen + 2;
2595*4882a593Smuzhiyun
2596*4882a593Smuzhiyun bytes_not_copied = copy_to_user(buf, fifo_buffer, bytes_not_copied);
2597*4882a593Smuzhiyun if (bytes_not_copied > 0) {
2598*4882a593Smuzhiyun dev_err(
2599*4882a593Smuzhiyun &priv->spi->dev,
2600*4882a593Smuzhiyun "%lu bytes could not be copied to user space!\n",
2601*4882a593Smuzhiyun bytes_not_copied
2602*4882a593Smuzhiyun );
2603*4882a593Smuzhiyun }
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "test_interface: Cmd len = %d\n", cmdlen);
2606*4882a593Smuzhiyun
2607*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "test_interface: Read\n");
2608*4882a593Smuzhiyun for (i = 0; i < cmdlen + 2; i++)
2609*4882a593Smuzhiyun dev_dbg(&priv->spi->dev, "%#03x\n", fifo_buffer[i]);
2610*4882a593Smuzhiyun
2611*4882a593Smuzhiyun kfree(fifo_buffer);
2612*4882a593Smuzhiyun
2613*4882a593Smuzhiyun return cmdlen + 2;
2614*4882a593Smuzhiyun }
2615*4882a593Smuzhiyun
2616*4882a593Smuzhiyun /**
2617*4882a593Smuzhiyun * ca8210_test_int_ioctl() - Called by a process in userspace to enact an
2618*4882a593Smuzhiyun * arbitrary action
2619*4882a593Smuzhiyun * @filp: file interface
2620*4882a593Smuzhiyun * @ioctl_num: which action to enact
2621*4882a593Smuzhiyun * @ioctl_param: arbitrary parameter for the action
2622*4882a593Smuzhiyun *
2623*4882a593Smuzhiyun * Return: status
2624*4882a593Smuzhiyun */
ca8210_test_int_ioctl(struct file * filp,unsigned int ioctl_num,unsigned long ioctl_param)2625*4882a593Smuzhiyun static long ca8210_test_int_ioctl(
2626*4882a593Smuzhiyun struct file *filp,
2627*4882a593Smuzhiyun unsigned int ioctl_num,
2628*4882a593Smuzhiyun unsigned long ioctl_param
2629*4882a593Smuzhiyun )
2630*4882a593Smuzhiyun {
2631*4882a593Smuzhiyun struct ca8210_priv *priv = filp->private_data;
2632*4882a593Smuzhiyun
2633*4882a593Smuzhiyun switch (ioctl_num) {
2634*4882a593Smuzhiyun case CA8210_IOCTL_HARD_RESET:
2635*4882a593Smuzhiyun ca8210_reset_send(priv->spi, ioctl_param);
2636*4882a593Smuzhiyun break;
2637*4882a593Smuzhiyun default:
2638*4882a593Smuzhiyun break;
2639*4882a593Smuzhiyun }
2640*4882a593Smuzhiyun return 0;
2641*4882a593Smuzhiyun }
2642*4882a593Smuzhiyun
2643*4882a593Smuzhiyun /**
2644*4882a593Smuzhiyun * ca8210_test_int_poll() - Called by a process in userspace to determine which
2645*4882a593Smuzhiyun * actions are currently possible for the file
2646*4882a593Smuzhiyun * @filp: file interface
2647*4882a593Smuzhiyun * @ptable: poll table
2648*4882a593Smuzhiyun *
2649*4882a593Smuzhiyun * Return: set of poll return flags
2650*4882a593Smuzhiyun */
ca8210_test_int_poll(struct file * filp,struct poll_table_struct * ptable)2651*4882a593Smuzhiyun static __poll_t ca8210_test_int_poll(
2652*4882a593Smuzhiyun struct file *filp,
2653*4882a593Smuzhiyun struct poll_table_struct *ptable
2654*4882a593Smuzhiyun )
2655*4882a593Smuzhiyun {
2656*4882a593Smuzhiyun __poll_t return_flags = 0;
2657*4882a593Smuzhiyun struct ca8210_priv *priv = filp->private_data;
2658*4882a593Smuzhiyun
2659*4882a593Smuzhiyun poll_wait(filp, &priv->test.readq, ptable);
2660*4882a593Smuzhiyun if (!kfifo_is_empty(&priv->test.up_fifo))
2661*4882a593Smuzhiyun return_flags |= (EPOLLIN | EPOLLRDNORM);
2662*4882a593Smuzhiyun if (wait_event_interruptible(
2663*4882a593Smuzhiyun priv->test.readq,
2664*4882a593Smuzhiyun !kfifo_is_empty(&priv->test.up_fifo))) {
2665*4882a593Smuzhiyun return EPOLLERR;
2666*4882a593Smuzhiyun }
2667*4882a593Smuzhiyun return return_flags;
2668*4882a593Smuzhiyun }
2669*4882a593Smuzhiyun
2670*4882a593Smuzhiyun static const struct file_operations test_int_fops = {
2671*4882a593Smuzhiyun .read = ca8210_test_int_user_read,
2672*4882a593Smuzhiyun .write = ca8210_test_int_user_write,
2673*4882a593Smuzhiyun .open = ca8210_test_int_open,
2674*4882a593Smuzhiyun .release = NULL,
2675*4882a593Smuzhiyun .unlocked_ioctl = ca8210_test_int_ioctl,
2676*4882a593Smuzhiyun .poll = ca8210_test_int_poll
2677*4882a593Smuzhiyun };
2678*4882a593Smuzhiyun
2679*4882a593Smuzhiyun /* Init/Deinit */
2680*4882a593Smuzhiyun
2681*4882a593Smuzhiyun /**
2682*4882a593Smuzhiyun * ca8210_get_platform_data() - Populate a ca8210_platform_data object
2683*4882a593Smuzhiyun * @spi_device: Pointer to ca8210 spi device object to get data for
2684*4882a593Smuzhiyun * @pdata: Pointer to ca8210_platform_data object to populate
2685*4882a593Smuzhiyun *
2686*4882a593Smuzhiyun * Return: 0 or linux error code
2687*4882a593Smuzhiyun */
ca8210_get_platform_data(struct spi_device * spi_device,struct ca8210_platform_data * pdata)2688*4882a593Smuzhiyun static int ca8210_get_platform_data(
2689*4882a593Smuzhiyun struct spi_device *spi_device,
2690*4882a593Smuzhiyun struct ca8210_platform_data *pdata
2691*4882a593Smuzhiyun )
2692*4882a593Smuzhiyun {
2693*4882a593Smuzhiyun int ret = 0;
2694*4882a593Smuzhiyun
2695*4882a593Smuzhiyun if (!spi_device->dev.of_node)
2696*4882a593Smuzhiyun return -EINVAL;
2697*4882a593Smuzhiyun
2698*4882a593Smuzhiyun pdata->extclockenable = of_property_read_bool(
2699*4882a593Smuzhiyun spi_device->dev.of_node,
2700*4882a593Smuzhiyun "extclock-enable"
2701*4882a593Smuzhiyun );
2702*4882a593Smuzhiyun if (pdata->extclockenable) {
2703*4882a593Smuzhiyun ret = of_property_read_u32(
2704*4882a593Smuzhiyun spi_device->dev.of_node,
2705*4882a593Smuzhiyun "extclock-freq",
2706*4882a593Smuzhiyun &pdata->extclockfreq
2707*4882a593Smuzhiyun );
2708*4882a593Smuzhiyun if (ret < 0)
2709*4882a593Smuzhiyun return ret;
2710*4882a593Smuzhiyun
2711*4882a593Smuzhiyun ret = of_property_read_u32(
2712*4882a593Smuzhiyun spi_device->dev.of_node,
2713*4882a593Smuzhiyun "extclock-gpio",
2714*4882a593Smuzhiyun &pdata->extclockgpio
2715*4882a593Smuzhiyun );
2716*4882a593Smuzhiyun }
2717*4882a593Smuzhiyun
2718*4882a593Smuzhiyun return ret;
2719*4882a593Smuzhiyun }
2720*4882a593Smuzhiyun
2721*4882a593Smuzhiyun /**
2722*4882a593Smuzhiyun * ca8210_config_extern_clk() - Configure the external clock provided by the
2723*4882a593Smuzhiyun * ca8210
2724*4882a593Smuzhiyun * @pdata: Pointer to ca8210_platform_data containing clock parameters
2725*4882a593Smuzhiyun * @spi: Pointer to target ca8210 spi device
2726*4882a593Smuzhiyun * @on: True to turn the clock on, false to turn off
2727*4882a593Smuzhiyun *
2728*4882a593Smuzhiyun * The external clock is configured with a frequency and output pin taken from
2729*4882a593Smuzhiyun * the platform data.
2730*4882a593Smuzhiyun *
2731*4882a593Smuzhiyun * Return: 0 or linux error code
2732*4882a593Smuzhiyun */
ca8210_config_extern_clk(struct ca8210_platform_data * pdata,struct spi_device * spi,bool on)2733*4882a593Smuzhiyun static int ca8210_config_extern_clk(
2734*4882a593Smuzhiyun struct ca8210_platform_data *pdata,
2735*4882a593Smuzhiyun struct spi_device *spi,
2736*4882a593Smuzhiyun bool on
2737*4882a593Smuzhiyun )
2738*4882a593Smuzhiyun {
2739*4882a593Smuzhiyun u8 clkparam[2];
2740*4882a593Smuzhiyun
2741*4882a593Smuzhiyun if (on) {
2742*4882a593Smuzhiyun dev_info(&spi->dev, "Switching external clock on\n");
2743*4882a593Smuzhiyun switch (pdata->extclockfreq) {
2744*4882a593Smuzhiyun case SIXTEEN_MHZ:
2745*4882a593Smuzhiyun clkparam[0] = 1;
2746*4882a593Smuzhiyun break;
2747*4882a593Smuzhiyun case EIGHT_MHZ:
2748*4882a593Smuzhiyun clkparam[0] = 2;
2749*4882a593Smuzhiyun break;
2750*4882a593Smuzhiyun case FOUR_MHZ:
2751*4882a593Smuzhiyun clkparam[0] = 3;
2752*4882a593Smuzhiyun break;
2753*4882a593Smuzhiyun case TWO_MHZ:
2754*4882a593Smuzhiyun clkparam[0] = 4;
2755*4882a593Smuzhiyun break;
2756*4882a593Smuzhiyun case ONE_MHZ:
2757*4882a593Smuzhiyun clkparam[0] = 5;
2758*4882a593Smuzhiyun break;
2759*4882a593Smuzhiyun default:
2760*4882a593Smuzhiyun dev_crit(&spi->dev, "Invalid extclock-freq\n");
2761*4882a593Smuzhiyun return -EINVAL;
2762*4882a593Smuzhiyun }
2763*4882a593Smuzhiyun clkparam[1] = pdata->extclockgpio;
2764*4882a593Smuzhiyun } else {
2765*4882a593Smuzhiyun dev_info(&spi->dev, "Switching external clock off\n");
2766*4882a593Smuzhiyun clkparam[0] = 0; /* off */
2767*4882a593Smuzhiyun clkparam[1] = 0;
2768*4882a593Smuzhiyun }
2769*4882a593Smuzhiyun return link_to_linux_err(
2770*4882a593Smuzhiyun hwme_set_request_sync(HWME_SYSCLKOUT, 2, clkparam, spi)
2771*4882a593Smuzhiyun );
2772*4882a593Smuzhiyun }
2773*4882a593Smuzhiyun
2774*4882a593Smuzhiyun /**
2775*4882a593Smuzhiyun * ca8210_register_ext_clock() - Register ca8210's external clock with kernel
2776*4882a593Smuzhiyun * @spi: Pointer to target ca8210 spi device
2777*4882a593Smuzhiyun *
2778*4882a593Smuzhiyun * Return: 0 or linux error code
2779*4882a593Smuzhiyun */
ca8210_register_ext_clock(struct spi_device * spi)2780*4882a593Smuzhiyun static int ca8210_register_ext_clock(struct spi_device *spi)
2781*4882a593Smuzhiyun {
2782*4882a593Smuzhiyun struct device_node *np = spi->dev.of_node;
2783*4882a593Smuzhiyun struct ca8210_priv *priv = spi_get_drvdata(spi);
2784*4882a593Smuzhiyun struct ca8210_platform_data *pdata = spi->dev.platform_data;
2785*4882a593Smuzhiyun int ret = 0;
2786*4882a593Smuzhiyun
2787*4882a593Smuzhiyun if (!np)
2788*4882a593Smuzhiyun return -EFAULT;
2789*4882a593Smuzhiyun
2790*4882a593Smuzhiyun priv->clk = clk_register_fixed_rate(
2791*4882a593Smuzhiyun &spi->dev,
2792*4882a593Smuzhiyun np->name,
2793*4882a593Smuzhiyun NULL,
2794*4882a593Smuzhiyun 0,
2795*4882a593Smuzhiyun pdata->extclockfreq
2796*4882a593Smuzhiyun );
2797*4882a593Smuzhiyun
2798*4882a593Smuzhiyun if (IS_ERR(priv->clk)) {
2799*4882a593Smuzhiyun dev_crit(&spi->dev, "Failed to register external clk\n");
2800*4882a593Smuzhiyun return PTR_ERR(priv->clk);
2801*4882a593Smuzhiyun }
2802*4882a593Smuzhiyun ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
2803*4882a593Smuzhiyun if (ret) {
2804*4882a593Smuzhiyun clk_unregister(priv->clk);
2805*4882a593Smuzhiyun dev_crit(
2806*4882a593Smuzhiyun &spi->dev,
2807*4882a593Smuzhiyun "Failed to register external clock as clock provider\n"
2808*4882a593Smuzhiyun );
2809*4882a593Smuzhiyun } else {
2810*4882a593Smuzhiyun dev_info(&spi->dev, "External clock set as clock provider\n");
2811*4882a593Smuzhiyun }
2812*4882a593Smuzhiyun
2813*4882a593Smuzhiyun return ret;
2814*4882a593Smuzhiyun }
2815*4882a593Smuzhiyun
2816*4882a593Smuzhiyun /**
2817*4882a593Smuzhiyun * ca8210_unregister_ext_clock() - Unregister ca8210's external clock with
2818*4882a593Smuzhiyun * kernel
2819*4882a593Smuzhiyun * @spi: Pointer to target ca8210 spi device
2820*4882a593Smuzhiyun */
ca8210_unregister_ext_clock(struct spi_device * spi)2821*4882a593Smuzhiyun static void ca8210_unregister_ext_clock(struct spi_device *spi)
2822*4882a593Smuzhiyun {
2823*4882a593Smuzhiyun struct ca8210_priv *priv = spi_get_drvdata(spi);
2824*4882a593Smuzhiyun
2825*4882a593Smuzhiyun if (!priv->clk)
2826*4882a593Smuzhiyun return
2827*4882a593Smuzhiyun
2828*4882a593Smuzhiyun of_clk_del_provider(spi->dev.of_node);
2829*4882a593Smuzhiyun clk_unregister(priv->clk);
2830*4882a593Smuzhiyun dev_info(&spi->dev, "External clock unregistered\n");
2831*4882a593Smuzhiyun }
2832*4882a593Smuzhiyun
2833*4882a593Smuzhiyun /**
2834*4882a593Smuzhiyun * ca8210_reset_init() - Initialise the reset input to the ca8210
2835*4882a593Smuzhiyun * @spi: Pointer to target ca8210 spi device
2836*4882a593Smuzhiyun *
2837*4882a593Smuzhiyun * Return: 0 or linux error code
2838*4882a593Smuzhiyun */
ca8210_reset_init(struct spi_device * spi)2839*4882a593Smuzhiyun static int ca8210_reset_init(struct spi_device *spi)
2840*4882a593Smuzhiyun {
2841*4882a593Smuzhiyun int ret;
2842*4882a593Smuzhiyun struct ca8210_platform_data *pdata = spi->dev.platform_data;
2843*4882a593Smuzhiyun
2844*4882a593Smuzhiyun pdata->gpio_reset = of_get_named_gpio(
2845*4882a593Smuzhiyun spi->dev.of_node,
2846*4882a593Smuzhiyun "reset-gpio",
2847*4882a593Smuzhiyun 0
2848*4882a593Smuzhiyun );
2849*4882a593Smuzhiyun
2850*4882a593Smuzhiyun ret = gpio_direction_output(pdata->gpio_reset, 1);
2851*4882a593Smuzhiyun if (ret < 0) {
2852*4882a593Smuzhiyun dev_crit(
2853*4882a593Smuzhiyun &spi->dev,
2854*4882a593Smuzhiyun "Reset GPIO %d did not set to output mode\n",
2855*4882a593Smuzhiyun pdata->gpio_reset
2856*4882a593Smuzhiyun );
2857*4882a593Smuzhiyun }
2858*4882a593Smuzhiyun
2859*4882a593Smuzhiyun return ret;
2860*4882a593Smuzhiyun }
2861*4882a593Smuzhiyun
2862*4882a593Smuzhiyun /**
2863*4882a593Smuzhiyun * ca8210_interrupt_init() - Initialise the irq output from the ca8210
2864*4882a593Smuzhiyun * @spi: Pointer to target ca8210 spi device
2865*4882a593Smuzhiyun *
2866*4882a593Smuzhiyun * Return: 0 or linux error code
2867*4882a593Smuzhiyun */
ca8210_interrupt_init(struct spi_device * spi)2868*4882a593Smuzhiyun static int ca8210_interrupt_init(struct spi_device *spi)
2869*4882a593Smuzhiyun {
2870*4882a593Smuzhiyun int ret;
2871*4882a593Smuzhiyun struct ca8210_platform_data *pdata = spi->dev.platform_data;
2872*4882a593Smuzhiyun
2873*4882a593Smuzhiyun pdata->gpio_irq = of_get_named_gpio(
2874*4882a593Smuzhiyun spi->dev.of_node,
2875*4882a593Smuzhiyun "irq-gpio",
2876*4882a593Smuzhiyun 0
2877*4882a593Smuzhiyun );
2878*4882a593Smuzhiyun
2879*4882a593Smuzhiyun pdata->irq_id = gpio_to_irq(pdata->gpio_irq);
2880*4882a593Smuzhiyun if (pdata->irq_id < 0) {
2881*4882a593Smuzhiyun dev_crit(
2882*4882a593Smuzhiyun &spi->dev,
2883*4882a593Smuzhiyun "Could not get irq for gpio pin %d\n",
2884*4882a593Smuzhiyun pdata->gpio_irq
2885*4882a593Smuzhiyun );
2886*4882a593Smuzhiyun gpio_free(pdata->gpio_irq);
2887*4882a593Smuzhiyun return pdata->irq_id;
2888*4882a593Smuzhiyun }
2889*4882a593Smuzhiyun
2890*4882a593Smuzhiyun ret = request_irq(
2891*4882a593Smuzhiyun pdata->irq_id,
2892*4882a593Smuzhiyun ca8210_interrupt_handler,
2893*4882a593Smuzhiyun IRQF_TRIGGER_FALLING,
2894*4882a593Smuzhiyun "ca8210-irq",
2895*4882a593Smuzhiyun spi_get_drvdata(spi)
2896*4882a593Smuzhiyun );
2897*4882a593Smuzhiyun if (ret) {
2898*4882a593Smuzhiyun dev_crit(&spi->dev, "request_irq %d failed\n", pdata->irq_id);
2899*4882a593Smuzhiyun gpio_unexport(pdata->gpio_irq);
2900*4882a593Smuzhiyun gpio_free(pdata->gpio_irq);
2901*4882a593Smuzhiyun }
2902*4882a593Smuzhiyun
2903*4882a593Smuzhiyun return ret;
2904*4882a593Smuzhiyun }
2905*4882a593Smuzhiyun
2906*4882a593Smuzhiyun /**
2907*4882a593Smuzhiyun * ca8210_dev_com_init() - Initialise the spi communication component
2908*4882a593Smuzhiyun * @priv: Pointer to private data structure
2909*4882a593Smuzhiyun *
2910*4882a593Smuzhiyun * Return: 0 or linux error code
2911*4882a593Smuzhiyun */
ca8210_dev_com_init(struct ca8210_priv * priv)2912*4882a593Smuzhiyun static int ca8210_dev_com_init(struct ca8210_priv *priv)
2913*4882a593Smuzhiyun {
2914*4882a593Smuzhiyun priv->mlme_workqueue = alloc_ordered_workqueue(
2915*4882a593Smuzhiyun "MLME work queue",
2916*4882a593Smuzhiyun WQ_UNBOUND
2917*4882a593Smuzhiyun );
2918*4882a593Smuzhiyun if (!priv->mlme_workqueue) {
2919*4882a593Smuzhiyun dev_crit(&priv->spi->dev, "alloc of mlme_workqueue failed!\n");
2920*4882a593Smuzhiyun return -ENOMEM;
2921*4882a593Smuzhiyun }
2922*4882a593Smuzhiyun
2923*4882a593Smuzhiyun priv->irq_workqueue = alloc_ordered_workqueue(
2924*4882a593Smuzhiyun "ca8210 irq worker",
2925*4882a593Smuzhiyun WQ_UNBOUND
2926*4882a593Smuzhiyun );
2927*4882a593Smuzhiyun if (!priv->irq_workqueue) {
2928*4882a593Smuzhiyun dev_crit(&priv->spi->dev, "alloc of irq_workqueue failed!\n");
2929*4882a593Smuzhiyun destroy_workqueue(priv->mlme_workqueue);
2930*4882a593Smuzhiyun return -ENOMEM;
2931*4882a593Smuzhiyun }
2932*4882a593Smuzhiyun
2933*4882a593Smuzhiyun return 0;
2934*4882a593Smuzhiyun }
2935*4882a593Smuzhiyun
2936*4882a593Smuzhiyun /**
2937*4882a593Smuzhiyun * ca8210_dev_com_clear() - Deinitialise the spi communication component
2938*4882a593Smuzhiyun * @priv: Pointer to private data structure
2939*4882a593Smuzhiyun */
ca8210_dev_com_clear(struct ca8210_priv * priv)2940*4882a593Smuzhiyun static void ca8210_dev_com_clear(struct ca8210_priv *priv)
2941*4882a593Smuzhiyun {
2942*4882a593Smuzhiyun flush_workqueue(priv->mlme_workqueue);
2943*4882a593Smuzhiyun destroy_workqueue(priv->mlme_workqueue);
2944*4882a593Smuzhiyun flush_workqueue(priv->irq_workqueue);
2945*4882a593Smuzhiyun destroy_workqueue(priv->irq_workqueue);
2946*4882a593Smuzhiyun }
2947*4882a593Smuzhiyun
2948*4882a593Smuzhiyun #define CA8210_MAX_TX_POWERS (9)
2949*4882a593Smuzhiyun static const s32 ca8210_tx_powers[CA8210_MAX_TX_POWERS] = {
2950*4882a593Smuzhiyun 800, 700, 600, 500, 400, 300, 200, 100, 0
2951*4882a593Smuzhiyun };
2952*4882a593Smuzhiyun
2953*4882a593Smuzhiyun #define CA8210_MAX_ED_LEVELS (21)
2954*4882a593Smuzhiyun static const s32 ca8210_ed_levels[CA8210_MAX_ED_LEVELS] = {
2955*4882a593Smuzhiyun -10300, -10250, -10200, -10150, -10100, -10050, -10000, -9950, -9900,
2956*4882a593Smuzhiyun -9850, -9800, -9750, -9700, -9650, -9600, -9550, -9500, -9450, -9400,
2957*4882a593Smuzhiyun -9350, -9300
2958*4882a593Smuzhiyun };
2959*4882a593Smuzhiyun
2960*4882a593Smuzhiyun /**
2961*4882a593Smuzhiyun * ca8210_hw_setup() - Populate the ieee802154_hw phy attributes with the
2962*4882a593Smuzhiyun * ca8210's defaults
2963*4882a593Smuzhiyun * @ca8210_hw: Pointer to ieee802154_hw to populate
2964*4882a593Smuzhiyun */
ca8210_hw_setup(struct ieee802154_hw * ca8210_hw)2965*4882a593Smuzhiyun static void ca8210_hw_setup(struct ieee802154_hw *ca8210_hw)
2966*4882a593Smuzhiyun {
2967*4882a593Smuzhiyun /* Support channels 11-26 */
2968*4882a593Smuzhiyun ca8210_hw->phy->supported.channels[0] = CA8210_VALID_CHANNELS;
2969*4882a593Smuzhiyun ca8210_hw->phy->supported.tx_powers_size = CA8210_MAX_TX_POWERS;
2970*4882a593Smuzhiyun ca8210_hw->phy->supported.tx_powers = ca8210_tx_powers;
2971*4882a593Smuzhiyun ca8210_hw->phy->supported.cca_ed_levels_size = CA8210_MAX_ED_LEVELS;
2972*4882a593Smuzhiyun ca8210_hw->phy->supported.cca_ed_levels = ca8210_ed_levels;
2973*4882a593Smuzhiyun ca8210_hw->phy->current_channel = 18;
2974*4882a593Smuzhiyun ca8210_hw->phy->current_page = 0;
2975*4882a593Smuzhiyun ca8210_hw->phy->transmit_power = 800;
2976*4882a593Smuzhiyun ca8210_hw->phy->cca.mode = NL802154_CCA_ENERGY_CARRIER;
2977*4882a593Smuzhiyun ca8210_hw->phy->cca.opt = NL802154_CCA_OPT_ENERGY_CARRIER_AND;
2978*4882a593Smuzhiyun ca8210_hw->phy->cca_ed_level = -9800;
2979*4882a593Smuzhiyun ca8210_hw->phy->symbol_duration = 16;
2980*4882a593Smuzhiyun ca8210_hw->phy->lifs_period = 40 * ca8210_hw->phy->symbol_duration;
2981*4882a593Smuzhiyun ca8210_hw->phy->sifs_period = 12 * ca8210_hw->phy->symbol_duration;
2982*4882a593Smuzhiyun ca8210_hw->flags =
2983*4882a593Smuzhiyun IEEE802154_HW_AFILT |
2984*4882a593Smuzhiyun IEEE802154_HW_OMIT_CKSUM |
2985*4882a593Smuzhiyun IEEE802154_HW_FRAME_RETRIES |
2986*4882a593Smuzhiyun IEEE802154_HW_PROMISCUOUS |
2987*4882a593Smuzhiyun IEEE802154_HW_CSMA_PARAMS;
2988*4882a593Smuzhiyun ca8210_hw->phy->flags =
2989*4882a593Smuzhiyun WPAN_PHY_FLAG_TXPOWER |
2990*4882a593Smuzhiyun WPAN_PHY_FLAG_CCA_ED_LEVEL |
2991*4882a593Smuzhiyun WPAN_PHY_FLAG_CCA_MODE;
2992*4882a593Smuzhiyun }
2993*4882a593Smuzhiyun
2994*4882a593Smuzhiyun /**
2995*4882a593Smuzhiyun * ca8210_test_interface_init() - Initialise the test file interface
2996*4882a593Smuzhiyun * @priv: Pointer to private data structure
2997*4882a593Smuzhiyun *
2998*4882a593Smuzhiyun * Provided as an alternative to the standard linux network interface, the test
2999*4882a593Smuzhiyun * interface exposes a file in the filesystem (ca8210_test) that allows
3000*4882a593Smuzhiyun * 802.15.4 SAP Commands and Cascoda EVBME commands to be sent directly to
3001*4882a593Smuzhiyun * the stack.
3002*4882a593Smuzhiyun *
3003*4882a593Smuzhiyun * Return: 0 or linux error code
3004*4882a593Smuzhiyun */
ca8210_test_interface_init(struct ca8210_priv * priv)3005*4882a593Smuzhiyun static int ca8210_test_interface_init(struct ca8210_priv *priv)
3006*4882a593Smuzhiyun {
3007*4882a593Smuzhiyun struct ca8210_test *test = &priv->test;
3008*4882a593Smuzhiyun char node_name[32];
3009*4882a593Smuzhiyun
3010*4882a593Smuzhiyun snprintf(
3011*4882a593Smuzhiyun node_name,
3012*4882a593Smuzhiyun sizeof(node_name),
3013*4882a593Smuzhiyun "ca8210@%d_%d",
3014*4882a593Smuzhiyun priv->spi->master->bus_num,
3015*4882a593Smuzhiyun priv->spi->chip_select
3016*4882a593Smuzhiyun );
3017*4882a593Smuzhiyun
3018*4882a593Smuzhiyun test->ca8210_dfs_spi_int = debugfs_create_file(
3019*4882a593Smuzhiyun node_name,
3020*4882a593Smuzhiyun 0600, /* S_IRUSR | S_IWUSR */
3021*4882a593Smuzhiyun NULL,
3022*4882a593Smuzhiyun priv,
3023*4882a593Smuzhiyun &test_int_fops
3024*4882a593Smuzhiyun );
3025*4882a593Smuzhiyun
3026*4882a593Smuzhiyun debugfs_create_symlink("ca8210", NULL, node_name);
3027*4882a593Smuzhiyun init_waitqueue_head(&test->readq);
3028*4882a593Smuzhiyun return kfifo_alloc(
3029*4882a593Smuzhiyun &test->up_fifo,
3030*4882a593Smuzhiyun CA8210_TEST_INT_FIFO_SIZE,
3031*4882a593Smuzhiyun GFP_KERNEL
3032*4882a593Smuzhiyun );
3033*4882a593Smuzhiyun }
3034*4882a593Smuzhiyun
3035*4882a593Smuzhiyun /**
3036*4882a593Smuzhiyun * ca8210_test_interface_clear() - Deinitialise the test file interface
3037*4882a593Smuzhiyun * @priv: Pointer to private data structure
3038*4882a593Smuzhiyun */
ca8210_test_interface_clear(struct ca8210_priv * priv)3039*4882a593Smuzhiyun static void ca8210_test_interface_clear(struct ca8210_priv *priv)
3040*4882a593Smuzhiyun {
3041*4882a593Smuzhiyun struct ca8210_test *test = &priv->test;
3042*4882a593Smuzhiyun
3043*4882a593Smuzhiyun debugfs_remove(test->ca8210_dfs_spi_int);
3044*4882a593Smuzhiyun kfifo_free(&test->up_fifo);
3045*4882a593Smuzhiyun dev_info(&priv->spi->dev, "Test interface removed\n");
3046*4882a593Smuzhiyun }
3047*4882a593Smuzhiyun
3048*4882a593Smuzhiyun /**
3049*4882a593Smuzhiyun * ca8210_remove() - Shut down a ca8210 upon being disconnected
3050*4882a593Smuzhiyun * @priv: Pointer to private data structure
3051*4882a593Smuzhiyun *
3052*4882a593Smuzhiyun * Return: 0 or linux error code
3053*4882a593Smuzhiyun */
ca8210_remove(struct spi_device * spi_device)3054*4882a593Smuzhiyun static int ca8210_remove(struct spi_device *spi_device)
3055*4882a593Smuzhiyun {
3056*4882a593Smuzhiyun struct ca8210_priv *priv;
3057*4882a593Smuzhiyun struct ca8210_platform_data *pdata;
3058*4882a593Smuzhiyun
3059*4882a593Smuzhiyun dev_info(&spi_device->dev, "Removing ca8210\n");
3060*4882a593Smuzhiyun
3061*4882a593Smuzhiyun pdata = spi_device->dev.platform_data;
3062*4882a593Smuzhiyun if (pdata) {
3063*4882a593Smuzhiyun if (pdata->extclockenable) {
3064*4882a593Smuzhiyun ca8210_unregister_ext_clock(spi_device);
3065*4882a593Smuzhiyun ca8210_config_extern_clk(pdata, spi_device, 0);
3066*4882a593Smuzhiyun }
3067*4882a593Smuzhiyun free_irq(pdata->irq_id, spi_device->dev.driver_data);
3068*4882a593Smuzhiyun kfree(pdata);
3069*4882a593Smuzhiyun spi_device->dev.platform_data = NULL;
3070*4882a593Smuzhiyun }
3071*4882a593Smuzhiyun /* get spi_device private data */
3072*4882a593Smuzhiyun priv = spi_get_drvdata(spi_device);
3073*4882a593Smuzhiyun if (priv) {
3074*4882a593Smuzhiyun dev_info(
3075*4882a593Smuzhiyun &spi_device->dev,
3076*4882a593Smuzhiyun "sync_down = %d, sync_up = %d\n",
3077*4882a593Smuzhiyun priv->sync_down,
3078*4882a593Smuzhiyun priv->sync_up
3079*4882a593Smuzhiyun );
3080*4882a593Smuzhiyun ca8210_dev_com_clear(spi_device->dev.driver_data);
3081*4882a593Smuzhiyun if (priv->hw) {
3082*4882a593Smuzhiyun if (priv->hw_registered)
3083*4882a593Smuzhiyun ieee802154_unregister_hw(priv->hw);
3084*4882a593Smuzhiyun ieee802154_free_hw(priv->hw);
3085*4882a593Smuzhiyun priv->hw = NULL;
3086*4882a593Smuzhiyun dev_info(
3087*4882a593Smuzhiyun &spi_device->dev,
3088*4882a593Smuzhiyun "Unregistered & freed ieee802154_hw.\n"
3089*4882a593Smuzhiyun );
3090*4882a593Smuzhiyun }
3091*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS))
3092*4882a593Smuzhiyun ca8210_test_interface_clear(priv);
3093*4882a593Smuzhiyun }
3094*4882a593Smuzhiyun
3095*4882a593Smuzhiyun return 0;
3096*4882a593Smuzhiyun }
3097*4882a593Smuzhiyun
3098*4882a593Smuzhiyun /**
3099*4882a593Smuzhiyun * ca8210_probe() - Set up a connected ca8210 upon being detected by the system
3100*4882a593Smuzhiyun * @priv: Pointer to private data structure
3101*4882a593Smuzhiyun *
3102*4882a593Smuzhiyun * Return: 0 or linux error code
3103*4882a593Smuzhiyun */
ca8210_probe(struct spi_device * spi_device)3104*4882a593Smuzhiyun static int ca8210_probe(struct spi_device *spi_device)
3105*4882a593Smuzhiyun {
3106*4882a593Smuzhiyun struct ca8210_priv *priv;
3107*4882a593Smuzhiyun struct ieee802154_hw *hw;
3108*4882a593Smuzhiyun struct ca8210_platform_data *pdata;
3109*4882a593Smuzhiyun int ret;
3110*4882a593Smuzhiyun
3111*4882a593Smuzhiyun dev_info(&spi_device->dev, "Inserting ca8210\n");
3112*4882a593Smuzhiyun
3113*4882a593Smuzhiyun /* allocate ieee802154_hw and private data */
3114*4882a593Smuzhiyun hw = ieee802154_alloc_hw(sizeof(struct ca8210_priv), &ca8210_phy_ops);
3115*4882a593Smuzhiyun if (!hw) {
3116*4882a593Smuzhiyun dev_crit(&spi_device->dev, "ieee802154_alloc_hw failed\n");
3117*4882a593Smuzhiyun ret = -ENOMEM;
3118*4882a593Smuzhiyun goto error;
3119*4882a593Smuzhiyun }
3120*4882a593Smuzhiyun
3121*4882a593Smuzhiyun priv = hw->priv;
3122*4882a593Smuzhiyun priv->hw = hw;
3123*4882a593Smuzhiyun priv->spi = spi_device;
3124*4882a593Smuzhiyun hw->parent = &spi_device->dev;
3125*4882a593Smuzhiyun spin_lock_init(&priv->lock);
3126*4882a593Smuzhiyun priv->async_tx_pending = false;
3127*4882a593Smuzhiyun priv->hw_registered = false;
3128*4882a593Smuzhiyun priv->sync_up = 0;
3129*4882a593Smuzhiyun priv->sync_down = 0;
3130*4882a593Smuzhiyun priv->promiscuous = false;
3131*4882a593Smuzhiyun priv->retries = 0;
3132*4882a593Smuzhiyun init_completion(&priv->ca8210_is_awake);
3133*4882a593Smuzhiyun init_completion(&priv->spi_transfer_complete);
3134*4882a593Smuzhiyun init_completion(&priv->sync_exchange_complete);
3135*4882a593Smuzhiyun spi_set_drvdata(priv->spi, priv);
3136*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS)) {
3137*4882a593Smuzhiyun cascoda_api_upstream = ca8210_test_int_driver_write;
3138*4882a593Smuzhiyun ca8210_test_interface_init(priv);
3139*4882a593Smuzhiyun } else {
3140*4882a593Smuzhiyun cascoda_api_upstream = NULL;
3141*4882a593Smuzhiyun }
3142*4882a593Smuzhiyun ca8210_hw_setup(hw);
3143*4882a593Smuzhiyun ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
3144*4882a593Smuzhiyun
3145*4882a593Smuzhiyun pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
3146*4882a593Smuzhiyun if (!pdata) {
3147*4882a593Smuzhiyun ret = -ENOMEM;
3148*4882a593Smuzhiyun goto error;
3149*4882a593Smuzhiyun }
3150*4882a593Smuzhiyun
3151*4882a593Smuzhiyun priv->spi->dev.platform_data = pdata;
3152*4882a593Smuzhiyun ret = ca8210_get_platform_data(priv->spi, pdata);
3153*4882a593Smuzhiyun if (ret) {
3154*4882a593Smuzhiyun dev_crit(&spi_device->dev, "ca8210_get_platform_data failed\n");
3155*4882a593Smuzhiyun goto error;
3156*4882a593Smuzhiyun }
3157*4882a593Smuzhiyun
3158*4882a593Smuzhiyun ret = ca8210_dev_com_init(priv);
3159*4882a593Smuzhiyun if (ret) {
3160*4882a593Smuzhiyun dev_crit(&spi_device->dev, "ca8210_dev_com_init failed\n");
3161*4882a593Smuzhiyun goto error;
3162*4882a593Smuzhiyun }
3163*4882a593Smuzhiyun ret = ca8210_reset_init(priv->spi);
3164*4882a593Smuzhiyun if (ret) {
3165*4882a593Smuzhiyun dev_crit(&spi_device->dev, "ca8210_reset_init failed\n");
3166*4882a593Smuzhiyun goto error;
3167*4882a593Smuzhiyun }
3168*4882a593Smuzhiyun
3169*4882a593Smuzhiyun ret = ca8210_interrupt_init(priv->spi);
3170*4882a593Smuzhiyun if (ret) {
3171*4882a593Smuzhiyun dev_crit(&spi_device->dev, "ca8210_interrupt_init failed\n");
3172*4882a593Smuzhiyun goto error;
3173*4882a593Smuzhiyun }
3174*4882a593Smuzhiyun
3175*4882a593Smuzhiyun msleep(100);
3176*4882a593Smuzhiyun
3177*4882a593Smuzhiyun ca8210_reset_send(priv->spi, 1);
3178*4882a593Smuzhiyun
3179*4882a593Smuzhiyun ret = tdme_chipinit(priv->spi);
3180*4882a593Smuzhiyun if (ret) {
3181*4882a593Smuzhiyun dev_crit(&spi_device->dev, "tdme_chipinit failed\n");
3182*4882a593Smuzhiyun goto error;
3183*4882a593Smuzhiyun }
3184*4882a593Smuzhiyun
3185*4882a593Smuzhiyun if (pdata->extclockenable) {
3186*4882a593Smuzhiyun ret = ca8210_config_extern_clk(pdata, priv->spi, 1);
3187*4882a593Smuzhiyun if (ret) {
3188*4882a593Smuzhiyun dev_crit(
3189*4882a593Smuzhiyun &spi_device->dev,
3190*4882a593Smuzhiyun "ca8210_config_extern_clk failed\n"
3191*4882a593Smuzhiyun );
3192*4882a593Smuzhiyun goto error;
3193*4882a593Smuzhiyun }
3194*4882a593Smuzhiyun ret = ca8210_register_ext_clock(priv->spi);
3195*4882a593Smuzhiyun if (ret) {
3196*4882a593Smuzhiyun dev_crit(
3197*4882a593Smuzhiyun &spi_device->dev,
3198*4882a593Smuzhiyun "ca8210_register_ext_clock failed\n"
3199*4882a593Smuzhiyun );
3200*4882a593Smuzhiyun goto error;
3201*4882a593Smuzhiyun }
3202*4882a593Smuzhiyun }
3203*4882a593Smuzhiyun
3204*4882a593Smuzhiyun ret = ieee802154_register_hw(hw);
3205*4882a593Smuzhiyun if (ret) {
3206*4882a593Smuzhiyun dev_crit(&spi_device->dev, "ieee802154_register_hw failed\n");
3207*4882a593Smuzhiyun goto error;
3208*4882a593Smuzhiyun }
3209*4882a593Smuzhiyun priv->hw_registered = true;
3210*4882a593Smuzhiyun
3211*4882a593Smuzhiyun return 0;
3212*4882a593Smuzhiyun error:
3213*4882a593Smuzhiyun msleep(100); /* wait for pending spi transfers to complete */
3214*4882a593Smuzhiyun ca8210_remove(spi_device);
3215*4882a593Smuzhiyun return link_to_linux_err(ret);
3216*4882a593Smuzhiyun }
3217*4882a593Smuzhiyun
3218*4882a593Smuzhiyun static const struct of_device_id ca8210_of_ids[] = {
3219*4882a593Smuzhiyun {.compatible = "cascoda,ca8210", },
3220*4882a593Smuzhiyun {},
3221*4882a593Smuzhiyun };
3222*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ca8210_of_ids);
3223*4882a593Smuzhiyun
3224*4882a593Smuzhiyun static struct spi_driver ca8210_spi_driver = {
3225*4882a593Smuzhiyun .driver = {
3226*4882a593Smuzhiyun .name = DRIVER_NAME,
3227*4882a593Smuzhiyun .owner = THIS_MODULE,
3228*4882a593Smuzhiyun .of_match_table = of_match_ptr(ca8210_of_ids),
3229*4882a593Smuzhiyun },
3230*4882a593Smuzhiyun .probe = ca8210_probe,
3231*4882a593Smuzhiyun .remove = ca8210_remove
3232*4882a593Smuzhiyun };
3233*4882a593Smuzhiyun
3234*4882a593Smuzhiyun module_spi_driver(ca8210_spi_driver);
3235*4882a593Smuzhiyun
3236*4882a593Smuzhiyun MODULE_AUTHOR("Harry Morris <h.morris@cascoda.com>");
3237*4882a593Smuzhiyun MODULE_DESCRIPTION("CA-8210 SoftMAC driver");
3238*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
3239*4882a593Smuzhiyun MODULE_VERSION("1.0");
3240