xref: /OK3568_Linux_fs/kernel/drivers/net/hippi/rrunner.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * rrunner.c: Linux driver for the Essential RoadRunner HIPPI board.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 1998-2002 by Jes Sorensen, <jes@wildopensource.com>.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Thanks to Essential Communication for providing us with hardware
8*4882a593Smuzhiyun  * and very comprehensive documentation without which I would not have
9*4882a593Smuzhiyun  * been able to write this driver. A special thank you to John Gibbon
10*4882a593Smuzhiyun  * for sorting out the legal issues, with the NDA, allowing the code to
11*4882a593Smuzhiyun  * be released under the GPL.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Thanks to Jayaram Bhat from ODS/Essential for fixing some of the
14*4882a593Smuzhiyun  * stupid bugs in my code.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * Softnet support and various other patches from Val Henson of
17*4882a593Smuzhiyun  * ODS/Essential.
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  * PCI DMA mapping code partly based on work by Francois Romieu.
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define DEBUG 1
24*4882a593Smuzhiyun #define RX_DMA_SKBUFF 1
25*4882a593Smuzhiyun #define PKT_COPY_THRESHOLD 512
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <linux/module.h>
28*4882a593Smuzhiyun #include <linux/types.h>
29*4882a593Smuzhiyun #include <linux/errno.h>
30*4882a593Smuzhiyun #include <linux/ioport.h>
31*4882a593Smuzhiyun #include <linux/pci.h>
32*4882a593Smuzhiyun #include <linux/kernel.h>
33*4882a593Smuzhiyun #include <linux/netdevice.h>
34*4882a593Smuzhiyun #include <linux/hippidevice.h>
35*4882a593Smuzhiyun #include <linux/skbuff.h>
36*4882a593Smuzhiyun #include <linux/delay.h>
37*4882a593Smuzhiyun #include <linux/mm.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun #include <net/sock.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #include <asm/cache.h>
42*4882a593Smuzhiyun #include <asm/byteorder.h>
43*4882a593Smuzhiyun #include <asm/io.h>
44*4882a593Smuzhiyun #include <asm/irq.h>
45*4882a593Smuzhiyun #include <linux/uaccess.h>
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define rr_if_busy(dev)     netif_queue_stopped(dev)
48*4882a593Smuzhiyun #define rr_if_running(dev)  netif_running(dev)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #include "rrunner.h"
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define RUN_AT(x) (jiffies + (x))
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun MODULE_AUTHOR("Jes Sorensen <jes@wildopensource.com>");
56*4882a593Smuzhiyun MODULE_DESCRIPTION("Essential RoadRunner HIPPI driver");
57*4882a593Smuzhiyun MODULE_LICENSE("GPL");
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static const char version[] =
60*4882a593Smuzhiyun "rrunner.c: v0.50 11/11/2002  Jes Sorensen (jes@wildopensource.com)\n";
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static const struct net_device_ops rr_netdev_ops = {
64*4882a593Smuzhiyun 	.ndo_open 		= rr_open,
65*4882a593Smuzhiyun 	.ndo_stop		= rr_close,
66*4882a593Smuzhiyun 	.ndo_do_ioctl		= rr_ioctl,
67*4882a593Smuzhiyun 	.ndo_start_xmit		= rr_start_xmit,
68*4882a593Smuzhiyun 	.ndo_set_mac_address	= hippi_mac_addr,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun  * Implementation notes:
73*4882a593Smuzhiyun  *
74*4882a593Smuzhiyun  * The DMA engine only allows for DMA within physical 64KB chunks of
75*4882a593Smuzhiyun  * memory. The current approach of the driver (and stack) is to use
76*4882a593Smuzhiyun  * linear blocks of memory for the skbuffs. However, as the data block
77*4882a593Smuzhiyun  * is always the first part of the skb and skbs are 2^n aligned so we
78*4882a593Smuzhiyun  * are guarantted to get the whole block within one 64KB align 64KB
79*4882a593Smuzhiyun  * chunk.
80*4882a593Smuzhiyun  *
81*4882a593Smuzhiyun  * On the long term, relying on being able to allocate 64KB linear
82*4882a593Smuzhiyun  * chunks of memory is not feasible and the skb handling code and the
83*4882a593Smuzhiyun  * stack will need to know about I/O vectors or something similar.
84*4882a593Smuzhiyun  */
85*4882a593Smuzhiyun 
rr_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)86*4882a593Smuzhiyun static int rr_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	struct net_device *dev;
89*4882a593Smuzhiyun 	static int version_disp;
90*4882a593Smuzhiyun 	u8 pci_latency;
91*4882a593Smuzhiyun 	struct rr_private *rrpriv;
92*4882a593Smuzhiyun 	void *tmpptr;
93*4882a593Smuzhiyun 	dma_addr_t ring_dma;
94*4882a593Smuzhiyun 	int ret = -ENOMEM;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	dev = alloc_hippi_dev(sizeof(struct rr_private));
97*4882a593Smuzhiyun 	if (!dev)
98*4882a593Smuzhiyun 		goto out3;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	ret = pci_enable_device(pdev);
101*4882a593Smuzhiyun 	if (ret) {
102*4882a593Smuzhiyun 		ret = -ENODEV;
103*4882a593Smuzhiyun 		goto out2;
104*4882a593Smuzhiyun 	}
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	SET_NETDEV_DEV(dev, &pdev->dev);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	ret = pci_request_regions(pdev, "rrunner");
111*4882a593Smuzhiyun 	if (ret < 0)
112*4882a593Smuzhiyun 		goto out;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	pci_set_drvdata(pdev, dev);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	rrpriv->pci_dev = pdev;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	spin_lock_init(&rrpriv->lock);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	dev->netdev_ops = &rr_netdev_ops;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/* display version info if adapter is found */
123*4882a593Smuzhiyun 	if (!version_disp) {
124*4882a593Smuzhiyun 		/* set display flag to TRUE so that */
125*4882a593Smuzhiyun 		/* we only display this string ONCE */
126*4882a593Smuzhiyun 		version_disp = 1;
127*4882a593Smuzhiyun 		printk(version);
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
131*4882a593Smuzhiyun 	if (pci_latency <= 0x58){
132*4882a593Smuzhiyun 		pci_latency = 0x58;
133*4882a593Smuzhiyun 		pci_write_config_byte(pdev, PCI_LATENCY_TIMER, pci_latency);
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	pci_set_master(pdev);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	printk(KERN_INFO "%s: Essential RoadRunner serial HIPPI "
139*4882a593Smuzhiyun 	       "at 0x%llx, irq %i, PCI latency %i\n", dev->name,
140*4882a593Smuzhiyun 	       (unsigned long long)pci_resource_start(pdev, 0),
141*4882a593Smuzhiyun 	       pdev->irq, pci_latency);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/*
144*4882a593Smuzhiyun 	 * Remap the MMIO regs into kernel space.
145*4882a593Smuzhiyun 	 */
146*4882a593Smuzhiyun 	rrpriv->regs = pci_iomap(pdev, 0, 0x1000);
147*4882a593Smuzhiyun 	if (!rrpriv->regs) {
148*4882a593Smuzhiyun 		printk(KERN_ERR "%s:  Unable to map I/O register, "
149*4882a593Smuzhiyun 			"RoadRunner will be disabled.\n", dev->name);
150*4882a593Smuzhiyun 		ret = -EIO;
151*4882a593Smuzhiyun 		goto out;
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	tmpptr = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
155*4882a593Smuzhiyun 				    GFP_KERNEL);
156*4882a593Smuzhiyun 	rrpriv->tx_ring = tmpptr;
157*4882a593Smuzhiyun 	rrpriv->tx_ring_dma = ring_dma;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	if (!tmpptr) {
160*4882a593Smuzhiyun 		ret = -ENOMEM;
161*4882a593Smuzhiyun 		goto out;
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	tmpptr = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
165*4882a593Smuzhiyun 				    GFP_KERNEL);
166*4882a593Smuzhiyun 	rrpriv->rx_ring = tmpptr;
167*4882a593Smuzhiyun 	rrpriv->rx_ring_dma = ring_dma;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	if (!tmpptr) {
170*4882a593Smuzhiyun 		ret = -ENOMEM;
171*4882a593Smuzhiyun 		goto out;
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	tmpptr = dma_alloc_coherent(&pdev->dev, EVT_RING_SIZE, &ring_dma,
175*4882a593Smuzhiyun 				    GFP_KERNEL);
176*4882a593Smuzhiyun 	rrpriv->evt_ring = tmpptr;
177*4882a593Smuzhiyun 	rrpriv->evt_ring_dma = ring_dma;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	if (!tmpptr) {
180*4882a593Smuzhiyun 		ret = -ENOMEM;
181*4882a593Smuzhiyun 		goto out;
182*4882a593Smuzhiyun 	}
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	/*
185*4882a593Smuzhiyun 	 * Don't access any register before this point!
186*4882a593Smuzhiyun 	 */
187*4882a593Smuzhiyun #ifdef __BIG_ENDIAN
188*4882a593Smuzhiyun 	writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
189*4882a593Smuzhiyun 		&rrpriv->regs->HostCtrl);
190*4882a593Smuzhiyun #endif
191*4882a593Smuzhiyun 	/*
192*4882a593Smuzhiyun 	 * Need to add a case for little-endian 64-bit hosts here.
193*4882a593Smuzhiyun 	 */
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	rr_init(dev);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	ret = register_netdev(dev);
198*4882a593Smuzhiyun 	if (ret)
199*4882a593Smuzhiyun 		goto out;
200*4882a593Smuzhiyun 	return 0;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun  out:
203*4882a593Smuzhiyun 	if (rrpriv->evt_ring)
204*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, EVT_RING_SIZE, rrpriv->evt_ring,
205*4882a593Smuzhiyun 				  rrpriv->evt_ring_dma);
206*4882a593Smuzhiyun 	if (rrpriv->rx_ring)
207*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, rrpriv->rx_ring,
208*4882a593Smuzhiyun 				  rrpriv->rx_ring_dma);
209*4882a593Smuzhiyun 	if (rrpriv->tx_ring)
210*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, rrpriv->tx_ring,
211*4882a593Smuzhiyun 				  rrpriv->tx_ring_dma);
212*4882a593Smuzhiyun 	if (rrpriv->regs)
213*4882a593Smuzhiyun 		pci_iounmap(pdev, rrpriv->regs);
214*4882a593Smuzhiyun 	if (pdev)
215*4882a593Smuzhiyun 		pci_release_regions(pdev);
216*4882a593Smuzhiyun  out2:
217*4882a593Smuzhiyun 	free_netdev(dev);
218*4882a593Smuzhiyun  out3:
219*4882a593Smuzhiyun 	return ret;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun 
rr_remove_one(struct pci_dev * pdev)222*4882a593Smuzhiyun static void rr_remove_one(struct pci_dev *pdev)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun 	struct net_device *dev = pci_get_drvdata(pdev);
225*4882a593Smuzhiyun 	struct rr_private *rr = netdev_priv(dev);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)) {
228*4882a593Smuzhiyun 		printk(KERN_ERR "%s: trying to unload running NIC\n",
229*4882a593Smuzhiyun 		       dev->name);
230*4882a593Smuzhiyun 		writel(HALT_NIC, &rr->regs->HostCtrl);
231*4882a593Smuzhiyun 	}
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	unregister_netdev(dev);
234*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, EVT_RING_SIZE, rr->evt_ring,
235*4882a593Smuzhiyun 			  rr->evt_ring_dma);
236*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, rr->rx_ring,
237*4882a593Smuzhiyun 			  rr->rx_ring_dma);
238*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, rr->tx_ring,
239*4882a593Smuzhiyun 			  rr->tx_ring_dma);
240*4882a593Smuzhiyun 	pci_iounmap(pdev, rr->regs);
241*4882a593Smuzhiyun 	pci_release_regions(pdev);
242*4882a593Smuzhiyun 	pci_disable_device(pdev);
243*4882a593Smuzhiyun 	free_netdev(dev);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /*
248*4882a593Smuzhiyun  * Commands are considered to be slow, thus there is no reason to
249*4882a593Smuzhiyun  * inline this.
250*4882a593Smuzhiyun  */
rr_issue_cmd(struct rr_private * rrpriv,struct cmd * cmd)251*4882a593Smuzhiyun static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
254*4882a593Smuzhiyun 	u32 idx;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	regs = rrpriv->regs;
257*4882a593Smuzhiyun 	/*
258*4882a593Smuzhiyun 	 * This is temporary - it will go away in the final version.
259*4882a593Smuzhiyun 	 * We probably also want to make this function inline.
260*4882a593Smuzhiyun 	 */
261*4882a593Smuzhiyun 	if (readl(&regs->HostCtrl) & NIC_HALTED){
262*4882a593Smuzhiyun 		printk("issuing command for halted NIC, code 0x%x, "
263*4882a593Smuzhiyun 		       "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));
264*4882a593Smuzhiyun 		if (readl(&regs->Mode) & FATAL_ERR)
265*4882a593Smuzhiyun 			printk("error codes Fail1 %02x, Fail2 %02x\n",
266*4882a593Smuzhiyun 			       readl(&regs->Fail1), readl(&regs->Fail2));
267*4882a593Smuzhiyun 	}
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	idx = rrpriv->info->cmd_ctrl.pi;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	writel(*(u32*)(cmd), &regs->CmdRing[idx]);
272*4882a593Smuzhiyun 	wmb();
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	idx = (idx - 1) % CMD_RING_ENTRIES;
275*4882a593Smuzhiyun 	rrpriv->info->cmd_ctrl.pi = idx;
276*4882a593Smuzhiyun 	wmb();
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	if (readl(&regs->Mode) & FATAL_ERR)
279*4882a593Smuzhiyun 		printk("error code %02x\n", readl(&regs->Fail1));
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun /*
284*4882a593Smuzhiyun  * Reset the board in a sensible manner. The NIC is already halted
285*4882a593Smuzhiyun  * when we get here and a spin-lock is held.
286*4882a593Smuzhiyun  */
rr_reset(struct net_device * dev)287*4882a593Smuzhiyun static int rr_reset(struct net_device *dev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	struct rr_private *rrpriv;
290*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
291*4882a593Smuzhiyun 	u32 start_pc;
292*4882a593Smuzhiyun 	int i;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
295*4882a593Smuzhiyun 	regs = rrpriv->regs;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	rr_load_firmware(dev);
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	writel(0x01000000, &regs->TX_state);
300*4882a593Smuzhiyun 	writel(0xff800000, &regs->RX_state);
301*4882a593Smuzhiyun 	writel(0, &regs->AssistState);
302*4882a593Smuzhiyun 	writel(CLEAR_INTA, &regs->LocalCtrl);
303*4882a593Smuzhiyun 	writel(0x01, &regs->BrkPt);
304*4882a593Smuzhiyun 	writel(0, &regs->Timer);
305*4882a593Smuzhiyun 	writel(0, &regs->TimerRef);
306*4882a593Smuzhiyun 	writel(RESET_DMA, &regs->DmaReadState);
307*4882a593Smuzhiyun 	writel(RESET_DMA, &regs->DmaWriteState);
308*4882a593Smuzhiyun 	writel(0, &regs->DmaWriteHostHi);
309*4882a593Smuzhiyun 	writel(0, &regs->DmaWriteHostLo);
310*4882a593Smuzhiyun 	writel(0, &regs->DmaReadHostHi);
311*4882a593Smuzhiyun 	writel(0, &regs->DmaReadHostLo);
312*4882a593Smuzhiyun 	writel(0, &regs->DmaReadLen);
313*4882a593Smuzhiyun 	writel(0, &regs->DmaWriteLen);
314*4882a593Smuzhiyun 	writel(0, &regs->DmaWriteLcl);
315*4882a593Smuzhiyun 	writel(0, &regs->DmaWriteIPchecksum);
316*4882a593Smuzhiyun 	writel(0, &regs->DmaReadLcl);
317*4882a593Smuzhiyun 	writel(0, &regs->DmaReadIPchecksum);
318*4882a593Smuzhiyun 	writel(0, &regs->PciState);
319*4882a593Smuzhiyun #if (BITS_PER_LONG == 64) && defined __LITTLE_ENDIAN
320*4882a593Smuzhiyun 	writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);
321*4882a593Smuzhiyun #elif (BITS_PER_LONG == 64)
322*4882a593Smuzhiyun 	writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);
323*4882a593Smuzhiyun #else
324*4882a593Smuzhiyun 	writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);
325*4882a593Smuzhiyun #endif
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun #if 0
328*4882a593Smuzhiyun 	/*
329*4882a593Smuzhiyun 	 * Don't worry, this is just black magic.
330*4882a593Smuzhiyun 	 */
331*4882a593Smuzhiyun 	writel(0xdf000, &regs->RxBase);
332*4882a593Smuzhiyun 	writel(0xdf000, &regs->RxPrd);
333*4882a593Smuzhiyun 	writel(0xdf000, &regs->RxCon);
334*4882a593Smuzhiyun 	writel(0xce000, &regs->TxBase);
335*4882a593Smuzhiyun 	writel(0xce000, &regs->TxPrd);
336*4882a593Smuzhiyun 	writel(0xce000, &regs->TxCon);
337*4882a593Smuzhiyun 	writel(0, &regs->RxIndPro);
338*4882a593Smuzhiyun 	writel(0, &regs->RxIndCon);
339*4882a593Smuzhiyun 	writel(0, &regs->RxIndRef);
340*4882a593Smuzhiyun 	writel(0, &regs->TxIndPro);
341*4882a593Smuzhiyun 	writel(0, &regs->TxIndCon);
342*4882a593Smuzhiyun 	writel(0, &regs->TxIndRef);
343*4882a593Smuzhiyun 	writel(0xcc000, &regs->pad10[0]);
344*4882a593Smuzhiyun 	writel(0, &regs->DrCmndPro);
345*4882a593Smuzhiyun 	writel(0, &regs->DrCmndCon);
346*4882a593Smuzhiyun 	writel(0, &regs->DwCmndPro);
347*4882a593Smuzhiyun 	writel(0, &regs->DwCmndCon);
348*4882a593Smuzhiyun 	writel(0, &regs->DwCmndRef);
349*4882a593Smuzhiyun 	writel(0, &regs->DrDataPro);
350*4882a593Smuzhiyun 	writel(0, &regs->DrDataCon);
351*4882a593Smuzhiyun 	writel(0, &regs->DrDataRef);
352*4882a593Smuzhiyun 	writel(0, &regs->DwDataPro);
353*4882a593Smuzhiyun 	writel(0, &regs->DwDataCon);
354*4882a593Smuzhiyun 	writel(0, &regs->DwDataRef);
355*4882a593Smuzhiyun #endif
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	writel(0xffffffff, &regs->MbEvent);
358*4882a593Smuzhiyun 	writel(0, &regs->Event);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	writel(0, &regs->TxPi);
361*4882a593Smuzhiyun 	writel(0, &regs->IpRxPi);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	writel(0, &regs->EvtCon);
364*4882a593Smuzhiyun 	writel(0, &regs->EvtPrd);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.pi = 0;
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	for (i = 0; i < CMD_RING_ENTRIES; i++)
369*4882a593Smuzhiyun 		writel(0, &regs->CmdRing[i]);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun /*
372*4882a593Smuzhiyun  * Why 32 ? is this not cache line size dependent?
373*4882a593Smuzhiyun  */
374*4882a593Smuzhiyun 	writel(RBURST_64|WBURST_64, &regs->PciState);
375*4882a593Smuzhiyun 	wmb();
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	start_pc = rr_read_eeprom_word(rrpriv,
378*4882a593Smuzhiyun 			offsetof(struct eeprom, rncd_info.FwStart));
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #if (DEBUG > 1)
381*4882a593Smuzhiyun 	printk("%s: Executing firmware at address 0x%06x\n",
382*4882a593Smuzhiyun 	       dev->name, start_pc);
383*4882a593Smuzhiyun #endif
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	writel(start_pc + 0x800, &regs->Pc);
386*4882a593Smuzhiyun 	wmb();
387*4882a593Smuzhiyun 	udelay(5);
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	writel(start_pc, &regs->Pc);
390*4882a593Smuzhiyun 	wmb();
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun /*
397*4882a593Smuzhiyun  * Read a string from the EEPROM.
398*4882a593Smuzhiyun  */
rr_read_eeprom(struct rr_private * rrpriv,unsigned long offset,unsigned char * buf,unsigned long length)399*4882a593Smuzhiyun static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
400*4882a593Smuzhiyun 				unsigned long offset,
401*4882a593Smuzhiyun 				unsigned char *buf,
402*4882a593Smuzhiyun 				unsigned long length)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun 	struct rr_regs __iomem *regs = rrpriv->regs;
405*4882a593Smuzhiyun 	u32 misc, io, host, i;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	io = readl(&regs->ExtIo);
408*4882a593Smuzhiyun 	writel(0, &regs->ExtIo);
409*4882a593Smuzhiyun 	misc = readl(&regs->LocalCtrl);
410*4882a593Smuzhiyun 	writel(0, &regs->LocalCtrl);
411*4882a593Smuzhiyun 	host = readl(&regs->HostCtrl);
412*4882a593Smuzhiyun 	writel(host | HALT_NIC, &regs->HostCtrl);
413*4882a593Smuzhiyun 	mb();
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	for (i = 0; i < length; i++){
416*4882a593Smuzhiyun 		writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
417*4882a593Smuzhiyun 		mb();
418*4882a593Smuzhiyun 		buf[i] = (readl(&regs->WinData) >> 24) & 0xff;
419*4882a593Smuzhiyun 		mb();
420*4882a593Smuzhiyun 	}
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	writel(host, &regs->HostCtrl);
423*4882a593Smuzhiyun 	writel(misc, &regs->LocalCtrl);
424*4882a593Smuzhiyun 	writel(io, &regs->ExtIo);
425*4882a593Smuzhiyun 	mb();
426*4882a593Smuzhiyun 	return i;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun /*
431*4882a593Smuzhiyun  * Shortcut to read one word (4 bytes) out of the EEPROM and convert
432*4882a593Smuzhiyun  * it to our CPU byte-order.
433*4882a593Smuzhiyun  */
rr_read_eeprom_word(struct rr_private * rrpriv,size_t offset)434*4882a593Smuzhiyun static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
435*4882a593Smuzhiyun 			    size_t offset)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	__be32 word;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	if ((rr_read_eeprom(rrpriv, offset,
440*4882a593Smuzhiyun 			    (unsigned char *)&word, 4) == 4))
441*4882a593Smuzhiyun 		return be32_to_cpu(word);
442*4882a593Smuzhiyun 	return 0;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun /*
447*4882a593Smuzhiyun  * Write a string to the EEPROM.
448*4882a593Smuzhiyun  *
449*4882a593Smuzhiyun  * This is only called when the firmware is not running.
450*4882a593Smuzhiyun  */
write_eeprom(struct rr_private * rrpriv,unsigned long offset,unsigned char * buf,unsigned long length)451*4882a593Smuzhiyun static unsigned int write_eeprom(struct rr_private *rrpriv,
452*4882a593Smuzhiyun 				 unsigned long offset,
453*4882a593Smuzhiyun 				 unsigned char *buf,
454*4882a593Smuzhiyun 				 unsigned long length)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun 	struct rr_regs __iomem *regs = rrpriv->regs;
457*4882a593Smuzhiyun 	u32 misc, io, data, i, j, ready, error = 0;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	io = readl(&regs->ExtIo);
460*4882a593Smuzhiyun 	writel(0, &regs->ExtIo);
461*4882a593Smuzhiyun 	misc = readl(&regs->LocalCtrl);
462*4882a593Smuzhiyun 	writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);
463*4882a593Smuzhiyun 	mb();
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	for (i = 0; i < length; i++){
466*4882a593Smuzhiyun 		writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
467*4882a593Smuzhiyun 		mb();
468*4882a593Smuzhiyun 		data = buf[i] << 24;
469*4882a593Smuzhiyun 		/*
470*4882a593Smuzhiyun 		 * Only try to write the data if it is not the same
471*4882a593Smuzhiyun 		 * value already.
472*4882a593Smuzhiyun 		 */
473*4882a593Smuzhiyun 		if ((readl(&regs->WinData) & 0xff000000) != data){
474*4882a593Smuzhiyun 			writel(data, &regs->WinData);
475*4882a593Smuzhiyun 			ready = 0;
476*4882a593Smuzhiyun 			j = 0;
477*4882a593Smuzhiyun 			mb();
478*4882a593Smuzhiyun 			while(!ready){
479*4882a593Smuzhiyun 				udelay(20);
480*4882a593Smuzhiyun 				if ((readl(&regs->WinData) & 0xff000000) ==
481*4882a593Smuzhiyun 				    data)
482*4882a593Smuzhiyun 					ready = 1;
483*4882a593Smuzhiyun 				mb();
484*4882a593Smuzhiyun 				if (j++ > 5000){
485*4882a593Smuzhiyun 					printk("data mismatch: %08x, "
486*4882a593Smuzhiyun 					       "WinData %08x\n", data,
487*4882a593Smuzhiyun 					       readl(&regs->WinData));
488*4882a593Smuzhiyun 					ready = 1;
489*4882a593Smuzhiyun 					error = 1;
490*4882a593Smuzhiyun 				}
491*4882a593Smuzhiyun 			}
492*4882a593Smuzhiyun 		}
493*4882a593Smuzhiyun 	}
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	writel(misc, &regs->LocalCtrl);
496*4882a593Smuzhiyun 	writel(io, &regs->ExtIo);
497*4882a593Smuzhiyun 	mb();
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	return error;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 
rr_init(struct net_device * dev)503*4882a593Smuzhiyun static int rr_init(struct net_device *dev)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct rr_private *rrpriv;
506*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
507*4882a593Smuzhiyun 	u32 sram_size, rev;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
510*4882a593Smuzhiyun 	regs = rrpriv->regs;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	rev = readl(&regs->FwRev);
513*4882a593Smuzhiyun 	rrpriv->fw_rev = rev;
514*4882a593Smuzhiyun 	if (rev > 0x00020024)
515*4882a593Smuzhiyun 		printk("  Firmware revision: %i.%i.%i\n", (rev >> 16),
516*4882a593Smuzhiyun 		       ((rev >> 8) & 0xff), (rev & 0xff));
517*4882a593Smuzhiyun 	else if (rev >= 0x00020000) {
518*4882a593Smuzhiyun 		printk("  Firmware revision: %i.%i.%i (2.0.37 or "
519*4882a593Smuzhiyun 		       "later is recommended)\n", (rev >> 16),
520*4882a593Smuzhiyun 		       ((rev >> 8) & 0xff), (rev & 0xff));
521*4882a593Smuzhiyun 	}else{
522*4882a593Smuzhiyun 		printk("  Firmware revision too old: %i.%i.%i, please "
523*4882a593Smuzhiyun 		       "upgrade to 2.0.37 or later.\n",
524*4882a593Smuzhiyun 		       (rev >> 16), ((rev >> 8) & 0xff), (rev & 0xff));
525*4882a593Smuzhiyun 	}
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun #if (DEBUG > 2)
528*4882a593Smuzhiyun 	printk("  Maximum receive rings %i\n", readl(&regs->MaxRxRng));
529*4882a593Smuzhiyun #endif
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	/*
532*4882a593Smuzhiyun 	 * Read the hardware address from the eeprom.  The HW address
533*4882a593Smuzhiyun 	 * is not really necessary for HIPPI but awfully convenient.
534*4882a593Smuzhiyun 	 * The pointer arithmetic to put it in dev_addr is ugly, but
535*4882a593Smuzhiyun 	 * Donald Becker does it this way for the GigE version of this
536*4882a593Smuzhiyun 	 * card and it's shorter and more portable than any
537*4882a593Smuzhiyun 	 * other method I've seen.  -VAL
538*4882a593Smuzhiyun 	 */
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	*(__be16 *)(dev->dev_addr) =
541*4882a593Smuzhiyun 	  htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
542*4882a593Smuzhiyun 	*(__be32 *)(dev->dev_addr+2) =
543*4882a593Smuzhiyun 	  htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	printk("  MAC: %pM\n", dev->dev_addr);
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	sram_size = rr_read_eeprom_word(rrpriv, 8);
548*4882a593Smuzhiyun 	printk("  SRAM size 0x%06x\n", sram_size);
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	return 0;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 
rr_init1(struct net_device * dev)554*4882a593Smuzhiyun static int rr_init1(struct net_device *dev)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	struct rr_private *rrpriv;
557*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
558*4882a593Smuzhiyun 	unsigned long myjif, flags;
559*4882a593Smuzhiyun 	struct cmd cmd;
560*4882a593Smuzhiyun 	u32 hostctrl;
561*4882a593Smuzhiyun 	int ecode = 0;
562*4882a593Smuzhiyun 	short i;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
565*4882a593Smuzhiyun 	regs = rrpriv->regs;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	spin_lock_irqsave(&rrpriv->lock, flags);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	hostctrl = readl(&regs->HostCtrl);
570*4882a593Smuzhiyun 	writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);
571*4882a593Smuzhiyun 	wmb();
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	if (hostctrl & PARITY_ERR){
574*4882a593Smuzhiyun 		printk("%s: Parity error halting NIC - this is serious!\n",
575*4882a593Smuzhiyun 		       dev->name);
576*4882a593Smuzhiyun 		spin_unlock_irqrestore(&rrpriv->lock, flags);
577*4882a593Smuzhiyun 		ecode = -EFAULT;
578*4882a593Smuzhiyun 		goto error;
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	set_rxaddr(regs, rrpriv->rx_ctrl_dma);
582*4882a593Smuzhiyun 	set_infoaddr(regs, rrpriv->info_dma);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
585*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
586*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.mode = 0;
587*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.pi = 0;
588*4882a593Smuzhiyun 	set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
591*4882a593Smuzhiyun 	rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
592*4882a593Smuzhiyun 	rrpriv->info->cmd_ctrl.mode = 0;
593*4882a593Smuzhiyun 	rrpriv->info->cmd_ctrl.pi = 15;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	for (i = 0; i < CMD_RING_ENTRIES; i++) {
596*4882a593Smuzhiyun 		writel(0, &regs->CmdRing[i]);
597*4882a593Smuzhiyun 	}
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	for (i = 0; i < TX_RING_ENTRIES; i++) {
600*4882a593Smuzhiyun 		rrpriv->tx_ring[i].size = 0;
601*4882a593Smuzhiyun 		set_rraddr(&rrpriv->tx_ring[i].addr, 0);
602*4882a593Smuzhiyun 		rrpriv->tx_skbuff[i] = NULL;
603*4882a593Smuzhiyun 	}
604*4882a593Smuzhiyun 	rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
605*4882a593Smuzhiyun 	rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
606*4882a593Smuzhiyun 	rrpriv->info->tx_ctrl.mode = 0;
607*4882a593Smuzhiyun 	rrpriv->info->tx_ctrl.pi = 0;
608*4882a593Smuzhiyun 	set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	/*
611*4882a593Smuzhiyun 	 * Set dirty_tx before we start receiving interrupts, otherwise
612*4882a593Smuzhiyun 	 * the interrupt handler might think it is supposed to process
613*4882a593Smuzhiyun 	 * tx ints before we are up and running, which may cause a null
614*4882a593Smuzhiyun 	 * pointer access in the int handler.
615*4882a593Smuzhiyun 	 */
616*4882a593Smuzhiyun 	rrpriv->tx_full = 0;
617*4882a593Smuzhiyun 	rrpriv->cur_rx = 0;
618*4882a593Smuzhiyun 	rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	rr_reset(dev);
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	/* Tuning values */
623*4882a593Smuzhiyun 	writel(0x5000, &regs->ConRetry);
624*4882a593Smuzhiyun 	writel(0x100, &regs->ConRetryTmr);
625*4882a593Smuzhiyun 	writel(0x500000, &regs->ConTmout);
626*4882a593Smuzhiyun  	writel(0x60, &regs->IntrTmr);
627*4882a593Smuzhiyun 	writel(0x500000, &regs->TxDataMvTimeout);
628*4882a593Smuzhiyun 	writel(0x200000, &regs->RxDataMvTimeout);
629*4882a593Smuzhiyun  	writel(0x80, &regs->WriteDmaThresh);
630*4882a593Smuzhiyun  	writel(0x80, &regs->ReadDmaThresh);
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	rrpriv->fw_running = 0;
633*4882a593Smuzhiyun 	wmb();
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	hostctrl &= ~(HALT_NIC | INVALID_INST_B | PARITY_ERR);
636*4882a593Smuzhiyun 	writel(hostctrl, &regs->HostCtrl);
637*4882a593Smuzhiyun 	wmb();
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	spin_unlock_irqrestore(&rrpriv->lock, flags);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	for (i = 0; i < RX_RING_ENTRIES; i++) {
642*4882a593Smuzhiyun 		struct sk_buff *skb;
643*4882a593Smuzhiyun 		dma_addr_t addr;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 		rrpriv->rx_ring[i].mode = 0;
646*4882a593Smuzhiyun 		skb = alloc_skb(dev->mtu + HIPPI_HLEN, GFP_ATOMIC);
647*4882a593Smuzhiyun 		if (!skb) {
648*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Unable to allocate memory "
649*4882a593Smuzhiyun 			       "for receive ring - halting NIC\n", dev->name);
650*4882a593Smuzhiyun 			ecode = -ENOMEM;
651*4882a593Smuzhiyun 			goto error;
652*4882a593Smuzhiyun 		}
653*4882a593Smuzhiyun 		rrpriv->rx_skbuff[i] = skb;
654*4882a593Smuzhiyun 		addr = dma_map_single(&rrpriv->pci_dev->dev, skb->data,
655*4882a593Smuzhiyun 				      dev->mtu + HIPPI_HLEN, DMA_FROM_DEVICE);
656*4882a593Smuzhiyun 		/*
657*4882a593Smuzhiyun 		 * Sanity test to see if we conflict with the DMA
658*4882a593Smuzhiyun 		 * limitations of the Roadrunner.
659*4882a593Smuzhiyun 		 */
660*4882a593Smuzhiyun 		if ((((unsigned long)skb->data) & 0xfff) > ~65320)
661*4882a593Smuzhiyun 			printk("skb alloc error\n");
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 		set_rraddr(&rrpriv->rx_ring[i].addr, addr);
664*4882a593Smuzhiyun 		rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
665*4882a593Smuzhiyun 	}
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
668*4882a593Smuzhiyun 	rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
669*4882a593Smuzhiyun 	rrpriv->rx_ctrl[4].mode = 8;
670*4882a593Smuzhiyun 	rrpriv->rx_ctrl[4].pi = 0;
671*4882a593Smuzhiyun 	wmb();
672*4882a593Smuzhiyun 	set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	udelay(1000);
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	/*
677*4882a593Smuzhiyun 	 * Now start the FirmWare.
678*4882a593Smuzhiyun 	 */
679*4882a593Smuzhiyun 	cmd.code = C_START_FW;
680*4882a593Smuzhiyun 	cmd.ring = 0;
681*4882a593Smuzhiyun 	cmd.index = 0;
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	rr_issue_cmd(rrpriv, &cmd);
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	/*
686*4882a593Smuzhiyun 	 * Give the FirmWare time to chew on the `get running' command.
687*4882a593Smuzhiyun 	 */
688*4882a593Smuzhiyun 	myjif = jiffies + 5 * HZ;
689*4882a593Smuzhiyun 	while (time_before(jiffies, myjif) && !rrpriv->fw_running)
690*4882a593Smuzhiyun 		cpu_relax();
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	netif_start_queue(dev);
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	return ecode;
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun  error:
697*4882a593Smuzhiyun 	/*
698*4882a593Smuzhiyun 	 * We might have gotten here because we are out of memory,
699*4882a593Smuzhiyun 	 * make sure we release everything we allocated before failing
700*4882a593Smuzhiyun 	 */
701*4882a593Smuzhiyun 	for (i = 0; i < RX_RING_ENTRIES; i++) {
702*4882a593Smuzhiyun 		struct sk_buff *skb = rrpriv->rx_skbuff[i];
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun 		if (skb) {
705*4882a593Smuzhiyun 			dma_unmap_single(&rrpriv->pci_dev->dev,
706*4882a593Smuzhiyun 					 rrpriv->rx_ring[i].addr.addrlo,
707*4882a593Smuzhiyun 					 dev->mtu + HIPPI_HLEN,
708*4882a593Smuzhiyun 					 DMA_FROM_DEVICE);
709*4882a593Smuzhiyun 			rrpriv->rx_ring[i].size = 0;
710*4882a593Smuzhiyun 			set_rraddr(&rrpriv->rx_ring[i].addr, 0);
711*4882a593Smuzhiyun 			dev_kfree_skb(skb);
712*4882a593Smuzhiyun 			rrpriv->rx_skbuff[i] = NULL;
713*4882a593Smuzhiyun 		}
714*4882a593Smuzhiyun 	}
715*4882a593Smuzhiyun 	return ecode;
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun /*
720*4882a593Smuzhiyun  * All events are considered to be slow (RX/TX ints do not generate
721*4882a593Smuzhiyun  * events) and are handled here, outside the main interrupt handler,
722*4882a593Smuzhiyun  * to reduce the size of the handler.
723*4882a593Smuzhiyun  */
rr_handle_event(struct net_device * dev,u32 prodidx,u32 eidx)724*4882a593Smuzhiyun static u32 rr_handle_event(struct net_device *dev, u32 prodidx, u32 eidx)
725*4882a593Smuzhiyun {
726*4882a593Smuzhiyun 	struct rr_private *rrpriv;
727*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
728*4882a593Smuzhiyun 	u32 tmp;
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
731*4882a593Smuzhiyun 	regs = rrpriv->regs;
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	while (prodidx != eidx){
734*4882a593Smuzhiyun 		switch (rrpriv->evt_ring[eidx].code){
735*4882a593Smuzhiyun 		case E_NIC_UP:
736*4882a593Smuzhiyun 			tmp = readl(&regs->FwRev);
737*4882a593Smuzhiyun 			printk(KERN_INFO "%s: Firmware revision %i.%i.%i "
738*4882a593Smuzhiyun 			       "up and running\n", dev->name,
739*4882a593Smuzhiyun 			       (tmp >> 16), ((tmp >> 8) & 0xff), (tmp & 0xff));
740*4882a593Smuzhiyun 			rrpriv->fw_running = 1;
741*4882a593Smuzhiyun 			writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);
742*4882a593Smuzhiyun 			wmb();
743*4882a593Smuzhiyun 			break;
744*4882a593Smuzhiyun 		case E_LINK_ON:
745*4882a593Smuzhiyun 			printk(KERN_INFO "%s: Optical link ON\n", dev->name);
746*4882a593Smuzhiyun 			break;
747*4882a593Smuzhiyun 		case E_LINK_OFF:
748*4882a593Smuzhiyun 			printk(KERN_INFO "%s: Optical link OFF\n", dev->name);
749*4882a593Smuzhiyun 			break;
750*4882a593Smuzhiyun 		case E_RX_IDLE:
751*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: RX data not moving\n",
752*4882a593Smuzhiyun 			       dev->name);
753*4882a593Smuzhiyun 			goto drop;
754*4882a593Smuzhiyun 		case E_WATCHDOG:
755*4882a593Smuzhiyun 			printk(KERN_INFO "%s: The watchdog is here to see "
756*4882a593Smuzhiyun 			       "us\n", dev->name);
757*4882a593Smuzhiyun 			break;
758*4882a593Smuzhiyun 		case E_INTERN_ERR:
759*4882a593Smuzhiyun 			printk(KERN_ERR "%s: HIPPI Internal NIC error\n",
760*4882a593Smuzhiyun 			       dev->name);
761*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
762*4882a593Smuzhiyun 			       &regs->HostCtrl);
763*4882a593Smuzhiyun 			wmb();
764*4882a593Smuzhiyun 			break;
765*4882a593Smuzhiyun 		case E_HOST_ERR:
766*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Host software error\n",
767*4882a593Smuzhiyun 			       dev->name);
768*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
769*4882a593Smuzhiyun 			       &regs->HostCtrl);
770*4882a593Smuzhiyun 			wmb();
771*4882a593Smuzhiyun 			break;
772*4882a593Smuzhiyun 		/*
773*4882a593Smuzhiyun 		 * TX events.
774*4882a593Smuzhiyun 		 */
775*4882a593Smuzhiyun 		case E_CON_REJ:
776*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Connection rejected\n",
777*4882a593Smuzhiyun 			       dev->name);
778*4882a593Smuzhiyun 			dev->stats.tx_aborted_errors++;
779*4882a593Smuzhiyun 			break;
780*4882a593Smuzhiyun 		case E_CON_TMOUT:
781*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Connection timeout\n",
782*4882a593Smuzhiyun 			       dev->name);
783*4882a593Smuzhiyun 			break;
784*4882a593Smuzhiyun 		case E_DISC_ERR:
785*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: HIPPI disconnect error\n",
786*4882a593Smuzhiyun 			       dev->name);
787*4882a593Smuzhiyun 			dev->stats.tx_aborted_errors++;
788*4882a593Smuzhiyun 			break;
789*4882a593Smuzhiyun 		case E_INT_PRTY:
790*4882a593Smuzhiyun 			printk(KERN_ERR "%s: HIPPI Internal Parity error\n",
791*4882a593Smuzhiyun 			       dev->name);
792*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
793*4882a593Smuzhiyun 			       &regs->HostCtrl);
794*4882a593Smuzhiyun 			wmb();
795*4882a593Smuzhiyun 			break;
796*4882a593Smuzhiyun 		case E_TX_IDLE:
797*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Transmitter idle\n",
798*4882a593Smuzhiyun 			       dev->name);
799*4882a593Smuzhiyun 			break;
800*4882a593Smuzhiyun 		case E_TX_LINK_DROP:
801*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Link lost during transmit\n",
802*4882a593Smuzhiyun 			       dev->name);
803*4882a593Smuzhiyun 			dev->stats.tx_aborted_errors++;
804*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
805*4882a593Smuzhiyun 			       &regs->HostCtrl);
806*4882a593Smuzhiyun 			wmb();
807*4882a593Smuzhiyun 			break;
808*4882a593Smuzhiyun 		case E_TX_INV_RNG:
809*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Invalid send ring block\n",
810*4882a593Smuzhiyun 			       dev->name);
811*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
812*4882a593Smuzhiyun 			       &regs->HostCtrl);
813*4882a593Smuzhiyun 			wmb();
814*4882a593Smuzhiyun 			break;
815*4882a593Smuzhiyun 		case E_TX_INV_BUF:
816*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Invalid send buffer address\n",
817*4882a593Smuzhiyun 			       dev->name);
818*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
819*4882a593Smuzhiyun 			       &regs->HostCtrl);
820*4882a593Smuzhiyun 			wmb();
821*4882a593Smuzhiyun 			break;
822*4882a593Smuzhiyun 		case E_TX_INV_DSC:
823*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Invalid descriptor address\n",
824*4882a593Smuzhiyun 			       dev->name);
825*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
826*4882a593Smuzhiyun 			       &regs->HostCtrl);
827*4882a593Smuzhiyun 			wmb();
828*4882a593Smuzhiyun 			break;
829*4882a593Smuzhiyun 		/*
830*4882a593Smuzhiyun 		 * RX events.
831*4882a593Smuzhiyun 		 */
832*4882a593Smuzhiyun 		case E_RX_RNG_OUT:
833*4882a593Smuzhiyun 			printk(KERN_INFO "%s: Receive ring full\n", dev->name);
834*4882a593Smuzhiyun 			break;
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 		case E_RX_PAR_ERR:
837*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Receive parity error\n",
838*4882a593Smuzhiyun 			       dev->name);
839*4882a593Smuzhiyun 			goto drop;
840*4882a593Smuzhiyun 		case E_RX_LLRC_ERR:
841*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Receive LLRC error\n",
842*4882a593Smuzhiyun 			       dev->name);
843*4882a593Smuzhiyun 			goto drop;
844*4882a593Smuzhiyun 		case E_PKT_LN_ERR:
845*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Receive packet length "
846*4882a593Smuzhiyun 			       "error\n", dev->name);
847*4882a593Smuzhiyun 			goto drop;
848*4882a593Smuzhiyun 		case E_DTA_CKSM_ERR:
849*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Data checksum error\n",
850*4882a593Smuzhiyun 			       dev->name);
851*4882a593Smuzhiyun 			goto drop;
852*4882a593Smuzhiyun 		case E_SHT_BST:
853*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Unexpected short burst "
854*4882a593Smuzhiyun 			       "error\n", dev->name);
855*4882a593Smuzhiyun 			goto drop;
856*4882a593Smuzhiyun 		case E_STATE_ERR:
857*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Recv. state transition"
858*4882a593Smuzhiyun 			       " error\n", dev->name);
859*4882a593Smuzhiyun 			goto drop;
860*4882a593Smuzhiyun 		case E_UNEXP_DATA:
861*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Unexpected data error\n",
862*4882a593Smuzhiyun 			       dev->name);
863*4882a593Smuzhiyun 			goto drop;
864*4882a593Smuzhiyun 		case E_LST_LNK_ERR:
865*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Link lost error\n",
866*4882a593Smuzhiyun 			       dev->name);
867*4882a593Smuzhiyun 			goto drop;
868*4882a593Smuzhiyun 		case E_FRM_ERR:
869*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Framing Error\n",
870*4882a593Smuzhiyun 			       dev->name);
871*4882a593Smuzhiyun 			goto drop;
872*4882a593Smuzhiyun 		case E_FLG_SYN_ERR:
873*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Flag sync. lost during "
874*4882a593Smuzhiyun 			       "packet\n", dev->name);
875*4882a593Smuzhiyun 			goto drop;
876*4882a593Smuzhiyun 		case E_RX_INV_BUF:
877*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Invalid receive buffer "
878*4882a593Smuzhiyun 			       "address\n", dev->name);
879*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
880*4882a593Smuzhiyun 			       &regs->HostCtrl);
881*4882a593Smuzhiyun 			wmb();
882*4882a593Smuzhiyun 			break;
883*4882a593Smuzhiyun 		case E_RX_INV_DSC:
884*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Invalid receive descriptor "
885*4882a593Smuzhiyun 			       "address\n", dev->name);
886*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
887*4882a593Smuzhiyun 			       &regs->HostCtrl);
888*4882a593Smuzhiyun 			wmb();
889*4882a593Smuzhiyun 			break;
890*4882a593Smuzhiyun 		case E_RNG_BLK:
891*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Invalid ring block\n",
892*4882a593Smuzhiyun 			       dev->name);
893*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
894*4882a593Smuzhiyun 			       &regs->HostCtrl);
895*4882a593Smuzhiyun 			wmb();
896*4882a593Smuzhiyun 			break;
897*4882a593Smuzhiyun 		drop:
898*4882a593Smuzhiyun 			/* Label packet to be dropped.
899*4882a593Smuzhiyun 			 * Actual dropping occurs in rx
900*4882a593Smuzhiyun 			 * handling.
901*4882a593Smuzhiyun 			 *
902*4882a593Smuzhiyun 			 * The index of packet we get to drop is
903*4882a593Smuzhiyun 			 * the index of the packet following
904*4882a593Smuzhiyun 			 * the bad packet. -kbf
905*4882a593Smuzhiyun 			 */
906*4882a593Smuzhiyun 			{
907*4882a593Smuzhiyun 				u16 index = rrpriv->evt_ring[eidx].index;
908*4882a593Smuzhiyun 				index = (index + (RX_RING_ENTRIES - 1)) %
909*4882a593Smuzhiyun 					RX_RING_ENTRIES;
910*4882a593Smuzhiyun 				rrpriv->rx_ring[index].mode |=
911*4882a593Smuzhiyun 					(PACKET_BAD | PACKET_END);
912*4882a593Smuzhiyun 			}
913*4882a593Smuzhiyun 			break;
914*4882a593Smuzhiyun 		default:
915*4882a593Smuzhiyun 			printk(KERN_WARNING "%s: Unhandled event 0x%02x\n",
916*4882a593Smuzhiyun 			       dev->name, rrpriv->evt_ring[eidx].code);
917*4882a593Smuzhiyun 		}
918*4882a593Smuzhiyun 		eidx = (eidx + 1) % EVT_RING_ENTRIES;
919*4882a593Smuzhiyun 	}
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.pi = eidx;
922*4882a593Smuzhiyun 	wmb();
923*4882a593Smuzhiyun 	return eidx;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun 
rx_int(struct net_device * dev,u32 rxlimit,u32 index)927*4882a593Smuzhiyun static void rx_int(struct net_device *dev, u32 rxlimit, u32 index)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun 	struct rr_private *rrpriv = netdev_priv(dev);
930*4882a593Smuzhiyun 	struct rr_regs __iomem *regs = rrpriv->regs;
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun 	do {
933*4882a593Smuzhiyun 		struct rx_desc *desc;
934*4882a593Smuzhiyun 		u32 pkt_len;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 		desc = &(rrpriv->rx_ring[index]);
937*4882a593Smuzhiyun 		pkt_len = desc->size;
938*4882a593Smuzhiyun #if (DEBUG > 2)
939*4882a593Smuzhiyun 		printk("index %i, rxlimit %i\n", index, rxlimit);
940*4882a593Smuzhiyun 		printk("len %x, mode %x\n", pkt_len, desc->mode);
941*4882a593Smuzhiyun #endif
942*4882a593Smuzhiyun 		if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
943*4882a593Smuzhiyun 			dev->stats.rx_dropped++;
944*4882a593Smuzhiyun 			goto defer;
945*4882a593Smuzhiyun 		}
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 		if (pkt_len > 0){
948*4882a593Smuzhiyun 			struct sk_buff *skb, *rx_skb;
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 			rx_skb = rrpriv->rx_skbuff[index];
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 			if (pkt_len < PKT_COPY_THRESHOLD) {
953*4882a593Smuzhiyun 				skb = alloc_skb(pkt_len, GFP_ATOMIC);
954*4882a593Smuzhiyun 				if (skb == NULL){
955*4882a593Smuzhiyun 					printk(KERN_WARNING "%s: Unable to allocate skb (%i bytes), deferring packet\n", dev->name, pkt_len);
956*4882a593Smuzhiyun 					dev->stats.rx_dropped++;
957*4882a593Smuzhiyun 					goto defer;
958*4882a593Smuzhiyun 				} else {
959*4882a593Smuzhiyun 					dma_sync_single_for_cpu(&rrpriv->pci_dev->dev,
960*4882a593Smuzhiyun 								desc->addr.addrlo,
961*4882a593Smuzhiyun 								pkt_len,
962*4882a593Smuzhiyun 								DMA_FROM_DEVICE);
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 					skb_put_data(skb, rx_skb->data,
965*4882a593Smuzhiyun 						     pkt_len);
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun 					dma_sync_single_for_device(&rrpriv->pci_dev->dev,
968*4882a593Smuzhiyun 								   desc->addr.addrlo,
969*4882a593Smuzhiyun 								   pkt_len,
970*4882a593Smuzhiyun 								   DMA_FROM_DEVICE);
971*4882a593Smuzhiyun 				}
972*4882a593Smuzhiyun 			}else{
973*4882a593Smuzhiyun 				struct sk_buff *newskb;
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 				newskb = alloc_skb(dev->mtu + HIPPI_HLEN,
976*4882a593Smuzhiyun 					GFP_ATOMIC);
977*4882a593Smuzhiyun 				if (newskb){
978*4882a593Smuzhiyun 					dma_addr_t addr;
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 					dma_unmap_single(&rrpriv->pci_dev->dev,
981*4882a593Smuzhiyun 							 desc->addr.addrlo,
982*4882a593Smuzhiyun 							 dev->mtu + HIPPI_HLEN,
983*4882a593Smuzhiyun 							 DMA_FROM_DEVICE);
984*4882a593Smuzhiyun 					skb = rx_skb;
985*4882a593Smuzhiyun 					skb_put(skb, pkt_len);
986*4882a593Smuzhiyun 					rrpriv->rx_skbuff[index] = newskb;
987*4882a593Smuzhiyun 					addr = dma_map_single(&rrpriv->pci_dev->dev,
988*4882a593Smuzhiyun 							      newskb->data,
989*4882a593Smuzhiyun 							      dev->mtu + HIPPI_HLEN,
990*4882a593Smuzhiyun 							      DMA_FROM_DEVICE);
991*4882a593Smuzhiyun 					set_rraddr(&desc->addr, addr);
992*4882a593Smuzhiyun 				} else {
993*4882a593Smuzhiyun 					printk("%s: Out of memory, deferring "
994*4882a593Smuzhiyun 					       "packet\n", dev->name);
995*4882a593Smuzhiyun 					dev->stats.rx_dropped++;
996*4882a593Smuzhiyun 					goto defer;
997*4882a593Smuzhiyun 				}
998*4882a593Smuzhiyun 			}
999*4882a593Smuzhiyun 			skb->protocol = hippi_type_trans(skb, dev);
1000*4882a593Smuzhiyun 
1001*4882a593Smuzhiyun 			netif_rx(skb);		/* send it up */
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 			dev->stats.rx_packets++;
1004*4882a593Smuzhiyun 			dev->stats.rx_bytes += pkt_len;
1005*4882a593Smuzhiyun 		}
1006*4882a593Smuzhiyun 	defer:
1007*4882a593Smuzhiyun 		desc->mode = 0;
1008*4882a593Smuzhiyun 		desc->size = dev->mtu + HIPPI_HLEN;
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 		if ((index & 7) == 7)
1011*4882a593Smuzhiyun 			writel(index, &regs->IpRxPi);
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 		index = (index + 1) % RX_RING_ENTRIES;
1014*4882a593Smuzhiyun 	} while(index != rxlimit);
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	rrpriv->cur_rx = index;
1017*4882a593Smuzhiyun 	wmb();
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 
rr_interrupt(int irq,void * dev_id)1021*4882a593Smuzhiyun static irqreturn_t rr_interrupt(int irq, void *dev_id)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun 	struct rr_private *rrpriv;
1024*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
1025*4882a593Smuzhiyun 	struct net_device *dev = (struct net_device *)dev_id;
1026*4882a593Smuzhiyun 	u32 prodidx, rxindex, eidx, txcsmr, rxlimit, txcon;
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
1029*4882a593Smuzhiyun 	regs = rrpriv->regs;
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun 	if (!(readl(&regs->HostCtrl) & RR_INT))
1032*4882a593Smuzhiyun 		return IRQ_NONE;
1033*4882a593Smuzhiyun 
1034*4882a593Smuzhiyun 	spin_lock(&rrpriv->lock);
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun 	prodidx = readl(&regs->EvtPrd);
1037*4882a593Smuzhiyun 	txcsmr = (prodidx >> 8) & 0xff;
1038*4882a593Smuzhiyun 	rxlimit = (prodidx >> 16) & 0xff;
1039*4882a593Smuzhiyun 	prodidx &= 0xff;
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun #if (DEBUG > 2)
1042*4882a593Smuzhiyun 	printk("%s: interrupt, prodidx = %i, eidx = %i\n", dev->name,
1043*4882a593Smuzhiyun 	       prodidx, rrpriv->info->evt_ctrl.pi);
1044*4882a593Smuzhiyun #endif
1045*4882a593Smuzhiyun 	/*
1046*4882a593Smuzhiyun 	 * Order here is important.  We must handle events
1047*4882a593Smuzhiyun 	 * before doing anything else in order to catch
1048*4882a593Smuzhiyun 	 * such things as LLRC errors, etc -kbf
1049*4882a593Smuzhiyun 	 */
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	eidx = rrpriv->info->evt_ctrl.pi;
1052*4882a593Smuzhiyun 	if (prodidx != eidx)
1053*4882a593Smuzhiyun 		eidx = rr_handle_event(dev, prodidx, eidx);
1054*4882a593Smuzhiyun 
1055*4882a593Smuzhiyun 	rxindex = rrpriv->cur_rx;
1056*4882a593Smuzhiyun 	if (rxindex != rxlimit)
1057*4882a593Smuzhiyun 		rx_int(dev, rxlimit, rxindex);
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	txcon = rrpriv->dirty_tx;
1060*4882a593Smuzhiyun 	if (txcsmr != txcon) {
1061*4882a593Smuzhiyun 		do {
1062*4882a593Smuzhiyun 			/* Due to occational firmware TX producer/consumer out
1063*4882a593Smuzhiyun 			 * of sync. error need to check entry in ring -kbf
1064*4882a593Smuzhiyun 			 */
1065*4882a593Smuzhiyun 			if(rrpriv->tx_skbuff[txcon]){
1066*4882a593Smuzhiyun 				struct tx_desc *desc;
1067*4882a593Smuzhiyun 				struct sk_buff *skb;
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 				desc = &(rrpriv->tx_ring[txcon]);
1070*4882a593Smuzhiyun 				skb = rrpriv->tx_skbuff[txcon];
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 				dev->stats.tx_packets++;
1073*4882a593Smuzhiyun 				dev->stats.tx_bytes += skb->len;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 				dma_unmap_single(&rrpriv->pci_dev->dev,
1076*4882a593Smuzhiyun 						 desc->addr.addrlo, skb->len,
1077*4882a593Smuzhiyun 						 DMA_TO_DEVICE);
1078*4882a593Smuzhiyun 				dev_kfree_skb_irq(skb);
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun 				rrpriv->tx_skbuff[txcon] = NULL;
1081*4882a593Smuzhiyun 				desc->size = 0;
1082*4882a593Smuzhiyun 				set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
1083*4882a593Smuzhiyun 				desc->mode = 0;
1084*4882a593Smuzhiyun 			}
1085*4882a593Smuzhiyun 			txcon = (txcon + 1) % TX_RING_ENTRIES;
1086*4882a593Smuzhiyun 		} while (txcsmr != txcon);
1087*4882a593Smuzhiyun 		wmb();
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 		rrpriv->dirty_tx = txcon;
1090*4882a593Smuzhiyun 		if (rrpriv->tx_full && rr_if_busy(dev) &&
1091*4882a593Smuzhiyun 		    (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
1092*4882a593Smuzhiyun 		     != rrpriv->dirty_tx)){
1093*4882a593Smuzhiyun 			rrpriv->tx_full = 0;
1094*4882a593Smuzhiyun 			netif_wake_queue(dev);
1095*4882a593Smuzhiyun 		}
1096*4882a593Smuzhiyun 	}
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun 	eidx |= ((txcsmr << 8) | (rxlimit << 16));
1099*4882a593Smuzhiyun 	writel(eidx, &regs->EvtCon);
1100*4882a593Smuzhiyun 	wmb();
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	spin_unlock(&rrpriv->lock);
1103*4882a593Smuzhiyun 	return IRQ_HANDLED;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun 
rr_raz_tx(struct rr_private * rrpriv,struct net_device * dev)1106*4882a593Smuzhiyun static inline void rr_raz_tx(struct rr_private *rrpriv,
1107*4882a593Smuzhiyun 			     struct net_device *dev)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun 	int i;
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 	for (i = 0; i < TX_RING_ENTRIES; i++) {
1112*4882a593Smuzhiyun 		struct sk_buff *skb = rrpriv->tx_skbuff[i];
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 		if (skb) {
1115*4882a593Smuzhiyun 			struct tx_desc *desc = &(rrpriv->tx_ring[i]);
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 			dma_unmap_single(&rrpriv->pci_dev->dev,
1118*4882a593Smuzhiyun 					 desc->addr.addrlo, skb->len,
1119*4882a593Smuzhiyun 					 DMA_TO_DEVICE);
1120*4882a593Smuzhiyun 			desc->size = 0;
1121*4882a593Smuzhiyun 			set_rraddr(&desc->addr, 0);
1122*4882a593Smuzhiyun 			dev_kfree_skb(skb);
1123*4882a593Smuzhiyun 			rrpriv->tx_skbuff[i] = NULL;
1124*4882a593Smuzhiyun 		}
1125*4882a593Smuzhiyun 	}
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun 
rr_raz_rx(struct rr_private * rrpriv,struct net_device * dev)1129*4882a593Smuzhiyun static inline void rr_raz_rx(struct rr_private *rrpriv,
1130*4882a593Smuzhiyun 			     struct net_device *dev)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun 	int i;
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun 	for (i = 0; i < RX_RING_ENTRIES; i++) {
1135*4882a593Smuzhiyun 		struct sk_buff *skb = rrpriv->rx_skbuff[i];
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 		if (skb) {
1138*4882a593Smuzhiyun 			struct rx_desc *desc = &(rrpriv->rx_ring[i]);
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 			dma_unmap_single(&rrpriv->pci_dev->dev,
1141*4882a593Smuzhiyun 					 desc->addr.addrlo,
1142*4882a593Smuzhiyun 					 dev->mtu + HIPPI_HLEN,
1143*4882a593Smuzhiyun 					 DMA_FROM_DEVICE);
1144*4882a593Smuzhiyun 			desc->size = 0;
1145*4882a593Smuzhiyun 			set_rraddr(&desc->addr, 0);
1146*4882a593Smuzhiyun 			dev_kfree_skb(skb);
1147*4882a593Smuzhiyun 			rrpriv->rx_skbuff[i] = NULL;
1148*4882a593Smuzhiyun 		}
1149*4882a593Smuzhiyun 	}
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun 
rr_timer(struct timer_list * t)1152*4882a593Smuzhiyun static void rr_timer(struct timer_list *t)
1153*4882a593Smuzhiyun {
1154*4882a593Smuzhiyun 	struct rr_private *rrpriv = from_timer(rrpriv, t, timer);
1155*4882a593Smuzhiyun 	struct net_device *dev = pci_get_drvdata(rrpriv->pci_dev);
1156*4882a593Smuzhiyun 	struct rr_regs __iomem *regs = rrpriv->regs;
1157*4882a593Smuzhiyun 	unsigned long flags;
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 	if (readl(&regs->HostCtrl) & NIC_HALTED){
1160*4882a593Smuzhiyun 		printk("%s: Restarting nic\n", dev->name);
1161*4882a593Smuzhiyun 		memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
1162*4882a593Smuzhiyun 		memset(rrpriv->info, 0, sizeof(struct rr_info));
1163*4882a593Smuzhiyun 		wmb();
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 		rr_raz_tx(rrpriv, dev);
1166*4882a593Smuzhiyun 		rr_raz_rx(rrpriv, dev);
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 		if (rr_init1(dev)) {
1169*4882a593Smuzhiyun 			spin_lock_irqsave(&rrpriv->lock, flags);
1170*4882a593Smuzhiyun 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
1171*4882a593Smuzhiyun 			       &regs->HostCtrl);
1172*4882a593Smuzhiyun 			spin_unlock_irqrestore(&rrpriv->lock, flags);
1173*4882a593Smuzhiyun 		}
1174*4882a593Smuzhiyun 	}
1175*4882a593Smuzhiyun 	rrpriv->timer.expires = RUN_AT(5*HZ);
1176*4882a593Smuzhiyun 	add_timer(&rrpriv->timer);
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 
rr_open(struct net_device * dev)1180*4882a593Smuzhiyun static int rr_open(struct net_device *dev)
1181*4882a593Smuzhiyun {
1182*4882a593Smuzhiyun 	struct rr_private *rrpriv = netdev_priv(dev);
1183*4882a593Smuzhiyun 	struct pci_dev *pdev = rrpriv->pci_dev;
1184*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
1185*4882a593Smuzhiyun 	int ecode = 0;
1186*4882a593Smuzhiyun 	unsigned long flags;
1187*4882a593Smuzhiyun 	dma_addr_t dma_addr;
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun 	regs = rrpriv->regs;
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 	if (rrpriv->fw_rev < 0x00020000) {
1192*4882a593Smuzhiyun 		printk(KERN_WARNING "%s: trying to configure device with "
1193*4882a593Smuzhiyun 		       "obsolete firmware\n", dev->name);
1194*4882a593Smuzhiyun 		ecode = -EBUSY;
1195*4882a593Smuzhiyun 		goto error;
1196*4882a593Smuzhiyun 	}
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun 	rrpriv->rx_ctrl = dma_alloc_coherent(&pdev->dev,
1199*4882a593Smuzhiyun 					     256 * sizeof(struct ring_ctrl),
1200*4882a593Smuzhiyun 					     &dma_addr, GFP_KERNEL);
1201*4882a593Smuzhiyun 	if (!rrpriv->rx_ctrl) {
1202*4882a593Smuzhiyun 		ecode = -ENOMEM;
1203*4882a593Smuzhiyun 		goto error;
1204*4882a593Smuzhiyun 	}
1205*4882a593Smuzhiyun 	rrpriv->rx_ctrl_dma = dma_addr;
1206*4882a593Smuzhiyun 
1207*4882a593Smuzhiyun 	rrpriv->info = dma_alloc_coherent(&pdev->dev, sizeof(struct rr_info),
1208*4882a593Smuzhiyun 					  &dma_addr, GFP_KERNEL);
1209*4882a593Smuzhiyun 	if (!rrpriv->info) {
1210*4882a593Smuzhiyun 		ecode = -ENOMEM;
1211*4882a593Smuzhiyun 		goto error;
1212*4882a593Smuzhiyun 	}
1213*4882a593Smuzhiyun 	rrpriv->info_dma = dma_addr;
1214*4882a593Smuzhiyun 	wmb();
1215*4882a593Smuzhiyun 
1216*4882a593Smuzhiyun 	spin_lock_irqsave(&rrpriv->lock, flags);
1217*4882a593Smuzhiyun 	writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
1218*4882a593Smuzhiyun 	readl(&regs->HostCtrl);
1219*4882a593Smuzhiyun 	spin_unlock_irqrestore(&rrpriv->lock, flags);
1220*4882a593Smuzhiyun 
1221*4882a593Smuzhiyun 	if (request_irq(pdev->irq, rr_interrupt, IRQF_SHARED, dev->name, dev)) {
1222*4882a593Smuzhiyun 		printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1223*4882a593Smuzhiyun 		       dev->name, pdev->irq);
1224*4882a593Smuzhiyun 		ecode = -EAGAIN;
1225*4882a593Smuzhiyun 		goto error;
1226*4882a593Smuzhiyun 	}
1227*4882a593Smuzhiyun 
1228*4882a593Smuzhiyun 	if ((ecode = rr_init1(dev)))
1229*4882a593Smuzhiyun 		goto error;
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun 	/* Set the timer to switch to check for link beat and perhaps switch
1232*4882a593Smuzhiyun 	   to an alternate media type. */
1233*4882a593Smuzhiyun 	timer_setup(&rrpriv->timer, rr_timer, 0);
1234*4882a593Smuzhiyun 	rrpriv->timer.expires = RUN_AT(5*HZ);           /* 5 sec. watchdog */
1235*4882a593Smuzhiyun 	add_timer(&rrpriv->timer);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	netif_start_queue(dev);
1238*4882a593Smuzhiyun 
1239*4882a593Smuzhiyun 	return ecode;
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun  error:
1242*4882a593Smuzhiyun 	spin_lock_irqsave(&rrpriv->lock, flags);
1243*4882a593Smuzhiyun 	writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
1244*4882a593Smuzhiyun 	spin_unlock_irqrestore(&rrpriv->lock, flags);
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	if (rrpriv->info) {
1247*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, sizeof(struct rr_info),
1248*4882a593Smuzhiyun 				  rrpriv->info, rrpriv->info_dma);
1249*4882a593Smuzhiyun 		rrpriv->info = NULL;
1250*4882a593Smuzhiyun 	}
1251*4882a593Smuzhiyun 	if (rrpriv->rx_ctrl) {
1252*4882a593Smuzhiyun 		dma_free_coherent(&pdev->dev, 256 * sizeof(struct ring_ctrl),
1253*4882a593Smuzhiyun 				  rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
1254*4882a593Smuzhiyun 		rrpriv->rx_ctrl = NULL;
1255*4882a593Smuzhiyun 	}
1256*4882a593Smuzhiyun 
1257*4882a593Smuzhiyun 	netif_stop_queue(dev);
1258*4882a593Smuzhiyun 
1259*4882a593Smuzhiyun 	return ecode;
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun 
1262*4882a593Smuzhiyun 
rr_dump(struct net_device * dev)1263*4882a593Smuzhiyun static void rr_dump(struct net_device *dev)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun 	struct rr_private *rrpriv;
1266*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
1267*4882a593Smuzhiyun 	u32 index, cons;
1268*4882a593Smuzhiyun 	short i;
1269*4882a593Smuzhiyun 	int len;
1270*4882a593Smuzhiyun 
1271*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
1272*4882a593Smuzhiyun 	regs = rrpriv->regs;
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 	printk("%s: dumping NIC TX rings\n", dev->name);
1275*4882a593Smuzhiyun 
1276*4882a593Smuzhiyun 	printk("RxPrd %08x, TxPrd %02x, EvtPrd %08x, TxPi %02x, TxCtrlPi %02x\n",
1277*4882a593Smuzhiyun 	       readl(&regs->RxPrd), readl(&regs->TxPrd),
1278*4882a593Smuzhiyun 	       readl(&regs->EvtPrd), readl(&regs->TxPi),
1279*4882a593Smuzhiyun 	       rrpriv->info->tx_ctrl.pi);
1280*4882a593Smuzhiyun 
1281*4882a593Smuzhiyun 	printk("Error code 0x%x\n", readl(&regs->Fail1));
1282*4882a593Smuzhiyun 
1283*4882a593Smuzhiyun 	index = (((readl(&regs->EvtPrd) >> 8) & 0xff) - 1) % TX_RING_ENTRIES;
1284*4882a593Smuzhiyun 	cons = rrpriv->dirty_tx;
1285*4882a593Smuzhiyun 	printk("TX ring index %i, TX consumer %i\n",
1286*4882a593Smuzhiyun 	       index, cons);
1287*4882a593Smuzhiyun 
1288*4882a593Smuzhiyun 	if (rrpriv->tx_skbuff[index]){
1289*4882a593Smuzhiyun 		len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
1290*4882a593Smuzhiyun 		printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
1291*4882a593Smuzhiyun 		for (i = 0; i < len; i++){
1292*4882a593Smuzhiyun 			if (!(i & 7))
1293*4882a593Smuzhiyun 				printk("\n");
1294*4882a593Smuzhiyun 			printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
1295*4882a593Smuzhiyun 		}
1296*4882a593Smuzhiyun 		printk("\n");
1297*4882a593Smuzhiyun 	}
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	if (rrpriv->tx_skbuff[cons]){
1300*4882a593Smuzhiyun 		len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
1301*4882a593Smuzhiyun 		printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
1302*4882a593Smuzhiyun 		printk("mode 0x%x, size 0x%x,\n phys %08Lx, skbuff-addr %p, truesize 0x%x\n",
1303*4882a593Smuzhiyun 		       rrpriv->tx_ring[cons].mode,
1304*4882a593Smuzhiyun 		       rrpriv->tx_ring[cons].size,
1305*4882a593Smuzhiyun 		       (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
1306*4882a593Smuzhiyun 		       rrpriv->tx_skbuff[cons]->data,
1307*4882a593Smuzhiyun 		       (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
1308*4882a593Smuzhiyun 		for (i = 0; i < len; i++){
1309*4882a593Smuzhiyun 			if (!(i & 7))
1310*4882a593Smuzhiyun 				printk("\n");
1311*4882a593Smuzhiyun 			printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
1312*4882a593Smuzhiyun 		}
1313*4882a593Smuzhiyun 		printk("\n");
1314*4882a593Smuzhiyun 	}
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	printk("dumping TX ring info:\n");
1317*4882a593Smuzhiyun 	for (i = 0; i < TX_RING_ENTRIES; i++)
1318*4882a593Smuzhiyun 		printk("mode 0x%x, size 0x%x, phys-addr %08Lx\n",
1319*4882a593Smuzhiyun 		       rrpriv->tx_ring[i].mode,
1320*4882a593Smuzhiyun 		       rrpriv->tx_ring[i].size,
1321*4882a593Smuzhiyun 		       (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
1322*4882a593Smuzhiyun 
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun 
rr_close(struct net_device * dev)1326*4882a593Smuzhiyun static int rr_close(struct net_device *dev)
1327*4882a593Smuzhiyun {
1328*4882a593Smuzhiyun 	struct rr_private *rrpriv = netdev_priv(dev);
1329*4882a593Smuzhiyun 	struct rr_regs __iomem *regs = rrpriv->regs;
1330*4882a593Smuzhiyun 	struct pci_dev *pdev = rrpriv->pci_dev;
1331*4882a593Smuzhiyun 	unsigned long flags;
1332*4882a593Smuzhiyun 	u32 tmp;
1333*4882a593Smuzhiyun 	short i;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	netif_stop_queue(dev);
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	/*
1339*4882a593Smuzhiyun 	 * Lock to make sure we are not cleaning up while another CPU
1340*4882a593Smuzhiyun 	 * is handling interrupts.
1341*4882a593Smuzhiyun 	 */
1342*4882a593Smuzhiyun 	spin_lock_irqsave(&rrpriv->lock, flags);
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	tmp = readl(&regs->HostCtrl);
1345*4882a593Smuzhiyun 	if (tmp & NIC_HALTED){
1346*4882a593Smuzhiyun 		printk("%s: NIC already halted\n", dev->name);
1347*4882a593Smuzhiyun 		rr_dump(dev);
1348*4882a593Smuzhiyun 	}else{
1349*4882a593Smuzhiyun 		tmp |= HALT_NIC | RR_CLEAR_INT;
1350*4882a593Smuzhiyun 		writel(tmp, &regs->HostCtrl);
1351*4882a593Smuzhiyun 		readl(&regs->HostCtrl);
1352*4882a593Smuzhiyun 	}
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun 	rrpriv->fw_running = 0;
1355*4882a593Smuzhiyun 
1356*4882a593Smuzhiyun 	spin_unlock_irqrestore(&rrpriv->lock, flags);
1357*4882a593Smuzhiyun 	del_timer_sync(&rrpriv->timer);
1358*4882a593Smuzhiyun 	spin_lock_irqsave(&rrpriv->lock, flags);
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	writel(0, &regs->TxPi);
1361*4882a593Smuzhiyun 	writel(0, &regs->IpRxPi);
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	writel(0, &regs->EvtCon);
1364*4882a593Smuzhiyun 	writel(0, &regs->EvtPrd);
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	for (i = 0; i < CMD_RING_ENTRIES; i++)
1367*4882a593Smuzhiyun 		writel(0, &regs->CmdRing[i]);
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun 	rrpriv->info->tx_ctrl.entries = 0;
1370*4882a593Smuzhiyun 	rrpriv->info->cmd_ctrl.pi = 0;
1371*4882a593Smuzhiyun 	rrpriv->info->evt_ctrl.pi = 0;
1372*4882a593Smuzhiyun 	rrpriv->rx_ctrl[4].entries = 0;
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun 	rr_raz_tx(rrpriv, dev);
1375*4882a593Smuzhiyun 	rr_raz_rx(rrpriv, dev);
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, 256 * sizeof(struct ring_ctrl),
1378*4882a593Smuzhiyun 			  rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
1379*4882a593Smuzhiyun 	rrpriv->rx_ctrl = NULL;
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	dma_free_coherent(&pdev->dev, sizeof(struct rr_info), rrpriv->info,
1382*4882a593Smuzhiyun 			  rrpriv->info_dma);
1383*4882a593Smuzhiyun 	rrpriv->info = NULL;
1384*4882a593Smuzhiyun 
1385*4882a593Smuzhiyun 	spin_unlock_irqrestore(&rrpriv->lock, flags);
1386*4882a593Smuzhiyun 	free_irq(pdev->irq, dev);
1387*4882a593Smuzhiyun 
1388*4882a593Smuzhiyun 	return 0;
1389*4882a593Smuzhiyun }
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 
rr_start_xmit(struct sk_buff * skb,struct net_device * dev)1392*4882a593Smuzhiyun static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
1393*4882a593Smuzhiyun 				 struct net_device *dev)
1394*4882a593Smuzhiyun {
1395*4882a593Smuzhiyun 	struct rr_private *rrpriv = netdev_priv(dev);
1396*4882a593Smuzhiyun 	struct rr_regs __iomem *regs = rrpriv->regs;
1397*4882a593Smuzhiyun 	struct hippi_cb *hcb = (struct hippi_cb *) skb->cb;
1398*4882a593Smuzhiyun 	struct ring_ctrl *txctrl;
1399*4882a593Smuzhiyun 	unsigned long flags;
1400*4882a593Smuzhiyun 	u32 index, len = skb->len;
1401*4882a593Smuzhiyun 	u32 *ifield;
1402*4882a593Smuzhiyun 	struct sk_buff *new_skb;
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 	if (readl(&regs->Mode) & FATAL_ERR)
1405*4882a593Smuzhiyun 		printk("error codes Fail1 %02x, Fail2 %02x\n",
1406*4882a593Smuzhiyun 		       readl(&regs->Fail1), readl(&regs->Fail2));
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	/*
1409*4882a593Smuzhiyun 	 * We probably need to deal with tbusy here to prevent overruns.
1410*4882a593Smuzhiyun 	 */
1411*4882a593Smuzhiyun 
1412*4882a593Smuzhiyun 	if (skb_headroom(skb) < 8){
1413*4882a593Smuzhiyun 		printk("incoming skb too small - reallocating\n");
1414*4882a593Smuzhiyun 		if (!(new_skb = dev_alloc_skb(len + 8))) {
1415*4882a593Smuzhiyun 			dev_kfree_skb(skb);
1416*4882a593Smuzhiyun 			netif_wake_queue(dev);
1417*4882a593Smuzhiyun 			return NETDEV_TX_OK;
1418*4882a593Smuzhiyun 		}
1419*4882a593Smuzhiyun 		skb_reserve(new_skb, 8);
1420*4882a593Smuzhiyun 		skb_put(new_skb, len);
1421*4882a593Smuzhiyun 		skb_copy_from_linear_data(skb, new_skb->data, len);
1422*4882a593Smuzhiyun 		dev_kfree_skb(skb);
1423*4882a593Smuzhiyun 		skb = new_skb;
1424*4882a593Smuzhiyun 	}
1425*4882a593Smuzhiyun 
1426*4882a593Smuzhiyun 	ifield = skb_push(skb, 8);
1427*4882a593Smuzhiyun 
1428*4882a593Smuzhiyun 	ifield[0] = 0;
1429*4882a593Smuzhiyun 	ifield[1] = hcb->ifield;
1430*4882a593Smuzhiyun 
1431*4882a593Smuzhiyun 	/*
1432*4882a593Smuzhiyun 	 * We don't need the lock before we are actually going to start
1433*4882a593Smuzhiyun 	 * fiddling with the control blocks.
1434*4882a593Smuzhiyun 	 */
1435*4882a593Smuzhiyun 	spin_lock_irqsave(&rrpriv->lock, flags);
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun 	txctrl = &rrpriv->info->tx_ctrl;
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun 	index = txctrl->pi;
1440*4882a593Smuzhiyun 
1441*4882a593Smuzhiyun 	rrpriv->tx_skbuff[index] = skb;
1442*4882a593Smuzhiyun 	set_rraddr(&rrpriv->tx_ring[index].addr,
1443*4882a593Smuzhiyun 		   dma_map_single(&rrpriv->pci_dev->dev, skb->data, len + 8, DMA_TO_DEVICE));
1444*4882a593Smuzhiyun 	rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
1445*4882a593Smuzhiyun 	rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
1446*4882a593Smuzhiyun 	txctrl->pi = (index + 1) % TX_RING_ENTRIES;
1447*4882a593Smuzhiyun 	wmb();
1448*4882a593Smuzhiyun 	writel(txctrl->pi, &regs->TxPi);
1449*4882a593Smuzhiyun 
1450*4882a593Smuzhiyun 	if (txctrl->pi == rrpriv->dirty_tx){
1451*4882a593Smuzhiyun 		rrpriv->tx_full = 1;
1452*4882a593Smuzhiyun 		netif_stop_queue(dev);
1453*4882a593Smuzhiyun 	}
1454*4882a593Smuzhiyun 
1455*4882a593Smuzhiyun 	spin_unlock_irqrestore(&rrpriv->lock, flags);
1456*4882a593Smuzhiyun 
1457*4882a593Smuzhiyun 	return NETDEV_TX_OK;
1458*4882a593Smuzhiyun }
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 
1461*4882a593Smuzhiyun /*
1462*4882a593Smuzhiyun  * Read the firmware out of the EEPROM and put it into the SRAM
1463*4882a593Smuzhiyun  * (or from user space - later)
1464*4882a593Smuzhiyun  *
1465*4882a593Smuzhiyun  * This operation requires the NIC to be halted and is performed with
1466*4882a593Smuzhiyun  * interrupts disabled and with the spinlock hold.
1467*4882a593Smuzhiyun  */
rr_load_firmware(struct net_device * dev)1468*4882a593Smuzhiyun static int rr_load_firmware(struct net_device *dev)
1469*4882a593Smuzhiyun {
1470*4882a593Smuzhiyun 	struct rr_private *rrpriv;
1471*4882a593Smuzhiyun 	struct rr_regs __iomem *regs;
1472*4882a593Smuzhiyun 	size_t eptr, segptr;
1473*4882a593Smuzhiyun 	int i, j;
1474*4882a593Smuzhiyun 	u32 localctrl, sptr, len, tmp;
1475*4882a593Smuzhiyun 	u32 p2len, p2size, nr_seg, revision, io, sram_size;
1476*4882a593Smuzhiyun 
1477*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
1478*4882a593Smuzhiyun 	regs = rrpriv->regs;
1479*4882a593Smuzhiyun 
1480*4882a593Smuzhiyun 	if (dev->flags & IFF_UP)
1481*4882a593Smuzhiyun 		return -EBUSY;
1482*4882a593Smuzhiyun 
1483*4882a593Smuzhiyun 	if (!(readl(&regs->HostCtrl) & NIC_HALTED)){
1484*4882a593Smuzhiyun 		printk("%s: Trying to load firmware to a running NIC.\n",
1485*4882a593Smuzhiyun 		       dev->name);
1486*4882a593Smuzhiyun 		return -EBUSY;
1487*4882a593Smuzhiyun 	}
1488*4882a593Smuzhiyun 
1489*4882a593Smuzhiyun 	localctrl = readl(&regs->LocalCtrl);
1490*4882a593Smuzhiyun 	writel(0, &regs->LocalCtrl);
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun 	writel(0, &regs->EvtPrd);
1493*4882a593Smuzhiyun 	writel(0, &regs->RxPrd);
1494*4882a593Smuzhiyun 	writel(0, &regs->TxPrd);
1495*4882a593Smuzhiyun 
1496*4882a593Smuzhiyun 	/*
1497*4882a593Smuzhiyun 	 * First wipe the entire SRAM, otherwise we might run into all
1498*4882a593Smuzhiyun 	 * kinds of trouble ... sigh, this took almost all afternoon
1499*4882a593Smuzhiyun 	 * to track down ;-(
1500*4882a593Smuzhiyun 	 */
1501*4882a593Smuzhiyun 	io = readl(&regs->ExtIo);
1502*4882a593Smuzhiyun 	writel(0, &regs->ExtIo);
1503*4882a593Smuzhiyun 	sram_size = rr_read_eeprom_word(rrpriv, 8);
1504*4882a593Smuzhiyun 
1505*4882a593Smuzhiyun 	for (i = 200; i < sram_size / 4; i++){
1506*4882a593Smuzhiyun 		writel(i * 4, &regs->WinBase);
1507*4882a593Smuzhiyun 		mb();
1508*4882a593Smuzhiyun 		writel(0, &regs->WinData);
1509*4882a593Smuzhiyun 		mb();
1510*4882a593Smuzhiyun 	}
1511*4882a593Smuzhiyun 	writel(io, &regs->ExtIo);
1512*4882a593Smuzhiyun 	mb();
1513*4882a593Smuzhiyun 
1514*4882a593Smuzhiyun 	eptr = rr_read_eeprom_word(rrpriv,
1515*4882a593Smuzhiyun 		       offsetof(struct eeprom, rncd_info.AddrRunCodeSegs));
1516*4882a593Smuzhiyun 	eptr = ((eptr & 0x1fffff) >> 3);
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
1519*4882a593Smuzhiyun 	p2len = (p2len << 2);
1520*4882a593Smuzhiyun 	p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
1521*4882a593Smuzhiyun 	p2size = ((p2size & 0x1fffff) >> 3);
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	if ((eptr < p2size) || (eptr > (p2size + p2len))){
1524*4882a593Smuzhiyun 		printk("%s: eptr is invalid\n", dev->name);
1525*4882a593Smuzhiyun 		goto out;
1526*4882a593Smuzhiyun 	}
1527*4882a593Smuzhiyun 
1528*4882a593Smuzhiyun 	revision = rr_read_eeprom_word(rrpriv,
1529*4882a593Smuzhiyun 			offsetof(struct eeprom, manf.HeaderFmt));
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun 	if (revision != 1){
1532*4882a593Smuzhiyun 		printk("%s: invalid firmware format (%i)\n",
1533*4882a593Smuzhiyun 		       dev->name, revision);
1534*4882a593Smuzhiyun 		goto out;
1535*4882a593Smuzhiyun 	}
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	nr_seg = rr_read_eeprom_word(rrpriv, eptr);
1538*4882a593Smuzhiyun 	eptr +=4;
1539*4882a593Smuzhiyun #if (DEBUG > 1)
1540*4882a593Smuzhiyun 	printk("%s: nr_seg %i\n", dev->name, nr_seg);
1541*4882a593Smuzhiyun #endif
1542*4882a593Smuzhiyun 
1543*4882a593Smuzhiyun 	for (i = 0; i < nr_seg; i++){
1544*4882a593Smuzhiyun 		sptr = rr_read_eeprom_word(rrpriv, eptr);
1545*4882a593Smuzhiyun 		eptr += 4;
1546*4882a593Smuzhiyun 		len = rr_read_eeprom_word(rrpriv, eptr);
1547*4882a593Smuzhiyun 		eptr += 4;
1548*4882a593Smuzhiyun 		segptr = rr_read_eeprom_word(rrpriv, eptr);
1549*4882a593Smuzhiyun 		segptr = ((segptr & 0x1fffff) >> 3);
1550*4882a593Smuzhiyun 		eptr += 4;
1551*4882a593Smuzhiyun #if (DEBUG > 1)
1552*4882a593Smuzhiyun 		printk("%s: segment %i, sram address %06x, length %04x, segptr %06x\n",
1553*4882a593Smuzhiyun 		       dev->name, i, sptr, len, segptr);
1554*4882a593Smuzhiyun #endif
1555*4882a593Smuzhiyun 		for (j = 0; j < len; j++){
1556*4882a593Smuzhiyun 			tmp = rr_read_eeprom_word(rrpriv, segptr);
1557*4882a593Smuzhiyun 			writel(sptr, &regs->WinBase);
1558*4882a593Smuzhiyun 			mb();
1559*4882a593Smuzhiyun 			writel(tmp, &regs->WinData);
1560*4882a593Smuzhiyun 			mb();
1561*4882a593Smuzhiyun 			segptr += 4;
1562*4882a593Smuzhiyun 			sptr += 4;
1563*4882a593Smuzhiyun 		}
1564*4882a593Smuzhiyun 	}
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun out:
1567*4882a593Smuzhiyun 	writel(localctrl, &regs->LocalCtrl);
1568*4882a593Smuzhiyun 	mb();
1569*4882a593Smuzhiyun 	return 0;
1570*4882a593Smuzhiyun }
1571*4882a593Smuzhiyun 
1572*4882a593Smuzhiyun 
rr_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1573*4882a593Smuzhiyun static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1574*4882a593Smuzhiyun {
1575*4882a593Smuzhiyun 	struct rr_private *rrpriv;
1576*4882a593Smuzhiyun 	unsigned char *image, *oldimage;
1577*4882a593Smuzhiyun 	unsigned long flags;
1578*4882a593Smuzhiyun 	unsigned int i;
1579*4882a593Smuzhiyun 	int error = -EOPNOTSUPP;
1580*4882a593Smuzhiyun 
1581*4882a593Smuzhiyun 	rrpriv = netdev_priv(dev);
1582*4882a593Smuzhiyun 
1583*4882a593Smuzhiyun 	switch(cmd){
1584*4882a593Smuzhiyun 	case SIOCRRGFW:
1585*4882a593Smuzhiyun 		if (!capable(CAP_SYS_RAWIO)){
1586*4882a593Smuzhiyun 			return -EPERM;
1587*4882a593Smuzhiyun 		}
1588*4882a593Smuzhiyun 
1589*4882a593Smuzhiyun 		image = kmalloc_array(EEPROM_WORDS, sizeof(u32), GFP_KERNEL);
1590*4882a593Smuzhiyun 		if (!image)
1591*4882a593Smuzhiyun 			return -ENOMEM;
1592*4882a593Smuzhiyun 
1593*4882a593Smuzhiyun 		if (rrpriv->fw_running){
1594*4882a593Smuzhiyun 			printk("%s: Firmware already running\n", dev->name);
1595*4882a593Smuzhiyun 			error = -EPERM;
1596*4882a593Smuzhiyun 			goto gf_out;
1597*4882a593Smuzhiyun 		}
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 		spin_lock_irqsave(&rrpriv->lock, flags);
1600*4882a593Smuzhiyun 		i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
1601*4882a593Smuzhiyun 		spin_unlock_irqrestore(&rrpriv->lock, flags);
1602*4882a593Smuzhiyun 		if (i != EEPROM_BYTES){
1603*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Error reading EEPROM\n",
1604*4882a593Smuzhiyun 			       dev->name);
1605*4882a593Smuzhiyun 			error = -EFAULT;
1606*4882a593Smuzhiyun 			goto gf_out;
1607*4882a593Smuzhiyun 		}
1608*4882a593Smuzhiyun 		error = copy_to_user(rq->ifr_data, image, EEPROM_BYTES);
1609*4882a593Smuzhiyun 		if (error)
1610*4882a593Smuzhiyun 			error = -EFAULT;
1611*4882a593Smuzhiyun 	gf_out:
1612*4882a593Smuzhiyun 		kfree(image);
1613*4882a593Smuzhiyun 		return error;
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 	case SIOCRRPFW:
1616*4882a593Smuzhiyun 		if (!capable(CAP_SYS_RAWIO)){
1617*4882a593Smuzhiyun 			return -EPERM;
1618*4882a593Smuzhiyun 		}
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 		image = memdup_user(rq->ifr_data, EEPROM_BYTES);
1621*4882a593Smuzhiyun 		if (IS_ERR(image))
1622*4882a593Smuzhiyun 			return PTR_ERR(image);
1623*4882a593Smuzhiyun 
1624*4882a593Smuzhiyun 		oldimage = kmalloc(EEPROM_BYTES, GFP_KERNEL);
1625*4882a593Smuzhiyun 		if (!oldimage) {
1626*4882a593Smuzhiyun 			kfree(image);
1627*4882a593Smuzhiyun 			return -ENOMEM;
1628*4882a593Smuzhiyun 		}
1629*4882a593Smuzhiyun 
1630*4882a593Smuzhiyun 		if (rrpriv->fw_running){
1631*4882a593Smuzhiyun 			printk("%s: Firmware already running\n", dev->name);
1632*4882a593Smuzhiyun 			error = -EPERM;
1633*4882a593Smuzhiyun 			goto wf_out;
1634*4882a593Smuzhiyun 		}
1635*4882a593Smuzhiyun 
1636*4882a593Smuzhiyun 		printk("%s: Updating EEPROM firmware\n", dev->name);
1637*4882a593Smuzhiyun 
1638*4882a593Smuzhiyun 		spin_lock_irqsave(&rrpriv->lock, flags);
1639*4882a593Smuzhiyun 		error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
1640*4882a593Smuzhiyun 		if (error)
1641*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Error writing EEPROM\n",
1642*4882a593Smuzhiyun 			       dev->name);
1643*4882a593Smuzhiyun 
1644*4882a593Smuzhiyun 		i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
1645*4882a593Smuzhiyun 		spin_unlock_irqrestore(&rrpriv->lock, flags);
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun 		if (i != EEPROM_BYTES)
1648*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Error reading back EEPROM "
1649*4882a593Smuzhiyun 			       "image\n", dev->name);
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun 		error = memcmp(image, oldimage, EEPROM_BYTES);
1652*4882a593Smuzhiyun 		if (error){
1653*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Error verifying EEPROM image\n",
1654*4882a593Smuzhiyun 			       dev->name);
1655*4882a593Smuzhiyun 			error = -EFAULT;
1656*4882a593Smuzhiyun 		}
1657*4882a593Smuzhiyun 	wf_out:
1658*4882a593Smuzhiyun 		kfree(oldimage);
1659*4882a593Smuzhiyun 		kfree(image);
1660*4882a593Smuzhiyun 		return error;
1661*4882a593Smuzhiyun 
1662*4882a593Smuzhiyun 	case SIOCRRID:
1663*4882a593Smuzhiyun 		return put_user(0x52523032, (int __user *)rq->ifr_data);
1664*4882a593Smuzhiyun 	default:
1665*4882a593Smuzhiyun 		return error;
1666*4882a593Smuzhiyun 	}
1667*4882a593Smuzhiyun }
1668*4882a593Smuzhiyun 
1669*4882a593Smuzhiyun static const struct pci_device_id rr_pci_tbl[] = {
1670*4882a593Smuzhiyun 	{ PCI_VENDOR_ID_ESSENTIAL, PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER,
1671*4882a593Smuzhiyun 		PCI_ANY_ID, PCI_ANY_ID, },
1672*4882a593Smuzhiyun 	{ 0,}
1673*4882a593Smuzhiyun };
1674*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, rr_pci_tbl);
1675*4882a593Smuzhiyun 
1676*4882a593Smuzhiyun static struct pci_driver rr_driver = {
1677*4882a593Smuzhiyun 	.name		= "rrunner",
1678*4882a593Smuzhiyun 	.id_table	= rr_pci_tbl,
1679*4882a593Smuzhiyun 	.probe		= rr_init_one,
1680*4882a593Smuzhiyun 	.remove		= rr_remove_one,
1681*4882a593Smuzhiyun };
1682*4882a593Smuzhiyun 
1683*4882a593Smuzhiyun module_pci_driver(rr_driver);
1684