1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*****************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * baycom_epp.c -- baycom epp radio modem driver.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1998-2000
8*4882a593Smuzhiyun * Thomas Sailer (sailer@ife.ee.ethz.ch)
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Please note that the GPL allows you to use the driver, NOT the radio.
11*4882a593Smuzhiyun * In order to use the radio, you need a license from the communications
12*4882a593Smuzhiyun * authority of your country.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * History:
15*4882a593Smuzhiyun * 0.1 xx.xx.1998 Initial version by Matthias Welwarsky (dg2fef)
16*4882a593Smuzhiyun * 0.2 21.04.1998 Massive rework by Thomas Sailer
17*4882a593Smuzhiyun * Integrated FPGA EPP modem configuration routines
18*4882a593Smuzhiyun * 0.3 11.05.1998 Took FPGA config out and moved it into a separate program
19*4882a593Smuzhiyun * 0.4 26.07.1999 Adapted to new lowlevel parport driver interface
20*4882a593Smuzhiyun * 0.5 03.08.1999 adapt to Linus' new __setup/__initcall
21*4882a593Smuzhiyun * removed some pre-2.2 kernel compatibility cruft
22*4882a593Smuzhiyun * 0.6 10.08.1999 Check if parport can do SPP and is safe to access during interrupt contexts
23*4882a593Smuzhiyun * 0.7 12.02.2000 adapted to softnet driver interface
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*****************************************************************************/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <linux/crc-ccitt.h>
29*4882a593Smuzhiyun #include <linux/module.h>
30*4882a593Smuzhiyun #include <linux/kernel.h>
31*4882a593Smuzhiyun #include <linux/init.h>
32*4882a593Smuzhiyun #include <linux/sched.h>
33*4882a593Smuzhiyun #include <linux/string.h>
34*4882a593Smuzhiyun #include <linux/workqueue.h>
35*4882a593Smuzhiyun #include <linux/fs.h>
36*4882a593Smuzhiyun #include <linux/parport.h>
37*4882a593Smuzhiyun #include <linux/if_arp.h>
38*4882a593Smuzhiyun #include <linux/hdlcdrv.h>
39*4882a593Smuzhiyun #include <linux/baycom.h>
40*4882a593Smuzhiyun #include <linux/jiffies.h>
41*4882a593Smuzhiyun #include <linux/random.h>
42*4882a593Smuzhiyun #include <net/ax25.h>
43*4882a593Smuzhiyun #include <linux/uaccess.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define BAYCOM_DEBUG
48*4882a593Smuzhiyun #define BAYCOM_MAGIC 19730510
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const char paranoia_str[] = KERN_ERR
53*4882a593Smuzhiyun "baycom_epp: bad magic number for hdlcdrv_state struct in routine %s\n";
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const char bc_drvname[] = "baycom_epp";
56*4882a593Smuzhiyun static const char bc_drvinfo[] = KERN_INFO "baycom_epp: (C) 1998-2000 Thomas Sailer, HB9JNX/AE4WA\n"
57*4882a593Smuzhiyun "baycom_epp: version 0.7\n";
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define NR_PORTS 4
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static struct net_device *baycom_device[NR_PORTS];
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* EPP status register */
68*4882a593Smuzhiyun #define EPP_DCDBIT 0x80
69*4882a593Smuzhiyun #define EPP_PTTBIT 0x08
70*4882a593Smuzhiyun #define EPP_NREF 0x01
71*4882a593Smuzhiyun #define EPP_NRAEF 0x02
72*4882a593Smuzhiyun #define EPP_NRHF 0x04
73*4882a593Smuzhiyun #define EPP_NTHF 0x20
74*4882a593Smuzhiyun #define EPP_NTAEF 0x10
75*4882a593Smuzhiyun #define EPP_NTEF EPP_PTTBIT
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* EPP control register */
78*4882a593Smuzhiyun #define EPP_TX_FIFO_ENABLE 0x10
79*4882a593Smuzhiyun #define EPP_RX_FIFO_ENABLE 0x08
80*4882a593Smuzhiyun #define EPP_MODEM_ENABLE 0x20
81*4882a593Smuzhiyun #define EPP_LEDS 0xC0
82*4882a593Smuzhiyun #define EPP_IRQ_ENABLE 0x10
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* LPT registers */
85*4882a593Smuzhiyun #define LPTREG_ECONTROL 0x402
86*4882a593Smuzhiyun #define LPTREG_CONFIGB 0x401
87*4882a593Smuzhiyun #define LPTREG_CONFIGA 0x400
88*4882a593Smuzhiyun #define LPTREG_EPPDATA 0x004
89*4882a593Smuzhiyun #define LPTREG_EPPADDR 0x003
90*4882a593Smuzhiyun #define LPTREG_CONTROL 0x002
91*4882a593Smuzhiyun #define LPTREG_STATUS 0x001
92*4882a593Smuzhiyun #define LPTREG_DATA 0x000
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* LPT control register */
95*4882a593Smuzhiyun #define LPTCTRL_PROGRAM 0x04 /* 0 to reprogram */
96*4882a593Smuzhiyun #define LPTCTRL_WRITE 0x01
97*4882a593Smuzhiyun #define LPTCTRL_ADDRSTB 0x08
98*4882a593Smuzhiyun #define LPTCTRL_DATASTB 0x02
99*4882a593Smuzhiyun #define LPTCTRL_INTEN 0x10
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* LPT status register */
102*4882a593Smuzhiyun #define LPTSTAT_SHIFT_NINTR 6
103*4882a593Smuzhiyun #define LPTSTAT_WAIT 0x80
104*4882a593Smuzhiyun #define LPTSTAT_NINTR (1<<LPTSTAT_SHIFT_NINTR)
105*4882a593Smuzhiyun #define LPTSTAT_PE 0x20
106*4882a593Smuzhiyun #define LPTSTAT_DONE 0x10
107*4882a593Smuzhiyun #define LPTSTAT_NERROR 0x08
108*4882a593Smuzhiyun #define LPTSTAT_EPPTIMEOUT 0x01
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* LPT data register */
111*4882a593Smuzhiyun #define LPTDATA_SHIFT_TDI 0
112*4882a593Smuzhiyun #define LPTDATA_SHIFT_TMS 2
113*4882a593Smuzhiyun #define LPTDATA_TDI (1<<LPTDATA_SHIFT_TDI)
114*4882a593Smuzhiyun #define LPTDATA_TCK 0x02
115*4882a593Smuzhiyun #define LPTDATA_TMS (1<<LPTDATA_SHIFT_TMS)
116*4882a593Smuzhiyun #define LPTDATA_INITBIAS 0x80
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* EPP modem config/status bits */
120*4882a593Smuzhiyun #define EPP_DCDBIT 0x80
121*4882a593Smuzhiyun #define EPP_PTTBIT 0x08
122*4882a593Smuzhiyun #define EPP_RXEBIT 0x01
123*4882a593Smuzhiyun #define EPP_RXAEBIT 0x02
124*4882a593Smuzhiyun #define EPP_RXHFULL 0x04
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define EPP_NTHF 0x20
127*4882a593Smuzhiyun #define EPP_NTAEF 0x10
128*4882a593Smuzhiyun #define EPP_NTEF EPP_PTTBIT
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #define EPP_TX_FIFO_ENABLE 0x10
131*4882a593Smuzhiyun #define EPP_RX_FIFO_ENABLE 0x08
132*4882a593Smuzhiyun #define EPP_MODEM_ENABLE 0x20
133*4882a593Smuzhiyun #define EPP_LEDS 0xC0
134*4882a593Smuzhiyun #define EPP_IRQ_ENABLE 0x10
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* Xilinx 4k JTAG instructions */
137*4882a593Smuzhiyun #define XC4K_IRLENGTH 3
138*4882a593Smuzhiyun #define XC4K_EXTEST 0
139*4882a593Smuzhiyun #define XC4K_PRELOAD 1
140*4882a593Smuzhiyun #define XC4K_CONFIGURE 5
141*4882a593Smuzhiyun #define XC4K_BYPASS 7
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define EPP_CONVENTIONAL 0
144*4882a593Smuzhiyun #define EPP_FPGA 1
145*4882a593Smuzhiyun #define EPP_FPGAEXTSTATUS 2
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun #define TXBUFFER_SIZE ((HDLCDRV_MAXFLEN*6/5)+8)
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun * Information that need to be kept for each board.
152*4882a593Smuzhiyun */
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun struct baycom_state {
155*4882a593Smuzhiyun int magic;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun struct pardevice *pdev;
158*4882a593Smuzhiyun struct net_device *dev;
159*4882a593Smuzhiyun unsigned int work_running;
160*4882a593Smuzhiyun struct delayed_work run_work;
161*4882a593Smuzhiyun unsigned int modem;
162*4882a593Smuzhiyun unsigned int bitrate;
163*4882a593Smuzhiyun unsigned char stat;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun struct {
166*4882a593Smuzhiyun unsigned int intclk;
167*4882a593Smuzhiyun unsigned int fclk;
168*4882a593Smuzhiyun unsigned int bps;
169*4882a593Smuzhiyun unsigned int extmodem;
170*4882a593Smuzhiyun unsigned int loopback;
171*4882a593Smuzhiyun } cfg;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun struct hdlcdrv_channel_params ch_params;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun struct {
176*4882a593Smuzhiyun unsigned int bitbuf, bitstream, numbits, state;
177*4882a593Smuzhiyun unsigned char *bufptr;
178*4882a593Smuzhiyun int bufcnt;
179*4882a593Smuzhiyun unsigned char buf[TXBUFFER_SIZE];
180*4882a593Smuzhiyun } hdlcrx;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun struct {
183*4882a593Smuzhiyun int calibrate;
184*4882a593Smuzhiyun int slotcnt;
185*4882a593Smuzhiyun int flags;
186*4882a593Smuzhiyun enum { tx_idle = 0, tx_keyup, tx_data, tx_tail } state;
187*4882a593Smuzhiyun unsigned char *bufptr;
188*4882a593Smuzhiyun int bufcnt;
189*4882a593Smuzhiyun unsigned char buf[TXBUFFER_SIZE];
190*4882a593Smuzhiyun } hdlctx;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun unsigned int ptt_keyed;
193*4882a593Smuzhiyun struct sk_buff *skb; /* next transmit packet */
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun #ifdef BAYCOM_DEBUG
196*4882a593Smuzhiyun struct debug_vals {
197*4882a593Smuzhiyun unsigned long last_jiffies;
198*4882a593Smuzhiyun unsigned cur_intcnt;
199*4882a593Smuzhiyun unsigned last_intcnt;
200*4882a593Smuzhiyun int cur_pllcorr;
201*4882a593Smuzhiyun int last_pllcorr;
202*4882a593Smuzhiyun unsigned int mod_cycles;
203*4882a593Smuzhiyun unsigned int demod_cycles;
204*4882a593Smuzhiyun } debug_vals;
205*4882a593Smuzhiyun #endif /* BAYCOM_DEBUG */
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun #define KISS_VERBOSE
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun #define PARAM_TXDELAY 1
215*4882a593Smuzhiyun #define PARAM_PERSIST 2
216*4882a593Smuzhiyun #define PARAM_SLOTTIME 3
217*4882a593Smuzhiyun #define PARAM_TXTAIL 4
218*4882a593Smuzhiyun #define PARAM_FULLDUP 5
219*4882a593Smuzhiyun #define PARAM_HARDWARE 6
220*4882a593Smuzhiyun #define PARAM_RETURN 255
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
223*4882a593Smuzhiyun /*
224*4882a593Smuzhiyun * the CRC routines are stolen from WAMPES
225*4882a593Smuzhiyun * by Dieter Deyke
226*4882a593Smuzhiyun */
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /*---------------------------------------------------------------------------*/
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun #if 0
232*4882a593Smuzhiyun static inline void append_crc_ccitt(unsigned char *buffer, int len)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun unsigned int crc = 0xffff;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun for (;len>0;len--)
237*4882a593Smuzhiyun crc = (crc >> 8) ^ crc_ccitt_table[(crc ^ *buffer++) & 0xff];
238*4882a593Smuzhiyun crc ^= 0xffff;
239*4882a593Smuzhiyun *buffer++ = crc;
240*4882a593Smuzhiyun *buffer++ = crc >> 8;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun #endif
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /*---------------------------------------------------------------------------*/
245*4882a593Smuzhiyun
check_crc_ccitt(const unsigned char * buf,int cnt)246*4882a593Smuzhiyun static inline int check_crc_ccitt(const unsigned char *buf, int cnt)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun return (crc_ccitt(0xffff, buf, cnt) & 0xffff) == 0xf0b8;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /*---------------------------------------------------------------------------*/
252*4882a593Smuzhiyun
calc_crc_ccitt(const unsigned char * buf,int cnt)253*4882a593Smuzhiyun static inline int calc_crc_ccitt(const unsigned char *buf, int cnt)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun return (crc_ccitt(0xffff, buf, cnt) ^ 0xffff) & 0xffff;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun #define tenms_to_flags(bc,tenms) ((tenms * bc->bitrate) / 800)
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
263*4882a593Smuzhiyun
baycom_int_freq(struct baycom_state * bc)264*4882a593Smuzhiyun static inline void baycom_int_freq(struct baycom_state *bc)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun #ifdef BAYCOM_DEBUG
267*4882a593Smuzhiyun unsigned long cur_jiffies = jiffies;
268*4882a593Smuzhiyun /*
269*4882a593Smuzhiyun * measure the interrupt frequency
270*4882a593Smuzhiyun */
271*4882a593Smuzhiyun bc->debug_vals.cur_intcnt++;
272*4882a593Smuzhiyun if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
273*4882a593Smuzhiyun bc->debug_vals.last_jiffies = cur_jiffies;
274*4882a593Smuzhiyun bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
275*4882a593Smuzhiyun bc->debug_vals.cur_intcnt = 0;
276*4882a593Smuzhiyun bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
277*4882a593Smuzhiyun bc->debug_vals.cur_pllcorr = 0;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun #endif /* BAYCOM_DEBUG */
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
283*4882a593Smuzhiyun /*
284*4882a593Smuzhiyun * eppconfig_path should be setable via /proc/sys.
285*4882a593Smuzhiyun */
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun static char const eppconfig_path[] = "/usr/sbin/eppfpga";
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun static char *envp[] = { "HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL };
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* eppconfig: called during ifconfig up to configure the modem */
eppconfig(struct baycom_state * bc)292*4882a593Smuzhiyun static int eppconfig(struct baycom_state *bc)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun char modearg[256];
295*4882a593Smuzhiyun char portarg[16];
296*4882a593Smuzhiyun char *argv[] = {
297*4882a593Smuzhiyun (char *)eppconfig_path,
298*4882a593Smuzhiyun "-s",
299*4882a593Smuzhiyun "-p", portarg,
300*4882a593Smuzhiyun "-m", modearg,
301*4882a593Smuzhiyun NULL };
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* set up arguments */
304*4882a593Smuzhiyun sprintf(modearg, "%sclk,%smodem,fclk=%d,bps=%d,divider=%d%s,extstat",
305*4882a593Smuzhiyun bc->cfg.intclk ? "int" : "ext",
306*4882a593Smuzhiyun bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
307*4882a593Smuzhiyun (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
308*4882a593Smuzhiyun bc->cfg.loopback ? ",loopback" : "");
309*4882a593Smuzhiyun sprintf(portarg, "%ld", bc->pdev->port->base);
310*4882a593Smuzhiyun printk(KERN_DEBUG "%s: %s -s -p %s -m %s\n", bc_drvname, eppconfig_path, portarg, modearg);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun return call_usermodehelper(eppconfig_path, argv, envp, UMH_WAIT_PROC);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
316*4882a593Smuzhiyun
do_kiss_params(struct baycom_state * bc,unsigned char * data,unsigned long len)317*4882a593Smuzhiyun static inline void do_kiss_params(struct baycom_state *bc,
318*4882a593Smuzhiyun unsigned char *data, unsigned long len)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun #ifdef KISS_VERBOSE
322*4882a593Smuzhiyun #define PKP(a,b) printk(KERN_INFO "baycomm_epp: channel params: " a "\n", b)
323*4882a593Smuzhiyun #else /* KISS_VERBOSE */
324*4882a593Smuzhiyun #define PKP(a,b)
325*4882a593Smuzhiyun #endif /* KISS_VERBOSE */
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (len < 2)
328*4882a593Smuzhiyun return;
329*4882a593Smuzhiyun switch(data[0]) {
330*4882a593Smuzhiyun case PARAM_TXDELAY:
331*4882a593Smuzhiyun bc->ch_params.tx_delay = data[1];
332*4882a593Smuzhiyun PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay);
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun case PARAM_PERSIST:
335*4882a593Smuzhiyun bc->ch_params.ppersist = data[1];
336*4882a593Smuzhiyun PKP("p persistence = %u", bc->ch_params.ppersist);
337*4882a593Smuzhiyun break;
338*4882a593Smuzhiyun case PARAM_SLOTTIME:
339*4882a593Smuzhiyun bc->ch_params.slottime = data[1];
340*4882a593Smuzhiyun PKP("slot time = %ums", bc->ch_params.slottime);
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun case PARAM_TXTAIL:
343*4882a593Smuzhiyun bc->ch_params.tx_tail = data[1];
344*4882a593Smuzhiyun PKP("TX tail = %ums", bc->ch_params.tx_tail);
345*4882a593Smuzhiyun break;
346*4882a593Smuzhiyun case PARAM_FULLDUP:
347*4882a593Smuzhiyun bc->ch_params.fulldup = !!data[1];
348*4882a593Smuzhiyun PKP("%s duplex", bc->ch_params.fulldup ? "full" : "half");
349*4882a593Smuzhiyun break;
350*4882a593Smuzhiyun default:
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun #undef PKP
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
357*4882a593Smuzhiyun
encode_hdlc(struct baycom_state * bc)358*4882a593Smuzhiyun static void encode_hdlc(struct baycom_state *bc)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun struct sk_buff *skb;
361*4882a593Smuzhiyun unsigned char *wp, *bp;
362*4882a593Smuzhiyun int pkt_len;
363*4882a593Smuzhiyun unsigned bitstream, notbitstream, bitbuf, numbit, crc;
364*4882a593Smuzhiyun unsigned char crcarr[2];
365*4882a593Smuzhiyun int j;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun if (bc->hdlctx.bufcnt > 0)
368*4882a593Smuzhiyun return;
369*4882a593Smuzhiyun skb = bc->skb;
370*4882a593Smuzhiyun if (!skb)
371*4882a593Smuzhiyun return;
372*4882a593Smuzhiyun bc->skb = NULL;
373*4882a593Smuzhiyun pkt_len = skb->len-1; /* strip KISS byte */
374*4882a593Smuzhiyun wp = bc->hdlctx.buf;
375*4882a593Smuzhiyun bp = skb->data+1;
376*4882a593Smuzhiyun crc = calc_crc_ccitt(bp, pkt_len);
377*4882a593Smuzhiyun crcarr[0] = crc;
378*4882a593Smuzhiyun crcarr[1] = crc >> 8;
379*4882a593Smuzhiyun *wp++ = 0x7e;
380*4882a593Smuzhiyun bitstream = bitbuf = numbit = 0;
381*4882a593Smuzhiyun while (pkt_len > -2) {
382*4882a593Smuzhiyun bitstream >>= 8;
383*4882a593Smuzhiyun bitstream |= ((unsigned int)*bp) << 8;
384*4882a593Smuzhiyun bitbuf |= ((unsigned int)*bp) << numbit;
385*4882a593Smuzhiyun notbitstream = ~bitstream;
386*4882a593Smuzhiyun bp++;
387*4882a593Smuzhiyun pkt_len--;
388*4882a593Smuzhiyun if (!pkt_len)
389*4882a593Smuzhiyun bp = crcarr;
390*4882a593Smuzhiyun for (j = 0; j < 8; j++)
391*4882a593Smuzhiyun if (unlikely(!(notbitstream & (0x1f0 << j)))) {
392*4882a593Smuzhiyun bitstream &= ~(0x100 << j);
393*4882a593Smuzhiyun bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
394*4882a593Smuzhiyun ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
395*4882a593Smuzhiyun numbit++;
396*4882a593Smuzhiyun notbitstream = ~bitstream;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun numbit += 8;
399*4882a593Smuzhiyun while (numbit >= 8) {
400*4882a593Smuzhiyun *wp++ = bitbuf;
401*4882a593Smuzhiyun bitbuf >>= 8;
402*4882a593Smuzhiyun numbit -= 8;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun bitbuf |= 0x7e7e << numbit;
406*4882a593Smuzhiyun numbit += 16;
407*4882a593Smuzhiyun while (numbit >= 8) {
408*4882a593Smuzhiyun *wp++ = bitbuf;
409*4882a593Smuzhiyun bitbuf >>= 8;
410*4882a593Smuzhiyun numbit -= 8;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun bc->hdlctx.bufptr = bc->hdlctx.buf;
413*4882a593Smuzhiyun bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;
414*4882a593Smuzhiyun dev_kfree_skb(skb);
415*4882a593Smuzhiyun bc->dev->stats.tx_packets++;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
419*4882a593Smuzhiyun
transmit(struct baycom_state * bc,int cnt,unsigned char stat)420*4882a593Smuzhiyun static int transmit(struct baycom_state *bc, int cnt, unsigned char stat)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun struct parport *pp = bc->pdev->port;
423*4882a593Smuzhiyun unsigned char tmp[128];
424*4882a593Smuzhiyun int i, j;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun if (bc->hdlctx.state == tx_tail && !(stat & EPP_PTTBIT))
427*4882a593Smuzhiyun bc->hdlctx.state = tx_idle;
428*4882a593Smuzhiyun if (bc->hdlctx.state == tx_idle && bc->hdlctx.calibrate <= 0) {
429*4882a593Smuzhiyun if (bc->hdlctx.bufcnt <= 0)
430*4882a593Smuzhiyun encode_hdlc(bc);
431*4882a593Smuzhiyun if (bc->hdlctx.bufcnt <= 0)
432*4882a593Smuzhiyun return 0;
433*4882a593Smuzhiyun if (!bc->ch_params.fulldup) {
434*4882a593Smuzhiyun if (!(stat & EPP_DCDBIT)) {
435*4882a593Smuzhiyun bc->hdlctx.slotcnt = bc->ch_params.slottime;
436*4882a593Smuzhiyun return 0;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun if ((--bc->hdlctx.slotcnt) > 0)
439*4882a593Smuzhiyun return 0;
440*4882a593Smuzhiyun bc->hdlctx.slotcnt = bc->ch_params.slottime;
441*4882a593Smuzhiyun if ((prandom_u32() % 256) > bc->ch_params.ppersist)
442*4882a593Smuzhiyun return 0;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun if (bc->hdlctx.state == tx_idle && bc->hdlctx.bufcnt > 0) {
446*4882a593Smuzhiyun bc->hdlctx.state = tx_keyup;
447*4882a593Smuzhiyun bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay);
448*4882a593Smuzhiyun bc->ptt_keyed++;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun while (cnt > 0) {
451*4882a593Smuzhiyun switch (bc->hdlctx.state) {
452*4882a593Smuzhiyun case tx_keyup:
453*4882a593Smuzhiyun i = min_t(int, cnt, bc->hdlctx.flags);
454*4882a593Smuzhiyun cnt -= i;
455*4882a593Smuzhiyun bc->hdlctx.flags -= i;
456*4882a593Smuzhiyun if (bc->hdlctx.flags <= 0)
457*4882a593Smuzhiyun bc->hdlctx.state = tx_data;
458*4882a593Smuzhiyun memset(tmp, 0x7e, sizeof(tmp));
459*4882a593Smuzhiyun while (i > 0) {
460*4882a593Smuzhiyun j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
461*4882a593Smuzhiyun if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
462*4882a593Smuzhiyun return -1;
463*4882a593Smuzhiyun i -= j;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun case tx_data:
468*4882a593Smuzhiyun if (bc->hdlctx.bufcnt <= 0) {
469*4882a593Smuzhiyun encode_hdlc(bc);
470*4882a593Smuzhiyun if (bc->hdlctx.bufcnt <= 0) {
471*4882a593Smuzhiyun bc->hdlctx.state = tx_tail;
472*4882a593Smuzhiyun bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_tail);
473*4882a593Smuzhiyun break;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun i = min_t(int, cnt, bc->hdlctx.bufcnt);
477*4882a593Smuzhiyun bc->hdlctx.bufcnt -= i;
478*4882a593Smuzhiyun cnt -= i;
479*4882a593Smuzhiyun if (i != pp->ops->epp_write_data(pp, bc->hdlctx.bufptr, i, 0))
480*4882a593Smuzhiyun return -1;
481*4882a593Smuzhiyun bc->hdlctx.bufptr += i;
482*4882a593Smuzhiyun break;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun case tx_tail:
485*4882a593Smuzhiyun encode_hdlc(bc);
486*4882a593Smuzhiyun if (bc->hdlctx.bufcnt > 0) {
487*4882a593Smuzhiyun bc->hdlctx.state = tx_data;
488*4882a593Smuzhiyun break;
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun i = min_t(int, cnt, bc->hdlctx.flags);
491*4882a593Smuzhiyun if (i) {
492*4882a593Smuzhiyun cnt -= i;
493*4882a593Smuzhiyun bc->hdlctx.flags -= i;
494*4882a593Smuzhiyun memset(tmp, 0x7e, sizeof(tmp));
495*4882a593Smuzhiyun while (i > 0) {
496*4882a593Smuzhiyun j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
497*4882a593Smuzhiyun if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
498*4882a593Smuzhiyun return -1;
499*4882a593Smuzhiyun i -= j;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun break;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun fallthrough;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun default:
506*4882a593Smuzhiyun if (bc->hdlctx.calibrate <= 0)
507*4882a593Smuzhiyun return 0;
508*4882a593Smuzhiyun i = min_t(int, cnt, bc->hdlctx.calibrate);
509*4882a593Smuzhiyun cnt -= i;
510*4882a593Smuzhiyun bc->hdlctx.calibrate -= i;
511*4882a593Smuzhiyun memset(tmp, 0, sizeof(tmp));
512*4882a593Smuzhiyun while (i > 0) {
513*4882a593Smuzhiyun j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
514*4882a593Smuzhiyun if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
515*4882a593Smuzhiyun return -1;
516*4882a593Smuzhiyun i -= j;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun break;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun return 0;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
525*4882a593Smuzhiyun
do_rxpacket(struct net_device * dev)526*4882a593Smuzhiyun static void do_rxpacket(struct net_device *dev)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
529*4882a593Smuzhiyun struct sk_buff *skb;
530*4882a593Smuzhiyun unsigned char *cp;
531*4882a593Smuzhiyun unsigned pktlen;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun if (bc->hdlcrx.bufcnt < 4)
534*4882a593Smuzhiyun return;
535*4882a593Smuzhiyun if (!check_crc_ccitt(bc->hdlcrx.buf, bc->hdlcrx.bufcnt))
536*4882a593Smuzhiyun return;
537*4882a593Smuzhiyun pktlen = bc->hdlcrx.bufcnt-2+1; /* KISS kludge */
538*4882a593Smuzhiyun if (!(skb = dev_alloc_skb(pktlen))) {
539*4882a593Smuzhiyun printk("%s: memory squeeze, dropping packet\n", dev->name);
540*4882a593Smuzhiyun dev->stats.rx_dropped++;
541*4882a593Smuzhiyun return;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun cp = skb_put(skb, pktlen);
544*4882a593Smuzhiyun *cp++ = 0; /* KISS kludge */
545*4882a593Smuzhiyun memcpy(cp, bc->hdlcrx.buf, pktlen - 1);
546*4882a593Smuzhiyun skb->protocol = ax25_type_trans(skb, dev);
547*4882a593Smuzhiyun netif_rx(skb);
548*4882a593Smuzhiyun dev->stats.rx_packets++;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
receive(struct net_device * dev,int cnt)551*4882a593Smuzhiyun static int receive(struct net_device *dev, int cnt)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
554*4882a593Smuzhiyun struct parport *pp = bc->pdev->port;
555*4882a593Smuzhiyun unsigned int bitbuf, notbitstream, bitstream, numbits, state;
556*4882a593Smuzhiyun unsigned char tmp[128];
557*4882a593Smuzhiyun unsigned char *cp;
558*4882a593Smuzhiyun int cnt2, ret = 0;
559*4882a593Smuzhiyun int j;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun numbits = bc->hdlcrx.numbits;
562*4882a593Smuzhiyun state = bc->hdlcrx.state;
563*4882a593Smuzhiyun bitstream = bc->hdlcrx.bitstream;
564*4882a593Smuzhiyun bitbuf = bc->hdlcrx.bitbuf;
565*4882a593Smuzhiyun while (cnt > 0) {
566*4882a593Smuzhiyun cnt2 = (cnt > sizeof(tmp)) ? sizeof(tmp) : cnt;
567*4882a593Smuzhiyun cnt -= cnt2;
568*4882a593Smuzhiyun if (cnt2 != pp->ops->epp_read_data(pp, tmp, cnt2, 0)) {
569*4882a593Smuzhiyun ret = -1;
570*4882a593Smuzhiyun break;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun cp = tmp;
573*4882a593Smuzhiyun for (; cnt2 > 0; cnt2--, cp++) {
574*4882a593Smuzhiyun bitstream >>= 8;
575*4882a593Smuzhiyun bitstream |= (*cp) << 8;
576*4882a593Smuzhiyun bitbuf >>= 8;
577*4882a593Smuzhiyun bitbuf |= (*cp) << 8;
578*4882a593Smuzhiyun numbits += 8;
579*4882a593Smuzhiyun notbitstream = ~bitstream;
580*4882a593Smuzhiyun for (j = 0; j < 8; j++) {
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun /* flag or abort */
583*4882a593Smuzhiyun if (unlikely(!(notbitstream & (0x0fc << j)))) {
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* abort received */
586*4882a593Smuzhiyun if (!(notbitstream & (0x1fc << j)))
587*4882a593Smuzhiyun state = 0;
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun /* flag received */
590*4882a593Smuzhiyun else if ((bitstream & (0x1fe << j)) == (0x0fc << j)) {
591*4882a593Smuzhiyun if (state)
592*4882a593Smuzhiyun do_rxpacket(dev);
593*4882a593Smuzhiyun bc->hdlcrx.bufcnt = 0;
594*4882a593Smuzhiyun bc->hdlcrx.bufptr = bc->hdlcrx.buf;
595*4882a593Smuzhiyun state = 1;
596*4882a593Smuzhiyun numbits = 7-j;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun /* stuffed bit */
601*4882a593Smuzhiyun else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
602*4882a593Smuzhiyun numbits--;
603*4882a593Smuzhiyun bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun while (state && numbits >= 8) {
607*4882a593Smuzhiyun if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
608*4882a593Smuzhiyun state = 0;
609*4882a593Smuzhiyun } else {
610*4882a593Smuzhiyun *(bc->hdlcrx.bufptr)++ = bitbuf >> (16-numbits);
611*4882a593Smuzhiyun bc->hdlcrx.bufcnt++;
612*4882a593Smuzhiyun numbits -= 8;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun bc->hdlcrx.numbits = numbits;
618*4882a593Smuzhiyun bc->hdlcrx.state = state;
619*4882a593Smuzhiyun bc->hdlcrx.bitstream = bitstream;
620*4882a593Smuzhiyun bc->hdlcrx.bitbuf = bitbuf;
621*4882a593Smuzhiyun return ret;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun #ifdef __i386__
627*4882a593Smuzhiyun #include <asm/msr.h>
628*4882a593Smuzhiyun #define GETTICK(x) \
629*4882a593Smuzhiyun ({ \
630*4882a593Smuzhiyun if (boot_cpu_has(X86_FEATURE_TSC)) \
631*4882a593Smuzhiyun x = (unsigned int)rdtsc(); \
632*4882a593Smuzhiyun })
633*4882a593Smuzhiyun #else /* __i386__ */
634*4882a593Smuzhiyun #define GETTICK(x)
635*4882a593Smuzhiyun #endif /* __i386__ */
636*4882a593Smuzhiyun
epp_bh(struct work_struct * work)637*4882a593Smuzhiyun static void epp_bh(struct work_struct *work)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun struct net_device *dev;
640*4882a593Smuzhiyun struct baycom_state *bc;
641*4882a593Smuzhiyun struct parport *pp;
642*4882a593Smuzhiyun unsigned char stat;
643*4882a593Smuzhiyun unsigned char tmp[2];
644*4882a593Smuzhiyun unsigned int time1 = 0, time2 = 0, time3 = 0;
645*4882a593Smuzhiyun int cnt, cnt2;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun bc = container_of(work, struct baycom_state, run_work.work);
648*4882a593Smuzhiyun dev = bc->dev;
649*4882a593Smuzhiyun if (!bc->work_running)
650*4882a593Smuzhiyun return;
651*4882a593Smuzhiyun baycom_int_freq(bc);
652*4882a593Smuzhiyun pp = bc->pdev->port;
653*4882a593Smuzhiyun /* update status */
654*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
655*4882a593Smuzhiyun goto epptimeout;
656*4882a593Smuzhiyun bc->stat = stat;
657*4882a593Smuzhiyun bc->debug_vals.last_pllcorr = stat;
658*4882a593Smuzhiyun GETTICK(time1);
659*4882a593Smuzhiyun if (bc->modem == EPP_FPGAEXTSTATUS) {
660*4882a593Smuzhiyun /* get input count */
661*4882a593Smuzhiyun tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|1;
662*4882a593Smuzhiyun if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
663*4882a593Smuzhiyun goto epptimeout;
664*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
665*4882a593Smuzhiyun goto epptimeout;
666*4882a593Smuzhiyun cnt = tmp[0] | (tmp[1] << 8);
667*4882a593Smuzhiyun cnt &= 0x7fff;
668*4882a593Smuzhiyun /* get output count */
669*4882a593Smuzhiyun tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|2;
670*4882a593Smuzhiyun if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
671*4882a593Smuzhiyun goto epptimeout;
672*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
673*4882a593Smuzhiyun goto epptimeout;
674*4882a593Smuzhiyun cnt2 = tmp[0] | (tmp[1] << 8);
675*4882a593Smuzhiyun cnt2 = 16384 - (cnt2 & 0x7fff);
676*4882a593Smuzhiyun /* return to normal */
677*4882a593Smuzhiyun tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
678*4882a593Smuzhiyun if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
679*4882a593Smuzhiyun goto epptimeout;
680*4882a593Smuzhiyun if (transmit(bc, cnt2, stat))
681*4882a593Smuzhiyun goto epptimeout;
682*4882a593Smuzhiyun GETTICK(time2);
683*4882a593Smuzhiyun if (receive(dev, cnt))
684*4882a593Smuzhiyun goto epptimeout;
685*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
686*4882a593Smuzhiyun goto epptimeout;
687*4882a593Smuzhiyun bc->stat = stat;
688*4882a593Smuzhiyun } else {
689*4882a593Smuzhiyun /* try to tx */
690*4882a593Smuzhiyun switch (stat & (EPP_NTAEF|EPP_NTHF)) {
691*4882a593Smuzhiyun case EPP_NTHF:
692*4882a593Smuzhiyun cnt = 2048 - 256;
693*4882a593Smuzhiyun break;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun case EPP_NTAEF:
696*4882a593Smuzhiyun cnt = 2048 - 1793;
697*4882a593Smuzhiyun break;
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun case 0:
700*4882a593Smuzhiyun cnt = 0;
701*4882a593Smuzhiyun break;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun default:
704*4882a593Smuzhiyun cnt = 2048 - 1025;
705*4882a593Smuzhiyun break;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun if (transmit(bc, cnt, stat))
708*4882a593Smuzhiyun goto epptimeout;
709*4882a593Smuzhiyun GETTICK(time2);
710*4882a593Smuzhiyun /* do receiver */
711*4882a593Smuzhiyun while ((stat & (EPP_NRAEF|EPP_NRHF)) != EPP_NRHF) {
712*4882a593Smuzhiyun switch (stat & (EPP_NRAEF|EPP_NRHF)) {
713*4882a593Smuzhiyun case EPP_NRAEF:
714*4882a593Smuzhiyun cnt = 1025;
715*4882a593Smuzhiyun break;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun case 0:
718*4882a593Smuzhiyun cnt = 1793;
719*4882a593Smuzhiyun break;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun default:
722*4882a593Smuzhiyun cnt = 256;
723*4882a593Smuzhiyun break;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun if (receive(dev, cnt))
726*4882a593Smuzhiyun goto epptimeout;
727*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
728*4882a593Smuzhiyun goto epptimeout;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun cnt = 0;
731*4882a593Smuzhiyun if (bc->bitrate < 50000)
732*4882a593Smuzhiyun cnt = 256;
733*4882a593Smuzhiyun else if (bc->bitrate < 100000)
734*4882a593Smuzhiyun cnt = 128;
735*4882a593Smuzhiyun while (cnt > 0 && stat & EPP_NREF) {
736*4882a593Smuzhiyun if (receive(dev, 1))
737*4882a593Smuzhiyun goto epptimeout;
738*4882a593Smuzhiyun cnt--;
739*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
740*4882a593Smuzhiyun goto epptimeout;
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun GETTICK(time3);
744*4882a593Smuzhiyun #ifdef BAYCOM_DEBUG
745*4882a593Smuzhiyun bc->debug_vals.mod_cycles = time2 - time1;
746*4882a593Smuzhiyun bc->debug_vals.demod_cycles = time3 - time2;
747*4882a593Smuzhiyun #endif /* BAYCOM_DEBUG */
748*4882a593Smuzhiyun schedule_delayed_work(&bc->run_work, 1);
749*4882a593Smuzhiyun if (!bc->skb)
750*4882a593Smuzhiyun netif_wake_queue(dev);
751*4882a593Smuzhiyun return;
752*4882a593Smuzhiyun epptimeout:
753*4882a593Smuzhiyun printk(KERN_ERR "%s: EPP timeout!\n", bc_drvname);
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */
757*4882a593Smuzhiyun /*
758*4882a593Smuzhiyun * ===================== network driver interface =========================
759*4882a593Smuzhiyun */
760*4882a593Smuzhiyun
baycom_send_packet(struct sk_buff * skb,struct net_device * dev)761*4882a593Smuzhiyun static int baycom_send_packet(struct sk_buff *skb, struct net_device *dev)
762*4882a593Smuzhiyun {
763*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun if (skb->protocol == htons(ETH_P_IP))
766*4882a593Smuzhiyun return ax25_ip_xmit(skb);
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun if (skb->data[0] != 0) {
769*4882a593Smuzhiyun do_kiss_params(bc, skb->data, skb->len);
770*4882a593Smuzhiyun dev_kfree_skb(skb);
771*4882a593Smuzhiyun return NETDEV_TX_OK;
772*4882a593Smuzhiyun }
773*4882a593Smuzhiyun if (bc->skb) {
774*4882a593Smuzhiyun dev_kfree_skb(skb);
775*4882a593Smuzhiyun return NETDEV_TX_OK;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun /* strip KISS byte */
778*4882a593Smuzhiyun if (skb->len >= HDLCDRV_MAXFLEN+1 || skb->len < 3) {
779*4882a593Smuzhiyun dev_kfree_skb(skb);
780*4882a593Smuzhiyun return NETDEV_TX_OK;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun netif_stop_queue(dev);
783*4882a593Smuzhiyun bc->skb = skb;
784*4882a593Smuzhiyun return NETDEV_TX_OK;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
788*4882a593Smuzhiyun
baycom_set_mac_address(struct net_device * dev,void * addr)789*4882a593Smuzhiyun static int baycom_set_mac_address(struct net_device *dev, void *addr)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun struct sockaddr *sa = (struct sockaddr *)addr;
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun /* addr is an AX.25 shifted ASCII mac address */
794*4882a593Smuzhiyun memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
795*4882a593Smuzhiyun return 0;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
799*4882a593Smuzhiyun
epp_wakeup(void * handle)800*4882a593Smuzhiyun static void epp_wakeup(void *handle)
801*4882a593Smuzhiyun {
802*4882a593Smuzhiyun struct net_device *dev = (struct net_device *)handle;
803*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun printk(KERN_DEBUG "baycom_epp: %s: why am I being woken up?\n", dev->name);
806*4882a593Smuzhiyun if (!parport_claim(bc->pdev))
807*4882a593Smuzhiyun printk(KERN_DEBUG "baycom_epp: %s: I'm broken.\n", dev->name);
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun /*
813*4882a593Smuzhiyun * Open/initialize the board. This is called (in the current kernel)
814*4882a593Smuzhiyun * sometime after booting when the 'ifconfig' program is run.
815*4882a593Smuzhiyun *
816*4882a593Smuzhiyun * This routine should set everything up anew at each open, even
817*4882a593Smuzhiyun * registers that "should" only need to be set once at boot, so that
818*4882a593Smuzhiyun * there is non-reboot way to recover if something goes wrong.
819*4882a593Smuzhiyun */
820*4882a593Smuzhiyun
epp_open(struct net_device * dev)821*4882a593Smuzhiyun static int epp_open(struct net_device *dev)
822*4882a593Smuzhiyun {
823*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
824*4882a593Smuzhiyun struct parport *pp = parport_find_base(dev->base_addr);
825*4882a593Smuzhiyun unsigned int i, j;
826*4882a593Smuzhiyun unsigned char tmp[128];
827*4882a593Smuzhiyun unsigned char stat;
828*4882a593Smuzhiyun unsigned long tstart;
829*4882a593Smuzhiyun struct pardev_cb par_cb;
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun if (!pp) {
832*4882a593Smuzhiyun printk(KERN_ERR "%s: parport at 0x%lx unknown\n", bc_drvname, dev->base_addr);
833*4882a593Smuzhiyun return -ENXIO;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun #if 0
836*4882a593Smuzhiyun if (pp->irq < 0) {
837*4882a593Smuzhiyun printk(KERN_ERR "%s: parport at 0x%lx has no irq\n", bc_drvname, pp->base);
838*4882a593Smuzhiyun parport_put_port(pp);
839*4882a593Smuzhiyun return -ENXIO;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun #endif
842*4882a593Smuzhiyun if ((~pp->modes) & (PARPORT_MODE_TRISTATE | PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT)) {
843*4882a593Smuzhiyun printk(KERN_ERR "%s: parport at 0x%lx cannot be used\n",
844*4882a593Smuzhiyun bc_drvname, pp->base);
845*4882a593Smuzhiyun parport_put_port(pp);
846*4882a593Smuzhiyun return -EIO;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun memset(&bc->modem, 0, sizeof(bc->modem));
849*4882a593Smuzhiyun memset(&par_cb, 0, sizeof(par_cb));
850*4882a593Smuzhiyun par_cb.wakeup = epp_wakeup;
851*4882a593Smuzhiyun par_cb.private = (void *)dev;
852*4882a593Smuzhiyun par_cb.flags = PARPORT_DEV_EXCL;
853*4882a593Smuzhiyun for (i = 0; i < NR_PORTS; i++)
854*4882a593Smuzhiyun if (baycom_device[i] == dev)
855*4882a593Smuzhiyun break;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun if (i == NR_PORTS) {
858*4882a593Smuzhiyun pr_err("%s: no device found\n", bc_drvname);
859*4882a593Smuzhiyun parport_put_port(pp);
860*4882a593Smuzhiyun return -ENODEV;
861*4882a593Smuzhiyun }
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun bc->pdev = parport_register_dev_model(pp, dev->name, &par_cb, i);
864*4882a593Smuzhiyun parport_put_port(pp);
865*4882a593Smuzhiyun if (!bc->pdev) {
866*4882a593Smuzhiyun printk(KERN_ERR "%s: cannot register parport at 0x%lx\n", bc_drvname, pp->base);
867*4882a593Smuzhiyun return -ENXIO;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun if (parport_claim(bc->pdev)) {
870*4882a593Smuzhiyun printk(KERN_ERR "%s: parport at 0x%lx busy\n", bc_drvname, pp->base);
871*4882a593Smuzhiyun parport_unregister_device(bc->pdev);
872*4882a593Smuzhiyun return -EBUSY;
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun dev->irq = /*pp->irq*/ 0;
875*4882a593Smuzhiyun INIT_DELAYED_WORK(&bc->run_work, epp_bh);
876*4882a593Smuzhiyun bc->work_running = 1;
877*4882a593Smuzhiyun bc->modem = EPP_CONVENTIONAL;
878*4882a593Smuzhiyun if (eppconfig(bc))
879*4882a593Smuzhiyun printk(KERN_INFO "%s: no FPGA detected, assuming conventional EPP modem\n", bc_drvname);
880*4882a593Smuzhiyun else
881*4882a593Smuzhiyun bc->modem = /*EPP_FPGA*/ EPP_FPGAEXTSTATUS;
882*4882a593Smuzhiyun parport_write_control(pp, LPTCTRL_PROGRAM); /* prepare EPP mode; we aren't using interrupts */
883*4882a593Smuzhiyun /* reset the modem */
884*4882a593Smuzhiyun tmp[0] = 0;
885*4882a593Smuzhiyun tmp[1] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
886*4882a593Smuzhiyun if (pp->ops->epp_write_addr(pp, tmp, 2, 0) != 2)
887*4882a593Smuzhiyun goto epptimeout;
888*4882a593Smuzhiyun /* autoprobe baud rate */
889*4882a593Smuzhiyun tstart = jiffies;
890*4882a593Smuzhiyun i = 0;
891*4882a593Smuzhiyun while (time_before(jiffies, tstart + HZ/3)) {
892*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
893*4882a593Smuzhiyun goto epptimeout;
894*4882a593Smuzhiyun if ((stat & (EPP_NRAEF|EPP_NRHF)) == EPP_NRHF) {
895*4882a593Smuzhiyun schedule();
896*4882a593Smuzhiyun continue;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
899*4882a593Smuzhiyun goto epptimeout;
900*4882a593Smuzhiyun if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
901*4882a593Smuzhiyun goto epptimeout;
902*4882a593Smuzhiyun i += 256;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun for (j = 0; j < 256; j++) {
905*4882a593Smuzhiyun if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
906*4882a593Smuzhiyun goto epptimeout;
907*4882a593Smuzhiyun if (!(stat & EPP_NREF))
908*4882a593Smuzhiyun break;
909*4882a593Smuzhiyun if (pp->ops->epp_read_data(pp, tmp, 1, 0) != 1)
910*4882a593Smuzhiyun goto epptimeout;
911*4882a593Smuzhiyun i++;
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun tstart = jiffies - tstart;
914*4882a593Smuzhiyun bc->bitrate = i * (8 * HZ) / tstart;
915*4882a593Smuzhiyun j = 1;
916*4882a593Smuzhiyun i = bc->bitrate >> 3;
917*4882a593Smuzhiyun while (j < 7 && i > 150) {
918*4882a593Smuzhiyun j++;
919*4882a593Smuzhiyun i >>= 1;
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun printk(KERN_INFO "%s: autoprobed bitrate: %d int divider: %d int rate: %d\n",
922*4882a593Smuzhiyun bc_drvname, bc->bitrate, j, bc->bitrate >> (j+2));
923*4882a593Smuzhiyun tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE/*|j*/;
924*4882a593Smuzhiyun if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
925*4882a593Smuzhiyun goto epptimeout;
926*4882a593Smuzhiyun /*
927*4882a593Smuzhiyun * initialise hdlc variables
928*4882a593Smuzhiyun */
929*4882a593Smuzhiyun bc->hdlcrx.state = 0;
930*4882a593Smuzhiyun bc->hdlcrx.numbits = 0;
931*4882a593Smuzhiyun bc->hdlctx.state = tx_idle;
932*4882a593Smuzhiyun bc->hdlctx.bufcnt = 0;
933*4882a593Smuzhiyun bc->hdlctx.slotcnt = bc->ch_params.slottime;
934*4882a593Smuzhiyun bc->hdlctx.calibrate = 0;
935*4882a593Smuzhiyun /* start the bottom half stuff */
936*4882a593Smuzhiyun schedule_delayed_work(&bc->run_work, 1);
937*4882a593Smuzhiyun netif_start_queue(dev);
938*4882a593Smuzhiyun return 0;
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun epptimeout:
941*4882a593Smuzhiyun printk(KERN_ERR "%s: epp timeout during bitrate probe\n", bc_drvname);
942*4882a593Smuzhiyun parport_write_control(pp, 0); /* reset the adapter */
943*4882a593Smuzhiyun parport_release(bc->pdev);
944*4882a593Smuzhiyun parport_unregister_device(bc->pdev);
945*4882a593Smuzhiyun return -EIO;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
949*4882a593Smuzhiyun
epp_close(struct net_device * dev)950*4882a593Smuzhiyun static int epp_close(struct net_device *dev)
951*4882a593Smuzhiyun {
952*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
953*4882a593Smuzhiyun struct parport *pp = bc->pdev->port;
954*4882a593Smuzhiyun unsigned char tmp[1];
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun bc->work_running = 0;
957*4882a593Smuzhiyun cancel_delayed_work_sync(&bc->run_work);
958*4882a593Smuzhiyun bc->stat = EPP_DCDBIT;
959*4882a593Smuzhiyun tmp[0] = 0;
960*4882a593Smuzhiyun pp->ops->epp_write_addr(pp, tmp, 1, 0);
961*4882a593Smuzhiyun parport_write_control(pp, 0); /* reset the adapter */
962*4882a593Smuzhiyun parport_release(bc->pdev);
963*4882a593Smuzhiyun parport_unregister_device(bc->pdev);
964*4882a593Smuzhiyun dev_kfree_skb(bc->skb);
965*4882a593Smuzhiyun bc->skb = NULL;
966*4882a593Smuzhiyun printk(KERN_INFO "%s: close epp at iobase 0x%lx irq %u\n",
967*4882a593Smuzhiyun bc_drvname, dev->base_addr, dev->irq);
968*4882a593Smuzhiyun return 0;
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
972*4882a593Smuzhiyun
baycom_setmode(struct baycom_state * bc,const char * modestr)973*4882a593Smuzhiyun static int baycom_setmode(struct baycom_state *bc, const char *modestr)
974*4882a593Smuzhiyun {
975*4882a593Smuzhiyun const char *cp;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun if (strstr(modestr,"intclk"))
978*4882a593Smuzhiyun bc->cfg.intclk = 1;
979*4882a593Smuzhiyun if (strstr(modestr,"extclk"))
980*4882a593Smuzhiyun bc->cfg.intclk = 0;
981*4882a593Smuzhiyun if (strstr(modestr,"intmodem"))
982*4882a593Smuzhiyun bc->cfg.extmodem = 0;
983*4882a593Smuzhiyun if (strstr(modestr,"extmodem"))
984*4882a593Smuzhiyun bc->cfg.extmodem = 1;
985*4882a593Smuzhiyun if (strstr(modestr,"noloopback"))
986*4882a593Smuzhiyun bc->cfg.loopback = 0;
987*4882a593Smuzhiyun if (strstr(modestr,"loopback"))
988*4882a593Smuzhiyun bc->cfg.loopback = 1;
989*4882a593Smuzhiyun if ((cp = strstr(modestr,"fclk="))) {
990*4882a593Smuzhiyun bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
991*4882a593Smuzhiyun if (bc->cfg.fclk < 1000000)
992*4882a593Smuzhiyun bc->cfg.fclk = 1000000;
993*4882a593Smuzhiyun if (bc->cfg.fclk > 25000000)
994*4882a593Smuzhiyun bc->cfg.fclk = 25000000;
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun if ((cp = strstr(modestr,"bps="))) {
997*4882a593Smuzhiyun bc->cfg.bps = simple_strtoul(cp+4, NULL, 0);
998*4882a593Smuzhiyun if (bc->cfg.bps < 1000)
999*4882a593Smuzhiyun bc->cfg.bps = 1000;
1000*4882a593Smuzhiyun if (bc->cfg.bps > 1500000)
1001*4882a593Smuzhiyun bc->cfg.bps = 1500000;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun return 0;
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
1007*4882a593Smuzhiyun
baycom_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)1008*4882a593Smuzhiyun static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1009*4882a593Smuzhiyun {
1010*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
1011*4882a593Smuzhiyun struct hdlcdrv_ioctl hi;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun if (cmd != SIOCDEVPRIVATE)
1014*4882a593Smuzhiyun return -ENOIOCTLCMD;
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun if (copy_from_user(&hi, ifr->ifr_data, sizeof(hi)))
1017*4882a593Smuzhiyun return -EFAULT;
1018*4882a593Smuzhiyun switch (hi.cmd) {
1019*4882a593Smuzhiyun default:
1020*4882a593Smuzhiyun return -ENOIOCTLCMD;
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun case HDLCDRVCTL_GETCHANNELPAR:
1023*4882a593Smuzhiyun hi.data.cp.tx_delay = bc->ch_params.tx_delay;
1024*4882a593Smuzhiyun hi.data.cp.tx_tail = bc->ch_params.tx_tail;
1025*4882a593Smuzhiyun hi.data.cp.slottime = bc->ch_params.slottime;
1026*4882a593Smuzhiyun hi.data.cp.ppersist = bc->ch_params.ppersist;
1027*4882a593Smuzhiyun hi.data.cp.fulldup = bc->ch_params.fulldup;
1028*4882a593Smuzhiyun break;
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun case HDLCDRVCTL_SETCHANNELPAR:
1031*4882a593Smuzhiyun if (!capable(CAP_NET_ADMIN))
1032*4882a593Smuzhiyun return -EACCES;
1033*4882a593Smuzhiyun bc->ch_params.tx_delay = hi.data.cp.tx_delay;
1034*4882a593Smuzhiyun bc->ch_params.tx_tail = hi.data.cp.tx_tail;
1035*4882a593Smuzhiyun bc->ch_params.slottime = hi.data.cp.slottime;
1036*4882a593Smuzhiyun bc->ch_params.ppersist = hi.data.cp.ppersist;
1037*4882a593Smuzhiyun bc->ch_params.fulldup = hi.data.cp.fulldup;
1038*4882a593Smuzhiyun bc->hdlctx.slotcnt = 1;
1039*4882a593Smuzhiyun return 0;
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun case HDLCDRVCTL_GETMODEMPAR:
1042*4882a593Smuzhiyun hi.data.mp.iobase = dev->base_addr;
1043*4882a593Smuzhiyun hi.data.mp.irq = dev->irq;
1044*4882a593Smuzhiyun hi.data.mp.dma = dev->dma;
1045*4882a593Smuzhiyun hi.data.mp.dma2 = 0;
1046*4882a593Smuzhiyun hi.data.mp.seriobase = 0;
1047*4882a593Smuzhiyun hi.data.mp.pariobase = 0;
1048*4882a593Smuzhiyun hi.data.mp.midiiobase = 0;
1049*4882a593Smuzhiyun break;
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun case HDLCDRVCTL_SETMODEMPAR:
1052*4882a593Smuzhiyun if ((!capable(CAP_SYS_RAWIO)) || netif_running(dev))
1053*4882a593Smuzhiyun return -EACCES;
1054*4882a593Smuzhiyun dev->base_addr = hi.data.mp.iobase;
1055*4882a593Smuzhiyun dev->irq = /*hi.data.mp.irq*/0;
1056*4882a593Smuzhiyun dev->dma = /*hi.data.mp.dma*/0;
1057*4882a593Smuzhiyun return 0;
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun case HDLCDRVCTL_GETSTAT:
1060*4882a593Smuzhiyun hi.data.cs.ptt = !!(bc->stat & EPP_PTTBIT);
1061*4882a593Smuzhiyun hi.data.cs.dcd = !(bc->stat & EPP_DCDBIT);
1062*4882a593Smuzhiyun hi.data.cs.ptt_keyed = bc->ptt_keyed;
1063*4882a593Smuzhiyun hi.data.cs.tx_packets = dev->stats.tx_packets;
1064*4882a593Smuzhiyun hi.data.cs.tx_errors = dev->stats.tx_errors;
1065*4882a593Smuzhiyun hi.data.cs.rx_packets = dev->stats.rx_packets;
1066*4882a593Smuzhiyun hi.data.cs.rx_errors = dev->stats.rx_errors;
1067*4882a593Smuzhiyun break;
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun case HDLCDRVCTL_OLDGETSTAT:
1070*4882a593Smuzhiyun hi.data.ocs.ptt = !!(bc->stat & EPP_PTTBIT);
1071*4882a593Smuzhiyun hi.data.ocs.dcd = !(bc->stat & EPP_DCDBIT);
1072*4882a593Smuzhiyun hi.data.ocs.ptt_keyed = bc->ptt_keyed;
1073*4882a593Smuzhiyun break;
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun case HDLCDRVCTL_CALIBRATE:
1076*4882a593Smuzhiyun if (!capable(CAP_SYS_RAWIO))
1077*4882a593Smuzhiyun return -EACCES;
1078*4882a593Smuzhiyun bc->hdlctx.calibrate = hi.data.calibrate * bc->bitrate / 8;
1079*4882a593Smuzhiyun return 0;
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun case HDLCDRVCTL_DRIVERNAME:
1082*4882a593Smuzhiyun strncpy(hi.data.drivername, "baycom_epp", sizeof(hi.data.drivername));
1083*4882a593Smuzhiyun break;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun case HDLCDRVCTL_GETMODE:
1086*4882a593Smuzhiyun sprintf(hi.data.modename, "%sclk,%smodem,fclk=%d,bps=%d%s",
1087*4882a593Smuzhiyun bc->cfg.intclk ? "int" : "ext",
1088*4882a593Smuzhiyun bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
1089*4882a593Smuzhiyun bc->cfg.loopback ? ",loopback" : "");
1090*4882a593Smuzhiyun break;
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun case HDLCDRVCTL_SETMODE:
1093*4882a593Smuzhiyun if (!capable(CAP_NET_ADMIN) || netif_running(dev))
1094*4882a593Smuzhiyun return -EACCES;
1095*4882a593Smuzhiyun hi.data.modename[sizeof(hi.data.modename)-1] = '\0';
1096*4882a593Smuzhiyun return baycom_setmode(bc, hi.data.modename);
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun case HDLCDRVCTL_MODELIST:
1099*4882a593Smuzhiyun strncpy(hi.data.modename, "intclk,extclk,intmodem,extmodem,divider=x",
1100*4882a593Smuzhiyun sizeof(hi.data.modename));
1101*4882a593Smuzhiyun break;
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun case HDLCDRVCTL_MODEMPARMASK:
1104*4882a593Smuzhiyun return HDLCDRV_PARMASK_IOBASE;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun if (copy_to_user(ifr->ifr_data, &hi, sizeof(hi)))
1108*4882a593Smuzhiyun return -EFAULT;
1109*4882a593Smuzhiyun return 0;
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun static const struct net_device_ops baycom_netdev_ops = {
1115*4882a593Smuzhiyun .ndo_open = epp_open,
1116*4882a593Smuzhiyun .ndo_stop = epp_close,
1117*4882a593Smuzhiyun .ndo_do_ioctl = baycom_ioctl,
1118*4882a593Smuzhiyun .ndo_start_xmit = baycom_send_packet,
1119*4882a593Smuzhiyun .ndo_set_mac_address = baycom_set_mac_address,
1120*4882a593Smuzhiyun };
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun /*
1123*4882a593Smuzhiyun * Check for a network adaptor of this type, and return '0' if one exists.
1124*4882a593Smuzhiyun * If dev->base_addr == 0, probe all likely locations.
1125*4882a593Smuzhiyun * If dev->base_addr == 1, always return failure.
1126*4882a593Smuzhiyun * If dev->base_addr == 2, allocate space for the device and return success
1127*4882a593Smuzhiyun * (detachable devices only).
1128*4882a593Smuzhiyun */
baycom_probe(struct net_device * dev)1129*4882a593Smuzhiyun static void baycom_probe(struct net_device *dev)
1130*4882a593Smuzhiyun {
1131*4882a593Smuzhiyun const struct hdlcdrv_channel_params dflt_ch_params = {
1132*4882a593Smuzhiyun 20, 2, 10, 40, 0
1133*4882a593Smuzhiyun };
1134*4882a593Smuzhiyun struct baycom_state *bc;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun /*
1137*4882a593Smuzhiyun * not a real probe! only initialize data structures
1138*4882a593Smuzhiyun */
1139*4882a593Smuzhiyun bc = netdev_priv(dev);
1140*4882a593Smuzhiyun /*
1141*4882a593Smuzhiyun * initialize the baycom_state struct
1142*4882a593Smuzhiyun */
1143*4882a593Smuzhiyun bc->ch_params = dflt_ch_params;
1144*4882a593Smuzhiyun bc->ptt_keyed = 0;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun /*
1147*4882a593Smuzhiyun * initialize the device struct
1148*4882a593Smuzhiyun */
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun /* Fill in the fields of the device structure */
1151*4882a593Smuzhiyun bc->skb = NULL;
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun dev->netdev_ops = &baycom_netdev_ops;
1154*4882a593Smuzhiyun dev->header_ops = &ax25_header_ops;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun dev->type = ARPHRD_AX25; /* AF_AX25 device */
1157*4882a593Smuzhiyun dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
1158*4882a593Smuzhiyun dev->mtu = AX25_DEF_PACLEN; /* eth_mtu is the default */
1159*4882a593Smuzhiyun dev->addr_len = AX25_ADDR_LEN; /* sizeof an ax.25 address */
1160*4882a593Smuzhiyun memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
1161*4882a593Smuzhiyun memcpy(dev->dev_addr, &null_ax25_address, AX25_ADDR_LEN);
1162*4882a593Smuzhiyun dev->tx_queue_len = 16;
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun /* New style flags */
1165*4882a593Smuzhiyun dev->flags = 0;
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun /*
1171*4882a593Smuzhiyun * command line settable parameters
1172*4882a593Smuzhiyun */
1173*4882a593Smuzhiyun static char *mode[NR_PORTS] = { "", };
1174*4882a593Smuzhiyun static int iobase[NR_PORTS] = { 0x378, };
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun module_param_array(mode, charp, NULL, 0);
1177*4882a593Smuzhiyun MODULE_PARM_DESC(mode, "baycom operating mode");
1178*4882a593Smuzhiyun module_param_hw_array(iobase, int, ioport, NULL, 0);
1179*4882a593Smuzhiyun MODULE_PARM_DESC(iobase, "baycom io base address");
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
1182*4882a593Smuzhiyun MODULE_DESCRIPTION("Baycom epp amateur radio modem driver");
1183*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1184*4882a593Smuzhiyun
1185*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
1186*4882a593Smuzhiyun
baycom_epp_par_probe(struct pardevice * par_dev)1187*4882a593Smuzhiyun static int baycom_epp_par_probe(struct pardevice *par_dev)
1188*4882a593Smuzhiyun {
1189*4882a593Smuzhiyun struct device_driver *drv = par_dev->dev.driver;
1190*4882a593Smuzhiyun int len = strlen(drv->name);
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun if (strncmp(par_dev->name, drv->name, len))
1193*4882a593Smuzhiyun return -ENODEV;
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun return 0;
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun static struct parport_driver baycom_epp_par_driver = {
1199*4882a593Smuzhiyun .name = "bce",
1200*4882a593Smuzhiyun .probe = baycom_epp_par_probe,
1201*4882a593Smuzhiyun .devmodel = true,
1202*4882a593Smuzhiyun };
1203*4882a593Smuzhiyun
baycom_epp_dev_setup(struct net_device * dev)1204*4882a593Smuzhiyun static void __init baycom_epp_dev_setup(struct net_device *dev)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun /*
1209*4882a593Smuzhiyun * initialize part of the baycom_state struct
1210*4882a593Smuzhiyun */
1211*4882a593Smuzhiyun bc->dev = dev;
1212*4882a593Smuzhiyun bc->magic = BAYCOM_MAGIC;
1213*4882a593Smuzhiyun bc->cfg.fclk = 19666600;
1214*4882a593Smuzhiyun bc->cfg.bps = 9600;
1215*4882a593Smuzhiyun /*
1216*4882a593Smuzhiyun * initialize part of the device struct
1217*4882a593Smuzhiyun */
1218*4882a593Smuzhiyun baycom_probe(dev);
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun
init_baycomepp(void)1221*4882a593Smuzhiyun static int __init init_baycomepp(void)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun int i, found = 0, ret;
1224*4882a593Smuzhiyun char set_hw = 1;
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun printk(bc_drvinfo);
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun ret = parport_register_driver(&baycom_epp_par_driver);
1229*4882a593Smuzhiyun if (ret)
1230*4882a593Smuzhiyun return ret;
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun /*
1233*4882a593Smuzhiyun * register net devices
1234*4882a593Smuzhiyun */
1235*4882a593Smuzhiyun for (i = 0; i < NR_PORTS; i++) {
1236*4882a593Smuzhiyun struct net_device *dev;
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun dev = alloc_netdev(sizeof(struct baycom_state), "bce%d",
1239*4882a593Smuzhiyun NET_NAME_UNKNOWN, baycom_epp_dev_setup);
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun if (!dev) {
1242*4882a593Smuzhiyun printk(KERN_WARNING "bce%d : out of memory\n", i);
1243*4882a593Smuzhiyun return found ? 0 : -ENOMEM;
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun sprintf(dev->name, "bce%d", i);
1247*4882a593Smuzhiyun dev->base_addr = iobase[i];
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun if (!mode[i])
1250*4882a593Smuzhiyun set_hw = 0;
1251*4882a593Smuzhiyun if (!set_hw)
1252*4882a593Smuzhiyun iobase[i] = 0;
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun if (register_netdev(dev)) {
1255*4882a593Smuzhiyun printk(KERN_WARNING "%s: cannot register net device %s\n", bc_drvname, dev->name);
1256*4882a593Smuzhiyun free_netdev(dev);
1257*4882a593Smuzhiyun break;
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun if (set_hw && baycom_setmode(netdev_priv(dev), mode[i]))
1260*4882a593Smuzhiyun set_hw = 0;
1261*4882a593Smuzhiyun baycom_device[i] = dev;
1262*4882a593Smuzhiyun found++;
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun if (found == 0) {
1266*4882a593Smuzhiyun parport_unregister_driver(&baycom_epp_par_driver);
1267*4882a593Smuzhiyun return -ENXIO;
1268*4882a593Smuzhiyun }
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun return 0;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
cleanup_baycomepp(void)1273*4882a593Smuzhiyun static void __exit cleanup_baycomepp(void)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun int i;
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun for(i = 0; i < NR_PORTS; i++) {
1278*4882a593Smuzhiyun struct net_device *dev = baycom_device[i];
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun if (dev) {
1281*4882a593Smuzhiyun struct baycom_state *bc = netdev_priv(dev);
1282*4882a593Smuzhiyun if (bc->magic == BAYCOM_MAGIC) {
1283*4882a593Smuzhiyun unregister_netdev(dev);
1284*4882a593Smuzhiyun free_netdev(dev);
1285*4882a593Smuzhiyun } else
1286*4882a593Smuzhiyun printk(paranoia_str, "cleanup_module");
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun parport_unregister_driver(&baycom_epp_par_driver);
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun module_init(init_baycomepp);
1293*4882a593Smuzhiyun module_exit(cleanup_baycomepp);
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun #ifndef MODULE
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun /*
1300*4882a593Smuzhiyun * format: baycom_epp=io,mode
1301*4882a593Smuzhiyun * mode: fpga config options
1302*4882a593Smuzhiyun */
1303*4882a593Smuzhiyun
baycom_epp_setup(char * str)1304*4882a593Smuzhiyun static int __init baycom_epp_setup(char *str)
1305*4882a593Smuzhiyun {
1306*4882a593Smuzhiyun static unsigned __initdata nr_dev = 0;
1307*4882a593Smuzhiyun int ints[2];
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun if (nr_dev >= NR_PORTS)
1310*4882a593Smuzhiyun return 0;
1311*4882a593Smuzhiyun str = get_options(str, 2, ints);
1312*4882a593Smuzhiyun if (ints[0] < 1)
1313*4882a593Smuzhiyun return 0;
1314*4882a593Smuzhiyun mode[nr_dev] = str;
1315*4882a593Smuzhiyun iobase[nr_dev] = ints[1];
1316*4882a593Smuzhiyun nr_dev++;
1317*4882a593Smuzhiyun return 1;
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun __setup("baycom_epp=", baycom_epp_setup);
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun #endif /* MODULE */
1323*4882a593Smuzhiyun /* --------------------------------------------------------------------- */
1324