1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * FUJITSU Extended Socket Network Device driver 4*4882a593Smuzhiyun * Copyright (c) 2015 FUJITSU LIMITED 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef FJES_REGS_H_ 8*4882a593Smuzhiyun #define FJES_REGS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/bitops.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define XSCT_DEVICE_REGISTER_SIZE 0x1000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* register offset */ 15*4882a593Smuzhiyun /* Information registers */ 16*4882a593Smuzhiyun #define XSCT_OWNER_EPID 0x0000 /* Owner EPID */ 17*4882a593Smuzhiyun #define XSCT_MAX_EP 0x0004 /* Maximum EP */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Device Control registers */ 20*4882a593Smuzhiyun #define XSCT_DCTL 0x0010 /* Device Control */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Command Control registers */ 23*4882a593Smuzhiyun #define XSCT_CR 0x0020 /* Command request */ 24*4882a593Smuzhiyun #define XSCT_CS 0x0024 /* Command status */ 25*4882a593Smuzhiyun #define XSCT_SHSTSAL 0x0028 /* Share status address Low */ 26*4882a593Smuzhiyun #define XSCT_SHSTSAH 0x002C /* Share status address High */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define XSCT_REQBL 0x0034 /* Request Buffer length */ 29*4882a593Smuzhiyun #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */ 30*4882a593Smuzhiyun #define XSCT_REQBAH 0x003C /* Request Buffer Address High */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define XSCT_RESPBL 0x0044 /* Response Buffer Length */ 33*4882a593Smuzhiyun #define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */ 34*4882a593Smuzhiyun #define XSCT_RESPBAH 0x004C /* Response Buffer Address High */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Interrupt Control registers */ 37*4882a593Smuzhiyun #define XSCT_IS 0x0080 /* Interrupt status */ 38*4882a593Smuzhiyun #define XSCT_IMS 0x0084 /* Interrupt mask set */ 39*4882a593Smuzhiyun #define XSCT_IMC 0x0088 /* Interrupt mask clear */ 40*4882a593Smuzhiyun #define XSCT_IG 0x008C /* Interrupt generator */ 41*4882a593Smuzhiyun #define XSCT_ICTL 0x0090 /* Interrupt control */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* register structure */ 44*4882a593Smuzhiyun /* Information registers */ 45*4882a593Smuzhiyun union REG_OWNER_EPID { 46*4882a593Smuzhiyun struct { 47*4882a593Smuzhiyun __le32 epid:16; 48*4882a593Smuzhiyun __le32:16; 49*4882a593Smuzhiyun } bits; 50*4882a593Smuzhiyun __le32 reg; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun union REG_MAX_EP { 54*4882a593Smuzhiyun struct { 55*4882a593Smuzhiyun __le32 maxep:16; 56*4882a593Smuzhiyun __le32:16; 57*4882a593Smuzhiyun } bits; 58*4882a593Smuzhiyun __le32 reg; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Device Control registers */ 62*4882a593Smuzhiyun union REG_DCTL { 63*4882a593Smuzhiyun struct { 64*4882a593Smuzhiyun __le32 reset:1; 65*4882a593Smuzhiyun __le32 rsv0:15; 66*4882a593Smuzhiyun __le32 rsv1:16; 67*4882a593Smuzhiyun } bits; 68*4882a593Smuzhiyun __le32 reg; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Command Control registers */ 72*4882a593Smuzhiyun union REG_CR { 73*4882a593Smuzhiyun struct { 74*4882a593Smuzhiyun __le32 req_code:16; 75*4882a593Smuzhiyun __le32 err_info:14; 76*4882a593Smuzhiyun __le32 error:1; 77*4882a593Smuzhiyun __le32 req_start:1; 78*4882a593Smuzhiyun } bits; 79*4882a593Smuzhiyun __le32 reg; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun union REG_CS { 83*4882a593Smuzhiyun struct { 84*4882a593Smuzhiyun __le32 req_code:16; 85*4882a593Smuzhiyun __le32 rsv0:14; 86*4882a593Smuzhiyun __le32 busy:1; 87*4882a593Smuzhiyun __le32 complete:1; 88*4882a593Smuzhiyun } bits; 89*4882a593Smuzhiyun __le32 reg; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Interrupt Control registers */ 93*4882a593Smuzhiyun union REG_ICTL { 94*4882a593Smuzhiyun struct { 95*4882a593Smuzhiyun __le32 automak:1; 96*4882a593Smuzhiyun __le32 rsv0:31; 97*4882a593Smuzhiyun } bits; 98*4882a593Smuzhiyun __le32 reg; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum REG_ICTL_MASK { 102*4882a593Smuzhiyun REG_ICTL_MASK_INFO_UPDATE = 1 << 20, 103*4882a593Smuzhiyun REG_ICTL_MASK_DEV_STOP_REQ = 1 << 19, 104*4882a593Smuzhiyun REG_ICTL_MASK_TXRX_STOP_REQ = 1 << 18, 105*4882a593Smuzhiyun REG_ICTL_MASK_TXRX_STOP_DONE = 1 << 17, 106*4882a593Smuzhiyun REG_ICTL_MASK_RX_DATA = 1 << 16, 107*4882a593Smuzhiyun REG_ICTL_MASK_ALL = GENMASK(20, 16), 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun enum REG_IS_MASK { 111*4882a593Smuzhiyun REG_IS_MASK_IS_ASSERT = 1 << 31, 112*4882a593Smuzhiyun REG_IS_MASK_EPID = GENMASK(15, 0), 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct fjes_hw; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define wr32(reg, val) \ 120*4882a593Smuzhiyun do { \ 121*4882a593Smuzhiyun u8 *base = hw->base; \ 122*4882a593Smuzhiyun writel((val), &base[(reg)]); \ 123*4882a593Smuzhiyun } while (0) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define rd32(reg) (fjes_hw_rd32(hw, reg)) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif /* FJES_REGS_H_ */ 128