1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * PTP 1588 clock using the IXP46X 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 OMICRON electronics GmbH 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _IXP46X_TS_H_ 9*4882a593Smuzhiyun #define _IXP46X_TS_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define DEFAULT_ADDEND 0xF0000029 12*4882a593Smuzhiyun #define TICKS_NS_SHIFT 4 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct ixp46x_channel_ctl { 15*4882a593Smuzhiyun u32 ch_control; /* 0x40 Time Synchronization Channel Control */ 16*4882a593Smuzhiyun u32 ch_event; /* 0x44 Time Synchronization Channel Event */ 17*4882a593Smuzhiyun u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */ 18*4882a593Smuzhiyun u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */ 19*4882a593Smuzhiyun u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */ 20*4882a593Smuzhiyun u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */ 21*4882a593Smuzhiyun u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */ 22*4882a593Smuzhiyun u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct ixp46x_ts_regs { 26*4882a593Smuzhiyun u32 control; /* 0x00 Time Sync Control Register */ 27*4882a593Smuzhiyun u32 event; /* 0x04 Time Sync Event Register */ 28*4882a593Smuzhiyun u32 addend; /* 0x08 Time Sync Addend Register */ 29*4882a593Smuzhiyun u32 accum; /* 0x0C Time Sync Accumulator Register */ 30*4882a593Smuzhiyun u32 test; /* 0x10 Time Sync Test Register */ 31*4882a593Smuzhiyun u32 unused; /* 0x14 */ 32*4882a593Smuzhiyun u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */ 33*4882a593Smuzhiyun u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */ 34*4882a593Smuzhiyun u32 systime_lo; /* 0x20 SystemTime_Low Register */ 35*4882a593Smuzhiyun u32 systime_hi; /* 0x24 SystemTime_High Register */ 36*4882a593Smuzhiyun u32 trgt_lo; /* 0x28 TargetTime_Low Register */ 37*4882a593Smuzhiyun u32 trgt_hi; /* 0x2C TargetTime_High Register */ 38*4882a593Smuzhiyun u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */ 39*4882a593Smuzhiyun u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */ 40*4882a593Smuzhiyun u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */ 41*4882a593Smuzhiyun u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct ixp46x_channel_ctl channel[3]; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 0x00 Time Sync Control Register Bits */ 47*4882a593Smuzhiyun #define TSCR_AMM (1<<3) 48*4882a593Smuzhiyun #define TSCR_ASM (1<<2) 49*4882a593Smuzhiyun #define TSCR_TTM (1<<1) 50*4882a593Smuzhiyun #define TSCR_RST (1<<0) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 0x04 Time Sync Event Register Bits */ 53*4882a593Smuzhiyun #define TSER_SNM (1<<3) 54*4882a593Smuzhiyun #define TSER_SNS (1<<2) 55*4882a593Smuzhiyun #define TTIPEND (1<<1) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 0x40 Time Synchronization Channel Control Register Bits */ 58*4882a593Smuzhiyun #define MASTER_MODE (1<<0) 59*4882a593Smuzhiyun #define TIMESTAMP_ALL (1<<1) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 0x44 Time Synchronization Channel Event Register Bits */ 62*4882a593Smuzhiyun #define TX_SNAPSHOT_LOCKED (1<<0) 63*4882a593Smuzhiyun #define RX_SNAPSHOT_LOCKED (1<<1) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* The ptp_ixp46x module will set this variable */ 66*4882a593Smuzhiyun extern int ixp46x_phc_index; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69