xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/via/via-velocity.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * This code is derived from the VIA reference driver (copyright message
4*4882a593Smuzhiyun  * below) provided to Red Hat by VIA Networking Technologies, Inc. for
5*4882a593Smuzhiyun  * addition to the Linux kernel.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * The code has been merged into one source file, cleaned up to follow
8*4882a593Smuzhiyun  * Linux coding style,  ported to the Linux 2.6 kernel tree and cleaned
9*4882a593Smuzhiyun  * for 64bit hardware platforms.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * TODO
12*4882a593Smuzhiyun  *	rx_copybreak/alignment
13*4882a593Smuzhiyun  *	More testing
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * The changes are (c) Copyright 2004, Red Hat Inc. <alan@lxorguk.ukuu.org.uk>
16*4882a593Smuzhiyun  * Additional fixes and clean up: Francois Romieu
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * This source has not been verified for use in safety critical systems.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * Please direct queries about the revamped driver to the linux-kernel
21*4882a593Smuzhiyun  * list not VIA.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Original code:
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
26*4882a593Smuzhiyun  * All rights reserved.
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  * Author: Chuang Liang-Shing, AJ Jiang
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  * Date: Jan 24, 2003
31*4882a593Smuzhiyun  *
32*4882a593Smuzhiyun  * MODULE_LICENSE("GPL");
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #include <linux/module.h>
38*4882a593Smuzhiyun #include <linux/types.h>
39*4882a593Smuzhiyun #include <linux/bitops.h>
40*4882a593Smuzhiyun #include <linux/init.h>
41*4882a593Smuzhiyun #include <linux/dma-mapping.h>
42*4882a593Smuzhiyun #include <linux/mm.h>
43*4882a593Smuzhiyun #include <linux/errno.h>
44*4882a593Smuzhiyun #include <linux/ioport.h>
45*4882a593Smuzhiyun #include <linux/pci.h>
46*4882a593Smuzhiyun #include <linux/kernel.h>
47*4882a593Smuzhiyun #include <linux/netdevice.h>
48*4882a593Smuzhiyun #include <linux/etherdevice.h>
49*4882a593Smuzhiyun #include <linux/skbuff.h>
50*4882a593Smuzhiyun #include <linux/delay.h>
51*4882a593Smuzhiyun #include <linux/timer.h>
52*4882a593Smuzhiyun #include <linux/slab.h>
53*4882a593Smuzhiyun #include <linux/interrupt.h>
54*4882a593Smuzhiyun #include <linux/string.h>
55*4882a593Smuzhiyun #include <linux/wait.h>
56*4882a593Smuzhiyun #include <linux/io.h>
57*4882a593Smuzhiyun #include <linux/if.h>
58*4882a593Smuzhiyun #include <linux/uaccess.h>
59*4882a593Smuzhiyun #include <linux/proc_fs.h>
60*4882a593Smuzhiyun #include <linux/of_address.h>
61*4882a593Smuzhiyun #include <linux/of_device.h>
62*4882a593Smuzhiyun #include <linux/of_irq.h>
63*4882a593Smuzhiyun #include <linux/inetdevice.h>
64*4882a593Smuzhiyun #include <linux/platform_device.h>
65*4882a593Smuzhiyun #include <linux/reboot.h>
66*4882a593Smuzhiyun #include <linux/ethtool.h>
67*4882a593Smuzhiyun #include <linux/mii.h>
68*4882a593Smuzhiyun #include <linux/in.h>
69*4882a593Smuzhiyun #include <linux/if_arp.h>
70*4882a593Smuzhiyun #include <linux/if_vlan.h>
71*4882a593Smuzhiyun #include <linux/ip.h>
72*4882a593Smuzhiyun #include <linux/tcp.h>
73*4882a593Smuzhiyun #include <linux/udp.h>
74*4882a593Smuzhiyun #include <linux/crc-ccitt.h>
75*4882a593Smuzhiyun #include <linux/crc32.h>
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #include "via-velocity.h"
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun enum velocity_bus_type {
80*4882a593Smuzhiyun 	BUS_PCI,
81*4882a593Smuzhiyun 	BUS_PLATFORM,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun static int velocity_nics;
85*4882a593Smuzhiyun 
velocity_set_power_state(struct velocity_info * vptr,char state)86*4882a593Smuzhiyun static void velocity_set_power_state(struct velocity_info *vptr, char state)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	void *addr = vptr->mac_regs;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	if (vptr->pdev)
91*4882a593Smuzhiyun 		pci_set_power_state(vptr->pdev, state);
92*4882a593Smuzhiyun 	else
93*4882a593Smuzhiyun 		writeb(state, addr + 0x154);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /**
97*4882a593Smuzhiyun  *	mac_get_cam_mask	-	Read a CAM mask
98*4882a593Smuzhiyun  *	@regs: register block for this velocity
99*4882a593Smuzhiyun  *	@mask: buffer to store mask
100*4882a593Smuzhiyun  *
101*4882a593Smuzhiyun  *	Fetch the mask bits of the selected CAM and store them into the
102*4882a593Smuzhiyun  *	provided mask buffer.
103*4882a593Smuzhiyun  */
mac_get_cam_mask(struct mac_regs __iomem * regs,u8 * mask)104*4882a593Smuzhiyun static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	int i;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/* Select CAM mask */
109*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	writeb(0, &regs->CAMADDR);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	/* read mask */
114*4882a593Smuzhiyun 	for (i = 0; i < 8; i++)
115*4882a593Smuzhiyun 		*mask++ = readb(&(regs->MARCAM[i]));
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* disable CAMEN */
118*4882a593Smuzhiyun 	writeb(0, &regs->CAMADDR);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* Select mar */
121*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /**
125*4882a593Smuzhiyun  *	mac_set_cam_mask	-	Set a CAM mask
126*4882a593Smuzhiyun  *	@regs: register block for this velocity
127*4882a593Smuzhiyun  *	@mask: CAM mask to load
128*4882a593Smuzhiyun  *
129*4882a593Smuzhiyun  *	Store a new mask into a CAM
130*4882a593Smuzhiyun  */
mac_set_cam_mask(struct mac_regs __iomem * regs,u8 * mask)131*4882a593Smuzhiyun static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	int i;
134*4882a593Smuzhiyun 	/* Select CAM mask */
135*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	writeb(CAMADDR_CAMEN, &regs->CAMADDR);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	for (i = 0; i < 8; i++)
140*4882a593Smuzhiyun 		writeb(*mask++, &(regs->MARCAM[i]));
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/* disable CAMEN */
143*4882a593Smuzhiyun 	writeb(0, &regs->CAMADDR);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	/* Select mar */
146*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
mac_set_vlan_cam_mask(struct mac_regs __iomem * regs,u8 * mask)149*4882a593Smuzhiyun static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	int i;
152*4882a593Smuzhiyun 	/* Select CAM mask */
153*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	for (i = 0; i < 8; i++)
158*4882a593Smuzhiyun 		writeb(*mask++, &(regs->MARCAM[i]));
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* disable CAMEN */
161*4882a593Smuzhiyun 	writeb(0, &regs->CAMADDR);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	/* Select mar */
164*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun /**
168*4882a593Smuzhiyun  *	mac_set_cam	-	set CAM data
169*4882a593Smuzhiyun  *	@regs: register block of this velocity
170*4882a593Smuzhiyun  *	@idx: Cam index
171*4882a593Smuzhiyun  *	@addr: 2 or 6 bytes of CAM data
172*4882a593Smuzhiyun  *
173*4882a593Smuzhiyun  *	Load an address or vlan tag into a CAM
174*4882a593Smuzhiyun  */
mac_set_cam(struct mac_regs __iomem * regs,int idx,const u8 * addr)175*4882a593Smuzhiyun static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	int i;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	/* Select CAM mask */
180*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	idx &= (64 - 1);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	for (i = 0; i < 6; i++)
187*4882a593Smuzhiyun 		writeb(*addr++, &(regs->MARCAM[i]));
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	udelay(10);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	writeb(0, &regs->CAMADDR);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/* Select mar */
196*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
mac_set_vlan_cam(struct mac_regs __iomem * regs,int idx,const u8 * addr)199*4882a593Smuzhiyun static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
200*4882a593Smuzhiyun 			     const u8 *addr)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/* Select CAM mask */
204*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	idx &= (64 - 1);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
209*4882a593Smuzhiyun 	writew(*((u16 *) addr), &regs->MARCAM[0]);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	udelay(10);
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	writeb(0, &regs->CAMADDR);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	/* Select mar */
218*4882a593Smuzhiyun 	BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun /**
223*4882a593Smuzhiyun  *	mac_wol_reset	-	reset WOL after exiting low power
224*4882a593Smuzhiyun  *	@regs: register block of this velocity
225*4882a593Smuzhiyun  *
226*4882a593Smuzhiyun  *	Called after we drop out of wake on lan mode in order to
227*4882a593Smuzhiyun  *	reset the Wake on lan features. This function doesn't restore
228*4882a593Smuzhiyun  *	the rest of the logic from the result of sleep/wakeup
229*4882a593Smuzhiyun  */
mac_wol_reset(struct mac_regs __iomem * regs)230*4882a593Smuzhiyun static void mac_wol_reset(struct mac_regs __iomem *regs)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	/* Turn off SWPTAG right after leaving power mode */
234*4882a593Smuzhiyun 	BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
235*4882a593Smuzhiyun 	/* clear sticky bits */
236*4882a593Smuzhiyun 	BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
239*4882a593Smuzhiyun 	BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
240*4882a593Smuzhiyun 	/* disable force PME-enable */
241*4882a593Smuzhiyun 	writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
242*4882a593Smuzhiyun 	/* disable power-event config bit */
243*4882a593Smuzhiyun 	writew(0xFFFF, &regs->WOLCRClr);
244*4882a593Smuzhiyun 	/* clear power status */
245*4882a593Smuzhiyun 	writew(0xFFFF, &regs->WOLSRClr);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun static const struct ethtool_ops velocity_ethtool_ops;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /*
251*4882a593Smuzhiyun     Define module options
252*4882a593Smuzhiyun */
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun MODULE_AUTHOR("VIA Networking Technologies, Inc.");
255*4882a593Smuzhiyun MODULE_LICENSE("GPL");
256*4882a593Smuzhiyun MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun #define VELOCITY_PARAM(N, D) \
259*4882a593Smuzhiyun 	static int N[MAX_UNITS] = OPTION_DEFAULT;\
260*4882a593Smuzhiyun 	module_param_array(N, int, NULL, 0); \
261*4882a593Smuzhiyun 	MODULE_PARM_DESC(N, D);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun #define RX_DESC_MIN     64
264*4882a593Smuzhiyun #define RX_DESC_MAX     255
265*4882a593Smuzhiyun #define RX_DESC_DEF     64
266*4882a593Smuzhiyun VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun #define TX_DESC_MIN     16
269*4882a593Smuzhiyun #define TX_DESC_MAX     256
270*4882a593Smuzhiyun #define TX_DESC_DEF     64
271*4882a593Smuzhiyun VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun #define RX_THRESH_MIN   0
274*4882a593Smuzhiyun #define RX_THRESH_MAX   3
275*4882a593Smuzhiyun #define RX_THRESH_DEF   0
276*4882a593Smuzhiyun /* rx_thresh[] is used for controlling the receive fifo threshold.
277*4882a593Smuzhiyun    0: indicate the rxfifo threshold is 128 bytes.
278*4882a593Smuzhiyun    1: indicate the rxfifo threshold is 512 bytes.
279*4882a593Smuzhiyun    2: indicate the rxfifo threshold is 1024 bytes.
280*4882a593Smuzhiyun    3: indicate the rxfifo threshold is store & forward.
281*4882a593Smuzhiyun */
282*4882a593Smuzhiyun VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun #define DMA_LENGTH_MIN  0
285*4882a593Smuzhiyun #define DMA_LENGTH_MAX  7
286*4882a593Smuzhiyun #define DMA_LENGTH_DEF  6
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun /* DMA_length[] is used for controlling the DMA length
289*4882a593Smuzhiyun    0: 8 DWORDs
290*4882a593Smuzhiyun    1: 16 DWORDs
291*4882a593Smuzhiyun    2: 32 DWORDs
292*4882a593Smuzhiyun    3: 64 DWORDs
293*4882a593Smuzhiyun    4: 128 DWORDs
294*4882a593Smuzhiyun    5: 256 DWORDs
295*4882a593Smuzhiyun    6: SF(flush till emply)
296*4882a593Smuzhiyun    7: SF(flush till emply)
297*4882a593Smuzhiyun */
298*4882a593Smuzhiyun VELOCITY_PARAM(DMA_length, "DMA length");
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun #define IP_ALIG_DEF     0
301*4882a593Smuzhiyun /* IP_byte_align[] is used for IP header DWORD byte aligned
302*4882a593Smuzhiyun    0: indicate the IP header won't be DWORD byte aligned.(Default) .
303*4882a593Smuzhiyun    1: indicate the IP header will be DWORD byte aligned.
304*4882a593Smuzhiyun       In some environment, the IP header should be DWORD byte aligned,
305*4882a593Smuzhiyun       or the packet will be droped when we receive it. (eg: IPVS)
306*4882a593Smuzhiyun */
307*4882a593Smuzhiyun VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun #define FLOW_CNTL_DEF   1
310*4882a593Smuzhiyun #define FLOW_CNTL_MIN   1
311*4882a593Smuzhiyun #define FLOW_CNTL_MAX   5
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun /* flow_control[] is used for setting the flow control ability of NIC.
314*4882a593Smuzhiyun    1: hardware deafult - AUTO (default). Use Hardware default value in ANAR.
315*4882a593Smuzhiyun    2: enable TX flow control.
316*4882a593Smuzhiyun    3: enable RX flow control.
317*4882a593Smuzhiyun    4: enable RX/TX flow control.
318*4882a593Smuzhiyun    5: disable
319*4882a593Smuzhiyun */
320*4882a593Smuzhiyun VELOCITY_PARAM(flow_control, "Enable flow control ability");
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun #define MED_LNK_DEF 0
323*4882a593Smuzhiyun #define MED_LNK_MIN 0
324*4882a593Smuzhiyun #define MED_LNK_MAX 5
325*4882a593Smuzhiyun /* speed_duplex[] is used for setting the speed and duplex mode of NIC.
326*4882a593Smuzhiyun    0: indicate autonegotiation for both speed and duplex mode
327*4882a593Smuzhiyun    1: indicate 100Mbps half duplex mode
328*4882a593Smuzhiyun    2: indicate 100Mbps full duplex mode
329*4882a593Smuzhiyun    3: indicate 10Mbps half duplex mode
330*4882a593Smuzhiyun    4: indicate 10Mbps full duplex mode
331*4882a593Smuzhiyun    5: indicate 1000Mbps full duplex mode
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun    Note:
334*4882a593Smuzhiyun    if EEPROM have been set to the force mode, this option is ignored
335*4882a593Smuzhiyun    by driver.
336*4882a593Smuzhiyun */
337*4882a593Smuzhiyun VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun #define WOL_OPT_DEF     0
340*4882a593Smuzhiyun #define WOL_OPT_MIN     0
341*4882a593Smuzhiyun #define WOL_OPT_MAX     7
342*4882a593Smuzhiyun /* wol_opts[] is used for controlling wake on lan behavior.
343*4882a593Smuzhiyun    0: Wake up if recevied a magic packet. (Default)
344*4882a593Smuzhiyun    1: Wake up if link status is on/off.
345*4882a593Smuzhiyun    2: Wake up if recevied an arp packet.
346*4882a593Smuzhiyun    4: Wake up if recevied any unicast packet.
347*4882a593Smuzhiyun    Those value can be sumed up to support more than one option.
348*4882a593Smuzhiyun */
349*4882a593Smuzhiyun VELOCITY_PARAM(wol_opts, "Wake On Lan options");
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun static int rx_copybreak = 200;
352*4882a593Smuzhiyun module_param(rx_copybreak, int, 0644);
353*4882a593Smuzhiyun MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun /*
356*4882a593Smuzhiyun  *	Internal board variants. At the moment we have only one
357*4882a593Smuzhiyun  */
358*4882a593Smuzhiyun static struct velocity_info_tbl chip_info_table[] = {
359*4882a593Smuzhiyun 	{CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
360*4882a593Smuzhiyun 	{ }
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun /*
364*4882a593Smuzhiyun  *	Describe the PCI device identifiers that we support in this
365*4882a593Smuzhiyun  *	device driver. Used for hotplug autoloading.
366*4882a593Smuzhiyun  */
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun static const struct pci_device_id velocity_pci_id_table[] = {
369*4882a593Smuzhiyun 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
370*4882a593Smuzhiyun 	{ }
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, velocity_pci_id_table);
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun /*
376*4882a593Smuzhiyun  *	Describe the OF device identifiers that we support in this
377*4882a593Smuzhiyun  *	device driver. Used for devicetree nodes.
378*4882a593Smuzhiyun  */
379*4882a593Smuzhiyun static const struct of_device_id velocity_of_ids[] = {
380*4882a593Smuzhiyun 	{ .compatible = "via,velocity-vt6110", .data = &chip_info_table[0] },
381*4882a593Smuzhiyun 	{ /* Sentinel */ },
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, velocity_of_ids);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun /**
386*4882a593Smuzhiyun  *	get_chip_name	- 	identifier to name
387*4882a593Smuzhiyun  *	@chip_id: chip identifier
388*4882a593Smuzhiyun  *
389*4882a593Smuzhiyun  *	Given a chip identifier return a suitable description. Returns
390*4882a593Smuzhiyun  *	a pointer a static string valid while the driver is loaded.
391*4882a593Smuzhiyun  */
get_chip_name(enum chip_type chip_id)392*4882a593Smuzhiyun static const char *get_chip_name(enum chip_type chip_id)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	int i;
395*4882a593Smuzhiyun 	for (i = 0; chip_info_table[i].name != NULL; i++)
396*4882a593Smuzhiyun 		if (chip_info_table[i].chip_id == chip_id)
397*4882a593Smuzhiyun 			break;
398*4882a593Smuzhiyun 	return chip_info_table[i].name;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun /**
402*4882a593Smuzhiyun  *	velocity_set_int_opt	-	parser for integer options
403*4882a593Smuzhiyun  *	@opt: pointer to option value
404*4882a593Smuzhiyun  *	@val: value the user requested (or -1 for default)
405*4882a593Smuzhiyun  *	@min: lowest value allowed
406*4882a593Smuzhiyun  *	@max: highest value allowed
407*4882a593Smuzhiyun  *	@def: default value
408*4882a593Smuzhiyun  *	@name: property name
409*4882a593Smuzhiyun  *
410*4882a593Smuzhiyun  *	Set an integer property in the module options. This function does
411*4882a593Smuzhiyun  *	all the verification and checking as well as reporting so that
412*4882a593Smuzhiyun  *	we don't duplicate code for each option.
413*4882a593Smuzhiyun  */
velocity_set_int_opt(int * opt,int val,int min,int max,int def,char * name)414*4882a593Smuzhiyun static void velocity_set_int_opt(int *opt, int val, int min, int max, int def,
415*4882a593Smuzhiyun 				 char *name)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun 	if (val == -1)
418*4882a593Smuzhiyun 		*opt = def;
419*4882a593Smuzhiyun 	else if (val < min || val > max) {
420*4882a593Smuzhiyun 		pr_notice("the value of parameter %s is invalid, the valid range is (%d-%d)\n",
421*4882a593Smuzhiyun 			  name, min, max);
422*4882a593Smuzhiyun 		*opt = def;
423*4882a593Smuzhiyun 	} else {
424*4882a593Smuzhiyun 		pr_info("set value of parameter %s to %d\n", name, val);
425*4882a593Smuzhiyun 		*opt = val;
426*4882a593Smuzhiyun 	}
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun /**
430*4882a593Smuzhiyun  *	velocity_set_bool_opt	-	parser for boolean options
431*4882a593Smuzhiyun  *	@opt: pointer to option value
432*4882a593Smuzhiyun  *	@val: value the user requested (or -1 for default)
433*4882a593Smuzhiyun  *	@def: default value (yes/no)
434*4882a593Smuzhiyun  *	@flag: numeric value to set for true.
435*4882a593Smuzhiyun  *	@name: property name
436*4882a593Smuzhiyun  *
437*4882a593Smuzhiyun  *	Set a boolean property in the module options. This function does
438*4882a593Smuzhiyun  *	all the verification and checking as well as reporting so that
439*4882a593Smuzhiyun  *	we don't duplicate code for each option.
440*4882a593Smuzhiyun  */
velocity_set_bool_opt(u32 * opt,int val,int def,u32 flag,char * name)441*4882a593Smuzhiyun static void velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag,
442*4882a593Smuzhiyun 				  char *name)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun 	(*opt) &= (~flag);
445*4882a593Smuzhiyun 	if (val == -1)
446*4882a593Smuzhiyun 		*opt |= (def ? flag : 0);
447*4882a593Smuzhiyun 	else if (val < 0 || val > 1) {
448*4882a593Smuzhiyun 		pr_notice("the value of parameter %s is invalid, the valid range is (%d-%d)\n",
449*4882a593Smuzhiyun 			  name, 0, 1);
450*4882a593Smuzhiyun 		*opt |= (def ? flag : 0);
451*4882a593Smuzhiyun 	} else {
452*4882a593Smuzhiyun 		pr_info("set parameter %s to %s\n",
453*4882a593Smuzhiyun 			name, val ? "TRUE" : "FALSE");
454*4882a593Smuzhiyun 		*opt |= (val ? flag : 0);
455*4882a593Smuzhiyun 	}
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun /**
459*4882a593Smuzhiyun  *	velocity_get_options	-	set options on device
460*4882a593Smuzhiyun  *	@opts: option structure for the device
461*4882a593Smuzhiyun  *	@index: index of option to use in module options array
462*4882a593Smuzhiyun  *
463*4882a593Smuzhiyun  *	Turn the module and command options into a single structure
464*4882a593Smuzhiyun  *	for the current device
465*4882a593Smuzhiyun  */
velocity_get_options(struct velocity_opt * opts,int index)466*4882a593Smuzhiyun static void velocity_get_options(struct velocity_opt *opts, int index)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index],
470*4882a593Smuzhiyun 			     RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF,
471*4882a593Smuzhiyun 			     "rx_thresh");
472*4882a593Smuzhiyun 	velocity_set_int_opt(&opts->DMA_length, DMA_length[index],
473*4882a593Smuzhiyun 			     DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF,
474*4882a593Smuzhiyun 			     "DMA_length");
475*4882a593Smuzhiyun 	velocity_set_int_opt(&opts->numrx, RxDescriptors[index],
476*4882a593Smuzhiyun 			     RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF,
477*4882a593Smuzhiyun 			     "RxDescriptors");
478*4882a593Smuzhiyun 	velocity_set_int_opt(&opts->numtx, TxDescriptors[index],
479*4882a593Smuzhiyun 			     TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF,
480*4882a593Smuzhiyun 			     "TxDescriptors");
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	velocity_set_int_opt(&opts->flow_cntl, flow_control[index],
483*4882a593Smuzhiyun 			     FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF,
484*4882a593Smuzhiyun 			     "flow_control");
485*4882a593Smuzhiyun 	velocity_set_bool_opt(&opts->flags, IP_byte_align[index],
486*4882a593Smuzhiyun 			      IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN,
487*4882a593Smuzhiyun 			      "IP_byte_align");
488*4882a593Smuzhiyun 	velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index],
489*4882a593Smuzhiyun 			     MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF,
490*4882a593Smuzhiyun 			     "Media link mode");
491*4882a593Smuzhiyun 	velocity_set_int_opt(&opts->wol_opts, wol_opts[index],
492*4882a593Smuzhiyun 			     WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF,
493*4882a593Smuzhiyun 			     "Wake On Lan options");
494*4882a593Smuzhiyun 	opts->numrx = (opts->numrx & ~3);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun /**
498*4882a593Smuzhiyun  *	velocity_init_cam_filter	-	initialise CAM
499*4882a593Smuzhiyun  *	@vptr: velocity to program
500*4882a593Smuzhiyun  *
501*4882a593Smuzhiyun  *	Initialize the content addressable memory used for filters. Load
502*4882a593Smuzhiyun  *	appropriately according to the presence of VLAN
503*4882a593Smuzhiyun  */
velocity_init_cam_filter(struct velocity_info * vptr)504*4882a593Smuzhiyun static void velocity_init_cam_filter(struct velocity_info *vptr)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
507*4882a593Smuzhiyun 	unsigned int vid, i = 0;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	/* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
510*4882a593Smuzhiyun 	WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
511*4882a593Smuzhiyun 	WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	/* Disable all CAMs */
514*4882a593Smuzhiyun 	memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
515*4882a593Smuzhiyun 	memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
516*4882a593Smuzhiyun 	mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
517*4882a593Smuzhiyun 	mac_set_cam_mask(regs, vptr->mCAMmask);
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	/* Enable VCAMs */
520*4882a593Smuzhiyun 	for_each_set_bit(vid, vptr->active_vlans, VLAN_N_VID) {
521*4882a593Smuzhiyun 		mac_set_vlan_cam(regs, i, (u8 *) &vid);
522*4882a593Smuzhiyun 		vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
523*4882a593Smuzhiyun 		if (++i >= VCAM_SIZE)
524*4882a593Smuzhiyun 			break;
525*4882a593Smuzhiyun 	}
526*4882a593Smuzhiyun 	mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun 
velocity_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)529*4882a593Smuzhiyun static int velocity_vlan_rx_add_vid(struct net_device *dev,
530*4882a593Smuzhiyun 				    __be16 proto, u16 vid)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	spin_lock_irq(&vptr->lock);
535*4882a593Smuzhiyun 	set_bit(vid, vptr->active_vlans);
536*4882a593Smuzhiyun 	velocity_init_cam_filter(vptr);
537*4882a593Smuzhiyun 	spin_unlock_irq(&vptr->lock);
538*4882a593Smuzhiyun 	return 0;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
velocity_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)541*4882a593Smuzhiyun static int velocity_vlan_rx_kill_vid(struct net_device *dev,
542*4882a593Smuzhiyun 				     __be16 proto, u16 vid)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	spin_lock_irq(&vptr->lock);
547*4882a593Smuzhiyun 	clear_bit(vid, vptr->active_vlans);
548*4882a593Smuzhiyun 	velocity_init_cam_filter(vptr);
549*4882a593Smuzhiyun 	spin_unlock_irq(&vptr->lock);
550*4882a593Smuzhiyun 	return 0;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun 
velocity_init_rx_ring_indexes(struct velocity_info * vptr)553*4882a593Smuzhiyun static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun /**
559*4882a593Smuzhiyun  *	velocity_rx_reset	-	handle a receive reset
560*4882a593Smuzhiyun  *	@vptr: velocity we are resetting
561*4882a593Smuzhiyun  *
562*4882a593Smuzhiyun  *	Reset the ownership and status for the receive ring side.
563*4882a593Smuzhiyun  *	Hand all the receive queue to the NIC.
564*4882a593Smuzhiyun  */
velocity_rx_reset(struct velocity_info * vptr)565*4882a593Smuzhiyun static void velocity_rx_reset(struct velocity_info *vptr)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
569*4882a593Smuzhiyun 	int i;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	velocity_init_rx_ring_indexes(vptr);
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	/*
574*4882a593Smuzhiyun 	 *	Init state, all RD entries belong to the NIC
575*4882a593Smuzhiyun 	 */
576*4882a593Smuzhiyun 	for (i = 0; i < vptr->options.numrx; ++i)
577*4882a593Smuzhiyun 		vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	writew(vptr->options.numrx, &regs->RBRDU);
580*4882a593Smuzhiyun 	writel(vptr->rx.pool_dma, &regs->RDBaseLo);
581*4882a593Smuzhiyun 	writew(0, &regs->RDIdx);
582*4882a593Smuzhiyun 	writew(vptr->options.numrx - 1, &regs->RDCSize);
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun /**
586*4882a593Smuzhiyun  *	velocity_get_opt_media_mode	-	get media selection
587*4882a593Smuzhiyun  *	@vptr: velocity adapter
588*4882a593Smuzhiyun  *
589*4882a593Smuzhiyun  *	Get the media mode stored in EEPROM or module options and load
590*4882a593Smuzhiyun  *	mii_status accordingly. The requested link state information
591*4882a593Smuzhiyun  *	is also returned.
592*4882a593Smuzhiyun  */
velocity_get_opt_media_mode(struct velocity_info * vptr)593*4882a593Smuzhiyun static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun 	u32 status = 0;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	switch (vptr->options.spd_dpx) {
598*4882a593Smuzhiyun 	case SPD_DPX_AUTO:
599*4882a593Smuzhiyun 		status = VELOCITY_AUTONEG_ENABLE;
600*4882a593Smuzhiyun 		break;
601*4882a593Smuzhiyun 	case SPD_DPX_100_FULL:
602*4882a593Smuzhiyun 		status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
603*4882a593Smuzhiyun 		break;
604*4882a593Smuzhiyun 	case SPD_DPX_10_FULL:
605*4882a593Smuzhiyun 		status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
606*4882a593Smuzhiyun 		break;
607*4882a593Smuzhiyun 	case SPD_DPX_100_HALF:
608*4882a593Smuzhiyun 		status = VELOCITY_SPEED_100;
609*4882a593Smuzhiyun 		break;
610*4882a593Smuzhiyun 	case SPD_DPX_10_HALF:
611*4882a593Smuzhiyun 		status = VELOCITY_SPEED_10;
612*4882a593Smuzhiyun 		break;
613*4882a593Smuzhiyun 	case SPD_DPX_1000_FULL:
614*4882a593Smuzhiyun 		status = VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
615*4882a593Smuzhiyun 		break;
616*4882a593Smuzhiyun 	}
617*4882a593Smuzhiyun 	vptr->mii_status = status;
618*4882a593Smuzhiyun 	return status;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun /**
622*4882a593Smuzhiyun  *	safe_disable_mii_autopoll	-	autopoll off
623*4882a593Smuzhiyun  *	@regs: velocity registers
624*4882a593Smuzhiyun  *
625*4882a593Smuzhiyun  *	Turn off the autopoll and wait for it to disable on the chip
626*4882a593Smuzhiyun  */
safe_disable_mii_autopoll(struct mac_regs __iomem * regs)627*4882a593Smuzhiyun static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun 	u16 ww;
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	/*  turn off MAUTO */
632*4882a593Smuzhiyun 	writeb(0, &regs->MIICR);
633*4882a593Smuzhiyun 	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
634*4882a593Smuzhiyun 		udelay(1);
635*4882a593Smuzhiyun 		if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
636*4882a593Smuzhiyun 			break;
637*4882a593Smuzhiyun 	}
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun /**
641*4882a593Smuzhiyun  *	enable_mii_autopoll	-	turn on autopolling
642*4882a593Smuzhiyun  *	@regs: velocity registers
643*4882a593Smuzhiyun  *
644*4882a593Smuzhiyun  *	Enable the MII link status autopoll feature on the Velocity
645*4882a593Smuzhiyun  *	hardware. Wait for it to enable.
646*4882a593Smuzhiyun  */
enable_mii_autopoll(struct mac_regs __iomem * regs)647*4882a593Smuzhiyun static void enable_mii_autopoll(struct mac_regs __iomem *regs)
648*4882a593Smuzhiyun {
649*4882a593Smuzhiyun 	int ii;
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	writeb(0, &(regs->MIICR));
652*4882a593Smuzhiyun 	writeb(MIIADR_SWMPL, &regs->MIIADR);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
655*4882a593Smuzhiyun 		udelay(1);
656*4882a593Smuzhiyun 		if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
657*4882a593Smuzhiyun 			break;
658*4882a593Smuzhiyun 	}
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	writeb(MIICR_MAUTO, &regs->MIICR);
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
663*4882a593Smuzhiyun 		udelay(1);
664*4882a593Smuzhiyun 		if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
665*4882a593Smuzhiyun 			break;
666*4882a593Smuzhiyun 	}
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun /**
671*4882a593Smuzhiyun  *	velocity_mii_read	-	read MII data
672*4882a593Smuzhiyun  *	@regs: velocity registers
673*4882a593Smuzhiyun  *	@index: MII register index
674*4882a593Smuzhiyun  *	@data: buffer for received data
675*4882a593Smuzhiyun  *
676*4882a593Smuzhiyun  *	Perform a single read of an MII 16bit register. Returns zero
677*4882a593Smuzhiyun  *	on success or -ETIMEDOUT if the PHY did not respond.
678*4882a593Smuzhiyun  */
velocity_mii_read(struct mac_regs __iomem * regs,u8 index,u16 * data)679*4882a593Smuzhiyun static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun 	u16 ww;
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	/*
684*4882a593Smuzhiyun 	 *	Disable MIICR_MAUTO, so that mii addr can be set normally
685*4882a593Smuzhiyun 	 */
686*4882a593Smuzhiyun 	safe_disable_mii_autopoll(regs);
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	writeb(index, &regs->MIIADR);
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(MIICR_RCMD, &regs->MIICR);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
693*4882a593Smuzhiyun 		if (!(readb(&regs->MIICR) & MIICR_RCMD))
694*4882a593Smuzhiyun 			break;
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	*data = readw(&regs->MIIDATA);
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	enable_mii_autopoll(regs);
700*4882a593Smuzhiyun 	if (ww == W_MAX_TIMEOUT)
701*4882a593Smuzhiyun 		return -ETIMEDOUT;
702*4882a593Smuzhiyun 	return 0;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun /**
706*4882a593Smuzhiyun  *	mii_check_media_mode	-	check media state
707*4882a593Smuzhiyun  *	@regs: velocity registers
708*4882a593Smuzhiyun  *
709*4882a593Smuzhiyun  *	Check the current MII status and determine the link status
710*4882a593Smuzhiyun  *	accordingly
711*4882a593Smuzhiyun  */
mii_check_media_mode(struct mac_regs __iomem * regs)712*4882a593Smuzhiyun static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun 	u32 status = 0;
715*4882a593Smuzhiyun 	u16 ANAR;
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
718*4882a593Smuzhiyun 		status |= VELOCITY_LINK_FAIL;
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
721*4882a593Smuzhiyun 		status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
722*4882a593Smuzhiyun 	else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
723*4882a593Smuzhiyun 		status |= (VELOCITY_SPEED_1000);
724*4882a593Smuzhiyun 	else {
725*4882a593Smuzhiyun 		velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
726*4882a593Smuzhiyun 		if (ANAR & ADVERTISE_100FULL)
727*4882a593Smuzhiyun 			status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
728*4882a593Smuzhiyun 		else if (ANAR & ADVERTISE_100HALF)
729*4882a593Smuzhiyun 			status |= VELOCITY_SPEED_100;
730*4882a593Smuzhiyun 		else if (ANAR & ADVERTISE_10FULL)
731*4882a593Smuzhiyun 			status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
732*4882a593Smuzhiyun 		else
733*4882a593Smuzhiyun 			status |= (VELOCITY_SPEED_10);
734*4882a593Smuzhiyun 	}
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
737*4882a593Smuzhiyun 		velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
738*4882a593Smuzhiyun 		if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
739*4882a593Smuzhiyun 		    == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
740*4882a593Smuzhiyun 			if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
741*4882a593Smuzhiyun 				status |= VELOCITY_AUTONEG_ENABLE;
742*4882a593Smuzhiyun 		}
743*4882a593Smuzhiyun 	}
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	return status;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun /**
749*4882a593Smuzhiyun  *	velocity_mii_write	-	write MII data
750*4882a593Smuzhiyun  *	@regs: velocity registers
751*4882a593Smuzhiyun  *	@mii_addr: MII register index
752*4882a593Smuzhiyun  *	@data: 16bit data for the MII register
753*4882a593Smuzhiyun  *
754*4882a593Smuzhiyun  *	Perform a single write to an MII 16bit register. Returns zero
755*4882a593Smuzhiyun  *	on success or -ETIMEDOUT if the PHY did not respond.
756*4882a593Smuzhiyun  */
velocity_mii_write(struct mac_regs __iomem * regs,u8 mii_addr,u16 data)757*4882a593Smuzhiyun static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
758*4882a593Smuzhiyun {
759*4882a593Smuzhiyun 	u16 ww;
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 	/*
762*4882a593Smuzhiyun 	 *	Disable MIICR_MAUTO, so that mii addr can be set normally
763*4882a593Smuzhiyun 	 */
764*4882a593Smuzhiyun 	safe_disable_mii_autopoll(regs);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	/* MII reg offset */
767*4882a593Smuzhiyun 	writeb(mii_addr, &regs->MIIADR);
768*4882a593Smuzhiyun 	/* set MII data */
769*4882a593Smuzhiyun 	writew(data, &regs->MIIDATA);
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun 	/* turn on MIICR_WCMD */
772*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(MIICR_WCMD, &regs->MIICR);
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	/* W_MAX_TIMEOUT is the timeout period */
775*4882a593Smuzhiyun 	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
776*4882a593Smuzhiyun 		udelay(5);
777*4882a593Smuzhiyun 		if (!(readb(&regs->MIICR) & MIICR_WCMD))
778*4882a593Smuzhiyun 			break;
779*4882a593Smuzhiyun 	}
780*4882a593Smuzhiyun 	enable_mii_autopoll(regs);
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 	if (ww == W_MAX_TIMEOUT)
783*4882a593Smuzhiyun 		return -ETIMEDOUT;
784*4882a593Smuzhiyun 	return 0;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun /**
788*4882a593Smuzhiyun  *	set_mii_flow_control	-	flow control setup
789*4882a593Smuzhiyun  *	@vptr: velocity interface
790*4882a593Smuzhiyun  *
791*4882a593Smuzhiyun  *	Set up the flow control on this interface according to
792*4882a593Smuzhiyun  *	the supplied user/eeprom options.
793*4882a593Smuzhiyun  */
set_mii_flow_control(struct velocity_info * vptr)794*4882a593Smuzhiyun static void set_mii_flow_control(struct velocity_info *vptr)
795*4882a593Smuzhiyun {
796*4882a593Smuzhiyun 	/*Enable or Disable PAUSE in ANAR */
797*4882a593Smuzhiyun 	switch (vptr->options.flow_cntl) {
798*4882a593Smuzhiyun 	case FLOW_CNTL_TX:
799*4882a593Smuzhiyun 		MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
800*4882a593Smuzhiyun 		MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
801*4882a593Smuzhiyun 		break;
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	case FLOW_CNTL_RX:
804*4882a593Smuzhiyun 		MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
805*4882a593Smuzhiyun 		MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
806*4882a593Smuzhiyun 		break;
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun 	case FLOW_CNTL_TX_RX:
809*4882a593Smuzhiyun 		MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
810*4882a593Smuzhiyun 		MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
811*4882a593Smuzhiyun 		break;
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	case FLOW_CNTL_DISABLE:
814*4882a593Smuzhiyun 		MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
815*4882a593Smuzhiyun 		MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
816*4882a593Smuzhiyun 		break;
817*4882a593Smuzhiyun 	default:
818*4882a593Smuzhiyun 		break;
819*4882a593Smuzhiyun 	}
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun /**
823*4882a593Smuzhiyun  *	mii_set_auto_on		-	autonegotiate on
824*4882a593Smuzhiyun  *	@vptr: velocity
825*4882a593Smuzhiyun  *
826*4882a593Smuzhiyun  *	Enable autonegotation on this interface
827*4882a593Smuzhiyun  */
mii_set_auto_on(struct velocity_info * vptr)828*4882a593Smuzhiyun static void mii_set_auto_on(struct velocity_info *vptr)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun 	if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
831*4882a593Smuzhiyun 		MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
832*4882a593Smuzhiyun 	else
833*4882a593Smuzhiyun 		MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun 
check_connection_type(struct mac_regs __iomem * regs)836*4882a593Smuzhiyun static u32 check_connection_type(struct mac_regs __iomem *regs)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun 	u32 status = 0;
839*4882a593Smuzhiyun 	u8 PHYSR0;
840*4882a593Smuzhiyun 	u16 ANAR;
841*4882a593Smuzhiyun 	PHYSR0 = readb(&regs->PHYSR0);
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	/*
844*4882a593Smuzhiyun 	   if (!(PHYSR0 & PHYSR0_LINKGD))
845*4882a593Smuzhiyun 	   status|=VELOCITY_LINK_FAIL;
846*4882a593Smuzhiyun 	 */
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun 	if (PHYSR0 & PHYSR0_FDPX)
849*4882a593Smuzhiyun 		status |= VELOCITY_DUPLEX_FULL;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	if (PHYSR0 & PHYSR0_SPDG)
852*4882a593Smuzhiyun 		status |= VELOCITY_SPEED_1000;
853*4882a593Smuzhiyun 	else if (PHYSR0 & PHYSR0_SPD10)
854*4882a593Smuzhiyun 		status |= VELOCITY_SPEED_10;
855*4882a593Smuzhiyun 	else
856*4882a593Smuzhiyun 		status |= VELOCITY_SPEED_100;
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
859*4882a593Smuzhiyun 		velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
860*4882a593Smuzhiyun 		if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
861*4882a593Smuzhiyun 		    == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
862*4882a593Smuzhiyun 			if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
863*4882a593Smuzhiyun 				status |= VELOCITY_AUTONEG_ENABLE;
864*4882a593Smuzhiyun 		}
865*4882a593Smuzhiyun 	}
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	return status;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun /**
871*4882a593Smuzhiyun  *	velocity_set_media_mode		-	set media mode
872*4882a593Smuzhiyun  *	@vptr: velocity adapter
873*4882a593Smuzhiyun  *	@mii_status: old MII link state
874*4882a593Smuzhiyun  *
875*4882a593Smuzhiyun  *	Check the media link state and configure the flow control
876*4882a593Smuzhiyun  *	PHY and also velocity hardware setup accordingly. In particular
877*4882a593Smuzhiyun  *	we need to set up CD polling and frame bursting.
878*4882a593Smuzhiyun  */
velocity_set_media_mode(struct velocity_info * vptr,u32 mii_status)879*4882a593Smuzhiyun static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
880*4882a593Smuzhiyun {
881*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun 	vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun 	/* Set mii link status */
886*4882a593Smuzhiyun 	set_mii_flow_control(vptr);
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun 	if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
889*4882a593Smuzhiyun 		MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	/*
892*4882a593Smuzhiyun 	 *	If connection type is AUTO
893*4882a593Smuzhiyun 	 */
894*4882a593Smuzhiyun 	if (mii_status & VELOCITY_AUTONEG_ENABLE) {
895*4882a593Smuzhiyun 		netdev_info(vptr->netdev, "Velocity is in AUTO mode\n");
896*4882a593Smuzhiyun 		/* clear force MAC mode bit */
897*4882a593Smuzhiyun 		BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
898*4882a593Smuzhiyun 		/* set duplex mode of MAC according to duplex mode of MII */
899*4882a593Smuzhiyun 		MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
900*4882a593Smuzhiyun 		MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
901*4882a593Smuzhiyun 		MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 		/* enable AUTO-NEGO mode */
904*4882a593Smuzhiyun 		mii_set_auto_on(vptr);
905*4882a593Smuzhiyun 	} else {
906*4882a593Smuzhiyun 		u16 CTRL1000;
907*4882a593Smuzhiyun 		u16 ANAR;
908*4882a593Smuzhiyun 		u8 CHIPGCR;
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 		/*
911*4882a593Smuzhiyun 		 * 1. if it's 3119, disable frame bursting in halfduplex mode
912*4882a593Smuzhiyun 		 *    and enable it in fullduplex mode
913*4882a593Smuzhiyun 		 * 2. set correct MII/GMII and half/full duplex mode in CHIPGCR
914*4882a593Smuzhiyun 		 * 3. only enable CD heart beat counter in 10HD mode
915*4882a593Smuzhiyun 		 */
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 		/* set force MAC mode bit */
918*4882a593Smuzhiyun 		BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 		CHIPGCR = readb(&regs->CHIPGCR);
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 		if (mii_status & VELOCITY_SPEED_1000)
923*4882a593Smuzhiyun 			CHIPGCR |= CHIPGCR_FCGMII;
924*4882a593Smuzhiyun 		else
925*4882a593Smuzhiyun 			CHIPGCR &= ~CHIPGCR_FCGMII;
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun 		if (mii_status & VELOCITY_DUPLEX_FULL) {
928*4882a593Smuzhiyun 			CHIPGCR |= CHIPGCR_FCFDX;
929*4882a593Smuzhiyun 			writeb(CHIPGCR, &regs->CHIPGCR);
930*4882a593Smuzhiyun 			netdev_info(vptr->netdev,
931*4882a593Smuzhiyun 				    "set Velocity to forced full mode\n");
932*4882a593Smuzhiyun 			if (vptr->rev_id < REV_ID_VT3216_A0)
933*4882a593Smuzhiyun 				BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
934*4882a593Smuzhiyun 		} else {
935*4882a593Smuzhiyun 			CHIPGCR &= ~CHIPGCR_FCFDX;
936*4882a593Smuzhiyun 			netdev_info(vptr->netdev,
937*4882a593Smuzhiyun 				    "set Velocity to forced half mode\n");
938*4882a593Smuzhiyun 			writeb(CHIPGCR, &regs->CHIPGCR);
939*4882a593Smuzhiyun 			if (vptr->rev_id < REV_ID_VT3216_A0)
940*4882a593Smuzhiyun 				BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
941*4882a593Smuzhiyun 		}
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 		velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
944*4882a593Smuzhiyun 		CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
945*4882a593Smuzhiyun 		if ((mii_status & VELOCITY_SPEED_1000) &&
946*4882a593Smuzhiyun 		    (mii_status & VELOCITY_DUPLEX_FULL)) {
947*4882a593Smuzhiyun 			CTRL1000 |= ADVERTISE_1000FULL;
948*4882a593Smuzhiyun 		}
949*4882a593Smuzhiyun 		velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun 		if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
952*4882a593Smuzhiyun 			BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
953*4882a593Smuzhiyun 		else
954*4882a593Smuzhiyun 			BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 		/* MII_REG_BITS_OFF(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); */
957*4882a593Smuzhiyun 		velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
958*4882a593Smuzhiyun 		ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
959*4882a593Smuzhiyun 		if (mii_status & VELOCITY_SPEED_100) {
960*4882a593Smuzhiyun 			if (mii_status & VELOCITY_DUPLEX_FULL)
961*4882a593Smuzhiyun 				ANAR |= ADVERTISE_100FULL;
962*4882a593Smuzhiyun 			else
963*4882a593Smuzhiyun 				ANAR |= ADVERTISE_100HALF;
964*4882a593Smuzhiyun 		} else if (mii_status & VELOCITY_SPEED_10) {
965*4882a593Smuzhiyun 			if (mii_status & VELOCITY_DUPLEX_FULL)
966*4882a593Smuzhiyun 				ANAR |= ADVERTISE_10FULL;
967*4882a593Smuzhiyun 			else
968*4882a593Smuzhiyun 				ANAR |= ADVERTISE_10HALF;
969*4882a593Smuzhiyun 		}
970*4882a593Smuzhiyun 		velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
971*4882a593Smuzhiyun 		/* enable AUTO-NEGO mode */
972*4882a593Smuzhiyun 		mii_set_auto_on(vptr);
973*4882a593Smuzhiyun 		/* MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); */
974*4882a593Smuzhiyun 	}
975*4882a593Smuzhiyun 	/* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */
976*4882a593Smuzhiyun 	/* vptr->mii_status=check_connection_type(vptr->mac_regs); */
977*4882a593Smuzhiyun 	return VELOCITY_LINK_CHANGE;
978*4882a593Smuzhiyun }
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun /**
981*4882a593Smuzhiyun  *	velocity_print_link_status	-	link status reporting
982*4882a593Smuzhiyun  *	@vptr: velocity to report on
983*4882a593Smuzhiyun  *
984*4882a593Smuzhiyun  *	Turn the link status of the velocity card into a kernel log
985*4882a593Smuzhiyun  *	description of the new link state, detailing speed and duplex
986*4882a593Smuzhiyun  *	status
987*4882a593Smuzhiyun  */
velocity_print_link_status(struct velocity_info * vptr)988*4882a593Smuzhiyun static void velocity_print_link_status(struct velocity_info *vptr)
989*4882a593Smuzhiyun {
990*4882a593Smuzhiyun 	const char *link;
991*4882a593Smuzhiyun 	const char *speed;
992*4882a593Smuzhiyun 	const char *duplex;
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 	if (vptr->mii_status & VELOCITY_LINK_FAIL) {
995*4882a593Smuzhiyun 		netdev_notice(vptr->netdev, "failed to detect cable link\n");
996*4882a593Smuzhiyun 		return;
997*4882a593Smuzhiyun 	}
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1000*4882a593Smuzhiyun 		link = "auto-negotiation";
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 		if (vptr->mii_status & VELOCITY_SPEED_1000)
1003*4882a593Smuzhiyun 			speed = "1000";
1004*4882a593Smuzhiyun 		else if (vptr->mii_status & VELOCITY_SPEED_100)
1005*4882a593Smuzhiyun 			speed = "100";
1006*4882a593Smuzhiyun 		else
1007*4882a593Smuzhiyun 			speed = "10";
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1010*4882a593Smuzhiyun 			duplex = "full";
1011*4882a593Smuzhiyun 		else
1012*4882a593Smuzhiyun 			duplex = "half";
1013*4882a593Smuzhiyun 	} else {
1014*4882a593Smuzhiyun 		link = "forced";
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 		switch (vptr->options.spd_dpx) {
1017*4882a593Smuzhiyun 		case SPD_DPX_1000_FULL:
1018*4882a593Smuzhiyun 			speed = "1000";
1019*4882a593Smuzhiyun 			duplex = "full";
1020*4882a593Smuzhiyun 			break;
1021*4882a593Smuzhiyun 		case SPD_DPX_100_HALF:
1022*4882a593Smuzhiyun 			speed = "100";
1023*4882a593Smuzhiyun 			duplex = "half";
1024*4882a593Smuzhiyun 			break;
1025*4882a593Smuzhiyun 		case SPD_DPX_100_FULL:
1026*4882a593Smuzhiyun 			speed = "100";
1027*4882a593Smuzhiyun 			duplex = "full";
1028*4882a593Smuzhiyun 			break;
1029*4882a593Smuzhiyun 		case SPD_DPX_10_HALF:
1030*4882a593Smuzhiyun 			speed = "10";
1031*4882a593Smuzhiyun 			duplex = "half";
1032*4882a593Smuzhiyun 			break;
1033*4882a593Smuzhiyun 		case SPD_DPX_10_FULL:
1034*4882a593Smuzhiyun 			speed = "10";
1035*4882a593Smuzhiyun 			duplex = "full";
1036*4882a593Smuzhiyun 			break;
1037*4882a593Smuzhiyun 		default:
1038*4882a593Smuzhiyun 			speed = "unknown";
1039*4882a593Smuzhiyun 			duplex = "unknown";
1040*4882a593Smuzhiyun 			break;
1041*4882a593Smuzhiyun 		}
1042*4882a593Smuzhiyun 	}
1043*4882a593Smuzhiyun 	netdev_notice(vptr->netdev, "Link %s speed %sM bps %s duplex\n",
1044*4882a593Smuzhiyun 		      link, speed, duplex);
1045*4882a593Smuzhiyun }
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun /**
1048*4882a593Smuzhiyun  *	enable_flow_control_ability	-	flow control
1049*4882a593Smuzhiyun  *	@vptr: veloity to configure
1050*4882a593Smuzhiyun  *
1051*4882a593Smuzhiyun  *	Set up flow control according to the flow control options
1052*4882a593Smuzhiyun  *	determined by the eeprom/configuration.
1053*4882a593Smuzhiyun  */
enable_flow_control_ability(struct velocity_info * vptr)1054*4882a593Smuzhiyun static void enable_flow_control_ability(struct velocity_info *vptr)
1055*4882a593Smuzhiyun {
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	switch (vptr->options.flow_cntl) {
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	case FLOW_CNTL_DEFAULT:
1062*4882a593Smuzhiyun 		if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, &regs->PHYSR0))
1063*4882a593Smuzhiyun 			writel(CR0_FDXRFCEN, &regs->CR0Set);
1064*4882a593Smuzhiyun 		else
1065*4882a593Smuzhiyun 			writel(CR0_FDXRFCEN, &regs->CR0Clr);
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 		if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, &regs->PHYSR0))
1068*4882a593Smuzhiyun 			writel(CR0_FDXTFCEN, &regs->CR0Set);
1069*4882a593Smuzhiyun 		else
1070*4882a593Smuzhiyun 			writel(CR0_FDXTFCEN, &regs->CR0Clr);
1071*4882a593Smuzhiyun 		break;
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	case FLOW_CNTL_TX:
1074*4882a593Smuzhiyun 		writel(CR0_FDXTFCEN, &regs->CR0Set);
1075*4882a593Smuzhiyun 		writel(CR0_FDXRFCEN, &regs->CR0Clr);
1076*4882a593Smuzhiyun 		break;
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	case FLOW_CNTL_RX:
1079*4882a593Smuzhiyun 		writel(CR0_FDXRFCEN, &regs->CR0Set);
1080*4882a593Smuzhiyun 		writel(CR0_FDXTFCEN, &regs->CR0Clr);
1081*4882a593Smuzhiyun 		break;
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	case FLOW_CNTL_TX_RX:
1084*4882a593Smuzhiyun 		writel(CR0_FDXTFCEN, &regs->CR0Set);
1085*4882a593Smuzhiyun 		writel(CR0_FDXRFCEN, &regs->CR0Set);
1086*4882a593Smuzhiyun 		break;
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	case FLOW_CNTL_DISABLE:
1089*4882a593Smuzhiyun 		writel(CR0_FDXRFCEN, &regs->CR0Clr);
1090*4882a593Smuzhiyun 		writel(CR0_FDXTFCEN, &regs->CR0Clr);
1091*4882a593Smuzhiyun 		break;
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun 	default:
1094*4882a593Smuzhiyun 		break;
1095*4882a593Smuzhiyun 	}
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun }
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun /**
1100*4882a593Smuzhiyun  *	velocity_soft_reset	-	soft reset
1101*4882a593Smuzhiyun  *	@vptr: velocity to reset
1102*4882a593Smuzhiyun  *
1103*4882a593Smuzhiyun  *	Kick off a soft reset of the velocity adapter and then poll
1104*4882a593Smuzhiyun  *	until the reset sequence has completed before returning.
1105*4882a593Smuzhiyun  */
velocity_soft_reset(struct velocity_info * vptr)1106*4882a593Smuzhiyun static int velocity_soft_reset(struct velocity_info *vptr)
1107*4882a593Smuzhiyun {
1108*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
1109*4882a593Smuzhiyun 	int i = 0;
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 	writel(CR0_SFRST, &regs->CR0Set);
1112*4882a593Smuzhiyun 
1113*4882a593Smuzhiyun 	for (i = 0; i < W_MAX_TIMEOUT; i++) {
1114*4882a593Smuzhiyun 		udelay(5);
1115*4882a593Smuzhiyun 		if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, &regs->CR0Set))
1116*4882a593Smuzhiyun 			break;
1117*4882a593Smuzhiyun 	}
1118*4882a593Smuzhiyun 
1119*4882a593Smuzhiyun 	if (i == W_MAX_TIMEOUT) {
1120*4882a593Smuzhiyun 		writel(CR0_FORSRST, &regs->CR0Set);
1121*4882a593Smuzhiyun 		/* FIXME: PCI POSTING */
1122*4882a593Smuzhiyun 		/* delay 2ms */
1123*4882a593Smuzhiyun 		mdelay(2);
1124*4882a593Smuzhiyun 	}
1125*4882a593Smuzhiyun 	return 0;
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun /**
1129*4882a593Smuzhiyun  *	velocity_set_multi	-	filter list change callback
1130*4882a593Smuzhiyun  *	@dev: network device
1131*4882a593Smuzhiyun  *
1132*4882a593Smuzhiyun  *	Called by the network layer when the filter lists need to change
1133*4882a593Smuzhiyun  *	for a velocity adapter. Reload the CAMs with the new address
1134*4882a593Smuzhiyun  *	filter ruleset.
1135*4882a593Smuzhiyun  */
velocity_set_multi(struct net_device * dev)1136*4882a593Smuzhiyun static void velocity_set_multi(struct net_device *dev)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
1139*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
1140*4882a593Smuzhiyun 	u8 rx_mode;
1141*4882a593Smuzhiyun 	int i;
1142*4882a593Smuzhiyun 	struct netdev_hw_addr *ha;
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	if (dev->flags & IFF_PROMISC) {	/* Set promiscuous. */
1145*4882a593Smuzhiyun 		writel(0xffffffff, &regs->MARCAM[0]);
1146*4882a593Smuzhiyun 		writel(0xffffffff, &regs->MARCAM[4]);
1147*4882a593Smuzhiyun 		rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
1148*4882a593Smuzhiyun 	} else if ((netdev_mc_count(dev) > vptr->multicast_limit) ||
1149*4882a593Smuzhiyun 		   (dev->flags & IFF_ALLMULTI)) {
1150*4882a593Smuzhiyun 		writel(0xffffffff, &regs->MARCAM[0]);
1151*4882a593Smuzhiyun 		writel(0xffffffff, &regs->MARCAM[4]);
1152*4882a593Smuzhiyun 		rx_mode = (RCR_AM | RCR_AB);
1153*4882a593Smuzhiyun 	} else {
1154*4882a593Smuzhiyun 		int offset = MCAM_SIZE - vptr->multicast_limit;
1155*4882a593Smuzhiyun 		mac_get_cam_mask(regs, vptr->mCAMmask);
1156*4882a593Smuzhiyun 
1157*4882a593Smuzhiyun 		i = 0;
1158*4882a593Smuzhiyun 		netdev_for_each_mc_addr(ha, dev) {
1159*4882a593Smuzhiyun 			mac_set_cam(regs, i + offset, ha->addr);
1160*4882a593Smuzhiyun 			vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
1161*4882a593Smuzhiyun 			i++;
1162*4882a593Smuzhiyun 		}
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun 		mac_set_cam_mask(regs, vptr->mCAMmask);
1165*4882a593Smuzhiyun 		rx_mode = RCR_AM | RCR_AB | RCR_AP;
1166*4882a593Smuzhiyun 	}
1167*4882a593Smuzhiyun 	if (dev->mtu > 1500)
1168*4882a593Smuzhiyun 		rx_mode |= RCR_AL;
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(rx_mode, &regs->RCR);
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun /*
1175*4882a593Smuzhiyun  * MII access , media link mode setting functions
1176*4882a593Smuzhiyun  */
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun /**
1179*4882a593Smuzhiyun  *	mii_init	-	set up MII
1180*4882a593Smuzhiyun  *	@vptr: velocity adapter
1181*4882a593Smuzhiyun  *	@mii_status:  links tatus
1182*4882a593Smuzhiyun  *
1183*4882a593Smuzhiyun  *	Set up the PHY for the current link state.
1184*4882a593Smuzhiyun  */
mii_init(struct velocity_info * vptr,u32 mii_status)1185*4882a593Smuzhiyun static void mii_init(struct velocity_info *vptr, u32 mii_status)
1186*4882a593Smuzhiyun {
1187*4882a593Smuzhiyun 	u16 BMCR;
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun 	switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
1190*4882a593Smuzhiyun 	case PHYID_ICPLUS_IP101A:
1191*4882a593Smuzhiyun 		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP),
1192*4882a593Smuzhiyun 						MII_ADVERTISE, vptr->mac_regs);
1193*4882a593Smuzhiyun 		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1194*4882a593Smuzhiyun 			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION,
1195*4882a593Smuzhiyun 								vptr->mac_regs);
1196*4882a593Smuzhiyun 		else
1197*4882a593Smuzhiyun 			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION,
1198*4882a593Smuzhiyun 								vptr->mac_regs);
1199*4882a593Smuzhiyun 		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1200*4882a593Smuzhiyun 		break;
1201*4882a593Smuzhiyun 	case PHYID_CICADA_CS8201:
1202*4882a593Smuzhiyun 		/*
1203*4882a593Smuzhiyun 		 *	Reset to hardware default
1204*4882a593Smuzhiyun 		 */
1205*4882a593Smuzhiyun 		MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1206*4882a593Smuzhiyun 		/*
1207*4882a593Smuzhiyun 		 *	Turn on ECHODIS bit in NWay-forced full mode and turn it
1208*4882a593Smuzhiyun 		 *	off it in NWay-forced half mode for NWay-forced v.s.
1209*4882a593Smuzhiyun 		 *	legacy-forced issue.
1210*4882a593Smuzhiyun 		 */
1211*4882a593Smuzhiyun 		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1212*4882a593Smuzhiyun 			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1213*4882a593Smuzhiyun 		else
1214*4882a593Smuzhiyun 			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1215*4882a593Smuzhiyun 		/*
1216*4882a593Smuzhiyun 		 *	Turn on Link/Activity LED enable bit for CIS8201
1217*4882a593Smuzhiyun 		 */
1218*4882a593Smuzhiyun 		MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1219*4882a593Smuzhiyun 		break;
1220*4882a593Smuzhiyun 	case PHYID_VT3216_32BIT:
1221*4882a593Smuzhiyun 	case PHYID_VT3216_64BIT:
1222*4882a593Smuzhiyun 		/*
1223*4882a593Smuzhiyun 		 *	Reset to hardware default
1224*4882a593Smuzhiyun 		 */
1225*4882a593Smuzhiyun 		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1226*4882a593Smuzhiyun 		/*
1227*4882a593Smuzhiyun 		 *	Turn on ECHODIS bit in NWay-forced full mode and turn it
1228*4882a593Smuzhiyun 		 *	off it in NWay-forced half mode for NWay-forced v.s.
1229*4882a593Smuzhiyun 		 *	legacy-forced issue
1230*4882a593Smuzhiyun 		 */
1231*4882a593Smuzhiyun 		if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1232*4882a593Smuzhiyun 			MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1233*4882a593Smuzhiyun 		else
1234*4882a593Smuzhiyun 			MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1235*4882a593Smuzhiyun 		break;
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	case PHYID_MARVELL_1000:
1238*4882a593Smuzhiyun 	case PHYID_MARVELL_1000S:
1239*4882a593Smuzhiyun 		/*
1240*4882a593Smuzhiyun 		 *	Assert CRS on Transmit
1241*4882a593Smuzhiyun 		 */
1242*4882a593Smuzhiyun 		MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
1243*4882a593Smuzhiyun 		/*
1244*4882a593Smuzhiyun 		 *	Reset to hardware default
1245*4882a593Smuzhiyun 		 */
1246*4882a593Smuzhiyun 		MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1247*4882a593Smuzhiyun 		break;
1248*4882a593Smuzhiyun 	default:
1249*4882a593Smuzhiyun 		;
1250*4882a593Smuzhiyun 	}
1251*4882a593Smuzhiyun 	velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
1252*4882a593Smuzhiyun 	if (BMCR & BMCR_ISOLATE) {
1253*4882a593Smuzhiyun 		BMCR &= ~BMCR_ISOLATE;
1254*4882a593Smuzhiyun 		velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
1255*4882a593Smuzhiyun 	}
1256*4882a593Smuzhiyun }
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun /**
1259*4882a593Smuzhiyun  * setup_queue_timers	-	Setup interrupt timers
1260*4882a593Smuzhiyun  * @vptr: velocity adapter
1261*4882a593Smuzhiyun  *
1262*4882a593Smuzhiyun  * Setup interrupt frequency during suppression (timeout if the frame
1263*4882a593Smuzhiyun  * count isn't filled).
1264*4882a593Smuzhiyun  */
setup_queue_timers(struct velocity_info * vptr)1265*4882a593Smuzhiyun static void setup_queue_timers(struct velocity_info *vptr)
1266*4882a593Smuzhiyun {
1267*4882a593Smuzhiyun 	/* Only for newer revisions */
1268*4882a593Smuzhiyun 	if (vptr->rev_id >= REV_ID_VT3216_A0) {
1269*4882a593Smuzhiyun 		u8 txqueue_timer = 0;
1270*4882a593Smuzhiyun 		u8 rxqueue_timer = 0;
1271*4882a593Smuzhiyun 
1272*4882a593Smuzhiyun 		if (vptr->mii_status & (VELOCITY_SPEED_1000 |
1273*4882a593Smuzhiyun 				VELOCITY_SPEED_100)) {
1274*4882a593Smuzhiyun 			txqueue_timer = vptr->options.txqueue_timer;
1275*4882a593Smuzhiyun 			rxqueue_timer = vptr->options.rxqueue_timer;
1276*4882a593Smuzhiyun 		}
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 		writeb(txqueue_timer, &vptr->mac_regs->TQETMR);
1279*4882a593Smuzhiyun 		writeb(rxqueue_timer, &vptr->mac_regs->RQETMR);
1280*4882a593Smuzhiyun 	}
1281*4882a593Smuzhiyun }
1282*4882a593Smuzhiyun 
1283*4882a593Smuzhiyun /**
1284*4882a593Smuzhiyun  * setup_adaptive_interrupts  -  Setup interrupt suppression
1285*4882a593Smuzhiyun  * @vptr: velocity adapter
1286*4882a593Smuzhiyun  *
1287*4882a593Smuzhiyun  * The velocity is able to suppress interrupt during high interrupt load.
1288*4882a593Smuzhiyun  * This function turns on that feature.
1289*4882a593Smuzhiyun  */
setup_adaptive_interrupts(struct velocity_info * vptr)1290*4882a593Smuzhiyun static void setup_adaptive_interrupts(struct velocity_info *vptr)
1291*4882a593Smuzhiyun {
1292*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
1293*4882a593Smuzhiyun 	u16 tx_intsup = vptr->options.tx_intsup;
1294*4882a593Smuzhiyun 	u16 rx_intsup = vptr->options.rx_intsup;
1295*4882a593Smuzhiyun 
1296*4882a593Smuzhiyun 	/* Setup default interrupt mask (will be changed below) */
1297*4882a593Smuzhiyun 	vptr->int_mask = INT_MASK_DEF;
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	/* Set Tx Interrupt Suppression Threshold */
1300*4882a593Smuzhiyun 	writeb(CAMCR_PS0, &regs->CAMCR);
1301*4882a593Smuzhiyun 	if (tx_intsup != 0) {
1302*4882a593Smuzhiyun 		vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I |
1303*4882a593Smuzhiyun 				ISR_PTX2I | ISR_PTX3I);
1304*4882a593Smuzhiyun 		writew(tx_intsup, &regs->ISRCTL);
1305*4882a593Smuzhiyun 	} else
1306*4882a593Smuzhiyun 		writew(ISRCTL_TSUPDIS, &regs->ISRCTL);
1307*4882a593Smuzhiyun 
1308*4882a593Smuzhiyun 	/* Set Rx Interrupt Suppression Threshold */
1309*4882a593Smuzhiyun 	writeb(CAMCR_PS1, &regs->CAMCR);
1310*4882a593Smuzhiyun 	if (rx_intsup != 0) {
1311*4882a593Smuzhiyun 		vptr->int_mask &= ~ISR_PRXI;
1312*4882a593Smuzhiyun 		writew(rx_intsup, &regs->ISRCTL);
1313*4882a593Smuzhiyun 	} else
1314*4882a593Smuzhiyun 		writew(ISRCTL_RSUPDIS, &regs->ISRCTL);
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	/* Select page to interrupt hold timer */
1317*4882a593Smuzhiyun 	writeb(0, &regs->CAMCR);
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun /**
1321*4882a593Smuzhiyun  *	velocity_init_registers	-	initialise MAC registers
1322*4882a593Smuzhiyun  *	@vptr: velocity to init
1323*4882a593Smuzhiyun  *	@type: type of initialisation (hot or cold)
1324*4882a593Smuzhiyun  *
1325*4882a593Smuzhiyun  *	Initialise the MAC on a reset or on first set up on the
1326*4882a593Smuzhiyun  *	hardware.
1327*4882a593Smuzhiyun  */
velocity_init_registers(struct velocity_info * vptr,enum velocity_init_type type)1328*4882a593Smuzhiyun static void velocity_init_registers(struct velocity_info *vptr,
1329*4882a593Smuzhiyun 				    enum velocity_init_type type)
1330*4882a593Smuzhiyun {
1331*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
1332*4882a593Smuzhiyun 	struct net_device *netdev = vptr->netdev;
1333*4882a593Smuzhiyun 	int i, mii_status;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	mac_wol_reset(regs);
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	switch (type) {
1338*4882a593Smuzhiyun 	case VELOCITY_INIT_RESET:
1339*4882a593Smuzhiyun 	case VELOCITY_INIT_WOL:
1340*4882a593Smuzhiyun 
1341*4882a593Smuzhiyun 		netif_stop_queue(netdev);
1342*4882a593Smuzhiyun 
1343*4882a593Smuzhiyun 		/*
1344*4882a593Smuzhiyun 		 *	Reset RX to prevent RX pointer not on the 4X location
1345*4882a593Smuzhiyun 		 */
1346*4882a593Smuzhiyun 		velocity_rx_reset(vptr);
1347*4882a593Smuzhiyun 		mac_rx_queue_run(regs);
1348*4882a593Smuzhiyun 		mac_rx_queue_wake(regs);
1349*4882a593Smuzhiyun 
1350*4882a593Smuzhiyun 		mii_status = velocity_get_opt_media_mode(vptr);
1351*4882a593Smuzhiyun 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1352*4882a593Smuzhiyun 			velocity_print_link_status(vptr);
1353*4882a593Smuzhiyun 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1354*4882a593Smuzhiyun 				netif_wake_queue(netdev);
1355*4882a593Smuzhiyun 		}
1356*4882a593Smuzhiyun 
1357*4882a593Smuzhiyun 		enable_flow_control_ability(vptr);
1358*4882a593Smuzhiyun 
1359*4882a593Smuzhiyun 		mac_clear_isr(regs);
1360*4882a593Smuzhiyun 		writel(CR0_STOP, &regs->CR0Clr);
1361*4882a593Smuzhiyun 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
1362*4882a593Smuzhiyun 							&regs->CR0Set);
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun 		break;
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	case VELOCITY_INIT_COLD:
1367*4882a593Smuzhiyun 	default:
1368*4882a593Smuzhiyun 		/*
1369*4882a593Smuzhiyun 		 *	Do reset
1370*4882a593Smuzhiyun 		 */
1371*4882a593Smuzhiyun 		velocity_soft_reset(vptr);
1372*4882a593Smuzhiyun 		mdelay(5);
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun 		if (!vptr->no_eeprom) {
1375*4882a593Smuzhiyun 			mac_eeprom_reload(regs);
1376*4882a593Smuzhiyun 			for (i = 0; i < 6; i++)
1377*4882a593Smuzhiyun 				writeb(netdev->dev_addr[i], regs->PAR + i);
1378*4882a593Smuzhiyun 		}
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 		/*
1381*4882a593Smuzhiyun 		 *	clear Pre_ACPI bit.
1382*4882a593Smuzhiyun 		 */
1383*4882a593Smuzhiyun 		BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
1384*4882a593Smuzhiyun 		mac_set_rx_thresh(regs, vptr->options.rx_thresh);
1385*4882a593Smuzhiyun 		mac_set_dma_length(regs, vptr->options.DMA_length);
1386*4882a593Smuzhiyun 
1387*4882a593Smuzhiyun 		writeb(WOLCFG_SAM | WOLCFG_SAB, &regs->WOLCFGSet);
1388*4882a593Smuzhiyun 		/*
1389*4882a593Smuzhiyun 		 *	Back off algorithm use original IEEE standard
1390*4882a593Smuzhiyun 		 */
1391*4882a593Smuzhiyun 		BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), &regs->CFGB);
1392*4882a593Smuzhiyun 
1393*4882a593Smuzhiyun 		/*
1394*4882a593Smuzhiyun 		 *	Init CAM filter
1395*4882a593Smuzhiyun 		 */
1396*4882a593Smuzhiyun 		velocity_init_cam_filter(vptr);
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 		/*
1399*4882a593Smuzhiyun 		 *	Set packet filter: Receive directed and broadcast address
1400*4882a593Smuzhiyun 		 */
1401*4882a593Smuzhiyun 		velocity_set_multi(netdev);
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 		/*
1404*4882a593Smuzhiyun 		 *	Enable MII auto-polling
1405*4882a593Smuzhiyun 		 */
1406*4882a593Smuzhiyun 		enable_mii_autopoll(regs);
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 		setup_adaptive_interrupts(vptr);
1409*4882a593Smuzhiyun 
1410*4882a593Smuzhiyun 		writel(vptr->rx.pool_dma, &regs->RDBaseLo);
1411*4882a593Smuzhiyun 		writew(vptr->options.numrx - 1, &regs->RDCSize);
1412*4882a593Smuzhiyun 		mac_rx_queue_run(regs);
1413*4882a593Smuzhiyun 		mac_rx_queue_wake(regs);
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 		writew(vptr->options.numtx - 1, &regs->TDCSize);
1416*4882a593Smuzhiyun 
1417*4882a593Smuzhiyun 		for (i = 0; i < vptr->tx.numq; i++) {
1418*4882a593Smuzhiyun 			writel(vptr->tx.pool_dma[i], &regs->TDBaseLo[i]);
1419*4882a593Smuzhiyun 			mac_tx_queue_run(regs, i);
1420*4882a593Smuzhiyun 		}
1421*4882a593Smuzhiyun 
1422*4882a593Smuzhiyun 		init_flow_control_register(vptr);
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun 		writel(CR0_STOP, &regs->CR0Clr);
1425*4882a593Smuzhiyun 		writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
1426*4882a593Smuzhiyun 
1427*4882a593Smuzhiyun 		mii_status = velocity_get_opt_media_mode(vptr);
1428*4882a593Smuzhiyun 		netif_stop_queue(netdev);
1429*4882a593Smuzhiyun 
1430*4882a593Smuzhiyun 		mii_init(vptr, mii_status);
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun 		if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1433*4882a593Smuzhiyun 			velocity_print_link_status(vptr);
1434*4882a593Smuzhiyun 			if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1435*4882a593Smuzhiyun 				netif_wake_queue(netdev);
1436*4882a593Smuzhiyun 		}
1437*4882a593Smuzhiyun 
1438*4882a593Smuzhiyun 		enable_flow_control_ability(vptr);
1439*4882a593Smuzhiyun 		mac_hw_mibs_init(regs);
1440*4882a593Smuzhiyun 		mac_write_int_mask(vptr->int_mask, regs);
1441*4882a593Smuzhiyun 		mac_clear_isr(regs);
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	}
1444*4882a593Smuzhiyun }
1445*4882a593Smuzhiyun 
velocity_give_many_rx_descs(struct velocity_info * vptr)1446*4882a593Smuzhiyun static void velocity_give_many_rx_descs(struct velocity_info *vptr)
1447*4882a593Smuzhiyun {
1448*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
1449*4882a593Smuzhiyun 	int avail, dirty, unusable;
1450*4882a593Smuzhiyun 
1451*4882a593Smuzhiyun 	/*
1452*4882a593Smuzhiyun 	 * RD number must be equal to 4X per hardware spec
1453*4882a593Smuzhiyun 	 * (programming guide rev 1.20, p.13)
1454*4882a593Smuzhiyun 	 */
1455*4882a593Smuzhiyun 	if (vptr->rx.filled < 4)
1456*4882a593Smuzhiyun 		return;
1457*4882a593Smuzhiyun 
1458*4882a593Smuzhiyun 	wmb();
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 	unusable = vptr->rx.filled & 0x0003;
1461*4882a593Smuzhiyun 	dirty = vptr->rx.dirty - unusable;
1462*4882a593Smuzhiyun 	for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
1463*4882a593Smuzhiyun 		dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
1464*4882a593Smuzhiyun 		vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
1465*4882a593Smuzhiyun 	}
1466*4882a593Smuzhiyun 
1467*4882a593Smuzhiyun 	writew(vptr->rx.filled & 0xfffc, &regs->RBRDU);
1468*4882a593Smuzhiyun 	vptr->rx.filled = unusable;
1469*4882a593Smuzhiyun }
1470*4882a593Smuzhiyun 
1471*4882a593Smuzhiyun /**
1472*4882a593Smuzhiyun  *	velocity_init_dma_rings	-	set up DMA rings
1473*4882a593Smuzhiyun  *	@vptr: Velocity to set up
1474*4882a593Smuzhiyun  *
1475*4882a593Smuzhiyun  *	Allocate PCI mapped DMA rings for the receive and transmit layer
1476*4882a593Smuzhiyun  *	to use.
1477*4882a593Smuzhiyun  */
velocity_init_dma_rings(struct velocity_info * vptr)1478*4882a593Smuzhiyun static int velocity_init_dma_rings(struct velocity_info *vptr)
1479*4882a593Smuzhiyun {
1480*4882a593Smuzhiyun 	struct velocity_opt *opt = &vptr->options;
1481*4882a593Smuzhiyun 	const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
1482*4882a593Smuzhiyun 	const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
1483*4882a593Smuzhiyun 	dma_addr_t pool_dma;
1484*4882a593Smuzhiyun 	void *pool;
1485*4882a593Smuzhiyun 	unsigned int i;
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun 	/*
1488*4882a593Smuzhiyun 	 * Allocate all RD/TD rings a single pool.
1489*4882a593Smuzhiyun 	 *
1490*4882a593Smuzhiyun 	 * dma_alloc_coherent() fulfills the requirement for 64 bytes
1491*4882a593Smuzhiyun 	 * alignment
1492*4882a593Smuzhiyun 	 */
1493*4882a593Smuzhiyun 	pool = dma_alloc_coherent(vptr->dev, tx_ring_size * vptr->tx.numq +
1494*4882a593Smuzhiyun 				    rx_ring_size, &pool_dma, GFP_ATOMIC);
1495*4882a593Smuzhiyun 	if (!pool) {
1496*4882a593Smuzhiyun 		dev_err(vptr->dev, "%s : DMA memory allocation failed.\n",
1497*4882a593Smuzhiyun 			vptr->netdev->name);
1498*4882a593Smuzhiyun 		return -ENOMEM;
1499*4882a593Smuzhiyun 	}
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun 	vptr->rx.ring = pool;
1502*4882a593Smuzhiyun 	vptr->rx.pool_dma = pool_dma;
1503*4882a593Smuzhiyun 
1504*4882a593Smuzhiyun 	pool += rx_ring_size;
1505*4882a593Smuzhiyun 	pool_dma += rx_ring_size;
1506*4882a593Smuzhiyun 
1507*4882a593Smuzhiyun 	for (i = 0; i < vptr->tx.numq; i++) {
1508*4882a593Smuzhiyun 		vptr->tx.rings[i] = pool;
1509*4882a593Smuzhiyun 		vptr->tx.pool_dma[i] = pool_dma;
1510*4882a593Smuzhiyun 		pool += tx_ring_size;
1511*4882a593Smuzhiyun 		pool_dma += tx_ring_size;
1512*4882a593Smuzhiyun 	}
1513*4882a593Smuzhiyun 
1514*4882a593Smuzhiyun 	return 0;
1515*4882a593Smuzhiyun }
1516*4882a593Smuzhiyun 
velocity_set_rxbufsize(struct velocity_info * vptr,int mtu)1517*4882a593Smuzhiyun static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
1518*4882a593Smuzhiyun {
1519*4882a593Smuzhiyun 	vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun /**
1523*4882a593Smuzhiyun  *	velocity_alloc_rx_buf	-	allocate aligned receive buffer
1524*4882a593Smuzhiyun  *	@vptr: velocity
1525*4882a593Smuzhiyun  *	@idx: ring index
1526*4882a593Smuzhiyun  *
1527*4882a593Smuzhiyun  *	Allocate a new full sized buffer for the reception of a frame and
1528*4882a593Smuzhiyun  *	map it into PCI space for the hardware to use. The hardware
1529*4882a593Smuzhiyun  *	requires *64* byte alignment of the buffer which makes life
1530*4882a593Smuzhiyun  *	less fun than would be ideal.
1531*4882a593Smuzhiyun  */
velocity_alloc_rx_buf(struct velocity_info * vptr,int idx)1532*4882a593Smuzhiyun static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1533*4882a593Smuzhiyun {
1534*4882a593Smuzhiyun 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
1535*4882a593Smuzhiyun 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	rd_info->skb = netdev_alloc_skb(vptr->netdev, vptr->rx.buf_sz + 64);
1538*4882a593Smuzhiyun 	if (rd_info->skb == NULL)
1539*4882a593Smuzhiyun 		return -ENOMEM;
1540*4882a593Smuzhiyun 
1541*4882a593Smuzhiyun 	/*
1542*4882a593Smuzhiyun 	 *	Do the gymnastics to get the buffer head for data at
1543*4882a593Smuzhiyun 	 *	64byte alignment.
1544*4882a593Smuzhiyun 	 */
1545*4882a593Smuzhiyun 	skb_reserve(rd_info->skb,
1546*4882a593Smuzhiyun 			64 - ((unsigned long) rd_info->skb->data & 63));
1547*4882a593Smuzhiyun 	rd_info->skb_dma = dma_map_single(vptr->dev, rd_info->skb->data,
1548*4882a593Smuzhiyun 					vptr->rx.buf_sz, DMA_FROM_DEVICE);
1549*4882a593Smuzhiyun 
1550*4882a593Smuzhiyun 	/*
1551*4882a593Smuzhiyun 	 *	Fill in the descriptor to match
1552*4882a593Smuzhiyun 	 */
1553*4882a593Smuzhiyun 
1554*4882a593Smuzhiyun 	*((u32 *) & (rd->rdesc0)) = 0;
1555*4882a593Smuzhiyun 	rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
1556*4882a593Smuzhiyun 	rd->pa_low = cpu_to_le32(rd_info->skb_dma);
1557*4882a593Smuzhiyun 	rd->pa_high = 0;
1558*4882a593Smuzhiyun 	return 0;
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun 
1561*4882a593Smuzhiyun 
velocity_rx_refill(struct velocity_info * vptr)1562*4882a593Smuzhiyun static int velocity_rx_refill(struct velocity_info *vptr)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun 	int dirty = vptr->rx.dirty, done = 0;
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun 	do {
1567*4882a593Smuzhiyun 		struct rx_desc *rd = vptr->rx.ring + dirty;
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun 		/* Fine for an all zero Rx desc at init time as well */
1570*4882a593Smuzhiyun 		if (rd->rdesc0.len & OWNED_BY_NIC)
1571*4882a593Smuzhiyun 			break;
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 		if (!vptr->rx.info[dirty].skb) {
1574*4882a593Smuzhiyun 			if (velocity_alloc_rx_buf(vptr, dirty) < 0)
1575*4882a593Smuzhiyun 				break;
1576*4882a593Smuzhiyun 		}
1577*4882a593Smuzhiyun 		done++;
1578*4882a593Smuzhiyun 		dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
1579*4882a593Smuzhiyun 	} while (dirty != vptr->rx.curr);
1580*4882a593Smuzhiyun 
1581*4882a593Smuzhiyun 	if (done) {
1582*4882a593Smuzhiyun 		vptr->rx.dirty = dirty;
1583*4882a593Smuzhiyun 		vptr->rx.filled += done;
1584*4882a593Smuzhiyun 	}
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun 	return done;
1587*4882a593Smuzhiyun }
1588*4882a593Smuzhiyun 
1589*4882a593Smuzhiyun /**
1590*4882a593Smuzhiyun  *	velocity_free_rd_ring	-	free receive ring
1591*4882a593Smuzhiyun  *	@vptr: velocity to clean up
1592*4882a593Smuzhiyun  *
1593*4882a593Smuzhiyun  *	Free the receive buffers for each ring slot and any
1594*4882a593Smuzhiyun  *	attached socket buffers that need to go away.
1595*4882a593Smuzhiyun  */
velocity_free_rd_ring(struct velocity_info * vptr)1596*4882a593Smuzhiyun static void velocity_free_rd_ring(struct velocity_info *vptr)
1597*4882a593Smuzhiyun {
1598*4882a593Smuzhiyun 	int i;
1599*4882a593Smuzhiyun 
1600*4882a593Smuzhiyun 	if (vptr->rx.info == NULL)
1601*4882a593Smuzhiyun 		return;
1602*4882a593Smuzhiyun 
1603*4882a593Smuzhiyun 	for (i = 0; i < vptr->options.numrx; i++) {
1604*4882a593Smuzhiyun 		struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
1605*4882a593Smuzhiyun 		struct rx_desc *rd = vptr->rx.ring + i;
1606*4882a593Smuzhiyun 
1607*4882a593Smuzhiyun 		memset(rd, 0, sizeof(*rd));
1608*4882a593Smuzhiyun 
1609*4882a593Smuzhiyun 		if (!rd_info->skb)
1610*4882a593Smuzhiyun 			continue;
1611*4882a593Smuzhiyun 		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
1612*4882a593Smuzhiyun 				 DMA_FROM_DEVICE);
1613*4882a593Smuzhiyun 		rd_info->skb_dma = 0;
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 		dev_kfree_skb(rd_info->skb);
1616*4882a593Smuzhiyun 		rd_info->skb = NULL;
1617*4882a593Smuzhiyun 	}
1618*4882a593Smuzhiyun 
1619*4882a593Smuzhiyun 	kfree(vptr->rx.info);
1620*4882a593Smuzhiyun 	vptr->rx.info = NULL;
1621*4882a593Smuzhiyun }
1622*4882a593Smuzhiyun 
1623*4882a593Smuzhiyun /**
1624*4882a593Smuzhiyun  *	velocity_init_rd_ring	-	set up receive ring
1625*4882a593Smuzhiyun  *	@vptr: velocity to configure
1626*4882a593Smuzhiyun  *
1627*4882a593Smuzhiyun  *	Allocate and set up the receive buffers for each ring slot and
1628*4882a593Smuzhiyun  *	assign them to the network adapter.
1629*4882a593Smuzhiyun  */
velocity_init_rd_ring(struct velocity_info * vptr)1630*4882a593Smuzhiyun static int velocity_init_rd_ring(struct velocity_info *vptr)
1631*4882a593Smuzhiyun {
1632*4882a593Smuzhiyun 	int ret = -ENOMEM;
1633*4882a593Smuzhiyun 
1634*4882a593Smuzhiyun 	vptr->rx.info = kcalloc(vptr->options.numrx,
1635*4882a593Smuzhiyun 				sizeof(struct velocity_rd_info), GFP_KERNEL);
1636*4882a593Smuzhiyun 	if (!vptr->rx.info)
1637*4882a593Smuzhiyun 		goto out;
1638*4882a593Smuzhiyun 
1639*4882a593Smuzhiyun 	velocity_init_rx_ring_indexes(vptr);
1640*4882a593Smuzhiyun 
1641*4882a593Smuzhiyun 	if (velocity_rx_refill(vptr) != vptr->options.numrx) {
1642*4882a593Smuzhiyun 		netdev_err(vptr->netdev, "failed to allocate RX buffer\n");
1643*4882a593Smuzhiyun 		velocity_free_rd_ring(vptr);
1644*4882a593Smuzhiyun 		goto out;
1645*4882a593Smuzhiyun 	}
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun 	ret = 0;
1648*4882a593Smuzhiyun out:
1649*4882a593Smuzhiyun 	return ret;
1650*4882a593Smuzhiyun }
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun /**
1653*4882a593Smuzhiyun  *	velocity_init_td_ring	-	set up transmit ring
1654*4882a593Smuzhiyun  *	@vptr:	velocity
1655*4882a593Smuzhiyun  *
1656*4882a593Smuzhiyun  *	Set up the transmit ring and chain the ring pointers together.
1657*4882a593Smuzhiyun  *	Returns zero on success or a negative posix errno code for
1658*4882a593Smuzhiyun  *	failure.
1659*4882a593Smuzhiyun  */
velocity_init_td_ring(struct velocity_info * vptr)1660*4882a593Smuzhiyun static int velocity_init_td_ring(struct velocity_info *vptr)
1661*4882a593Smuzhiyun {
1662*4882a593Smuzhiyun 	int j;
1663*4882a593Smuzhiyun 
1664*4882a593Smuzhiyun 	/* Init the TD ring entries */
1665*4882a593Smuzhiyun 	for (j = 0; j < vptr->tx.numq; j++) {
1666*4882a593Smuzhiyun 
1667*4882a593Smuzhiyun 		vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
1668*4882a593Smuzhiyun 					    sizeof(struct velocity_td_info),
1669*4882a593Smuzhiyun 					    GFP_KERNEL);
1670*4882a593Smuzhiyun 		if (!vptr->tx.infos[j])	{
1671*4882a593Smuzhiyun 			while (--j >= 0)
1672*4882a593Smuzhiyun 				kfree(vptr->tx.infos[j]);
1673*4882a593Smuzhiyun 			return -ENOMEM;
1674*4882a593Smuzhiyun 		}
1675*4882a593Smuzhiyun 
1676*4882a593Smuzhiyun 		vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
1677*4882a593Smuzhiyun 	}
1678*4882a593Smuzhiyun 	return 0;
1679*4882a593Smuzhiyun }
1680*4882a593Smuzhiyun 
1681*4882a593Smuzhiyun /**
1682*4882a593Smuzhiyun  *	velocity_free_dma_rings	-	free PCI ring pointers
1683*4882a593Smuzhiyun  *	@vptr: Velocity to free from
1684*4882a593Smuzhiyun  *
1685*4882a593Smuzhiyun  *	Clean up the PCI ring buffers allocated to this velocity.
1686*4882a593Smuzhiyun  */
velocity_free_dma_rings(struct velocity_info * vptr)1687*4882a593Smuzhiyun static void velocity_free_dma_rings(struct velocity_info *vptr)
1688*4882a593Smuzhiyun {
1689*4882a593Smuzhiyun 	const int size = vptr->options.numrx * sizeof(struct rx_desc) +
1690*4882a593Smuzhiyun 		vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
1691*4882a593Smuzhiyun 
1692*4882a593Smuzhiyun 	dma_free_coherent(vptr->dev, size, vptr->rx.ring, vptr->rx.pool_dma);
1693*4882a593Smuzhiyun }
1694*4882a593Smuzhiyun 
velocity_init_rings(struct velocity_info * vptr,int mtu)1695*4882a593Smuzhiyun static int velocity_init_rings(struct velocity_info *vptr, int mtu)
1696*4882a593Smuzhiyun {
1697*4882a593Smuzhiyun 	int ret;
1698*4882a593Smuzhiyun 
1699*4882a593Smuzhiyun 	velocity_set_rxbufsize(vptr, mtu);
1700*4882a593Smuzhiyun 
1701*4882a593Smuzhiyun 	ret = velocity_init_dma_rings(vptr);
1702*4882a593Smuzhiyun 	if (ret < 0)
1703*4882a593Smuzhiyun 		goto out;
1704*4882a593Smuzhiyun 
1705*4882a593Smuzhiyun 	ret = velocity_init_rd_ring(vptr);
1706*4882a593Smuzhiyun 	if (ret < 0)
1707*4882a593Smuzhiyun 		goto err_free_dma_rings_0;
1708*4882a593Smuzhiyun 
1709*4882a593Smuzhiyun 	ret = velocity_init_td_ring(vptr);
1710*4882a593Smuzhiyun 	if (ret < 0)
1711*4882a593Smuzhiyun 		goto err_free_rd_ring_1;
1712*4882a593Smuzhiyun out:
1713*4882a593Smuzhiyun 	return ret;
1714*4882a593Smuzhiyun 
1715*4882a593Smuzhiyun err_free_rd_ring_1:
1716*4882a593Smuzhiyun 	velocity_free_rd_ring(vptr);
1717*4882a593Smuzhiyun err_free_dma_rings_0:
1718*4882a593Smuzhiyun 	velocity_free_dma_rings(vptr);
1719*4882a593Smuzhiyun 	goto out;
1720*4882a593Smuzhiyun }
1721*4882a593Smuzhiyun 
1722*4882a593Smuzhiyun /**
1723*4882a593Smuzhiyun  *	velocity_free_tx_buf	-	free transmit buffer
1724*4882a593Smuzhiyun  *	@vptr: velocity
1725*4882a593Smuzhiyun  *	@tdinfo: buffer
1726*4882a593Smuzhiyun  *	@td: transmit descriptor to free
1727*4882a593Smuzhiyun  *
1728*4882a593Smuzhiyun  *	Release an transmit buffer. If the buffer was preallocated then
1729*4882a593Smuzhiyun  *	recycle it, if not then unmap the buffer.
1730*4882a593Smuzhiyun  */
velocity_free_tx_buf(struct velocity_info * vptr,struct velocity_td_info * tdinfo,struct tx_desc * td)1731*4882a593Smuzhiyun static void velocity_free_tx_buf(struct velocity_info *vptr,
1732*4882a593Smuzhiyun 		struct velocity_td_info *tdinfo, struct tx_desc *td)
1733*4882a593Smuzhiyun {
1734*4882a593Smuzhiyun 	struct sk_buff *skb = tdinfo->skb;
1735*4882a593Smuzhiyun 	int i;
1736*4882a593Smuzhiyun 
1737*4882a593Smuzhiyun 	/*
1738*4882a593Smuzhiyun 	 *	Don't unmap the pre-allocated tx_bufs
1739*4882a593Smuzhiyun 	 */
1740*4882a593Smuzhiyun 	for (i = 0; i < tdinfo->nskb_dma; i++) {
1741*4882a593Smuzhiyun 		size_t pktlen = max_t(size_t, skb->len, ETH_ZLEN);
1742*4882a593Smuzhiyun 
1743*4882a593Smuzhiyun 		/* For scatter-gather */
1744*4882a593Smuzhiyun 		if (skb_shinfo(skb)->nr_frags > 0)
1745*4882a593Smuzhiyun 			pktlen = max_t(size_t, pktlen,
1746*4882a593Smuzhiyun 				       td->td_buf[i].size & ~TD_QUEUE);
1747*4882a593Smuzhiyun 
1748*4882a593Smuzhiyun 		dma_unmap_single(vptr->dev, tdinfo->skb_dma[i],
1749*4882a593Smuzhiyun 				 le16_to_cpu(pktlen), DMA_TO_DEVICE);
1750*4882a593Smuzhiyun 	}
1751*4882a593Smuzhiyun 	dev_consume_skb_irq(skb);
1752*4882a593Smuzhiyun 	tdinfo->skb = NULL;
1753*4882a593Smuzhiyun }
1754*4882a593Smuzhiyun 
1755*4882a593Smuzhiyun /*
1756*4882a593Smuzhiyun  *	FIXME: could we merge this with velocity_free_tx_buf ?
1757*4882a593Smuzhiyun  */
velocity_free_td_ring_entry(struct velocity_info * vptr,int q,int n)1758*4882a593Smuzhiyun static void velocity_free_td_ring_entry(struct velocity_info *vptr,
1759*4882a593Smuzhiyun 							 int q, int n)
1760*4882a593Smuzhiyun {
1761*4882a593Smuzhiyun 	struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
1762*4882a593Smuzhiyun 	int i;
1763*4882a593Smuzhiyun 
1764*4882a593Smuzhiyun 	if (td_info == NULL)
1765*4882a593Smuzhiyun 		return;
1766*4882a593Smuzhiyun 
1767*4882a593Smuzhiyun 	if (td_info->skb) {
1768*4882a593Smuzhiyun 		for (i = 0; i < td_info->nskb_dma; i++) {
1769*4882a593Smuzhiyun 			if (td_info->skb_dma[i]) {
1770*4882a593Smuzhiyun 				dma_unmap_single(vptr->dev, td_info->skb_dma[i],
1771*4882a593Smuzhiyun 					td_info->skb->len, DMA_TO_DEVICE);
1772*4882a593Smuzhiyun 				td_info->skb_dma[i] = 0;
1773*4882a593Smuzhiyun 			}
1774*4882a593Smuzhiyun 		}
1775*4882a593Smuzhiyun 		dev_kfree_skb(td_info->skb);
1776*4882a593Smuzhiyun 		td_info->skb = NULL;
1777*4882a593Smuzhiyun 	}
1778*4882a593Smuzhiyun }
1779*4882a593Smuzhiyun 
1780*4882a593Smuzhiyun /**
1781*4882a593Smuzhiyun  *	velocity_free_td_ring	-	free td ring
1782*4882a593Smuzhiyun  *	@vptr: velocity
1783*4882a593Smuzhiyun  *
1784*4882a593Smuzhiyun  *	Free up the transmit ring for this particular velocity adapter.
1785*4882a593Smuzhiyun  *	We free the ring contents but not the ring itself.
1786*4882a593Smuzhiyun  */
velocity_free_td_ring(struct velocity_info * vptr)1787*4882a593Smuzhiyun static void velocity_free_td_ring(struct velocity_info *vptr)
1788*4882a593Smuzhiyun {
1789*4882a593Smuzhiyun 	int i, j;
1790*4882a593Smuzhiyun 
1791*4882a593Smuzhiyun 	for (j = 0; j < vptr->tx.numq; j++) {
1792*4882a593Smuzhiyun 		if (vptr->tx.infos[j] == NULL)
1793*4882a593Smuzhiyun 			continue;
1794*4882a593Smuzhiyun 		for (i = 0; i < vptr->options.numtx; i++)
1795*4882a593Smuzhiyun 			velocity_free_td_ring_entry(vptr, j, i);
1796*4882a593Smuzhiyun 
1797*4882a593Smuzhiyun 		kfree(vptr->tx.infos[j]);
1798*4882a593Smuzhiyun 		vptr->tx.infos[j] = NULL;
1799*4882a593Smuzhiyun 	}
1800*4882a593Smuzhiyun }
1801*4882a593Smuzhiyun 
velocity_free_rings(struct velocity_info * vptr)1802*4882a593Smuzhiyun static void velocity_free_rings(struct velocity_info *vptr)
1803*4882a593Smuzhiyun {
1804*4882a593Smuzhiyun 	velocity_free_td_ring(vptr);
1805*4882a593Smuzhiyun 	velocity_free_rd_ring(vptr);
1806*4882a593Smuzhiyun 	velocity_free_dma_rings(vptr);
1807*4882a593Smuzhiyun }
1808*4882a593Smuzhiyun 
1809*4882a593Smuzhiyun /**
1810*4882a593Smuzhiyun  *	velocity_error	-	handle error from controller
1811*4882a593Smuzhiyun  *	@vptr: velocity
1812*4882a593Smuzhiyun  *	@status: card status
1813*4882a593Smuzhiyun  *
1814*4882a593Smuzhiyun  *	Process an error report from the hardware and attempt to recover
1815*4882a593Smuzhiyun  *	the card itself. At the moment we cannot recover from some
1816*4882a593Smuzhiyun  *	theoretically impossible errors but this could be fixed using
1817*4882a593Smuzhiyun  *	the pci_device_failed logic to bounce the hardware
1818*4882a593Smuzhiyun  *
1819*4882a593Smuzhiyun  */
velocity_error(struct velocity_info * vptr,int status)1820*4882a593Smuzhiyun static void velocity_error(struct velocity_info *vptr, int status)
1821*4882a593Smuzhiyun {
1822*4882a593Smuzhiyun 
1823*4882a593Smuzhiyun 	if (status & ISR_TXSTLI) {
1824*4882a593Smuzhiyun 		struct mac_regs __iomem *regs = vptr->mac_regs;
1825*4882a593Smuzhiyun 
1826*4882a593Smuzhiyun 		netdev_err(vptr->netdev, "TD structure error TDindex=%hx\n",
1827*4882a593Smuzhiyun 			   readw(&regs->TDIdx[0]));
1828*4882a593Smuzhiyun 		BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
1829*4882a593Smuzhiyun 		writew(TRDCSR_RUN, &regs->TDCSRClr);
1830*4882a593Smuzhiyun 		netif_stop_queue(vptr->netdev);
1831*4882a593Smuzhiyun 
1832*4882a593Smuzhiyun 		/* FIXME: port over the pci_device_failed code and use it
1833*4882a593Smuzhiyun 		   here */
1834*4882a593Smuzhiyun 	}
1835*4882a593Smuzhiyun 
1836*4882a593Smuzhiyun 	if (status & ISR_SRCI) {
1837*4882a593Smuzhiyun 		struct mac_regs __iomem *regs = vptr->mac_regs;
1838*4882a593Smuzhiyun 		int linked;
1839*4882a593Smuzhiyun 
1840*4882a593Smuzhiyun 		if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1841*4882a593Smuzhiyun 			vptr->mii_status = check_connection_type(regs);
1842*4882a593Smuzhiyun 
1843*4882a593Smuzhiyun 			/*
1844*4882a593Smuzhiyun 			 *	If it is a 3119, disable frame bursting in
1845*4882a593Smuzhiyun 			 *	halfduplex mode and enable it in fullduplex
1846*4882a593Smuzhiyun 			 *	 mode
1847*4882a593Smuzhiyun 			 */
1848*4882a593Smuzhiyun 			if (vptr->rev_id < REV_ID_VT3216_A0) {
1849*4882a593Smuzhiyun 				if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1850*4882a593Smuzhiyun 					BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
1851*4882a593Smuzhiyun 				else
1852*4882a593Smuzhiyun 					BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
1853*4882a593Smuzhiyun 			}
1854*4882a593Smuzhiyun 			/*
1855*4882a593Smuzhiyun 			 *	Only enable CD heart beat counter in 10HD mode
1856*4882a593Smuzhiyun 			 */
1857*4882a593Smuzhiyun 			if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
1858*4882a593Smuzhiyun 				BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
1859*4882a593Smuzhiyun 			else
1860*4882a593Smuzhiyun 				BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
1861*4882a593Smuzhiyun 
1862*4882a593Smuzhiyun 			setup_queue_timers(vptr);
1863*4882a593Smuzhiyun 		}
1864*4882a593Smuzhiyun 		/*
1865*4882a593Smuzhiyun 		 *	Get link status from PHYSR0
1866*4882a593Smuzhiyun 		 */
1867*4882a593Smuzhiyun 		linked = readb(&regs->PHYSR0) & PHYSR0_LINKGD;
1868*4882a593Smuzhiyun 
1869*4882a593Smuzhiyun 		if (linked) {
1870*4882a593Smuzhiyun 			vptr->mii_status &= ~VELOCITY_LINK_FAIL;
1871*4882a593Smuzhiyun 			netif_carrier_on(vptr->netdev);
1872*4882a593Smuzhiyun 		} else {
1873*4882a593Smuzhiyun 			vptr->mii_status |= VELOCITY_LINK_FAIL;
1874*4882a593Smuzhiyun 			netif_carrier_off(vptr->netdev);
1875*4882a593Smuzhiyun 		}
1876*4882a593Smuzhiyun 
1877*4882a593Smuzhiyun 		velocity_print_link_status(vptr);
1878*4882a593Smuzhiyun 		enable_flow_control_ability(vptr);
1879*4882a593Smuzhiyun 
1880*4882a593Smuzhiyun 		/*
1881*4882a593Smuzhiyun 		 *	Re-enable auto-polling because SRCI will disable
1882*4882a593Smuzhiyun 		 *	auto-polling
1883*4882a593Smuzhiyun 		 */
1884*4882a593Smuzhiyun 
1885*4882a593Smuzhiyun 		enable_mii_autopoll(regs);
1886*4882a593Smuzhiyun 
1887*4882a593Smuzhiyun 		if (vptr->mii_status & VELOCITY_LINK_FAIL)
1888*4882a593Smuzhiyun 			netif_stop_queue(vptr->netdev);
1889*4882a593Smuzhiyun 		else
1890*4882a593Smuzhiyun 			netif_wake_queue(vptr->netdev);
1891*4882a593Smuzhiyun 
1892*4882a593Smuzhiyun 	}
1893*4882a593Smuzhiyun 	if (status & ISR_MIBFI)
1894*4882a593Smuzhiyun 		velocity_update_hw_mibs(vptr);
1895*4882a593Smuzhiyun 	if (status & ISR_LSTEI)
1896*4882a593Smuzhiyun 		mac_rx_queue_wake(vptr->mac_regs);
1897*4882a593Smuzhiyun }
1898*4882a593Smuzhiyun 
1899*4882a593Smuzhiyun /**
1900*4882a593Smuzhiyun  *	tx_srv		-	transmit interrupt service
1901*4882a593Smuzhiyun  *	@vptr: Velocity
1902*4882a593Smuzhiyun  *
1903*4882a593Smuzhiyun  *	Scan the queues looking for transmitted packets that
1904*4882a593Smuzhiyun  *	we can complete and clean up. Update any statistics as
1905*4882a593Smuzhiyun  *	necessary/
1906*4882a593Smuzhiyun  */
velocity_tx_srv(struct velocity_info * vptr)1907*4882a593Smuzhiyun static int velocity_tx_srv(struct velocity_info *vptr)
1908*4882a593Smuzhiyun {
1909*4882a593Smuzhiyun 	struct tx_desc *td;
1910*4882a593Smuzhiyun 	int qnum;
1911*4882a593Smuzhiyun 	int full = 0;
1912*4882a593Smuzhiyun 	int idx;
1913*4882a593Smuzhiyun 	int works = 0;
1914*4882a593Smuzhiyun 	struct velocity_td_info *tdinfo;
1915*4882a593Smuzhiyun 	struct net_device_stats *stats = &vptr->netdev->stats;
1916*4882a593Smuzhiyun 
1917*4882a593Smuzhiyun 	for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
1918*4882a593Smuzhiyun 		for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
1919*4882a593Smuzhiyun 			idx = (idx + 1) % vptr->options.numtx) {
1920*4882a593Smuzhiyun 
1921*4882a593Smuzhiyun 			/*
1922*4882a593Smuzhiyun 			 *	Get Tx Descriptor
1923*4882a593Smuzhiyun 			 */
1924*4882a593Smuzhiyun 			td = &(vptr->tx.rings[qnum][idx]);
1925*4882a593Smuzhiyun 			tdinfo = &(vptr->tx.infos[qnum][idx]);
1926*4882a593Smuzhiyun 
1927*4882a593Smuzhiyun 			if (td->tdesc0.len & OWNED_BY_NIC)
1928*4882a593Smuzhiyun 				break;
1929*4882a593Smuzhiyun 
1930*4882a593Smuzhiyun 			if ((works++ > 15))
1931*4882a593Smuzhiyun 				break;
1932*4882a593Smuzhiyun 
1933*4882a593Smuzhiyun 			if (td->tdesc0.TSR & TSR0_TERR) {
1934*4882a593Smuzhiyun 				stats->tx_errors++;
1935*4882a593Smuzhiyun 				stats->tx_dropped++;
1936*4882a593Smuzhiyun 				if (td->tdesc0.TSR & TSR0_CDH)
1937*4882a593Smuzhiyun 					stats->tx_heartbeat_errors++;
1938*4882a593Smuzhiyun 				if (td->tdesc0.TSR & TSR0_CRS)
1939*4882a593Smuzhiyun 					stats->tx_carrier_errors++;
1940*4882a593Smuzhiyun 				if (td->tdesc0.TSR & TSR0_ABT)
1941*4882a593Smuzhiyun 					stats->tx_aborted_errors++;
1942*4882a593Smuzhiyun 				if (td->tdesc0.TSR & TSR0_OWC)
1943*4882a593Smuzhiyun 					stats->tx_window_errors++;
1944*4882a593Smuzhiyun 			} else {
1945*4882a593Smuzhiyun 				stats->tx_packets++;
1946*4882a593Smuzhiyun 				stats->tx_bytes += tdinfo->skb->len;
1947*4882a593Smuzhiyun 			}
1948*4882a593Smuzhiyun 			velocity_free_tx_buf(vptr, tdinfo, td);
1949*4882a593Smuzhiyun 			vptr->tx.used[qnum]--;
1950*4882a593Smuzhiyun 		}
1951*4882a593Smuzhiyun 		vptr->tx.tail[qnum] = idx;
1952*4882a593Smuzhiyun 
1953*4882a593Smuzhiyun 		if (AVAIL_TD(vptr, qnum) < 1)
1954*4882a593Smuzhiyun 			full = 1;
1955*4882a593Smuzhiyun 	}
1956*4882a593Smuzhiyun 	/*
1957*4882a593Smuzhiyun 	 *	Look to see if we should kick the transmit network
1958*4882a593Smuzhiyun 	 *	layer for more work.
1959*4882a593Smuzhiyun 	 */
1960*4882a593Smuzhiyun 	if (netif_queue_stopped(vptr->netdev) && (full == 0) &&
1961*4882a593Smuzhiyun 	    (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
1962*4882a593Smuzhiyun 		netif_wake_queue(vptr->netdev);
1963*4882a593Smuzhiyun 	}
1964*4882a593Smuzhiyun 	return works;
1965*4882a593Smuzhiyun }
1966*4882a593Smuzhiyun 
1967*4882a593Smuzhiyun /**
1968*4882a593Smuzhiyun  *	velocity_rx_csum	-	checksum process
1969*4882a593Smuzhiyun  *	@rd: receive packet descriptor
1970*4882a593Smuzhiyun  *	@skb: network layer packet buffer
1971*4882a593Smuzhiyun  *
1972*4882a593Smuzhiyun  *	Process the status bits for the received packet and determine
1973*4882a593Smuzhiyun  *	if the checksum was computed and verified by the hardware
1974*4882a593Smuzhiyun  */
velocity_rx_csum(struct rx_desc * rd,struct sk_buff * skb)1975*4882a593Smuzhiyun static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1976*4882a593Smuzhiyun {
1977*4882a593Smuzhiyun 	skb_checksum_none_assert(skb);
1978*4882a593Smuzhiyun 
1979*4882a593Smuzhiyun 	if (rd->rdesc1.CSM & CSM_IPKT) {
1980*4882a593Smuzhiyun 		if (rd->rdesc1.CSM & CSM_IPOK) {
1981*4882a593Smuzhiyun 			if ((rd->rdesc1.CSM & CSM_TCPKT) ||
1982*4882a593Smuzhiyun 					(rd->rdesc1.CSM & CSM_UDPKT)) {
1983*4882a593Smuzhiyun 				if (!(rd->rdesc1.CSM & CSM_TUPOK))
1984*4882a593Smuzhiyun 					return;
1985*4882a593Smuzhiyun 			}
1986*4882a593Smuzhiyun 			skb->ip_summed = CHECKSUM_UNNECESSARY;
1987*4882a593Smuzhiyun 		}
1988*4882a593Smuzhiyun 	}
1989*4882a593Smuzhiyun }
1990*4882a593Smuzhiyun 
1991*4882a593Smuzhiyun /**
1992*4882a593Smuzhiyun  *	velocity_rx_copy	-	in place Rx copy for small packets
1993*4882a593Smuzhiyun  *	@rx_skb: network layer packet buffer candidate
1994*4882a593Smuzhiyun  *	@pkt_size: received data size
1995*4882a593Smuzhiyun  *	@vptr: velocity adapter
1996*4882a593Smuzhiyun  *
1997*4882a593Smuzhiyun  *	Replace the current skb that is scheduled for Rx processing by a
1998*4882a593Smuzhiyun  *	shorter, immediately allocated skb, if the received packet is small
1999*4882a593Smuzhiyun  *	enough. This function returns a negative value if the received
2000*4882a593Smuzhiyun  *	packet is too big or if memory is exhausted.
2001*4882a593Smuzhiyun  */
velocity_rx_copy(struct sk_buff ** rx_skb,int pkt_size,struct velocity_info * vptr)2002*4882a593Smuzhiyun static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
2003*4882a593Smuzhiyun 			    struct velocity_info *vptr)
2004*4882a593Smuzhiyun {
2005*4882a593Smuzhiyun 	int ret = -1;
2006*4882a593Smuzhiyun 	if (pkt_size < rx_copybreak) {
2007*4882a593Smuzhiyun 		struct sk_buff *new_skb;
2008*4882a593Smuzhiyun 
2009*4882a593Smuzhiyun 		new_skb = netdev_alloc_skb_ip_align(vptr->netdev, pkt_size);
2010*4882a593Smuzhiyun 		if (new_skb) {
2011*4882a593Smuzhiyun 			new_skb->ip_summed = rx_skb[0]->ip_summed;
2012*4882a593Smuzhiyun 			skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
2013*4882a593Smuzhiyun 			*rx_skb = new_skb;
2014*4882a593Smuzhiyun 			ret = 0;
2015*4882a593Smuzhiyun 		}
2016*4882a593Smuzhiyun 
2017*4882a593Smuzhiyun 	}
2018*4882a593Smuzhiyun 	return ret;
2019*4882a593Smuzhiyun }
2020*4882a593Smuzhiyun 
2021*4882a593Smuzhiyun /**
2022*4882a593Smuzhiyun  *	velocity_iph_realign	-	IP header alignment
2023*4882a593Smuzhiyun  *	@vptr: velocity we are handling
2024*4882a593Smuzhiyun  *	@skb: network layer packet buffer
2025*4882a593Smuzhiyun  *	@pkt_size: received data size
2026*4882a593Smuzhiyun  *
2027*4882a593Smuzhiyun  *	Align IP header on a 2 bytes boundary. This behavior can be
2028*4882a593Smuzhiyun  *	configured by the user.
2029*4882a593Smuzhiyun  */
velocity_iph_realign(struct velocity_info * vptr,struct sk_buff * skb,int pkt_size)2030*4882a593Smuzhiyun static inline void velocity_iph_realign(struct velocity_info *vptr,
2031*4882a593Smuzhiyun 					struct sk_buff *skb, int pkt_size)
2032*4882a593Smuzhiyun {
2033*4882a593Smuzhiyun 	if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
2034*4882a593Smuzhiyun 		memmove(skb->data + 2, skb->data, pkt_size);
2035*4882a593Smuzhiyun 		skb_reserve(skb, 2);
2036*4882a593Smuzhiyun 	}
2037*4882a593Smuzhiyun }
2038*4882a593Smuzhiyun 
2039*4882a593Smuzhiyun /**
2040*4882a593Smuzhiyun  *	velocity_receive_frame	-	received packet processor
2041*4882a593Smuzhiyun  *	@vptr: velocity we are handling
2042*4882a593Smuzhiyun  *	@idx: ring index
2043*4882a593Smuzhiyun  *
2044*4882a593Smuzhiyun  *	A packet has arrived. We process the packet and if appropriate
2045*4882a593Smuzhiyun  *	pass the frame up the network stack
2046*4882a593Smuzhiyun  */
velocity_receive_frame(struct velocity_info * vptr,int idx)2047*4882a593Smuzhiyun static int velocity_receive_frame(struct velocity_info *vptr, int idx)
2048*4882a593Smuzhiyun {
2049*4882a593Smuzhiyun 	struct net_device_stats *stats = &vptr->netdev->stats;
2050*4882a593Smuzhiyun 	struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
2051*4882a593Smuzhiyun 	struct rx_desc *rd = &(vptr->rx.ring[idx]);
2052*4882a593Smuzhiyun 	int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
2053*4882a593Smuzhiyun 	struct sk_buff *skb;
2054*4882a593Smuzhiyun 
2055*4882a593Smuzhiyun 	if (unlikely(rd->rdesc0.RSR & (RSR_STP | RSR_EDP | RSR_RL))) {
2056*4882a593Smuzhiyun 		if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP))
2057*4882a593Smuzhiyun 			netdev_err(vptr->netdev, "received frame spans multiple RDs\n");
2058*4882a593Smuzhiyun 		stats->rx_length_errors++;
2059*4882a593Smuzhiyun 		return -EINVAL;
2060*4882a593Smuzhiyun 	}
2061*4882a593Smuzhiyun 
2062*4882a593Smuzhiyun 	if (rd->rdesc0.RSR & RSR_MAR)
2063*4882a593Smuzhiyun 		stats->multicast++;
2064*4882a593Smuzhiyun 
2065*4882a593Smuzhiyun 	skb = rd_info->skb;
2066*4882a593Smuzhiyun 
2067*4882a593Smuzhiyun 	dma_sync_single_for_cpu(vptr->dev, rd_info->skb_dma,
2068*4882a593Smuzhiyun 				    vptr->rx.buf_sz, DMA_FROM_DEVICE);
2069*4882a593Smuzhiyun 
2070*4882a593Smuzhiyun 	velocity_rx_csum(rd, skb);
2071*4882a593Smuzhiyun 
2072*4882a593Smuzhiyun 	if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
2073*4882a593Smuzhiyun 		velocity_iph_realign(vptr, skb, pkt_len);
2074*4882a593Smuzhiyun 		rd_info->skb = NULL;
2075*4882a593Smuzhiyun 		dma_unmap_single(vptr->dev, rd_info->skb_dma, vptr->rx.buf_sz,
2076*4882a593Smuzhiyun 				 DMA_FROM_DEVICE);
2077*4882a593Smuzhiyun 	} else {
2078*4882a593Smuzhiyun 		dma_sync_single_for_device(vptr->dev, rd_info->skb_dma,
2079*4882a593Smuzhiyun 					   vptr->rx.buf_sz, DMA_FROM_DEVICE);
2080*4882a593Smuzhiyun 	}
2081*4882a593Smuzhiyun 
2082*4882a593Smuzhiyun 	skb_put(skb, pkt_len - 4);
2083*4882a593Smuzhiyun 	skb->protocol = eth_type_trans(skb, vptr->netdev);
2084*4882a593Smuzhiyun 
2085*4882a593Smuzhiyun 	if (rd->rdesc0.RSR & RSR_DETAG) {
2086*4882a593Smuzhiyun 		u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
2087*4882a593Smuzhiyun 
2088*4882a593Smuzhiyun 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
2089*4882a593Smuzhiyun 	}
2090*4882a593Smuzhiyun 	netif_receive_skb(skb);
2091*4882a593Smuzhiyun 
2092*4882a593Smuzhiyun 	stats->rx_bytes += pkt_len;
2093*4882a593Smuzhiyun 	stats->rx_packets++;
2094*4882a593Smuzhiyun 
2095*4882a593Smuzhiyun 	return 0;
2096*4882a593Smuzhiyun }
2097*4882a593Smuzhiyun 
2098*4882a593Smuzhiyun /**
2099*4882a593Smuzhiyun  *	velocity_rx_srv		-	service RX interrupt
2100*4882a593Smuzhiyun  *	@vptr: velocity
2101*4882a593Smuzhiyun  *	@budget_left: remaining budget
2102*4882a593Smuzhiyun  *
2103*4882a593Smuzhiyun  *	Walk the receive ring of the velocity adapter and remove
2104*4882a593Smuzhiyun  *	any received packets from the receive queue. Hand the ring
2105*4882a593Smuzhiyun  *	slots back to the adapter for reuse.
2106*4882a593Smuzhiyun  */
velocity_rx_srv(struct velocity_info * vptr,int budget_left)2107*4882a593Smuzhiyun static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
2108*4882a593Smuzhiyun {
2109*4882a593Smuzhiyun 	struct net_device_stats *stats = &vptr->netdev->stats;
2110*4882a593Smuzhiyun 	int rd_curr = vptr->rx.curr;
2111*4882a593Smuzhiyun 	int works = 0;
2112*4882a593Smuzhiyun 
2113*4882a593Smuzhiyun 	while (works < budget_left) {
2114*4882a593Smuzhiyun 		struct rx_desc *rd = vptr->rx.ring + rd_curr;
2115*4882a593Smuzhiyun 
2116*4882a593Smuzhiyun 		if (!vptr->rx.info[rd_curr].skb)
2117*4882a593Smuzhiyun 			break;
2118*4882a593Smuzhiyun 
2119*4882a593Smuzhiyun 		if (rd->rdesc0.len & OWNED_BY_NIC)
2120*4882a593Smuzhiyun 			break;
2121*4882a593Smuzhiyun 
2122*4882a593Smuzhiyun 		rmb();
2123*4882a593Smuzhiyun 
2124*4882a593Smuzhiyun 		/*
2125*4882a593Smuzhiyun 		 *	Don't drop CE or RL error frame although RXOK is off
2126*4882a593Smuzhiyun 		 */
2127*4882a593Smuzhiyun 		if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
2128*4882a593Smuzhiyun 			if (velocity_receive_frame(vptr, rd_curr) < 0)
2129*4882a593Smuzhiyun 				stats->rx_dropped++;
2130*4882a593Smuzhiyun 		} else {
2131*4882a593Smuzhiyun 			if (rd->rdesc0.RSR & RSR_CRC)
2132*4882a593Smuzhiyun 				stats->rx_crc_errors++;
2133*4882a593Smuzhiyun 			if (rd->rdesc0.RSR & RSR_FAE)
2134*4882a593Smuzhiyun 				stats->rx_frame_errors++;
2135*4882a593Smuzhiyun 
2136*4882a593Smuzhiyun 			stats->rx_dropped++;
2137*4882a593Smuzhiyun 		}
2138*4882a593Smuzhiyun 
2139*4882a593Smuzhiyun 		rd->size |= RX_INTEN;
2140*4882a593Smuzhiyun 
2141*4882a593Smuzhiyun 		rd_curr++;
2142*4882a593Smuzhiyun 		if (rd_curr >= vptr->options.numrx)
2143*4882a593Smuzhiyun 			rd_curr = 0;
2144*4882a593Smuzhiyun 		works++;
2145*4882a593Smuzhiyun 	}
2146*4882a593Smuzhiyun 
2147*4882a593Smuzhiyun 	vptr->rx.curr = rd_curr;
2148*4882a593Smuzhiyun 
2149*4882a593Smuzhiyun 	if ((works > 0) && (velocity_rx_refill(vptr) > 0))
2150*4882a593Smuzhiyun 		velocity_give_many_rx_descs(vptr);
2151*4882a593Smuzhiyun 
2152*4882a593Smuzhiyun 	VAR_USED(stats);
2153*4882a593Smuzhiyun 	return works;
2154*4882a593Smuzhiyun }
2155*4882a593Smuzhiyun 
velocity_poll(struct napi_struct * napi,int budget)2156*4882a593Smuzhiyun static int velocity_poll(struct napi_struct *napi, int budget)
2157*4882a593Smuzhiyun {
2158*4882a593Smuzhiyun 	struct velocity_info *vptr = container_of(napi,
2159*4882a593Smuzhiyun 			struct velocity_info, napi);
2160*4882a593Smuzhiyun 	unsigned int rx_done;
2161*4882a593Smuzhiyun 	unsigned long flags;
2162*4882a593Smuzhiyun 
2163*4882a593Smuzhiyun 	/*
2164*4882a593Smuzhiyun 	 * Do rx and tx twice for performance (taken from the VIA
2165*4882a593Smuzhiyun 	 * out-of-tree driver).
2166*4882a593Smuzhiyun 	 */
2167*4882a593Smuzhiyun 	rx_done = velocity_rx_srv(vptr, budget);
2168*4882a593Smuzhiyun 	spin_lock_irqsave(&vptr->lock, flags);
2169*4882a593Smuzhiyun 	velocity_tx_srv(vptr);
2170*4882a593Smuzhiyun 	/* If budget not fully consumed, exit the polling mode */
2171*4882a593Smuzhiyun 	if (rx_done < budget) {
2172*4882a593Smuzhiyun 		napi_complete_done(napi, rx_done);
2173*4882a593Smuzhiyun 		mac_enable_int(vptr->mac_regs);
2174*4882a593Smuzhiyun 	}
2175*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vptr->lock, flags);
2176*4882a593Smuzhiyun 
2177*4882a593Smuzhiyun 	return rx_done;
2178*4882a593Smuzhiyun }
2179*4882a593Smuzhiyun 
2180*4882a593Smuzhiyun /**
2181*4882a593Smuzhiyun  *	velocity_intr		-	interrupt callback
2182*4882a593Smuzhiyun  *	@irq: interrupt number
2183*4882a593Smuzhiyun  *	@dev_instance: interrupting device
2184*4882a593Smuzhiyun  *
2185*4882a593Smuzhiyun  *	Called whenever an interrupt is generated by the velocity
2186*4882a593Smuzhiyun  *	adapter IRQ line. We may not be the source of the interrupt
2187*4882a593Smuzhiyun  *	and need to identify initially if we are, and if not exit as
2188*4882a593Smuzhiyun  *	efficiently as possible.
2189*4882a593Smuzhiyun  */
velocity_intr(int irq,void * dev_instance)2190*4882a593Smuzhiyun static irqreturn_t velocity_intr(int irq, void *dev_instance)
2191*4882a593Smuzhiyun {
2192*4882a593Smuzhiyun 	struct net_device *dev = dev_instance;
2193*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2194*4882a593Smuzhiyun 	u32 isr_status;
2195*4882a593Smuzhiyun 
2196*4882a593Smuzhiyun 	spin_lock(&vptr->lock);
2197*4882a593Smuzhiyun 	isr_status = mac_read_isr(vptr->mac_regs);
2198*4882a593Smuzhiyun 
2199*4882a593Smuzhiyun 	/* Not us ? */
2200*4882a593Smuzhiyun 	if (isr_status == 0) {
2201*4882a593Smuzhiyun 		spin_unlock(&vptr->lock);
2202*4882a593Smuzhiyun 		return IRQ_NONE;
2203*4882a593Smuzhiyun 	}
2204*4882a593Smuzhiyun 
2205*4882a593Smuzhiyun 	/* Ack the interrupt */
2206*4882a593Smuzhiyun 	mac_write_isr(vptr->mac_regs, isr_status);
2207*4882a593Smuzhiyun 
2208*4882a593Smuzhiyun 	if (likely(napi_schedule_prep(&vptr->napi))) {
2209*4882a593Smuzhiyun 		mac_disable_int(vptr->mac_regs);
2210*4882a593Smuzhiyun 		__napi_schedule(&vptr->napi);
2211*4882a593Smuzhiyun 	}
2212*4882a593Smuzhiyun 
2213*4882a593Smuzhiyun 	if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
2214*4882a593Smuzhiyun 		velocity_error(vptr, isr_status);
2215*4882a593Smuzhiyun 
2216*4882a593Smuzhiyun 	spin_unlock(&vptr->lock);
2217*4882a593Smuzhiyun 
2218*4882a593Smuzhiyun 	return IRQ_HANDLED;
2219*4882a593Smuzhiyun }
2220*4882a593Smuzhiyun 
2221*4882a593Smuzhiyun /**
2222*4882a593Smuzhiyun  *	velocity_open		-	interface activation callback
2223*4882a593Smuzhiyun  *	@dev: network layer device to open
2224*4882a593Smuzhiyun  *
2225*4882a593Smuzhiyun  *	Called when the network layer brings the interface up. Returns
2226*4882a593Smuzhiyun  *	a negative posix error code on failure, or zero on success.
2227*4882a593Smuzhiyun  *
2228*4882a593Smuzhiyun  *	All the ring allocation and set up is done on open for this
2229*4882a593Smuzhiyun  *	adapter to minimise memory usage when inactive
2230*4882a593Smuzhiyun  */
velocity_open(struct net_device * dev)2231*4882a593Smuzhiyun static int velocity_open(struct net_device *dev)
2232*4882a593Smuzhiyun {
2233*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2234*4882a593Smuzhiyun 	int ret;
2235*4882a593Smuzhiyun 
2236*4882a593Smuzhiyun 	ret = velocity_init_rings(vptr, dev->mtu);
2237*4882a593Smuzhiyun 	if (ret < 0)
2238*4882a593Smuzhiyun 		goto out;
2239*4882a593Smuzhiyun 
2240*4882a593Smuzhiyun 	/* Ensure chip is running */
2241*4882a593Smuzhiyun 	velocity_set_power_state(vptr, PCI_D0);
2242*4882a593Smuzhiyun 
2243*4882a593Smuzhiyun 	velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2244*4882a593Smuzhiyun 
2245*4882a593Smuzhiyun 	ret = request_irq(dev->irq, velocity_intr, IRQF_SHARED,
2246*4882a593Smuzhiyun 			  dev->name, dev);
2247*4882a593Smuzhiyun 	if (ret < 0) {
2248*4882a593Smuzhiyun 		/* Power down the chip */
2249*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D3hot);
2250*4882a593Smuzhiyun 		velocity_free_rings(vptr);
2251*4882a593Smuzhiyun 		goto out;
2252*4882a593Smuzhiyun 	}
2253*4882a593Smuzhiyun 
2254*4882a593Smuzhiyun 	velocity_give_many_rx_descs(vptr);
2255*4882a593Smuzhiyun 
2256*4882a593Smuzhiyun 	mac_enable_int(vptr->mac_regs);
2257*4882a593Smuzhiyun 	netif_start_queue(dev);
2258*4882a593Smuzhiyun 	napi_enable(&vptr->napi);
2259*4882a593Smuzhiyun 	vptr->flags |= VELOCITY_FLAGS_OPENED;
2260*4882a593Smuzhiyun out:
2261*4882a593Smuzhiyun 	return ret;
2262*4882a593Smuzhiyun }
2263*4882a593Smuzhiyun 
2264*4882a593Smuzhiyun /**
2265*4882a593Smuzhiyun  *	velocity_shutdown	-	shut down the chip
2266*4882a593Smuzhiyun  *	@vptr: velocity to deactivate
2267*4882a593Smuzhiyun  *
2268*4882a593Smuzhiyun  *	Shuts down the internal operations of the velocity and
2269*4882a593Smuzhiyun  *	disables interrupts, autopolling, transmit and receive
2270*4882a593Smuzhiyun  */
velocity_shutdown(struct velocity_info * vptr)2271*4882a593Smuzhiyun static void velocity_shutdown(struct velocity_info *vptr)
2272*4882a593Smuzhiyun {
2273*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
2274*4882a593Smuzhiyun 	mac_disable_int(regs);
2275*4882a593Smuzhiyun 	writel(CR0_STOP, &regs->CR0Set);
2276*4882a593Smuzhiyun 	writew(0xFFFF, &regs->TDCSRClr);
2277*4882a593Smuzhiyun 	writeb(0xFF, &regs->RDCSRClr);
2278*4882a593Smuzhiyun 	safe_disable_mii_autopoll(regs);
2279*4882a593Smuzhiyun 	mac_clear_isr(regs);
2280*4882a593Smuzhiyun }
2281*4882a593Smuzhiyun 
2282*4882a593Smuzhiyun /**
2283*4882a593Smuzhiyun  *	velocity_change_mtu	-	MTU change callback
2284*4882a593Smuzhiyun  *	@dev: network device
2285*4882a593Smuzhiyun  *	@new_mtu: desired MTU
2286*4882a593Smuzhiyun  *
2287*4882a593Smuzhiyun  *	Handle requests from the networking layer for MTU change on
2288*4882a593Smuzhiyun  *	this interface. It gets called on a change by the network layer.
2289*4882a593Smuzhiyun  *	Return zero for success or negative posix error code.
2290*4882a593Smuzhiyun  */
velocity_change_mtu(struct net_device * dev,int new_mtu)2291*4882a593Smuzhiyun static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2292*4882a593Smuzhiyun {
2293*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2294*4882a593Smuzhiyun 	int ret = 0;
2295*4882a593Smuzhiyun 
2296*4882a593Smuzhiyun 	if (!netif_running(dev)) {
2297*4882a593Smuzhiyun 		dev->mtu = new_mtu;
2298*4882a593Smuzhiyun 		goto out_0;
2299*4882a593Smuzhiyun 	}
2300*4882a593Smuzhiyun 
2301*4882a593Smuzhiyun 	if (dev->mtu != new_mtu) {
2302*4882a593Smuzhiyun 		struct velocity_info *tmp_vptr;
2303*4882a593Smuzhiyun 		unsigned long flags;
2304*4882a593Smuzhiyun 		struct rx_info rx;
2305*4882a593Smuzhiyun 		struct tx_info tx;
2306*4882a593Smuzhiyun 
2307*4882a593Smuzhiyun 		tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
2308*4882a593Smuzhiyun 		if (!tmp_vptr) {
2309*4882a593Smuzhiyun 			ret = -ENOMEM;
2310*4882a593Smuzhiyun 			goto out_0;
2311*4882a593Smuzhiyun 		}
2312*4882a593Smuzhiyun 
2313*4882a593Smuzhiyun 		tmp_vptr->netdev = dev;
2314*4882a593Smuzhiyun 		tmp_vptr->pdev = vptr->pdev;
2315*4882a593Smuzhiyun 		tmp_vptr->dev = vptr->dev;
2316*4882a593Smuzhiyun 		tmp_vptr->options = vptr->options;
2317*4882a593Smuzhiyun 		tmp_vptr->tx.numq = vptr->tx.numq;
2318*4882a593Smuzhiyun 
2319*4882a593Smuzhiyun 		ret = velocity_init_rings(tmp_vptr, new_mtu);
2320*4882a593Smuzhiyun 		if (ret < 0)
2321*4882a593Smuzhiyun 			goto out_free_tmp_vptr_1;
2322*4882a593Smuzhiyun 
2323*4882a593Smuzhiyun 		napi_disable(&vptr->napi);
2324*4882a593Smuzhiyun 
2325*4882a593Smuzhiyun 		spin_lock_irqsave(&vptr->lock, flags);
2326*4882a593Smuzhiyun 
2327*4882a593Smuzhiyun 		netif_stop_queue(dev);
2328*4882a593Smuzhiyun 		velocity_shutdown(vptr);
2329*4882a593Smuzhiyun 
2330*4882a593Smuzhiyun 		rx = vptr->rx;
2331*4882a593Smuzhiyun 		tx = vptr->tx;
2332*4882a593Smuzhiyun 
2333*4882a593Smuzhiyun 		vptr->rx = tmp_vptr->rx;
2334*4882a593Smuzhiyun 		vptr->tx = tmp_vptr->tx;
2335*4882a593Smuzhiyun 
2336*4882a593Smuzhiyun 		tmp_vptr->rx = rx;
2337*4882a593Smuzhiyun 		tmp_vptr->tx = tx;
2338*4882a593Smuzhiyun 
2339*4882a593Smuzhiyun 		dev->mtu = new_mtu;
2340*4882a593Smuzhiyun 
2341*4882a593Smuzhiyun 		velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2342*4882a593Smuzhiyun 
2343*4882a593Smuzhiyun 		velocity_give_many_rx_descs(vptr);
2344*4882a593Smuzhiyun 
2345*4882a593Smuzhiyun 		napi_enable(&vptr->napi);
2346*4882a593Smuzhiyun 
2347*4882a593Smuzhiyun 		mac_enable_int(vptr->mac_regs);
2348*4882a593Smuzhiyun 		netif_start_queue(dev);
2349*4882a593Smuzhiyun 
2350*4882a593Smuzhiyun 		spin_unlock_irqrestore(&vptr->lock, flags);
2351*4882a593Smuzhiyun 
2352*4882a593Smuzhiyun 		velocity_free_rings(tmp_vptr);
2353*4882a593Smuzhiyun 
2354*4882a593Smuzhiyun out_free_tmp_vptr_1:
2355*4882a593Smuzhiyun 		kfree(tmp_vptr);
2356*4882a593Smuzhiyun 	}
2357*4882a593Smuzhiyun out_0:
2358*4882a593Smuzhiyun 	return ret;
2359*4882a593Smuzhiyun }
2360*4882a593Smuzhiyun 
2361*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
2362*4882a593Smuzhiyun /**
2363*4882a593Smuzhiyun  *  velocity_poll_controller		-	Velocity Poll controller function
2364*4882a593Smuzhiyun  *  @dev: network device
2365*4882a593Smuzhiyun  *
2366*4882a593Smuzhiyun  *
2367*4882a593Smuzhiyun  *  Used by NETCONSOLE and other diagnostic tools to allow network I/P
2368*4882a593Smuzhiyun  *  with interrupts disabled.
2369*4882a593Smuzhiyun  */
velocity_poll_controller(struct net_device * dev)2370*4882a593Smuzhiyun static void velocity_poll_controller(struct net_device *dev)
2371*4882a593Smuzhiyun {
2372*4882a593Smuzhiyun 	disable_irq(dev->irq);
2373*4882a593Smuzhiyun 	velocity_intr(dev->irq, dev);
2374*4882a593Smuzhiyun 	enable_irq(dev->irq);
2375*4882a593Smuzhiyun }
2376*4882a593Smuzhiyun #endif
2377*4882a593Smuzhiyun 
2378*4882a593Smuzhiyun /**
2379*4882a593Smuzhiyun  *	velocity_mii_ioctl		-	MII ioctl handler
2380*4882a593Smuzhiyun  *	@dev: network device
2381*4882a593Smuzhiyun  *	@ifr: the ifreq block for the ioctl
2382*4882a593Smuzhiyun  *	@cmd: the command
2383*4882a593Smuzhiyun  *
2384*4882a593Smuzhiyun  *	Process MII requests made via ioctl from the network layer. These
2385*4882a593Smuzhiyun  *	are used by tools like kudzu to interrogate the link state of the
2386*4882a593Smuzhiyun  *	hardware
2387*4882a593Smuzhiyun  */
velocity_mii_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2388*4882a593Smuzhiyun static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2389*4882a593Smuzhiyun {
2390*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2391*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
2392*4882a593Smuzhiyun 	unsigned long flags;
2393*4882a593Smuzhiyun 	struct mii_ioctl_data *miidata = if_mii(ifr);
2394*4882a593Smuzhiyun 	int err;
2395*4882a593Smuzhiyun 
2396*4882a593Smuzhiyun 	switch (cmd) {
2397*4882a593Smuzhiyun 	case SIOCGMIIPHY:
2398*4882a593Smuzhiyun 		miidata->phy_id = readb(&regs->MIIADR) & 0x1f;
2399*4882a593Smuzhiyun 		break;
2400*4882a593Smuzhiyun 	case SIOCGMIIREG:
2401*4882a593Smuzhiyun 		if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
2402*4882a593Smuzhiyun 			return -ETIMEDOUT;
2403*4882a593Smuzhiyun 		break;
2404*4882a593Smuzhiyun 	case SIOCSMIIREG:
2405*4882a593Smuzhiyun 		spin_lock_irqsave(&vptr->lock, flags);
2406*4882a593Smuzhiyun 		err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
2407*4882a593Smuzhiyun 		spin_unlock_irqrestore(&vptr->lock, flags);
2408*4882a593Smuzhiyun 		check_connection_type(vptr->mac_regs);
2409*4882a593Smuzhiyun 		if (err)
2410*4882a593Smuzhiyun 			return err;
2411*4882a593Smuzhiyun 		break;
2412*4882a593Smuzhiyun 	default:
2413*4882a593Smuzhiyun 		return -EOPNOTSUPP;
2414*4882a593Smuzhiyun 	}
2415*4882a593Smuzhiyun 	return 0;
2416*4882a593Smuzhiyun }
2417*4882a593Smuzhiyun 
2418*4882a593Smuzhiyun /**
2419*4882a593Smuzhiyun  *	velocity_ioctl		-	ioctl entry point
2420*4882a593Smuzhiyun  *	@dev: network device
2421*4882a593Smuzhiyun  *	@rq: interface request ioctl
2422*4882a593Smuzhiyun  *	@cmd: command code
2423*4882a593Smuzhiyun  *
2424*4882a593Smuzhiyun  *	Called when the user issues an ioctl request to the network
2425*4882a593Smuzhiyun  *	device in question. The velocity interface supports MII.
2426*4882a593Smuzhiyun  */
velocity_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)2427*4882a593Smuzhiyun static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2428*4882a593Smuzhiyun {
2429*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2430*4882a593Smuzhiyun 	int ret;
2431*4882a593Smuzhiyun 
2432*4882a593Smuzhiyun 	/* If we are asked for information and the device is power
2433*4882a593Smuzhiyun 	   saving then we need to bring the device back up to talk to it */
2434*4882a593Smuzhiyun 
2435*4882a593Smuzhiyun 	if (!netif_running(dev))
2436*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D0);
2437*4882a593Smuzhiyun 
2438*4882a593Smuzhiyun 	switch (cmd) {
2439*4882a593Smuzhiyun 	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
2440*4882a593Smuzhiyun 	case SIOCGMIIREG:	/* Read MII PHY register. */
2441*4882a593Smuzhiyun 	case SIOCSMIIREG:	/* Write to MII PHY register. */
2442*4882a593Smuzhiyun 		ret = velocity_mii_ioctl(dev, rq, cmd);
2443*4882a593Smuzhiyun 		break;
2444*4882a593Smuzhiyun 
2445*4882a593Smuzhiyun 	default:
2446*4882a593Smuzhiyun 		ret = -EOPNOTSUPP;
2447*4882a593Smuzhiyun 	}
2448*4882a593Smuzhiyun 	if (!netif_running(dev))
2449*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D3hot);
2450*4882a593Smuzhiyun 
2451*4882a593Smuzhiyun 
2452*4882a593Smuzhiyun 	return ret;
2453*4882a593Smuzhiyun }
2454*4882a593Smuzhiyun 
2455*4882a593Smuzhiyun /**
2456*4882a593Smuzhiyun  *	velocity_get_status	-	statistics callback
2457*4882a593Smuzhiyun  *	@dev: network device
2458*4882a593Smuzhiyun  *
2459*4882a593Smuzhiyun  *	Callback from the network layer to allow driver statistics
2460*4882a593Smuzhiyun  *	to be resynchronized with hardware collected state. In the
2461*4882a593Smuzhiyun  *	case of the velocity we need to pull the MIB counters from
2462*4882a593Smuzhiyun  *	the hardware into the counters before letting the network
2463*4882a593Smuzhiyun  *	layer display them.
2464*4882a593Smuzhiyun  */
velocity_get_stats(struct net_device * dev)2465*4882a593Smuzhiyun static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2466*4882a593Smuzhiyun {
2467*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2468*4882a593Smuzhiyun 
2469*4882a593Smuzhiyun 	/* If the hardware is down, don't touch MII */
2470*4882a593Smuzhiyun 	if (!netif_running(dev))
2471*4882a593Smuzhiyun 		return &dev->stats;
2472*4882a593Smuzhiyun 
2473*4882a593Smuzhiyun 	spin_lock_irq(&vptr->lock);
2474*4882a593Smuzhiyun 	velocity_update_hw_mibs(vptr);
2475*4882a593Smuzhiyun 	spin_unlock_irq(&vptr->lock);
2476*4882a593Smuzhiyun 
2477*4882a593Smuzhiyun 	dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
2478*4882a593Smuzhiyun 	dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
2479*4882a593Smuzhiyun 	dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
2480*4882a593Smuzhiyun 
2481*4882a593Smuzhiyun //  unsigned long   rx_dropped;     /* no space in linux buffers    */
2482*4882a593Smuzhiyun 	dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
2483*4882a593Smuzhiyun 	/* detailed rx_errors: */
2484*4882a593Smuzhiyun //  unsigned long   rx_length_errors;
2485*4882a593Smuzhiyun //  unsigned long   rx_over_errors;     /* receiver ring buff overflow  */
2486*4882a593Smuzhiyun 	dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
2487*4882a593Smuzhiyun //  unsigned long   rx_frame_errors;    /* recv'd frame alignment error */
2488*4882a593Smuzhiyun //  unsigned long   rx_fifo_errors;     /* recv'r fifo overrun      */
2489*4882a593Smuzhiyun //  unsigned long   rx_missed_errors;   /* receiver missed packet   */
2490*4882a593Smuzhiyun 
2491*4882a593Smuzhiyun 	/* detailed tx_errors */
2492*4882a593Smuzhiyun //  unsigned long   tx_fifo_errors;
2493*4882a593Smuzhiyun 
2494*4882a593Smuzhiyun 	return &dev->stats;
2495*4882a593Smuzhiyun }
2496*4882a593Smuzhiyun 
2497*4882a593Smuzhiyun /**
2498*4882a593Smuzhiyun  *	velocity_close		-	close adapter callback
2499*4882a593Smuzhiyun  *	@dev: network device
2500*4882a593Smuzhiyun  *
2501*4882a593Smuzhiyun  *	Callback from the network layer when the velocity is being
2502*4882a593Smuzhiyun  *	deactivated by the network layer
2503*4882a593Smuzhiyun  */
velocity_close(struct net_device * dev)2504*4882a593Smuzhiyun static int velocity_close(struct net_device *dev)
2505*4882a593Smuzhiyun {
2506*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2507*4882a593Smuzhiyun 
2508*4882a593Smuzhiyun 	napi_disable(&vptr->napi);
2509*4882a593Smuzhiyun 	netif_stop_queue(dev);
2510*4882a593Smuzhiyun 	velocity_shutdown(vptr);
2511*4882a593Smuzhiyun 
2512*4882a593Smuzhiyun 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
2513*4882a593Smuzhiyun 		velocity_get_ip(vptr);
2514*4882a593Smuzhiyun 
2515*4882a593Smuzhiyun 	free_irq(dev->irq, dev);
2516*4882a593Smuzhiyun 
2517*4882a593Smuzhiyun 	velocity_free_rings(vptr);
2518*4882a593Smuzhiyun 
2519*4882a593Smuzhiyun 	vptr->flags &= (~VELOCITY_FLAGS_OPENED);
2520*4882a593Smuzhiyun 	return 0;
2521*4882a593Smuzhiyun }
2522*4882a593Smuzhiyun 
2523*4882a593Smuzhiyun /**
2524*4882a593Smuzhiyun  *	velocity_xmit		-	transmit packet callback
2525*4882a593Smuzhiyun  *	@skb: buffer to transmit
2526*4882a593Smuzhiyun  *	@dev: network device
2527*4882a593Smuzhiyun  *
2528*4882a593Smuzhiyun  *	Called by the networ layer to request a packet is queued to
2529*4882a593Smuzhiyun  *	the velocity. Returns zero on success.
2530*4882a593Smuzhiyun  */
velocity_xmit(struct sk_buff * skb,struct net_device * dev)2531*4882a593Smuzhiyun static netdev_tx_t velocity_xmit(struct sk_buff *skb,
2532*4882a593Smuzhiyun 				 struct net_device *dev)
2533*4882a593Smuzhiyun {
2534*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2535*4882a593Smuzhiyun 	int qnum = 0;
2536*4882a593Smuzhiyun 	struct tx_desc *td_ptr;
2537*4882a593Smuzhiyun 	struct velocity_td_info *tdinfo;
2538*4882a593Smuzhiyun 	unsigned long flags;
2539*4882a593Smuzhiyun 	int pktlen;
2540*4882a593Smuzhiyun 	int index, prev;
2541*4882a593Smuzhiyun 	int i = 0;
2542*4882a593Smuzhiyun 
2543*4882a593Smuzhiyun 	if (skb_padto(skb, ETH_ZLEN))
2544*4882a593Smuzhiyun 		goto out;
2545*4882a593Smuzhiyun 
2546*4882a593Smuzhiyun 	/* The hardware can handle at most 7 memory segments, so merge
2547*4882a593Smuzhiyun 	 * the skb if there are more */
2548*4882a593Smuzhiyun 	if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
2549*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
2550*4882a593Smuzhiyun 		return NETDEV_TX_OK;
2551*4882a593Smuzhiyun 	}
2552*4882a593Smuzhiyun 
2553*4882a593Smuzhiyun 	pktlen = skb_shinfo(skb)->nr_frags == 0 ?
2554*4882a593Smuzhiyun 			max_t(unsigned int, skb->len, ETH_ZLEN) :
2555*4882a593Smuzhiyun 				skb_headlen(skb);
2556*4882a593Smuzhiyun 
2557*4882a593Smuzhiyun 	spin_lock_irqsave(&vptr->lock, flags);
2558*4882a593Smuzhiyun 
2559*4882a593Smuzhiyun 	index = vptr->tx.curr[qnum];
2560*4882a593Smuzhiyun 	td_ptr = &(vptr->tx.rings[qnum][index]);
2561*4882a593Smuzhiyun 	tdinfo = &(vptr->tx.infos[qnum][index]);
2562*4882a593Smuzhiyun 
2563*4882a593Smuzhiyun 	td_ptr->tdesc1.TCR = TCR0_TIC;
2564*4882a593Smuzhiyun 	td_ptr->td_buf[0].size &= ~TD_QUEUE;
2565*4882a593Smuzhiyun 
2566*4882a593Smuzhiyun 	/*
2567*4882a593Smuzhiyun 	 *	Map the linear network buffer into PCI space and
2568*4882a593Smuzhiyun 	 *	add it to the transmit ring.
2569*4882a593Smuzhiyun 	 */
2570*4882a593Smuzhiyun 	tdinfo->skb = skb;
2571*4882a593Smuzhiyun 	tdinfo->skb_dma[0] = dma_map_single(vptr->dev, skb->data, pktlen,
2572*4882a593Smuzhiyun 								DMA_TO_DEVICE);
2573*4882a593Smuzhiyun 	td_ptr->tdesc0.len = cpu_to_le16(pktlen);
2574*4882a593Smuzhiyun 	td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2575*4882a593Smuzhiyun 	td_ptr->td_buf[0].pa_high = 0;
2576*4882a593Smuzhiyun 	td_ptr->td_buf[0].size = cpu_to_le16(pktlen);
2577*4882a593Smuzhiyun 
2578*4882a593Smuzhiyun 	/* Handle fragments */
2579*4882a593Smuzhiyun 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2580*4882a593Smuzhiyun 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2581*4882a593Smuzhiyun 
2582*4882a593Smuzhiyun 		tdinfo->skb_dma[i + 1] = skb_frag_dma_map(vptr->dev,
2583*4882a593Smuzhiyun 							  frag, 0,
2584*4882a593Smuzhiyun 							  skb_frag_size(frag),
2585*4882a593Smuzhiyun 							  DMA_TO_DEVICE);
2586*4882a593Smuzhiyun 
2587*4882a593Smuzhiyun 		td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
2588*4882a593Smuzhiyun 		td_ptr->td_buf[i + 1].pa_high = 0;
2589*4882a593Smuzhiyun 		td_ptr->td_buf[i + 1].size = cpu_to_le16(skb_frag_size(frag));
2590*4882a593Smuzhiyun 	}
2591*4882a593Smuzhiyun 	tdinfo->nskb_dma = i + 1;
2592*4882a593Smuzhiyun 
2593*4882a593Smuzhiyun 	td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
2594*4882a593Smuzhiyun 
2595*4882a593Smuzhiyun 	if (skb_vlan_tag_present(skb)) {
2596*4882a593Smuzhiyun 		td_ptr->tdesc1.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2597*4882a593Smuzhiyun 		td_ptr->tdesc1.TCR |= TCR0_VETAG;
2598*4882a593Smuzhiyun 	}
2599*4882a593Smuzhiyun 
2600*4882a593Smuzhiyun 	/*
2601*4882a593Smuzhiyun 	 *	Handle hardware checksum
2602*4882a593Smuzhiyun 	 */
2603*4882a593Smuzhiyun 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
2604*4882a593Smuzhiyun 		const struct iphdr *ip = ip_hdr(skb);
2605*4882a593Smuzhiyun 		if (ip->protocol == IPPROTO_TCP)
2606*4882a593Smuzhiyun 			td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2607*4882a593Smuzhiyun 		else if (ip->protocol == IPPROTO_UDP)
2608*4882a593Smuzhiyun 			td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2609*4882a593Smuzhiyun 		td_ptr->tdesc1.TCR |= TCR0_IPCK;
2610*4882a593Smuzhiyun 	}
2611*4882a593Smuzhiyun 
2612*4882a593Smuzhiyun 	prev = index - 1;
2613*4882a593Smuzhiyun 	if (prev < 0)
2614*4882a593Smuzhiyun 		prev = vptr->options.numtx - 1;
2615*4882a593Smuzhiyun 	td_ptr->tdesc0.len |= OWNED_BY_NIC;
2616*4882a593Smuzhiyun 	vptr->tx.used[qnum]++;
2617*4882a593Smuzhiyun 	vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
2618*4882a593Smuzhiyun 
2619*4882a593Smuzhiyun 	if (AVAIL_TD(vptr, qnum) < 1)
2620*4882a593Smuzhiyun 		netif_stop_queue(dev);
2621*4882a593Smuzhiyun 
2622*4882a593Smuzhiyun 	td_ptr = &(vptr->tx.rings[qnum][prev]);
2623*4882a593Smuzhiyun 	td_ptr->td_buf[0].size |= TD_QUEUE;
2624*4882a593Smuzhiyun 	mac_tx_queue_wake(vptr->mac_regs, qnum);
2625*4882a593Smuzhiyun 
2626*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vptr->lock, flags);
2627*4882a593Smuzhiyun out:
2628*4882a593Smuzhiyun 	return NETDEV_TX_OK;
2629*4882a593Smuzhiyun }
2630*4882a593Smuzhiyun 
2631*4882a593Smuzhiyun static const struct net_device_ops velocity_netdev_ops = {
2632*4882a593Smuzhiyun 	.ndo_open		= velocity_open,
2633*4882a593Smuzhiyun 	.ndo_stop		= velocity_close,
2634*4882a593Smuzhiyun 	.ndo_start_xmit		= velocity_xmit,
2635*4882a593Smuzhiyun 	.ndo_get_stats		= velocity_get_stats,
2636*4882a593Smuzhiyun 	.ndo_validate_addr	= eth_validate_addr,
2637*4882a593Smuzhiyun 	.ndo_set_mac_address	= eth_mac_addr,
2638*4882a593Smuzhiyun 	.ndo_set_rx_mode	= velocity_set_multi,
2639*4882a593Smuzhiyun 	.ndo_change_mtu		= velocity_change_mtu,
2640*4882a593Smuzhiyun 	.ndo_do_ioctl		= velocity_ioctl,
2641*4882a593Smuzhiyun 	.ndo_vlan_rx_add_vid	= velocity_vlan_rx_add_vid,
2642*4882a593Smuzhiyun 	.ndo_vlan_rx_kill_vid	= velocity_vlan_rx_kill_vid,
2643*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
2644*4882a593Smuzhiyun 	.ndo_poll_controller = velocity_poll_controller,
2645*4882a593Smuzhiyun #endif
2646*4882a593Smuzhiyun };
2647*4882a593Smuzhiyun 
2648*4882a593Smuzhiyun /**
2649*4882a593Smuzhiyun  *	velocity_init_info	-	init private data
2650*4882a593Smuzhiyun  *	@vptr: Velocity info
2651*4882a593Smuzhiyun  *	@info: Board type
2652*4882a593Smuzhiyun  *
2653*4882a593Smuzhiyun  *	Set up the initial velocity_info struct for the device that has been
2654*4882a593Smuzhiyun  *	discovered.
2655*4882a593Smuzhiyun  */
velocity_init_info(struct velocity_info * vptr,const struct velocity_info_tbl * info)2656*4882a593Smuzhiyun static void velocity_init_info(struct velocity_info *vptr,
2657*4882a593Smuzhiyun 				const struct velocity_info_tbl *info)
2658*4882a593Smuzhiyun {
2659*4882a593Smuzhiyun 	vptr->chip_id = info->chip_id;
2660*4882a593Smuzhiyun 	vptr->tx.numq = info->txqueue;
2661*4882a593Smuzhiyun 	vptr->multicast_limit = MCAM_SIZE;
2662*4882a593Smuzhiyun 	spin_lock_init(&vptr->lock);
2663*4882a593Smuzhiyun }
2664*4882a593Smuzhiyun 
2665*4882a593Smuzhiyun /**
2666*4882a593Smuzhiyun  *	velocity_get_pci_info	-	retrieve PCI info for device
2667*4882a593Smuzhiyun  *	@vptr: velocity device
2668*4882a593Smuzhiyun  *
2669*4882a593Smuzhiyun  *	Retrieve the PCI configuration space data that interests us from
2670*4882a593Smuzhiyun  *	the kernel PCI layer
2671*4882a593Smuzhiyun  */
velocity_get_pci_info(struct velocity_info * vptr)2672*4882a593Smuzhiyun static int velocity_get_pci_info(struct velocity_info *vptr)
2673*4882a593Smuzhiyun {
2674*4882a593Smuzhiyun 	struct pci_dev *pdev = vptr->pdev;
2675*4882a593Smuzhiyun 
2676*4882a593Smuzhiyun 	pci_set_master(pdev);
2677*4882a593Smuzhiyun 
2678*4882a593Smuzhiyun 	vptr->ioaddr = pci_resource_start(pdev, 0);
2679*4882a593Smuzhiyun 	vptr->memaddr = pci_resource_start(pdev, 1);
2680*4882a593Smuzhiyun 
2681*4882a593Smuzhiyun 	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2682*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2683*4882a593Smuzhiyun 			   "region #0 is not an I/O resource, aborting.\n");
2684*4882a593Smuzhiyun 		return -EINVAL;
2685*4882a593Smuzhiyun 	}
2686*4882a593Smuzhiyun 
2687*4882a593Smuzhiyun 	if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
2688*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2689*4882a593Smuzhiyun 			   "region #1 is an I/O resource, aborting.\n");
2690*4882a593Smuzhiyun 		return -EINVAL;
2691*4882a593Smuzhiyun 	}
2692*4882a593Smuzhiyun 
2693*4882a593Smuzhiyun 	if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
2694*4882a593Smuzhiyun 		dev_err(&pdev->dev, "region #1 is too small.\n");
2695*4882a593Smuzhiyun 		return -EINVAL;
2696*4882a593Smuzhiyun 	}
2697*4882a593Smuzhiyun 
2698*4882a593Smuzhiyun 	return 0;
2699*4882a593Smuzhiyun }
2700*4882a593Smuzhiyun 
2701*4882a593Smuzhiyun /**
2702*4882a593Smuzhiyun  *	velocity_get_platform_info - retrieve platform info for device
2703*4882a593Smuzhiyun  *	@vptr: velocity device
2704*4882a593Smuzhiyun  *
2705*4882a593Smuzhiyun  *	Retrieve the Platform configuration data that interests us
2706*4882a593Smuzhiyun  */
velocity_get_platform_info(struct velocity_info * vptr)2707*4882a593Smuzhiyun static int velocity_get_platform_info(struct velocity_info *vptr)
2708*4882a593Smuzhiyun {
2709*4882a593Smuzhiyun 	struct resource res;
2710*4882a593Smuzhiyun 	int ret;
2711*4882a593Smuzhiyun 
2712*4882a593Smuzhiyun 	if (of_get_property(vptr->dev->of_node, "no-eeprom", NULL))
2713*4882a593Smuzhiyun 		vptr->no_eeprom = 1;
2714*4882a593Smuzhiyun 
2715*4882a593Smuzhiyun 	ret = of_address_to_resource(vptr->dev->of_node, 0, &res);
2716*4882a593Smuzhiyun 	if (ret) {
2717*4882a593Smuzhiyun 		dev_err(vptr->dev, "unable to find memory address\n");
2718*4882a593Smuzhiyun 		return ret;
2719*4882a593Smuzhiyun 	}
2720*4882a593Smuzhiyun 
2721*4882a593Smuzhiyun 	vptr->memaddr = res.start;
2722*4882a593Smuzhiyun 
2723*4882a593Smuzhiyun 	if (resource_size(&res) < VELOCITY_IO_SIZE) {
2724*4882a593Smuzhiyun 		dev_err(vptr->dev, "memory region is too small.\n");
2725*4882a593Smuzhiyun 		return -EINVAL;
2726*4882a593Smuzhiyun 	}
2727*4882a593Smuzhiyun 
2728*4882a593Smuzhiyun 	return 0;
2729*4882a593Smuzhiyun }
2730*4882a593Smuzhiyun 
2731*4882a593Smuzhiyun /**
2732*4882a593Smuzhiyun  *	velocity_print_info	-	per driver data
2733*4882a593Smuzhiyun  *	@vptr: velocity
2734*4882a593Smuzhiyun  *
2735*4882a593Smuzhiyun  *	Print per driver data as the kernel driver finds Velocity
2736*4882a593Smuzhiyun  *	hardware
2737*4882a593Smuzhiyun  */
velocity_print_info(struct velocity_info * vptr)2738*4882a593Smuzhiyun static void velocity_print_info(struct velocity_info *vptr)
2739*4882a593Smuzhiyun {
2740*4882a593Smuzhiyun 	netdev_info(vptr->netdev, "%s - Ethernet Address: %pM\n",
2741*4882a593Smuzhiyun 		    get_chip_name(vptr->chip_id), vptr->netdev->dev_addr);
2742*4882a593Smuzhiyun }
2743*4882a593Smuzhiyun 
velocity_get_link(struct net_device * dev)2744*4882a593Smuzhiyun static u32 velocity_get_link(struct net_device *dev)
2745*4882a593Smuzhiyun {
2746*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
2747*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
2748*4882a593Smuzhiyun 	return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, &regs->PHYSR0) ? 1 : 0;
2749*4882a593Smuzhiyun }
2750*4882a593Smuzhiyun 
2751*4882a593Smuzhiyun /**
2752*4882a593Smuzhiyun  *	velocity_probe - set up discovered velocity device
2753*4882a593Smuzhiyun  *	@dev: PCI device
2754*4882a593Smuzhiyun  *	@info: table of match
2755*4882a593Smuzhiyun  *	@irq: interrupt info
2756*4882a593Smuzhiyun  *	@bustype: bus that device is connected to
2757*4882a593Smuzhiyun  *
2758*4882a593Smuzhiyun  *	Configure a discovered adapter from scratch. Return a negative
2759*4882a593Smuzhiyun  *	errno error code on failure paths.
2760*4882a593Smuzhiyun  */
velocity_probe(struct device * dev,int irq,const struct velocity_info_tbl * info,enum velocity_bus_type bustype)2761*4882a593Smuzhiyun static int velocity_probe(struct device *dev, int irq,
2762*4882a593Smuzhiyun 			   const struct velocity_info_tbl *info,
2763*4882a593Smuzhiyun 			   enum velocity_bus_type bustype)
2764*4882a593Smuzhiyun {
2765*4882a593Smuzhiyun 	struct net_device *netdev;
2766*4882a593Smuzhiyun 	int i;
2767*4882a593Smuzhiyun 	struct velocity_info *vptr;
2768*4882a593Smuzhiyun 	struct mac_regs __iomem *regs;
2769*4882a593Smuzhiyun 	int ret = -ENOMEM;
2770*4882a593Smuzhiyun 
2771*4882a593Smuzhiyun 	/* FIXME: this driver, like almost all other ethernet drivers,
2772*4882a593Smuzhiyun 	 * can support more than MAX_UNITS.
2773*4882a593Smuzhiyun 	 */
2774*4882a593Smuzhiyun 	if (velocity_nics >= MAX_UNITS) {
2775*4882a593Smuzhiyun 		dev_notice(dev, "already found %d NICs.\n", velocity_nics);
2776*4882a593Smuzhiyun 		return -ENODEV;
2777*4882a593Smuzhiyun 	}
2778*4882a593Smuzhiyun 
2779*4882a593Smuzhiyun 	netdev = alloc_etherdev(sizeof(struct velocity_info));
2780*4882a593Smuzhiyun 	if (!netdev)
2781*4882a593Smuzhiyun 		goto out;
2782*4882a593Smuzhiyun 
2783*4882a593Smuzhiyun 	/* Chain it all together */
2784*4882a593Smuzhiyun 
2785*4882a593Smuzhiyun 	SET_NETDEV_DEV(netdev, dev);
2786*4882a593Smuzhiyun 	vptr = netdev_priv(netdev);
2787*4882a593Smuzhiyun 
2788*4882a593Smuzhiyun 	pr_info_once("%s Ver. %s\n", VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
2789*4882a593Smuzhiyun 	pr_info_once("Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
2790*4882a593Smuzhiyun 	pr_info_once("Copyright (c) 2004 Red Hat Inc.\n");
2791*4882a593Smuzhiyun 
2792*4882a593Smuzhiyun 	netdev->irq = irq;
2793*4882a593Smuzhiyun 	vptr->netdev = netdev;
2794*4882a593Smuzhiyun 	vptr->dev = dev;
2795*4882a593Smuzhiyun 
2796*4882a593Smuzhiyun 	velocity_init_info(vptr, info);
2797*4882a593Smuzhiyun 
2798*4882a593Smuzhiyun 	if (bustype == BUS_PCI) {
2799*4882a593Smuzhiyun 		vptr->pdev = to_pci_dev(dev);
2800*4882a593Smuzhiyun 
2801*4882a593Smuzhiyun 		ret = velocity_get_pci_info(vptr);
2802*4882a593Smuzhiyun 		if (ret < 0)
2803*4882a593Smuzhiyun 			goto err_free_dev;
2804*4882a593Smuzhiyun 	} else {
2805*4882a593Smuzhiyun 		vptr->pdev = NULL;
2806*4882a593Smuzhiyun 		ret = velocity_get_platform_info(vptr);
2807*4882a593Smuzhiyun 		if (ret < 0)
2808*4882a593Smuzhiyun 			goto err_free_dev;
2809*4882a593Smuzhiyun 	}
2810*4882a593Smuzhiyun 
2811*4882a593Smuzhiyun 	regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
2812*4882a593Smuzhiyun 	if (regs == NULL) {
2813*4882a593Smuzhiyun 		ret = -EIO;
2814*4882a593Smuzhiyun 		goto err_free_dev;
2815*4882a593Smuzhiyun 	}
2816*4882a593Smuzhiyun 
2817*4882a593Smuzhiyun 	vptr->mac_regs = regs;
2818*4882a593Smuzhiyun 	vptr->rev_id = readb(&regs->rev_id);
2819*4882a593Smuzhiyun 
2820*4882a593Smuzhiyun 	mac_wol_reset(regs);
2821*4882a593Smuzhiyun 
2822*4882a593Smuzhiyun 	for (i = 0; i < 6; i++)
2823*4882a593Smuzhiyun 		netdev->dev_addr[i] = readb(&regs->PAR[i]);
2824*4882a593Smuzhiyun 
2825*4882a593Smuzhiyun 
2826*4882a593Smuzhiyun 	velocity_get_options(&vptr->options, velocity_nics);
2827*4882a593Smuzhiyun 
2828*4882a593Smuzhiyun 	/*
2829*4882a593Smuzhiyun 	 *	Mask out the options cannot be set to the chip
2830*4882a593Smuzhiyun 	 */
2831*4882a593Smuzhiyun 
2832*4882a593Smuzhiyun 	vptr->options.flags &= info->flags;
2833*4882a593Smuzhiyun 
2834*4882a593Smuzhiyun 	/*
2835*4882a593Smuzhiyun 	 *	Enable the chip specified capbilities
2836*4882a593Smuzhiyun 	 */
2837*4882a593Smuzhiyun 
2838*4882a593Smuzhiyun 	vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
2839*4882a593Smuzhiyun 
2840*4882a593Smuzhiyun 	vptr->wol_opts = vptr->options.wol_opts;
2841*4882a593Smuzhiyun 	vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
2842*4882a593Smuzhiyun 
2843*4882a593Smuzhiyun 	vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
2844*4882a593Smuzhiyun 
2845*4882a593Smuzhiyun 	netdev->netdev_ops = &velocity_netdev_ops;
2846*4882a593Smuzhiyun 	netdev->ethtool_ops = &velocity_ethtool_ops;
2847*4882a593Smuzhiyun 	netif_napi_add(netdev, &vptr->napi, velocity_poll,
2848*4882a593Smuzhiyun 							VELOCITY_NAPI_WEIGHT);
2849*4882a593Smuzhiyun 
2850*4882a593Smuzhiyun 	netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
2851*4882a593Smuzhiyun 			   NETIF_F_HW_VLAN_CTAG_TX;
2852*4882a593Smuzhiyun 	netdev->features |= NETIF_F_HW_VLAN_CTAG_TX |
2853*4882a593Smuzhiyun 			NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX |
2854*4882a593Smuzhiyun 			NETIF_F_IP_CSUM;
2855*4882a593Smuzhiyun 
2856*4882a593Smuzhiyun 	/* MTU range: 64 - 9000 */
2857*4882a593Smuzhiyun 	netdev->min_mtu = VELOCITY_MIN_MTU;
2858*4882a593Smuzhiyun 	netdev->max_mtu = VELOCITY_MAX_MTU;
2859*4882a593Smuzhiyun 
2860*4882a593Smuzhiyun 	ret = register_netdev(netdev);
2861*4882a593Smuzhiyun 	if (ret < 0)
2862*4882a593Smuzhiyun 		goto err_iounmap;
2863*4882a593Smuzhiyun 
2864*4882a593Smuzhiyun 	if (!velocity_get_link(netdev)) {
2865*4882a593Smuzhiyun 		netif_carrier_off(netdev);
2866*4882a593Smuzhiyun 		vptr->mii_status |= VELOCITY_LINK_FAIL;
2867*4882a593Smuzhiyun 	}
2868*4882a593Smuzhiyun 
2869*4882a593Smuzhiyun 	velocity_print_info(vptr);
2870*4882a593Smuzhiyun 	dev_set_drvdata(vptr->dev, netdev);
2871*4882a593Smuzhiyun 
2872*4882a593Smuzhiyun 	/* and leave the chip powered down */
2873*4882a593Smuzhiyun 
2874*4882a593Smuzhiyun 	velocity_set_power_state(vptr, PCI_D3hot);
2875*4882a593Smuzhiyun 	velocity_nics++;
2876*4882a593Smuzhiyun out:
2877*4882a593Smuzhiyun 	return ret;
2878*4882a593Smuzhiyun 
2879*4882a593Smuzhiyun err_iounmap:
2880*4882a593Smuzhiyun 	netif_napi_del(&vptr->napi);
2881*4882a593Smuzhiyun 	iounmap(regs);
2882*4882a593Smuzhiyun err_free_dev:
2883*4882a593Smuzhiyun 	free_netdev(netdev);
2884*4882a593Smuzhiyun 	goto out;
2885*4882a593Smuzhiyun }
2886*4882a593Smuzhiyun 
2887*4882a593Smuzhiyun /**
2888*4882a593Smuzhiyun  *	velocity_remove	- device unplug
2889*4882a593Smuzhiyun  *	@dev: device being removed
2890*4882a593Smuzhiyun  *
2891*4882a593Smuzhiyun  *	Device unload callback. Called on an unplug or on module
2892*4882a593Smuzhiyun  *	unload for each active device that is present. Disconnects
2893*4882a593Smuzhiyun  *	the device from the network layer and frees all the resources
2894*4882a593Smuzhiyun  */
velocity_remove(struct device * dev)2895*4882a593Smuzhiyun static int velocity_remove(struct device *dev)
2896*4882a593Smuzhiyun {
2897*4882a593Smuzhiyun 	struct net_device *netdev = dev_get_drvdata(dev);
2898*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(netdev);
2899*4882a593Smuzhiyun 
2900*4882a593Smuzhiyun 	unregister_netdev(netdev);
2901*4882a593Smuzhiyun 	netif_napi_del(&vptr->napi);
2902*4882a593Smuzhiyun 	iounmap(vptr->mac_regs);
2903*4882a593Smuzhiyun 	free_netdev(netdev);
2904*4882a593Smuzhiyun 	velocity_nics--;
2905*4882a593Smuzhiyun 
2906*4882a593Smuzhiyun 	return 0;
2907*4882a593Smuzhiyun }
2908*4882a593Smuzhiyun 
velocity_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2909*4882a593Smuzhiyun static int velocity_pci_probe(struct pci_dev *pdev,
2910*4882a593Smuzhiyun 			       const struct pci_device_id *ent)
2911*4882a593Smuzhiyun {
2912*4882a593Smuzhiyun 	const struct velocity_info_tbl *info =
2913*4882a593Smuzhiyun 					&chip_info_table[ent->driver_data];
2914*4882a593Smuzhiyun 	int ret;
2915*4882a593Smuzhiyun 
2916*4882a593Smuzhiyun 	ret = pci_enable_device(pdev);
2917*4882a593Smuzhiyun 	if (ret < 0)
2918*4882a593Smuzhiyun 		return ret;
2919*4882a593Smuzhiyun 
2920*4882a593Smuzhiyun 	ret = pci_request_regions(pdev, VELOCITY_NAME);
2921*4882a593Smuzhiyun 	if (ret < 0) {
2922*4882a593Smuzhiyun 		dev_err(&pdev->dev, "No PCI resources.\n");
2923*4882a593Smuzhiyun 		goto fail1;
2924*4882a593Smuzhiyun 	}
2925*4882a593Smuzhiyun 
2926*4882a593Smuzhiyun 	ret = velocity_probe(&pdev->dev, pdev->irq, info, BUS_PCI);
2927*4882a593Smuzhiyun 	if (ret == 0)
2928*4882a593Smuzhiyun 		return 0;
2929*4882a593Smuzhiyun 
2930*4882a593Smuzhiyun 	pci_release_regions(pdev);
2931*4882a593Smuzhiyun fail1:
2932*4882a593Smuzhiyun 	pci_disable_device(pdev);
2933*4882a593Smuzhiyun 	return ret;
2934*4882a593Smuzhiyun }
2935*4882a593Smuzhiyun 
velocity_pci_remove(struct pci_dev * pdev)2936*4882a593Smuzhiyun static void velocity_pci_remove(struct pci_dev *pdev)
2937*4882a593Smuzhiyun {
2938*4882a593Smuzhiyun 	velocity_remove(&pdev->dev);
2939*4882a593Smuzhiyun 
2940*4882a593Smuzhiyun 	pci_release_regions(pdev);
2941*4882a593Smuzhiyun 	pci_disable_device(pdev);
2942*4882a593Smuzhiyun }
2943*4882a593Smuzhiyun 
velocity_platform_probe(struct platform_device * pdev)2944*4882a593Smuzhiyun static int velocity_platform_probe(struct platform_device *pdev)
2945*4882a593Smuzhiyun {
2946*4882a593Smuzhiyun 	const struct of_device_id *of_id;
2947*4882a593Smuzhiyun 	const struct velocity_info_tbl *info;
2948*4882a593Smuzhiyun 	int irq;
2949*4882a593Smuzhiyun 
2950*4882a593Smuzhiyun 	of_id = of_match_device(velocity_of_ids, &pdev->dev);
2951*4882a593Smuzhiyun 	if (!of_id)
2952*4882a593Smuzhiyun 		return -EINVAL;
2953*4882a593Smuzhiyun 	info = of_id->data;
2954*4882a593Smuzhiyun 
2955*4882a593Smuzhiyun 	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
2956*4882a593Smuzhiyun 	if (!irq)
2957*4882a593Smuzhiyun 		return -EINVAL;
2958*4882a593Smuzhiyun 
2959*4882a593Smuzhiyun 	return velocity_probe(&pdev->dev, irq, info, BUS_PLATFORM);
2960*4882a593Smuzhiyun }
2961*4882a593Smuzhiyun 
velocity_platform_remove(struct platform_device * pdev)2962*4882a593Smuzhiyun static int velocity_platform_remove(struct platform_device *pdev)
2963*4882a593Smuzhiyun {
2964*4882a593Smuzhiyun 	velocity_remove(&pdev->dev);
2965*4882a593Smuzhiyun 
2966*4882a593Smuzhiyun 	return 0;
2967*4882a593Smuzhiyun }
2968*4882a593Smuzhiyun 
2969*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
2970*4882a593Smuzhiyun /**
2971*4882a593Smuzhiyun  *	wol_calc_crc		-	WOL CRC
2972*4882a593Smuzhiyun  *	@size: size of the wake mask
2973*4882a593Smuzhiyun  *	@pattern: data pattern
2974*4882a593Smuzhiyun  *	@mask_pattern: mask
2975*4882a593Smuzhiyun  *
2976*4882a593Smuzhiyun  *	Compute the wake on lan crc hashes for the packet header
2977*4882a593Smuzhiyun  *	we are interested in.
2978*4882a593Smuzhiyun  */
wol_calc_crc(int size,u8 * pattern,u8 * mask_pattern)2979*4882a593Smuzhiyun static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
2980*4882a593Smuzhiyun {
2981*4882a593Smuzhiyun 	u16 crc = 0xFFFF;
2982*4882a593Smuzhiyun 	u8 mask;
2983*4882a593Smuzhiyun 	int i, j;
2984*4882a593Smuzhiyun 
2985*4882a593Smuzhiyun 	for (i = 0; i < size; i++) {
2986*4882a593Smuzhiyun 		mask = mask_pattern[i];
2987*4882a593Smuzhiyun 
2988*4882a593Smuzhiyun 		/* Skip this loop if the mask equals to zero */
2989*4882a593Smuzhiyun 		if (mask == 0x00)
2990*4882a593Smuzhiyun 			continue;
2991*4882a593Smuzhiyun 
2992*4882a593Smuzhiyun 		for (j = 0; j < 8; j++) {
2993*4882a593Smuzhiyun 			if ((mask & 0x01) == 0) {
2994*4882a593Smuzhiyun 				mask >>= 1;
2995*4882a593Smuzhiyun 				continue;
2996*4882a593Smuzhiyun 			}
2997*4882a593Smuzhiyun 			mask >>= 1;
2998*4882a593Smuzhiyun 			crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
2999*4882a593Smuzhiyun 		}
3000*4882a593Smuzhiyun 	}
3001*4882a593Smuzhiyun 	/*	Finally, invert the result once to get the correct data */
3002*4882a593Smuzhiyun 	crc = ~crc;
3003*4882a593Smuzhiyun 	return bitrev32(crc) >> 16;
3004*4882a593Smuzhiyun }
3005*4882a593Smuzhiyun 
3006*4882a593Smuzhiyun /**
3007*4882a593Smuzhiyun  *	velocity_set_wol	-	set up for wake on lan
3008*4882a593Smuzhiyun  *	@vptr: velocity to set WOL status on
3009*4882a593Smuzhiyun  *
3010*4882a593Smuzhiyun  *	Set a card up for wake on lan either by unicast or by
3011*4882a593Smuzhiyun  *	ARP packet.
3012*4882a593Smuzhiyun  *
3013*4882a593Smuzhiyun  *	FIXME: check static buffer is safe here
3014*4882a593Smuzhiyun  */
velocity_set_wol(struct velocity_info * vptr)3015*4882a593Smuzhiyun static int velocity_set_wol(struct velocity_info *vptr)
3016*4882a593Smuzhiyun {
3017*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
3018*4882a593Smuzhiyun 	enum speed_opt spd_dpx = vptr->options.spd_dpx;
3019*4882a593Smuzhiyun 	static u8 buf[256];
3020*4882a593Smuzhiyun 	int i;
3021*4882a593Smuzhiyun 
3022*4882a593Smuzhiyun 	static u32 mask_pattern[2][4] = {
3023*4882a593Smuzhiyun 		{0x00203000, 0x000003C0, 0x00000000, 0x0000000}, /* ARP */
3024*4882a593Smuzhiyun 		{0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}	 /* Magic Packet */
3025*4882a593Smuzhiyun 	};
3026*4882a593Smuzhiyun 
3027*4882a593Smuzhiyun 	writew(0xFFFF, &regs->WOLCRClr);
3028*4882a593Smuzhiyun 	writeb(WOLCFG_SAB | WOLCFG_SAM, &regs->WOLCFGSet);
3029*4882a593Smuzhiyun 	writew(WOLCR_MAGIC_EN, &regs->WOLCRSet);
3030*4882a593Smuzhiyun 
3031*4882a593Smuzhiyun 	/*
3032*4882a593Smuzhiyun 	   if (vptr->wol_opts & VELOCITY_WOL_PHY)
3033*4882a593Smuzhiyun 	   writew((WOLCR_LINKON_EN|WOLCR_LINKOFF_EN), &regs->WOLCRSet);
3034*4882a593Smuzhiyun 	 */
3035*4882a593Smuzhiyun 
3036*4882a593Smuzhiyun 	if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3037*4882a593Smuzhiyun 		writew(WOLCR_UNICAST_EN, &regs->WOLCRSet);
3038*4882a593Smuzhiyun 
3039*4882a593Smuzhiyun 	if (vptr->wol_opts & VELOCITY_WOL_ARP) {
3040*4882a593Smuzhiyun 		struct arp_packet *arp = (struct arp_packet *) buf;
3041*4882a593Smuzhiyun 		u16 crc;
3042*4882a593Smuzhiyun 		memset(buf, 0, sizeof(struct arp_packet) + 7);
3043*4882a593Smuzhiyun 
3044*4882a593Smuzhiyun 		for (i = 0; i < 4; i++)
3045*4882a593Smuzhiyun 			writel(mask_pattern[0][i], &regs->ByteMask[0][i]);
3046*4882a593Smuzhiyun 
3047*4882a593Smuzhiyun 		arp->type = htons(ETH_P_ARP);
3048*4882a593Smuzhiyun 		arp->ar_op = htons(1);
3049*4882a593Smuzhiyun 
3050*4882a593Smuzhiyun 		memcpy(arp->ar_tip, vptr->ip_addr, 4);
3051*4882a593Smuzhiyun 
3052*4882a593Smuzhiyun 		crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
3053*4882a593Smuzhiyun 				(u8 *) & mask_pattern[0][0]);
3054*4882a593Smuzhiyun 
3055*4882a593Smuzhiyun 		writew(crc, &regs->PatternCRC[0]);
3056*4882a593Smuzhiyun 		writew(WOLCR_ARP_EN, &regs->WOLCRSet);
3057*4882a593Smuzhiyun 	}
3058*4882a593Smuzhiyun 
3059*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(PWCFG_WOLTYPE, &regs->PWCFGSet);
3060*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, &regs->PWCFGSet);
3061*4882a593Smuzhiyun 
3062*4882a593Smuzhiyun 	writew(0x0FFF, &regs->WOLSRClr);
3063*4882a593Smuzhiyun 
3064*4882a593Smuzhiyun 	if (spd_dpx == SPD_DPX_1000_FULL)
3065*4882a593Smuzhiyun 		goto mac_done;
3066*4882a593Smuzhiyun 
3067*4882a593Smuzhiyun 	if (spd_dpx != SPD_DPX_AUTO)
3068*4882a593Smuzhiyun 		goto advertise_done;
3069*4882a593Smuzhiyun 
3070*4882a593Smuzhiyun 	if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
3071*4882a593Smuzhiyun 		if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
3072*4882a593Smuzhiyun 			MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
3073*4882a593Smuzhiyun 
3074*4882a593Smuzhiyun 		MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
3075*4882a593Smuzhiyun 	}
3076*4882a593Smuzhiyun 
3077*4882a593Smuzhiyun 	if (vptr->mii_status & VELOCITY_SPEED_1000)
3078*4882a593Smuzhiyun 		MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
3079*4882a593Smuzhiyun 
3080*4882a593Smuzhiyun advertise_done:
3081*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
3082*4882a593Smuzhiyun 
3083*4882a593Smuzhiyun 	{
3084*4882a593Smuzhiyun 		u8 GCR;
3085*4882a593Smuzhiyun 		GCR = readb(&regs->CHIPGCR);
3086*4882a593Smuzhiyun 		GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
3087*4882a593Smuzhiyun 		writeb(GCR, &regs->CHIPGCR);
3088*4882a593Smuzhiyun 	}
3089*4882a593Smuzhiyun 
3090*4882a593Smuzhiyun mac_done:
3091*4882a593Smuzhiyun 	BYTE_REG_BITS_OFF(ISR_PWEI, &regs->ISR);
3092*4882a593Smuzhiyun 	/* Turn on SWPTAG just before entering power mode */
3093*4882a593Smuzhiyun 	BYTE_REG_BITS_ON(STICKHW_SWPTAG, &regs->STICKHW);
3094*4882a593Smuzhiyun 	/* Go to bed ..... */
3095*4882a593Smuzhiyun 	BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
3096*4882a593Smuzhiyun 
3097*4882a593Smuzhiyun 	return 0;
3098*4882a593Smuzhiyun }
3099*4882a593Smuzhiyun 
3100*4882a593Smuzhiyun /**
3101*4882a593Smuzhiyun  *	velocity_save_context	-	save registers
3102*4882a593Smuzhiyun  *	@vptr: velocity
3103*4882a593Smuzhiyun  *	@context: buffer for stored context
3104*4882a593Smuzhiyun  *
3105*4882a593Smuzhiyun  *	Retrieve the current configuration from the velocity hardware
3106*4882a593Smuzhiyun  *	and stash it in the context structure, for use by the context
3107*4882a593Smuzhiyun  *	restore functions. This allows us to save things we need across
3108*4882a593Smuzhiyun  *	power down states
3109*4882a593Smuzhiyun  */
velocity_save_context(struct velocity_info * vptr,struct velocity_context * context)3110*4882a593Smuzhiyun static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
3111*4882a593Smuzhiyun {
3112*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
3113*4882a593Smuzhiyun 	u16 i;
3114*4882a593Smuzhiyun 	u8 __iomem *ptr = (u8 __iomem *)regs;
3115*4882a593Smuzhiyun 
3116*4882a593Smuzhiyun 	for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
3117*4882a593Smuzhiyun 		*((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3118*4882a593Smuzhiyun 
3119*4882a593Smuzhiyun 	for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
3120*4882a593Smuzhiyun 		*((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3121*4882a593Smuzhiyun 
3122*4882a593Smuzhiyun 	for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3123*4882a593Smuzhiyun 		*((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3124*4882a593Smuzhiyun 
3125*4882a593Smuzhiyun }
3126*4882a593Smuzhiyun 
velocity_suspend(struct device * dev)3127*4882a593Smuzhiyun static int velocity_suspend(struct device *dev)
3128*4882a593Smuzhiyun {
3129*4882a593Smuzhiyun 	struct net_device *netdev = dev_get_drvdata(dev);
3130*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(netdev);
3131*4882a593Smuzhiyun 	unsigned long flags;
3132*4882a593Smuzhiyun 
3133*4882a593Smuzhiyun 	if (!netif_running(vptr->netdev))
3134*4882a593Smuzhiyun 		return 0;
3135*4882a593Smuzhiyun 
3136*4882a593Smuzhiyun 	netif_device_detach(vptr->netdev);
3137*4882a593Smuzhiyun 
3138*4882a593Smuzhiyun 	spin_lock_irqsave(&vptr->lock, flags);
3139*4882a593Smuzhiyun 	if (vptr->pdev)
3140*4882a593Smuzhiyun 		pci_save_state(vptr->pdev);
3141*4882a593Smuzhiyun 
3142*4882a593Smuzhiyun 	if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
3143*4882a593Smuzhiyun 		velocity_get_ip(vptr);
3144*4882a593Smuzhiyun 		velocity_save_context(vptr, &vptr->context);
3145*4882a593Smuzhiyun 		velocity_shutdown(vptr);
3146*4882a593Smuzhiyun 		velocity_set_wol(vptr);
3147*4882a593Smuzhiyun 		if (vptr->pdev)
3148*4882a593Smuzhiyun 			pci_enable_wake(vptr->pdev, PCI_D3hot, 1);
3149*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D3hot);
3150*4882a593Smuzhiyun 	} else {
3151*4882a593Smuzhiyun 		velocity_save_context(vptr, &vptr->context);
3152*4882a593Smuzhiyun 		velocity_shutdown(vptr);
3153*4882a593Smuzhiyun 		if (vptr->pdev)
3154*4882a593Smuzhiyun 			pci_disable_device(vptr->pdev);
3155*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D3hot);
3156*4882a593Smuzhiyun 	}
3157*4882a593Smuzhiyun 
3158*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vptr->lock, flags);
3159*4882a593Smuzhiyun 	return 0;
3160*4882a593Smuzhiyun }
3161*4882a593Smuzhiyun 
3162*4882a593Smuzhiyun /**
3163*4882a593Smuzhiyun  *	velocity_restore_context	-	restore registers
3164*4882a593Smuzhiyun  *	@vptr: velocity
3165*4882a593Smuzhiyun  *	@context: buffer for stored context
3166*4882a593Smuzhiyun  *
3167*4882a593Smuzhiyun  *	Reload the register configuration from the velocity context
3168*4882a593Smuzhiyun  *	created by velocity_save_context.
3169*4882a593Smuzhiyun  */
velocity_restore_context(struct velocity_info * vptr,struct velocity_context * context)3170*4882a593Smuzhiyun static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
3171*4882a593Smuzhiyun {
3172*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
3173*4882a593Smuzhiyun 	int i;
3174*4882a593Smuzhiyun 	u8 __iomem *ptr = (u8 __iomem *)regs;
3175*4882a593Smuzhiyun 
3176*4882a593Smuzhiyun 	for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
3177*4882a593Smuzhiyun 		writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3178*4882a593Smuzhiyun 
3179*4882a593Smuzhiyun 	/* Just skip cr0 */
3180*4882a593Smuzhiyun 	for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
3181*4882a593Smuzhiyun 		/* Clear */
3182*4882a593Smuzhiyun 		writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
3183*4882a593Smuzhiyun 		/* Set */
3184*4882a593Smuzhiyun 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3185*4882a593Smuzhiyun 	}
3186*4882a593Smuzhiyun 
3187*4882a593Smuzhiyun 	for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
3188*4882a593Smuzhiyun 		writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3189*4882a593Smuzhiyun 
3190*4882a593Smuzhiyun 	for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3191*4882a593Smuzhiyun 		writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3192*4882a593Smuzhiyun 
3193*4882a593Smuzhiyun 	for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
3194*4882a593Smuzhiyun 		writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3195*4882a593Smuzhiyun }
3196*4882a593Smuzhiyun 
velocity_resume(struct device * dev)3197*4882a593Smuzhiyun static int velocity_resume(struct device *dev)
3198*4882a593Smuzhiyun {
3199*4882a593Smuzhiyun 	struct net_device *netdev = dev_get_drvdata(dev);
3200*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(netdev);
3201*4882a593Smuzhiyun 	unsigned long flags;
3202*4882a593Smuzhiyun 	int i;
3203*4882a593Smuzhiyun 
3204*4882a593Smuzhiyun 	if (!netif_running(vptr->netdev))
3205*4882a593Smuzhiyun 		return 0;
3206*4882a593Smuzhiyun 
3207*4882a593Smuzhiyun 	velocity_set_power_state(vptr, PCI_D0);
3208*4882a593Smuzhiyun 
3209*4882a593Smuzhiyun 	if (vptr->pdev) {
3210*4882a593Smuzhiyun 		pci_enable_wake(vptr->pdev, PCI_D0, 0);
3211*4882a593Smuzhiyun 		pci_restore_state(vptr->pdev);
3212*4882a593Smuzhiyun 	}
3213*4882a593Smuzhiyun 
3214*4882a593Smuzhiyun 	mac_wol_reset(vptr->mac_regs);
3215*4882a593Smuzhiyun 
3216*4882a593Smuzhiyun 	spin_lock_irqsave(&vptr->lock, flags);
3217*4882a593Smuzhiyun 	velocity_restore_context(vptr, &vptr->context);
3218*4882a593Smuzhiyun 	velocity_init_registers(vptr, VELOCITY_INIT_WOL);
3219*4882a593Smuzhiyun 	mac_disable_int(vptr->mac_regs);
3220*4882a593Smuzhiyun 
3221*4882a593Smuzhiyun 	velocity_tx_srv(vptr);
3222*4882a593Smuzhiyun 
3223*4882a593Smuzhiyun 	for (i = 0; i < vptr->tx.numq; i++) {
3224*4882a593Smuzhiyun 		if (vptr->tx.used[i])
3225*4882a593Smuzhiyun 			mac_tx_queue_wake(vptr->mac_regs, i);
3226*4882a593Smuzhiyun 	}
3227*4882a593Smuzhiyun 
3228*4882a593Smuzhiyun 	mac_enable_int(vptr->mac_regs);
3229*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vptr->lock, flags);
3230*4882a593Smuzhiyun 	netif_device_attach(vptr->netdev);
3231*4882a593Smuzhiyun 
3232*4882a593Smuzhiyun 	return 0;
3233*4882a593Smuzhiyun }
3234*4882a593Smuzhiyun #endif	/* CONFIG_PM_SLEEP */
3235*4882a593Smuzhiyun 
3236*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(velocity_pm_ops, velocity_suspend, velocity_resume);
3237*4882a593Smuzhiyun 
3238*4882a593Smuzhiyun /*
3239*4882a593Smuzhiyun  *	Definition for our device driver. The PCI layer interface
3240*4882a593Smuzhiyun  *	uses this to handle all our card discover and plugging
3241*4882a593Smuzhiyun  */
3242*4882a593Smuzhiyun static struct pci_driver velocity_pci_driver = {
3243*4882a593Smuzhiyun 	.name		= VELOCITY_NAME,
3244*4882a593Smuzhiyun 	.id_table	= velocity_pci_id_table,
3245*4882a593Smuzhiyun 	.probe		= velocity_pci_probe,
3246*4882a593Smuzhiyun 	.remove		= velocity_pci_remove,
3247*4882a593Smuzhiyun 	.driver = {
3248*4882a593Smuzhiyun 		.pm = &velocity_pm_ops,
3249*4882a593Smuzhiyun 	},
3250*4882a593Smuzhiyun };
3251*4882a593Smuzhiyun 
3252*4882a593Smuzhiyun static struct platform_driver velocity_platform_driver = {
3253*4882a593Smuzhiyun 	.probe		= velocity_platform_probe,
3254*4882a593Smuzhiyun 	.remove		= velocity_platform_remove,
3255*4882a593Smuzhiyun 	.driver = {
3256*4882a593Smuzhiyun 		.name = "via-velocity",
3257*4882a593Smuzhiyun 		.of_match_table = velocity_of_ids,
3258*4882a593Smuzhiyun 		.pm = &velocity_pm_ops,
3259*4882a593Smuzhiyun 	},
3260*4882a593Smuzhiyun };
3261*4882a593Smuzhiyun 
3262*4882a593Smuzhiyun /**
3263*4882a593Smuzhiyun  *	velocity_ethtool_up	-	pre hook for ethtool
3264*4882a593Smuzhiyun  *	@dev: network device
3265*4882a593Smuzhiyun  *
3266*4882a593Smuzhiyun  *	Called before an ethtool operation. We need to make sure the
3267*4882a593Smuzhiyun  *	chip is out of D3 state before we poke at it. In case of ethtool
3268*4882a593Smuzhiyun  *	ops nesting, only wake the device up in the outermost block.
3269*4882a593Smuzhiyun  */
velocity_ethtool_up(struct net_device * dev)3270*4882a593Smuzhiyun static int velocity_ethtool_up(struct net_device *dev)
3271*4882a593Smuzhiyun {
3272*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3273*4882a593Smuzhiyun 
3274*4882a593Smuzhiyun 	if (vptr->ethtool_ops_nesting == U32_MAX)
3275*4882a593Smuzhiyun 		return -EBUSY;
3276*4882a593Smuzhiyun 	if (!vptr->ethtool_ops_nesting++ && !netif_running(dev))
3277*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D0);
3278*4882a593Smuzhiyun 	return 0;
3279*4882a593Smuzhiyun }
3280*4882a593Smuzhiyun 
3281*4882a593Smuzhiyun /**
3282*4882a593Smuzhiyun  *	velocity_ethtool_down	-	post hook for ethtool
3283*4882a593Smuzhiyun  *	@dev: network device
3284*4882a593Smuzhiyun  *
3285*4882a593Smuzhiyun  *	Called after an ethtool operation. Restore the chip back to D3
3286*4882a593Smuzhiyun  *	state if it isn't running. In case of ethtool ops nesting, only
3287*4882a593Smuzhiyun  *	put the device to sleep in the outermost block.
3288*4882a593Smuzhiyun  */
velocity_ethtool_down(struct net_device * dev)3289*4882a593Smuzhiyun static void velocity_ethtool_down(struct net_device *dev)
3290*4882a593Smuzhiyun {
3291*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3292*4882a593Smuzhiyun 
3293*4882a593Smuzhiyun 	if (!--vptr->ethtool_ops_nesting && !netif_running(dev))
3294*4882a593Smuzhiyun 		velocity_set_power_state(vptr, PCI_D3hot);
3295*4882a593Smuzhiyun }
3296*4882a593Smuzhiyun 
velocity_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)3297*4882a593Smuzhiyun static int velocity_get_link_ksettings(struct net_device *dev,
3298*4882a593Smuzhiyun 				       struct ethtool_link_ksettings *cmd)
3299*4882a593Smuzhiyun {
3300*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3301*4882a593Smuzhiyun 	struct mac_regs __iomem *regs = vptr->mac_regs;
3302*4882a593Smuzhiyun 	u32 status;
3303*4882a593Smuzhiyun 	u32 supported, advertising;
3304*4882a593Smuzhiyun 
3305*4882a593Smuzhiyun 	status = check_connection_type(vptr->mac_regs);
3306*4882a593Smuzhiyun 
3307*4882a593Smuzhiyun 	supported = SUPPORTED_TP |
3308*4882a593Smuzhiyun 			SUPPORTED_Autoneg |
3309*4882a593Smuzhiyun 			SUPPORTED_10baseT_Half |
3310*4882a593Smuzhiyun 			SUPPORTED_10baseT_Full |
3311*4882a593Smuzhiyun 			SUPPORTED_100baseT_Half |
3312*4882a593Smuzhiyun 			SUPPORTED_100baseT_Full |
3313*4882a593Smuzhiyun 			SUPPORTED_1000baseT_Half |
3314*4882a593Smuzhiyun 			SUPPORTED_1000baseT_Full;
3315*4882a593Smuzhiyun 
3316*4882a593Smuzhiyun 	advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
3317*4882a593Smuzhiyun 	if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
3318*4882a593Smuzhiyun 		advertising |=
3319*4882a593Smuzhiyun 			ADVERTISED_10baseT_Half |
3320*4882a593Smuzhiyun 			ADVERTISED_10baseT_Full |
3321*4882a593Smuzhiyun 			ADVERTISED_100baseT_Half |
3322*4882a593Smuzhiyun 			ADVERTISED_100baseT_Full |
3323*4882a593Smuzhiyun 			ADVERTISED_1000baseT_Half |
3324*4882a593Smuzhiyun 			ADVERTISED_1000baseT_Full;
3325*4882a593Smuzhiyun 	} else {
3326*4882a593Smuzhiyun 		switch (vptr->options.spd_dpx) {
3327*4882a593Smuzhiyun 		case SPD_DPX_1000_FULL:
3328*4882a593Smuzhiyun 			advertising |= ADVERTISED_1000baseT_Full;
3329*4882a593Smuzhiyun 			break;
3330*4882a593Smuzhiyun 		case SPD_DPX_100_HALF:
3331*4882a593Smuzhiyun 			advertising |= ADVERTISED_100baseT_Half;
3332*4882a593Smuzhiyun 			break;
3333*4882a593Smuzhiyun 		case SPD_DPX_100_FULL:
3334*4882a593Smuzhiyun 			advertising |= ADVERTISED_100baseT_Full;
3335*4882a593Smuzhiyun 			break;
3336*4882a593Smuzhiyun 		case SPD_DPX_10_HALF:
3337*4882a593Smuzhiyun 			advertising |= ADVERTISED_10baseT_Half;
3338*4882a593Smuzhiyun 			break;
3339*4882a593Smuzhiyun 		case SPD_DPX_10_FULL:
3340*4882a593Smuzhiyun 			advertising |= ADVERTISED_10baseT_Full;
3341*4882a593Smuzhiyun 			break;
3342*4882a593Smuzhiyun 		default:
3343*4882a593Smuzhiyun 			break;
3344*4882a593Smuzhiyun 		}
3345*4882a593Smuzhiyun 	}
3346*4882a593Smuzhiyun 
3347*4882a593Smuzhiyun 	if (status & VELOCITY_SPEED_1000)
3348*4882a593Smuzhiyun 		cmd->base.speed = SPEED_1000;
3349*4882a593Smuzhiyun 	else if (status & VELOCITY_SPEED_100)
3350*4882a593Smuzhiyun 		cmd->base.speed = SPEED_100;
3351*4882a593Smuzhiyun 	else
3352*4882a593Smuzhiyun 		cmd->base.speed = SPEED_10;
3353*4882a593Smuzhiyun 
3354*4882a593Smuzhiyun 	cmd->base.autoneg = (status & VELOCITY_AUTONEG_ENABLE) ?
3355*4882a593Smuzhiyun 		AUTONEG_ENABLE : AUTONEG_DISABLE;
3356*4882a593Smuzhiyun 	cmd->base.port = PORT_TP;
3357*4882a593Smuzhiyun 	cmd->base.phy_address = readb(&regs->MIIADR) & 0x1F;
3358*4882a593Smuzhiyun 
3359*4882a593Smuzhiyun 	if (status & VELOCITY_DUPLEX_FULL)
3360*4882a593Smuzhiyun 		cmd->base.duplex = DUPLEX_FULL;
3361*4882a593Smuzhiyun 	else
3362*4882a593Smuzhiyun 		cmd->base.duplex = DUPLEX_HALF;
3363*4882a593Smuzhiyun 
3364*4882a593Smuzhiyun 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3365*4882a593Smuzhiyun 						supported);
3366*4882a593Smuzhiyun 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3367*4882a593Smuzhiyun 						advertising);
3368*4882a593Smuzhiyun 
3369*4882a593Smuzhiyun 	return 0;
3370*4882a593Smuzhiyun }
3371*4882a593Smuzhiyun 
velocity_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)3372*4882a593Smuzhiyun static int velocity_set_link_ksettings(struct net_device *dev,
3373*4882a593Smuzhiyun 				       const struct ethtool_link_ksettings *cmd)
3374*4882a593Smuzhiyun {
3375*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3376*4882a593Smuzhiyun 	u32 speed = cmd->base.speed;
3377*4882a593Smuzhiyun 	u32 curr_status;
3378*4882a593Smuzhiyun 	u32 new_status = 0;
3379*4882a593Smuzhiyun 	int ret = 0;
3380*4882a593Smuzhiyun 
3381*4882a593Smuzhiyun 	curr_status = check_connection_type(vptr->mac_regs);
3382*4882a593Smuzhiyun 	curr_status &= (~VELOCITY_LINK_FAIL);
3383*4882a593Smuzhiyun 
3384*4882a593Smuzhiyun 	new_status |= ((cmd->base.autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
3385*4882a593Smuzhiyun 	new_status |= ((speed == SPEED_1000) ? VELOCITY_SPEED_1000 : 0);
3386*4882a593Smuzhiyun 	new_status |= ((speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
3387*4882a593Smuzhiyun 	new_status |= ((speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
3388*4882a593Smuzhiyun 	new_status |= ((cmd->base.duplex == DUPLEX_FULL) ?
3389*4882a593Smuzhiyun 		       VELOCITY_DUPLEX_FULL : 0);
3390*4882a593Smuzhiyun 
3391*4882a593Smuzhiyun 	if ((new_status & VELOCITY_AUTONEG_ENABLE) &&
3392*4882a593Smuzhiyun 	    (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE))) {
3393*4882a593Smuzhiyun 		ret = -EINVAL;
3394*4882a593Smuzhiyun 	} else {
3395*4882a593Smuzhiyun 		enum speed_opt spd_dpx;
3396*4882a593Smuzhiyun 
3397*4882a593Smuzhiyun 		if (new_status & VELOCITY_AUTONEG_ENABLE)
3398*4882a593Smuzhiyun 			spd_dpx = SPD_DPX_AUTO;
3399*4882a593Smuzhiyun 		else if ((new_status & VELOCITY_SPEED_1000) &&
3400*4882a593Smuzhiyun 			 (new_status & VELOCITY_DUPLEX_FULL)) {
3401*4882a593Smuzhiyun 			spd_dpx = SPD_DPX_1000_FULL;
3402*4882a593Smuzhiyun 		} else if (new_status & VELOCITY_SPEED_100)
3403*4882a593Smuzhiyun 			spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3404*4882a593Smuzhiyun 				SPD_DPX_100_FULL : SPD_DPX_100_HALF;
3405*4882a593Smuzhiyun 		else if (new_status & VELOCITY_SPEED_10)
3406*4882a593Smuzhiyun 			spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3407*4882a593Smuzhiyun 				SPD_DPX_10_FULL : SPD_DPX_10_HALF;
3408*4882a593Smuzhiyun 		else
3409*4882a593Smuzhiyun 			return -EOPNOTSUPP;
3410*4882a593Smuzhiyun 
3411*4882a593Smuzhiyun 		vptr->options.spd_dpx = spd_dpx;
3412*4882a593Smuzhiyun 
3413*4882a593Smuzhiyun 		velocity_set_media_mode(vptr, new_status);
3414*4882a593Smuzhiyun 	}
3415*4882a593Smuzhiyun 
3416*4882a593Smuzhiyun 	return ret;
3417*4882a593Smuzhiyun }
3418*4882a593Smuzhiyun 
velocity_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)3419*4882a593Smuzhiyun static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3420*4882a593Smuzhiyun {
3421*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3422*4882a593Smuzhiyun 
3423*4882a593Smuzhiyun 	strlcpy(info->driver, VELOCITY_NAME, sizeof(info->driver));
3424*4882a593Smuzhiyun 	strlcpy(info->version, VELOCITY_VERSION, sizeof(info->version));
3425*4882a593Smuzhiyun 	if (vptr->pdev)
3426*4882a593Smuzhiyun 		strlcpy(info->bus_info, pci_name(vptr->pdev),
3427*4882a593Smuzhiyun 						sizeof(info->bus_info));
3428*4882a593Smuzhiyun 	else
3429*4882a593Smuzhiyun 		strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
3430*4882a593Smuzhiyun }
3431*4882a593Smuzhiyun 
velocity_ethtool_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)3432*4882a593Smuzhiyun static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3433*4882a593Smuzhiyun {
3434*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3435*4882a593Smuzhiyun 	wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
3436*4882a593Smuzhiyun 	wol->wolopts |= WAKE_MAGIC;
3437*4882a593Smuzhiyun 	/*
3438*4882a593Smuzhiyun 	   if (vptr->wol_opts & VELOCITY_WOL_PHY)
3439*4882a593Smuzhiyun 		   wol.wolopts|=WAKE_PHY;
3440*4882a593Smuzhiyun 			 */
3441*4882a593Smuzhiyun 	if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3442*4882a593Smuzhiyun 		wol->wolopts |= WAKE_UCAST;
3443*4882a593Smuzhiyun 	if (vptr->wol_opts & VELOCITY_WOL_ARP)
3444*4882a593Smuzhiyun 		wol->wolopts |= WAKE_ARP;
3445*4882a593Smuzhiyun 	memcpy(&wol->sopass, vptr->wol_passwd, 6);
3446*4882a593Smuzhiyun }
3447*4882a593Smuzhiyun 
velocity_ethtool_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)3448*4882a593Smuzhiyun static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3449*4882a593Smuzhiyun {
3450*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3451*4882a593Smuzhiyun 
3452*4882a593Smuzhiyun 	if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
3453*4882a593Smuzhiyun 		return -EFAULT;
3454*4882a593Smuzhiyun 	vptr->wol_opts = VELOCITY_WOL_MAGIC;
3455*4882a593Smuzhiyun 
3456*4882a593Smuzhiyun 	/*
3457*4882a593Smuzhiyun 	   if (wol.wolopts & WAKE_PHY) {
3458*4882a593Smuzhiyun 	   vptr->wol_opts|=VELOCITY_WOL_PHY;
3459*4882a593Smuzhiyun 	   vptr->flags |=VELOCITY_FLAGS_WOL_ENABLED;
3460*4882a593Smuzhiyun 	   }
3461*4882a593Smuzhiyun 	 */
3462*4882a593Smuzhiyun 
3463*4882a593Smuzhiyun 	if (wol->wolopts & WAKE_MAGIC) {
3464*4882a593Smuzhiyun 		vptr->wol_opts |= VELOCITY_WOL_MAGIC;
3465*4882a593Smuzhiyun 		vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3466*4882a593Smuzhiyun 	}
3467*4882a593Smuzhiyun 	if (wol->wolopts & WAKE_UCAST) {
3468*4882a593Smuzhiyun 		vptr->wol_opts |= VELOCITY_WOL_UCAST;
3469*4882a593Smuzhiyun 		vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3470*4882a593Smuzhiyun 	}
3471*4882a593Smuzhiyun 	if (wol->wolopts & WAKE_ARP) {
3472*4882a593Smuzhiyun 		vptr->wol_opts |= VELOCITY_WOL_ARP;
3473*4882a593Smuzhiyun 		vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3474*4882a593Smuzhiyun 	}
3475*4882a593Smuzhiyun 	memcpy(vptr->wol_passwd, wol->sopass, 6);
3476*4882a593Smuzhiyun 	return 0;
3477*4882a593Smuzhiyun }
3478*4882a593Smuzhiyun 
get_pending_timer_val(int val)3479*4882a593Smuzhiyun static int get_pending_timer_val(int val)
3480*4882a593Smuzhiyun {
3481*4882a593Smuzhiyun 	int mult_bits = val >> 6;
3482*4882a593Smuzhiyun 	int mult = 1;
3483*4882a593Smuzhiyun 
3484*4882a593Smuzhiyun 	switch (mult_bits)
3485*4882a593Smuzhiyun 	{
3486*4882a593Smuzhiyun 	case 1:
3487*4882a593Smuzhiyun 		mult = 4; break;
3488*4882a593Smuzhiyun 	case 2:
3489*4882a593Smuzhiyun 		mult = 16; break;
3490*4882a593Smuzhiyun 	case 3:
3491*4882a593Smuzhiyun 		mult = 64; break;
3492*4882a593Smuzhiyun 	case 0:
3493*4882a593Smuzhiyun 	default:
3494*4882a593Smuzhiyun 		break;
3495*4882a593Smuzhiyun 	}
3496*4882a593Smuzhiyun 
3497*4882a593Smuzhiyun 	return (val & 0x3f) * mult;
3498*4882a593Smuzhiyun }
3499*4882a593Smuzhiyun 
set_pending_timer_val(int * val,u32 us)3500*4882a593Smuzhiyun static void set_pending_timer_val(int *val, u32 us)
3501*4882a593Smuzhiyun {
3502*4882a593Smuzhiyun 	u8 mult = 0;
3503*4882a593Smuzhiyun 	u8 shift = 0;
3504*4882a593Smuzhiyun 
3505*4882a593Smuzhiyun 	if (us >= 0x3f) {
3506*4882a593Smuzhiyun 		mult = 1; /* mult with 4 */
3507*4882a593Smuzhiyun 		shift = 2;
3508*4882a593Smuzhiyun 	}
3509*4882a593Smuzhiyun 	if (us >= 0x3f * 4) {
3510*4882a593Smuzhiyun 		mult = 2; /* mult with 16 */
3511*4882a593Smuzhiyun 		shift = 4;
3512*4882a593Smuzhiyun 	}
3513*4882a593Smuzhiyun 	if (us >= 0x3f * 16) {
3514*4882a593Smuzhiyun 		mult = 3; /* mult with 64 */
3515*4882a593Smuzhiyun 		shift = 6;
3516*4882a593Smuzhiyun 	}
3517*4882a593Smuzhiyun 
3518*4882a593Smuzhiyun 	*val = (mult << 6) | ((us >> shift) & 0x3f);
3519*4882a593Smuzhiyun }
3520*4882a593Smuzhiyun 
3521*4882a593Smuzhiyun 
velocity_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd)3522*4882a593Smuzhiyun static int velocity_get_coalesce(struct net_device *dev,
3523*4882a593Smuzhiyun 		struct ethtool_coalesce *ecmd)
3524*4882a593Smuzhiyun {
3525*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3526*4882a593Smuzhiyun 
3527*4882a593Smuzhiyun 	ecmd->tx_max_coalesced_frames = vptr->options.tx_intsup;
3528*4882a593Smuzhiyun 	ecmd->rx_max_coalesced_frames = vptr->options.rx_intsup;
3529*4882a593Smuzhiyun 
3530*4882a593Smuzhiyun 	ecmd->rx_coalesce_usecs = get_pending_timer_val(vptr->options.rxqueue_timer);
3531*4882a593Smuzhiyun 	ecmd->tx_coalesce_usecs = get_pending_timer_val(vptr->options.txqueue_timer);
3532*4882a593Smuzhiyun 
3533*4882a593Smuzhiyun 	return 0;
3534*4882a593Smuzhiyun }
3535*4882a593Smuzhiyun 
velocity_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd)3536*4882a593Smuzhiyun static int velocity_set_coalesce(struct net_device *dev,
3537*4882a593Smuzhiyun 		struct ethtool_coalesce *ecmd)
3538*4882a593Smuzhiyun {
3539*4882a593Smuzhiyun 	struct velocity_info *vptr = netdev_priv(dev);
3540*4882a593Smuzhiyun 	int max_us = 0x3f * 64;
3541*4882a593Smuzhiyun 	unsigned long flags;
3542*4882a593Smuzhiyun 
3543*4882a593Smuzhiyun 	/* 6 bits of  */
3544*4882a593Smuzhiyun 	if (ecmd->tx_coalesce_usecs > max_us)
3545*4882a593Smuzhiyun 		return -EINVAL;
3546*4882a593Smuzhiyun 	if (ecmd->rx_coalesce_usecs > max_us)
3547*4882a593Smuzhiyun 		return -EINVAL;
3548*4882a593Smuzhiyun 
3549*4882a593Smuzhiyun 	if (ecmd->tx_max_coalesced_frames > 0xff)
3550*4882a593Smuzhiyun 		return -EINVAL;
3551*4882a593Smuzhiyun 	if (ecmd->rx_max_coalesced_frames > 0xff)
3552*4882a593Smuzhiyun 		return -EINVAL;
3553*4882a593Smuzhiyun 
3554*4882a593Smuzhiyun 	vptr->options.rx_intsup = ecmd->rx_max_coalesced_frames;
3555*4882a593Smuzhiyun 	vptr->options.tx_intsup = ecmd->tx_max_coalesced_frames;
3556*4882a593Smuzhiyun 
3557*4882a593Smuzhiyun 	set_pending_timer_val(&vptr->options.rxqueue_timer,
3558*4882a593Smuzhiyun 			ecmd->rx_coalesce_usecs);
3559*4882a593Smuzhiyun 	set_pending_timer_val(&vptr->options.txqueue_timer,
3560*4882a593Smuzhiyun 			ecmd->tx_coalesce_usecs);
3561*4882a593Smuzhiyun 
3562*4882a593Smuzhiyun 	/* Setup the interrupt suppression and queue timers */
3563*4882a593Smuzhiyun 	spin_lock_irqsave(&vptr->lock, flags);
3564*4882a593Smuzhiyun 	mac_disable_int(vptr->mac_regs);
3565*4882a593Smuzhiyun 	setup_adaptive_interrupts(vptr);
3566*4882a593Smuzhiyun 	setup_queue_timers(vptr);
3567*4882a593Smuzhiyun 
3568*4882a593Smuzhiyun 	mac_write_int_mask(vptr->int_mask, vptr->mac_regs);
3569*4882a593Smuzhiyun 	mac_clear_isr(vptr->mac_regs);
3570*4882a593Smuzhiyun 	mac_enable_int(vptr->mac_regs);
3571*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vptr->lock, flags);
3572*4882a593Smuzhiyun 
3573*4882a593Smuzhiyun 	return 0;
3574*4882a593Smuzhiyun }
3575*4882a593Smuzhiyun 
3576*4882a593Smuzhiyun static const char velocity_gstrings[][ETH_GSTRING_LEN] = {
3577*4882a593Smuzhiyun 	"rx_all",
3578*4882a593Smuzhiyun 	"rx_ok",
3579*4882a593Smuzhiyun 	"tx_ok",
3580*4882a593Smuzhiyun 	"rx_error",
3581*4882a593Smuzhiyun 	"rx_runt_ok",
3582*4882a593Smuzhiyun 	"rx_runt_err",
3583*4882a593Smuzhiyun 	"rx_64",
3584*4882a593Smuzhiyun 	"tx_64",
3585*4882a593Smuzhiyun 	"rx_65_to_127",
3586*4882a593Smuzhiyun 	"tx_65_to_127",
3587*4882a593Smuzhiyun 	"rx_128_to_255",
3588*4882a593Smuzhiyun 	"tx_128_to_255",
3589*4882a593Smuzhiyun 	"rx_256_to_511",
3590*4882a593Smuzhiyun 	"tx_256_to_511",
3591*4882a593Smuzhiyun 	"rx_512_to_1023",
3592*4882a593Smuzhiyun 	"tx_512_to_1023",
3593*4882a593Smuzhiyun 	"rx_1024_to_1518",
3594*4882a593Smuzhiyun 	"tx_1024_to_1518",
3595*4882a593Smuzhiyun 	"tx_ether_collisions",
3596*4882a593Smuzhiyun 	"rx_crc_errors",
3597*4882a593Smuzhiyun 	"rx_jumbo",
3598*4882a593Smuzhiyun 	"tx_jumbo",
3599*4882a593Smuzhiyun 	"rx_mac_control_frames",
3600*4882a593Smuzhiyun 	"tx_mac_control_frames",
3601*4882a593Smuzhiyun 	"rx_frame_alignment_errors",
3602*4882a593Smuzhiyun 	"rx_long_ok",
3603*4882a593Smuzhiyun 	"rx_long_err",
3604*4882a593Smuzhiyun 	"tx_sqe_errors",
3605*4882a593Smuzhiyun 	"rx_no_buf",
3606*4882a593Smuzhiyun 	"rx_symbol_errors",
3607*4882a593Smuzhiyun 	"in_range_length_errors",
3608*4882a593Smuzhiyun 	"late_collisions"
3609*4882a593Smuzhiyun };
3610*4882a593Smuzhiyun 
velocity_get_strings(struct net_device * dev,u32 sset,u8 * data)3611*4882a593Smuzhiyun static void velocity_get_strings(struct net_device *dev, u32 sset, u8 *data)
3612*4882a593Smuzhiyun {
3613*4882a593Smuzhiyun 	switch (sset) {
3614*4882a593Smuzhiyun 	case ETH_SS_STATS:
3615*4882a593Smuzhiyun 		memcpy(data, *velocity_gstrings, sizeof(velocity_gstrings));
3616*4882a593Smuzhiyun 		break;
3617*4882a593Smuzhiyun 	}
3618*4882a593Smuzhiyun }
3619*4882a593Smuzhiyun 
velocity_get_sset_count(struct net_device * dev,int sset)3620*4882a593Smuzhiyun static int velocity_get_sset_count(struct net_device *dev, int sset)
3621*4882a593Smuzhiyun {
3622*4882a593Smuzhiyun 	switch (sset) {
3623*4882a593Smuzhiyun 	case ETH_SS_STATS:
3624*4882a593Smuzhiyun 		return ARRAY_SIZE(velocity_gstrings);
3625*4882a593Smuzhiyun 	default:
3626*4882a593Smuzhiyun 		return -EOPNOTSUPP;
3627*4882a593Smuzhiyun 	}
3628*4882a593Smuzhiyun }
3629*4882a593Smuzhiyun 
velocity_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)3630*4882a593Smuzhiyun static void velocity_get_ethtool_stats(struct net_device *dev,
3631*4882a593Smuzhiyun 				       struct ethtool_stats *stats, u64 *data)
3632*4882a593Smuzhiyun {
3633*4882a593Smuzhiyun 	if (netif_running(dev)) {
3634*4882a593Smuzhiyun 		struct velocity_info *vptr = netdev_priv(dev);
3635*4882a593Smuzhiyun 		u32 *p = vptr->mib_counter;
3636*4882a593Smuzhiyun 		int i;
3637*4882a593Smuzhiyun 
3638*4882a593Smuzhiyun 		spin_lock_irq(&vptr->lock);
3639*4882a593Smuzhiyun 		velocity_update_hw_mibs(vptr);
3640*4882a593Smuzhiyun 		spin_unlock_irq(&vptr->lock);
3641*4882a593Smuzhiyun 
3642*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(velocity_gstrings); i++)
3643*4882a593Smuzhiyun 			*data++ = *p++;
3644*4882a593Smuzhiyun 	}
3645*4882a593Smuzhiyun }
3646*4882a593Smuzhiyun 
3647*4882a593Smuzhiyun static const struct ethtool_ops velocity_ethtool_ops = {
3648*4882a593Smuzhiyun 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3649*4882a593Smuzhiyun 				     ETHTOOL_COALESCE_MAX_FRAMES,
3650*4882a593Smuzhiyun 	.get_drvinfo		= velocity_get_drvinfo,
3651*4882a593Smuzhiyun 	.get_wol		= velocity_ethtool_get_wol,
3652*4882a593Smuzhiyun 	.set_wol		= velocity_ethtool_set_wol,
3653*4882a593Smuzhiyun 	.get_link		= velocity_get_link,
3654*4882a593Smuzhiyun 	.get_strings		= velocity_get_strings,
3655*4882a593Smuzhiyun 	.get_sset_count		= velocity_get_sset_count,
3656*4882a593Smuzhiyun 	.get_ethtool_stats	= velocity_get_ethtool_stats,
3657*4882a593Smuzhiyun 	.get_coalesce		= velocity_get_coalesce,
3658*4882a593Smuzhiyun 	.set_coalesce		= velocity_set_coalesce,
3659*4882a593Smuzhiyun 	.begin			= velocity_ethtool_up,
3660*4882a593Smuzhiyun 	.complete		= velocity_ethtool_down,
3661*4882a593Smuzhiyun 	.get_link_ksettings	= velocity_get_link_ksettings,
3662*4882a593Smuzhiyun 	.set_link_ksettings	= velocity_set_link_ksettings,
3663*4882a593Smuzhiyun };
3664*4882a593Smuzhiyun 
3665*4882a593Smuzhiyun #if defined(CONFIG_PM) && defined(CONFIG_INET)
velocity_netdev_event(struct notifier_block * nb,unsigned long notification,void * ptr)3666*4882a593Smuzhiyun static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
3667*4882a593Smuzhiyun {
3668*4882a593Smuzhiyun 	struct in_ifaddr *ifa = ptr;
3669*4882a593Smuzhiyun 	struct net_device *dev = ifa->ifa_dev->dev;
3670*4882a593Smuzhiyun 
3671*4882a593Smuzhiyun 	if (dev_net(dev) == &init_net &&
3672*4882a593Smuzhiyun 	    dev->netdev_ops == &velocity_netdev_ops)
3673*4882a593Smuzhiyun 		velocity_get_ip(netdev_priv(dev));
3674*4882a593Smuzhiyun 
3675*4882a593Smuzhiyun 	return NOTIFY_DONE;
3676*4882a593Smuzhiyun }
3677*4882a593Smuzhiyun 
3678*4882a593Smuzhiyun static struct notifier_block velocity_inetaddr_notifier = {
3679*4882a593Smuzhiyun 	.notifier_call	= velocity_netdev_event,
3680*4882a593Smuzhiyun };
3681*4882a593Smuzhiyun 
velocity_register_notifier(void)3682*4882a593Smuzhiyun static void velocity_register_notifier(void)
3683*4882a593Smuzhiyun {
3684*4882a593Smuzhiyun 	register_inetaddr_notifier(&velocity_inetaddr_notifier);
3685*4882a593Smuzhiyun }
3686*4882a593Smuzhiyun 
velocity_unregister_notifier(void)3687*4882a593Smuzhiyun static void velocity_unregister_notifier(void)
3688*4882a593Smuzhiyun {
3689*4882a593Smuzhiyun 	unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
3690*4882a593Smuzhiyun }
3691*4882a593Smuzhiyun 
3692*4882a593Smuzhiyun #else
3693*4882a593Smuzhiyun 
3694*4882a593Smuzhiyun #define velocity_register_notifier()	do {} while (0)
3695*4882a593Smuzhiyun #define velocity_unregister_notifier()	do {} while (0)
3696*4882a593Smuzhiyun 
3697*4882a593Smuzhiyun #endif	/* defined(CONFIG_PM) && defined(CONFIG_INET) */
3698*4882a593Smuzhiyun 
3699*4882a593Smuzhiyun /**
3700*4882a593Smuzhiyun  *	velocity_init_module	-	load time function
3701*4882a593Smuzhiyun  *
3702*4882a593Smuzhiyun  *	Called when the velocity module is loaded. The PCI driver
3703*4882a593Smuzhiyun  *	is registered with the PCI layer, and in turn will call
3704*4882a593Smuzhiyun  *	the probe functions for each velocity adapter installed
3705*4882a593Smuzhiyun  *	in the system.
3706*4882a593Smuzhiyun  */
velocity_init_module(void)3707*4882a593Smuzhiyun static int __init velocity_init_module(void)
3708*4882a593Smuzhiyun {
3709*4882a593Smuzhiyun 	int ret_pci, ret_platform;
3710*4882a593Smuzhiyun 
3711*4882a593Smuzhiyun 	velocity_register_notifier();
3712*4882a593Smuzhiyun 
3713*4882a593Smuzhiyun 	ret_pci = pci_register_driver(&velocity_pci_driver);
3714*4882a593Smuzhiyun 	ret_platform = platform_driver_register(&velocity_platform_driver);
3715*4882a593Smuzhiyun 
3716*4882a593Smuzhiyun 	/* if both_registers failed, remove the notifier */
3717*4882a593Smuzhiyun 	if ((ret_pci < 0) && (ret_platform < 0)) {
3718*4882a593Smuzhiyun 		velocity_unregister_notifier();
3719*4882a593Smuzhiyun 		return ret_pci;
3720*4882a593Smuzhiyun 	}
3721*4882a593Smuzhiyun 
3722*4882a593Smuzhiyun 	return 0;
3723*4882a593Smuzhiyun }
3724*4882a593Smuzhiyun 
3725*4882a593Smuzhiyun /**
3726*4882a593Smuzhiyun  *	velocity_cleanup	-	module unload
3727*4882a593Smuzhiyun  *
3728*4882a593Smuzhiyun  *	When the velocity hardware is unloaded this function is called.
3729*4882a593Smuzhiyun  *	It will clean up the notifiers and the unregister the PCI
3730*4882a593Smuzhiyun  *	driver interface for this hardware. This in turn cleans up
3731*4882a593Smuzhiyun  *	all discovered interfaces before returning from the function
3732*4882a593Smuzhiyun  */
velocity_cleanup_module(void)3733*4882a593Smuzhiyun static void __exit velocity_cleanup_module(void)
3734*4882a593Smuzhiyun {
3735*4882a593Smuzhiyun 	velocity_unregister_notifier();
3736*4882a593Smuzhiyun 
3737*4882a593Smuzhiyun 	pci_unregister_driver(&velocity_pci_driver);
3738*4882a593Smuzhiyun 	platform_driver_unregister(&velocity_platform_driver);
3739*4882a593Smuzhiyun }
3740*4882a593Smuzhiyun 
3741*4882a593Smuzhiyun module_init(velocity_init_module);
3742*4882a593Smuzhiyun module_exit(velocity_cleanup_module);
3743