xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/tundra/tsi108_eth.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*******************************************************************************
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun   Copyright(c) 2006 Tundra Semiconductor Corporation.
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun *******************************************************************************/
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /* This driver is based on the driver code originally developed
10*4882a593Smuzhiyun  * for the Intel IOC80314 (ForestLake) Gigabit Ethernet by
11*4882a593Smuzhiyun  * scott.wood@timesys.com  * Copyright (C) 2003 TimeSys Corporation
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Currently changes from original version are:
14*4882a593Smuzhiyun  * - porting to Tsi108-based platform and kernel 2.6 (kong.lai@tundra.com)
15*4882a593Smuzhiyun  * - modifications to handle two ports independently and support for
16*4882a593Smuzhiyun  *   additional PHY devices (alexandre.bounine@tundra.com)
17*4882a593Smuzhiyun  * - Get hardware information from platform device. (tie-fei.zang@freescale.com)
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun #include <linux/interrupt.h>
24*4882a593Smuzhiyun #include <linux/net.h>
25*4882a593Smuzhiyun #include <linux/netdevice.h>
26*4882a593Smuzhiyun #include <linux/etherdevice.h>
27*4882a593Smuzhiyun #include <linux/ethtool.h>
28*4882a593Smuzhiyun #include <linux/skbuff.h>
29*4882a593Smuzhiyun #include <linux/spinlock.h>
30*4882a593Smuzhiyun #include <linux/delay.h>
31*4882a593Smuzhiyun #include <linux/crc32.h>
32*4882a593Smuzhiyun #include <linux/mii.h>
33*4882a593Smuzhiyun #include <linux/device.h>
34*4882a593Smuzhiyun #include <linux/pci.h>
35*4882a593Smuzhiyun #include <linux/rtnetlink.h>
36*4882a593Smuzhiyun #include <linux/timer.h>
37*4882a593Smuzhiyun #include <linux/platform_device.h>
38*4882a593Smuzhiyun #include <linux/gfp.h>
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #include <asm/io.h>
41*4882a593Smuzhiyun #include <asm/tsi108.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #include "tsi108_eth.h"
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define MII_READ_DELAY 10000	/* max link wait time in msec */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define TSI108_RXRING_LEN     256
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /* NOTE: The driver currently does not support receiving packets
50*4882a593Smuzhiyun  * larger than the buffer size, so don't decrease this (unless you
51*4882a593Smuzhiyun  * want to add such support).
52*4882a593Smuzhiyun  */
53*4882a593Smuzhiyun #define TSI108_RXBUF_SIZE     1536
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define TSI108_TXRING_LEN     256
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define TSI108_TX_INT_FREQ    64
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* Check the phy status every half a second. */
60*4882a593Smuzhiyun #define CHECK_PHY_INTERVAL (HZ/2)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static int tsi108_init_one(struct platform_device *pdev);
63*4882a593Smuzhiyun static int tsi108_ether_remove(struct platform_device *pdev);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun struct tsi108_prv_data {
66*4882a593Smuzhiyun 	void  __iomem *regs;	/* Base of normal regs */
67*4882a593Smuzhiyun 	void  __iomem *phyregs;	/* Base of register bank used for PHY access */
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	struct net_device *dev;
70*4882a593Smuzhiyun 	struct napi_struct napi;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	unsigned int phy;		/* Index of PHY for this interface */
73*4882a593Smuzhiyun 	unsigned int irq_num;
74*4882a593Smuzhiyun 	unsigned int id;
75*4882a593Smuzhiyun 	unsigned int phy_type;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	struct timer_list timer;/* Timer that triggers the check phy function */
78*4882a593Smuzhiyun 	unsigned int rxtail;	/* Next entry in rxring to read */
79*4882a593Smuzhiyun 	unsigned int rxhead;	/* Next entry in rxring to give a new buffer */
80*4882a593Smuzhiyun 	unsigned int rxfree;	/* Number of free, allocated RX buffers */
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	unsigned int rxpending;	/* Non-zero if there are still descriptors
83*4882a593Smuzhiyun 				 * to be processed from a previous descriptor
84*4882a593Smuzhiyun 				 * interrupt condition that has been cleared */
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	unsigned int txtail;	/* Next TX descriptor to check status on */
87*4882a593Smuzhiyun 	unsigned int txhead;	/* Next TX descriptor to use */
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	/* Number of free TX descriptors.  This could be calculated from
90*4882a593Smuzhiyun 	 * rxhead and rxtail if one descriptor were left unused to disambiguate
91*4882a593Smuzhiyun 	 * full and empty conditions, but it's simpler to just keep track
92*4882a593Smuzhiyun 	 * explicitly. */
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	unsigned int txfree;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	unsigned int phy_ok;		/* The PHY is currently powered on. */
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	/* PHY status (duplex is 1 for half, 2 for full,
99*4882a593Smuzhiyun 	 * so that the default 0 indicates that neither has
100*4882a593Smuzhiyun 	 * yet been configured). */
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	unsigned int link_up;
103*4882a593Smuzhiyun 	unsigned int speed;
104*4882a593Smuzhiyun 	unsigned int duplex;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	tx_desc *txring;
107*4882a593Smuzhiyun 	rx_desc *rxring;
108*4882a593Smuzhiyun 	struct sk_buff *txskbs[TSI108_TXRING_LEN];
109*4882a593Smuzhiyun 	struct sk_buff *rxskbs[TSI108_RXRING_LEN];
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	dma_addr_t txdma, rxdma;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	/* txlock nests in misclock and phy_lock */
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	spinlock_t txlock, misclock;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* stats is used to hold the upper bits of each hardware counter,
118*4882a593Smuzhiyun 	 * and tmpstats is used to hold the full values for returning
119*4882a593Smuzhiyun 	 * to the caller of get_stats().  They must be separate in case
120*4882a593Smuzhiyun 	 * an overflow interrupt occurs before the stats are consumed.
121*4882a593Smuzhiyun 	 */
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	struct net_device_stats stats;
124*4882a593Smuzhiyun 	struct net_device_stats tmpstats;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	/* These stats are kept separate in hardware, thus require individual
127*4882a593Smuzhiyun 	 * fields for handling carry.  They are combined in get_stats.
128*4882a593Smuzhiyun 	 */
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	unsigned long rx_fcs;	/* Add to rx_frame_errors */
131*4882a593Smuzhiyun 	unsigned long rx_short_fcs;	/* Add to rx_frame_errors */
132*4882a593Smuzhiyun 	unsigned long rx_long_fcs;	/* Add to rx_frame_errors */
133*4882a593Smuzhiyun 	unsigned long rx_underruns;	/* Add to rx_length_errors */
134*4882a593Smuzhiyun 	unsigned long rx_overruns;	/* Add to rx_length_errors */
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	unsigned long tx_coll_abort;	/* Add to tx_aborted_errors/collisions */
137*4882a593Smuzhiyun 	unsigned long tx_pause_drop;	/* Add to tx_aborted_errors */
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	unsigned long mc_hash[16];
140*4882a593Smuzhiyun 	u32 msg_enable;			/* debug message level */
141*4882a593Smuzhiyun 	struct mii_if_info mii_if;
142*4882a593Smuzhiyun 	unsigned int init_media;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	struct platform_device *pdev;
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /* Structure for a device driver */
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun static struct platform_driver tsi_eth_driver = {
150*4882a593Smuzhiyun 	.probe = tsi108_init_one,
151*4882a593Smuzhiyun 	.remove = tsi108_ether_remove,
152*4882a593Smuzhiyun 	.driver	= {
153*4882a593Smuzhiyun 		.name = "tsi-ethernet",
154*4882a593Smuzhiyun 	},
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static void tsi108_timed_checker(struct timer_list *t);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun #ifdef DEBUG
dump_eth_one(struct net_device * dev)160*4882a593Smuzhiyun static void dump_eth_one(struct net_device *dev)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	printk("Dumping %s...\n", dev->name);
165*4882a593Smuzhiyun 	printk("intstat %x intmask %x phy_ok %d"
166*4882a593Smuzhiyun 	       " link %d speed %d duplex %d\n",
167*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_INTSTAT),
168*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_INTMASK), data->phy_ok,
169*4882a593Smuzhiyun 	       data->link_up, data->speed, data->duplex);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	printk("TX: head %d, tail %d, free %d, stat %x, estat %x, err %x\n",
172*4882a593Smuzhiyun 	       data->txhead, data->txtail, data->txfree,
173*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_TXSTAT),
174*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_TXESTAT),
175*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_TXERR));
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	printk("RX: head %d, tail %d, free %d, stat %x,"
178*4882a593Smuzhiyun 	       " estat %x, err %x, pending %d\n\n",
179*4882a593Smuzhiyun 	       data->rxhead, data->rxtail, data->rxfree,
180*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_RXSTAT),
181*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_RXESTAT),
182*4882a593Smuzhiyun 	       TSI_READ(TSI108_EC_RXERR), data->rxpending);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun #endif
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun /* Synchronization is needed between the thread and up/down events.
187*4882a593Smuzhiyun  * Note that the PHY is accessed through the same registers for both
188*4882a593Smuzhiyun  * interfaces, so this can't be made interface-specific.
189*4882a593Smuzhiyun  */
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun static DEFINE_SPINLOCK(phy_lock);
192*4882a593Smuzhiyun 
tsi108_read_mii(struct tsi108_prv_data * data,int reg)193*4882a593Smuzhiyun static int tsi108_read_mii(struct tsi108_prv_data *data, int reg)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	unsigned i;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
198*4882a593Smuzhiyun 				(data->phy << TSI108_MAC_MII_ADDR_PHY) |
199*4882a593Smuzhiyun 				(reg << TSI108_MAC_MII_ADDR_REG));
200*4882a593Smuzhiyun 	TSI_WRITE_PHY(TSI108_MAC_MII_CMD, 0);
201*4882a593Smuzhiyun 	TSI_WRITE_PHY(TSI108_MAC_MII_CMD, TSI108_MAC_MII_CMD_READ);
202*4882a593Smuzhiyun 	for (i = 0; i < 100; i++) {
203*4882a593Smuzhiyun 		if (!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
204*4882a593Smuzhiyun 		      (TSI108_MAC_MII_IND_NOTVALID | TSI108_MAC_MII_IND_BUSY)))
205*4882a593Smuzhiyun 			break;
206*4882a593Smuzhiyun 		udelay(10);
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	if (i == 100)
210*4882a593Smuzhiyun 		return 0xffff;
211*4882a593Smuzhiyun 	else
212*4882a593Smuzhiyun 		return TSI_READ_PHY(TSI108_MAC_MII_DATAIN);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
tsi108_write_mii(struct tsi108_prv_data * data,int reg,u16 val)215*4882a593Smuzhiyun static void tsi108_write_mii(struct tsi108_prv_data *data,
216*4882a593Smuzhiyun 				int reg, u16 val)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun 	unsigned i = 100;
219*4882a593Smuzhiyun 	TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
220*4882a593Smuzhiyun 				(data->phy << TSI108_MAC_MII_ADDR_PHY) |
221*4882a593Smuzhiyun 				(reg << TSI108_MAC_MII_ADDR_REG));
222*4882a593Smuzhiyun 	TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val);
223*4882a593Smuzhiyun 	while (i--) {
224*4882a593Smuzhiyun 		if(!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
225*4882a593Smuzhiyun 			TSI108_MAC_MII_IND_BUSY))
226*4882a593Smuzhiyun 			break;
227*4882a593Smuzhiyun 		udelay(10);
228*4882a593Smuzhiyun 	}
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun 
tsi108_mdio_read(struct net_device * dev,int addr,int reg)231*4882a593Smuzhiyun static int tsi108_mdio_read(struct net_device *dev, int addr, int reg)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
234*4882a593Smuzhiyun 	return tsi108_read_mii(data, reg);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
tsi108_mdio_write(struct net_device * dev,int addr,int reg,int val)237*4882a593Smuzhiyun static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
240*4882a593Smuzhiyun 	tsi108_write_mii(data, reg, val);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
tsi108_write_tbi(struct tsi108_prv_data * data,int reg,u16 val)243*4882a593Smuzhiyun static inline void tsi108_write_tbi(struct tsi108_prv_data *data,
244*4882a593Smuzhiyun 					int reg, u16 val)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	unsigned i = 1000;
247*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_MII_ADDR,
248*4882a593Smuzhiyun 			     (0x1e << TSI108_MAC_MII_ADDR_PHY)
249*4882a593Smuzhiyun 			     | (reg << TSI108_MAC_MII_ADDR_REG));
250*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_MII_DATAOUT, val);
251*4882a593Smuzhiyun 	while(i--) {
252*4882a593Smuzhiyun 		if(!(TSI_READ(TSI108_MAC_MII_IND) & TSI108_MAC_MII_IND_BUSY))
253*4882a593Smuzhiyun 			return;
254*4882a593Smuzhiyun 		udelay(10);
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 	printk(KERN_ERR "%s function time out\n", __func__);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
mii_speed(struct mii_if_info * mii)259*4882a593Smuzhiyun static int mii_speed(struct mii_if_info *mii)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	int advert, lpa, val, media;
262*4882a593Smuzhiyun 	int lpa2 = 0;
263*4882a593Smuzhiyun 	int speed;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (!mii_link_ok(mii))
266*4882a593Smuzhiyun 		return 0;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
269*4882a593Smuzhiyun 	if ((val & BMSR_ANEGCOMPLETE) == 0)
270*4882a593Smuzhiyun 		return 0;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
273*4882a593Smuzhiyun 	lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
274*4882a593Smuzhiyun 	media = mii_nway_result(advert & lpa);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	if (mii->supports_gmii)
277*4882a593Smuzhiyun 		lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	speed = lpa2 & (LPA_1000FULL | LPA_1000HALF) ? 1000 :
280*4882a593Smuzhiyun 			(media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 100 : 10);
281*4882a593Smuzhiyun 	return speed;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
tsi108_check_phy(struct net_device * dev)284*4882a593Smuzhiyun static void tsi108_check_phy(struct net_device *dev)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
287*4882a593Smuzhiyun 	u32 mac_cfg2_reg, portctrl_reg;
288*4882a593Smuzhiyun 	u32 duplex;
289*4882a593Smuzhiyun 	u32 speed;
290*4882a593Smuzhiyun 	unsigned long flags;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	spin_lock_irqsave(&phy_lock, flags);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	if (!data->phy_ok)
295*4882a593Smuzhiyun 		goto out;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	duplex = mii_check_media(&data->mii_if, netif_msg_link(data), data->init_media);
298*4882a593Smuzhiyun 	data->init_media = 0;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	if (netif_carrier_ok(dev)) {
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		speed = mii_speed(&data->mii_if);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 		if ((speed != data->speed) || duplex) {
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 			mac_cfg2_reg = TSI_READ(TSI108_MAC_CFG2);
307*4882a593Smuzhiyun 			portctrl_reg = TSI_READ(TSI108_EC_PORTCTRL);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 			mac_cfg2_reg &= ~TSI108_MAC_CFG2_IFACE_MASK;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 			if (speed == 1000) {
312*4882a593Smuzhiyun 				mac_cfg2_reg |= TSI108_MAC_CFG2_GIG;
313*4882a593Smuzhiyun 				portctrl_reg &= ~TSI108_EC_PORTCTRL_NOGIG;
314*4882a593Smuzhiyun 			} else {
315*4882a593Smuzhiyun 				mac_cfg2_reg |= TSI108_MAC_CFG2_NOGIG;
316*4882a593Smuzhiyun 				portctrl_reg |= TSI108_EC_PORTCTRL_NOGIG;
317*4882a593Smuzhiyun 			}
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 			data->speed = speed;
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 			if (data->mii_if.full_duplex) {
322*4882a593Smuzhiyun 				mac_cfg2_reg |= TSI108_MAC_CFG2_FULLDUPLEX;
323*4882a593Smuzhiyun 				portctrl_reg &= ~TSI108_EC_PORTCTRL_HALFDUPLEX;
324*4882a593Smuzhiyun 				data->duplex = 2;
325*4882a593Smuzhiyun 			} else {
326*4882a593Smuzhiyun 				mac_cfg2_reg &= ~TSI108_MAC_CFG2_FULLDUPLEX;
327*4882a593Smuzhiyun 				portctrl_reg |= TSI108_EC_PORTCTRL_HALFDUPLEX;
328*4882a593Smuzhiyun 				data->duplex = 1;
329*4882a593Smuzhiyun 			}
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 			TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg);
332*4882a593Smuzhiyun 			TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg);
333*4882a593Smuzhiyun 		}
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 		if (data->link_up == 0) {
336*4882a593Smuzhiyun 			/* The manual says it can take 3-4 usecs for the speed change
337*4882a593Smuzhiyun 			 * to take effect.
338*4882a593Smuzhiyun 			 */
339*4882a593Smuzhiyun 			udelay(5);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 			spin_lock(&data->txlock);
342*4882a593Smuzhiyun 			if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
343*4882a593Smuzhiyun 				netif_wake_queue(dev);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 			data->link_up = 1;
346*4882a593Smuzhiyun 			spin_unlock(&data->txlock);
347*4882a593Smuzhiyun 		}
348*4882a593Smuzhiyun 	} else {
349*4882a593Smuzhiyun 		if (data->link_up == 1) {
350*4882a593Smuzhiyun 			netif_stop_queue(dev);
351*4882a593Smuzhiyun 			data->link_up = 0;
352*4882a593Smuzhiyun 			printk(KERN_NOTICE "%s : link is down\n", dev->name);
353*4882a593Smuzhiyun 		}
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 		goto out;
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun out:
360*4882a593Smuzhiyun 	spin_unlock_irqrestore(&phy_lock, flags);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun static inline void
tsi108_stat_carry_one(int carry,int carry_bit,int carry_shift,unsigned long * upper)364*4882a593Smuzhiyun tsi108_stat_carry_one(int carry, int carry_bit, int carry_shift,
365*4882a593Smuzhiyun 		      unsigned long *upper)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	if (carry & carry_bit)
368*4882a593Smuzhiyun 		*upper += carry_shift;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
tsi108_stat_carry(struct net_device * dev)371*4882a593Smuzhiyun static void tsi108_stat_carry(struct net_device *dev)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
374*4882a593Smuzhiyun 	unsigned long flags;
375*4882a593Smuzhiyun 	u32 carry1, carry2;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	spin_lock_irqsave(&data->misclock, flags);
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	carry1 = TSI_READ(TSI108_STAT_CARRY1);
380*4882a593Smuzhiyun 	carry2 = TSI_READ(TSI108_STAT_CARRY2);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	TSI_WRITE(TSI108_STAT_CARRY1, carry1);
383*4882a593Smuzhiyun 	TSI_WRITE(TSI108_STAT_CARRY2, carry2);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXBYTES,
386*4882a593Smuzhiyun 			      TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXPKTS,
389*4882a593Smuzhiyun 			      TSI108_STAT_RXPKTS_CARRY,
390*4882a593Smuzhiyun 			      &data->stats.rx_packets);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFCS,
393*4882a593Smuzhiyun 			      TSI108_STAT_RXFCS_CARRY, &data->rx_fcs);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXMCAST,
396*4882a593Smuzhiyun 			      TSI108_STAT_RXMCAST_CARRY,
397*4882a593Smuzhiyun 			      &data->stats.multicast);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXALIGN,
400*4882a593Smuzhiyun 			      TSI108_STAT_RXALIGN_CARRY,
401*4882a593Smuzhiyun 			      &data->stats.rx_frame_errors);
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXLENGTH,
404*4882a593Smuzhiyun 			      TSI108_STAT_RXLENGTH_CARRY,
405*4882a593Smuzhiyun 			      &data->stats.rx_length_errors);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXRUNT,
408*4882a593Smuzhiyun 			      TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJUMBO,
411*4882a593Smuzhiyun 			      TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFRAG,
414*4882a593Smuzhiyun 			      TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJABBER,
417*4882a593Smuzhiyun 			      TSI108_STAT_RXJABBER_CARRY, &data->rx_long_fcs);
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXDROP,
420*4882a593Smuzhiyun 			      TSI108_STAT_RXDROP_CARRY,
421*4882a593Smuzhiyun 			      &data->stats.rx_missed_errors);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXBYTES,
424*4882a593Smuzhiyun 			      TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPKTS,
427*4882a593Smuzhiyun 			      TSI108_STAT_TXPKTS_CARRY,
428*4882a593Smuzhiyun 			      &data->stats.tx_packets);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXDEF,
431*4882a593Smuzhiyun 			      TSI108_STAT_TXEXDEF_CARRY,
432*4882a593Smuzhiyun 			      &data->stats.tx_aborted_errors);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXCOL,
435*4882a593Smuzhiyun 			      TSI108_STAT_TXEXCOL_CARRY, &data->tx_coll_abort);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXTCOL,
438*4882a593Smuzhiyun 			      TSI108_STAT_TXTCOL_CARRY,
439*4882a593Smuzhiyun 			      &data->stats.collisions);
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPAUSE,
442*4882a593Smuzhiyun 			      TSI108_STAT_TXPAUSEDROP_CARRY,
443*4882a593Smuzhiyun 			      &data->tx_pause_drop);
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	spin_unlock_irqrestore(&data->misclock, flags);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun /* Read a stat counter atomically with respect to carries.
449*4882a593Smuzhiyun  * data->misclock must be held.
450*4882a593Smuzhiyun  */
451*4882a593Smuzhiyun static inline unsigned long
tsi108_read_stat(struct tsi108_prv_data * data,int reg,int carry_bit,int carry_shift,unsigned long * upper)452*4882a593Smuzhiyun tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit,
453*4882a593Smuzhiyun 		 int carry_shift, unsigned long *upper)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun 	int carryreg;
456*4882a593Smuzhiyun 	unsigned long val;
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	if (reg < 0xb0)
459*4882a593Smuzhiyun 		carryreg = TSI108_STAT_CARRY1;
460*4882a593Smuzhiyun 	else
461*4882a593Smuzhiyun 		carryreg = TSI108_STAT_CARRY2;
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun       again:
464*4882a593Smuzhiyun 	val = TSI_READ(reg) | *upper;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	/* Check to see if it overflowed, but the interrupt hasn't
467*4882a593Smuzhiyun 	 * been serviced yet.  If so, handle the carry here, and
468*4882a593Smuzhiyun 	 * try again.
469*4882a593Smuzhiyun 	 */
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	if (unlikely(TSI_READ(carryreg) & carry_bit)) {
472*4882a593Smuzhiyun 		*upper += carry_shift;
473*4882a593Smuzhiyun 		TSI_WRITE(carryreg, carry_bit);
474*4882a593Smuzhiyun 		goto again;
475*4882a593Smuzhiyun 	}
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	return val;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun 
tsi108_get_stats(struct net_device * dev)480*4882a593Smuzhiyun static struct net_device_stats *tsi108_get_stats(struct net_device *dev)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun 	unsigned long excol;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
485*4882a593Smuzhiyun 	spin_lock_irq(&data->misclock);
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	data->tmpstats.rx_packets =
488*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXPKTS,
489*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXPKTS,
490*4882a593Smuzhiyun 			     TSI108_STAT_RXPKTS_CARRY, &data->stats.rx_packets);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	data->tmpstats.tx_packets =
493*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_TXPKTS,
494*4882a593Smuzhiyun 			     TSI108_STAT_CARRY2_TXPKTS,
495*4882a593Smuzhiyun 			     TSI108_STAT_TXPKTS_CARRY, &data->stats.tx_packets);
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	data->tmpstats.rx_bytes =
498*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXBYTES,
499*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXBYTES,
500*4882a593Smuzhiyun 			     TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	data->tmpstats.tx_bytes =
503*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_TXBYTES,
504*4882a593Smuzhiyun 			     TSI108_STAT_CARRY2_TXBYTES,
505*4882a593Smuzhiyun 			     TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	data->tmpstats.multicast =
508*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXMCAST,
509*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXMCAST,
510*4882a593Smuzhiyun 			     TSI108_STAT_RXMCAST_CARRY, &data->stats.multicast);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	excol = tsi108_read_stat(data, TSI108_STAT_TXEXCOL,
513*4882a593Smuzhiyun 				 TSI108_STAT_CARRY2_TXEXCOL,
514*4882a593Smuzhiyun 				 TSI108_STAT_TXEXCOL_CARRY,
515*4882a593Smuzhiyun 				 &data->tx_coll_abort);
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	data->tmpstats.collisions =
518*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_TXTCOL,
519*4882a593Smuzhiyun 			     TSI108_STAT_CARRY2_TXTCOL,
520*4882a593Smuzhiyun 			     TSI108_STAT_TXTCOL_CARRY, &data->stats.collisions);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	data->tmpstats.collisions += excol;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	data->tmpstats.rx_length_errors =
525*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXLENGTH,
526*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXLENGTH,
527*4882a593Smuzhiyun 			     TSI108_STAT_RXLENGTH_CARRY,
528*4882a593Smuzhiyun 			     &data->stats.rx_length_errors);
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	data->tmpstats.rx_length_errors +=
531*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXRUNT,
532*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXRUNT,
533*4882a593Smuzhiyun 			     TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	data->tmpstats.rx_length_errors +=
536*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXJUMBO,
537*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXJUMBO,
538*4882a593Smuzhiyun 			     TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	data->tmpstats.rx_frame_errors =
541*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXALIGN,
542*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXALIGN,
543*4882a593Smuzhiyun 			     TSI108_STAT_RXALIGN_CARRY,
544*4882a593Smuzhiyun 			     &data->stats.rx_frame_errors);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	data->tmpstats.rx_frame_errors +=
547*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXFCS,
548*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXFCS, TSI108_STAT_RXFCS_CARRY,
549*4882a593Smuzhiyun 			     &data->rx_fcs);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	data->tmpstats.rx_frame_errors +=
552*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXFRAG,
553*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXFRAG,
554*4882a593Smuzhiyun 			     TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	data->tmpstats.rx_missed_errors =
557*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_RXDROP,
558*4882a593Smuzhiyun 			     TSI108_STAT_CARRY1_RXDROP,
559*4882a593Smuzhiyun 			     TSI108_STAT_RXDROP_CARRY,
560*4882a593Smuzhiyun 			     &data->stats.rx_missed_errors);
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	/* These three are maintained by software. */
563*4882a593Smuzhiyun 	data->tmpstats.rx_fifo_errors = data->stats.rx_fifo_errors;
564*4882a593Smuzhiyun 	data->tmpstats.rx_crc_errors = data->stats.rx_crc_errors;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	data->tmpstats.tx_aborted_errors =
567*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_TXEXDEF,
568*4882a593Smuzhiyun 			     TSI108_STAT_CARRY2_TXEXDEF,
569*4882a593Smuzhiyun 			     TSI108_STAT_TXEXDEF_CARRY,
570*4882a593Smuzhiyun 			     &data->stats.tx_aborted_errors);
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	data->tmpstats.tx_aborted_errors +=
573*4882a593Smuzhiyun 	    tsi108_read_stat(data, TSI108_STAT_TXPAUSEDROP,
574*4882a593Smuzhiyun 			     TSI108_STAT_CARRY2_TXPAUSE,
575*4882a593Smuzhiyun 			     TSI108_STAT_TXPAUSEDROP_CARRY,
576*4882a593Smuzhiyun 			     &data->tx_pause_drop);
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	data->tmpstats.tx_aborted_errors += excol;
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	data->tmpstats.tx_errors = data->tmpstats.tx_aborted_errors;
581*4882a593Smuzhiyun 	data->tmpstats.rx_errors = data->tmpstats.rx_length_errors +
582*4882a593Smuzhiyun 	    data->tmpstats.rx_crc_errors +
583*4882a593Smuzhiyun 	    data->tmpstats.rx_frame_errors +
584*4882a593Smuzhiyun 	    data->tmpstats.rx_fifo_errors + data->tmpstats.rx_missed_errors;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	spin_unlock_irq(&data->misclock);
587*4882a593Smuzhiyun 	return &data->tmpstats;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun 
tsi108_restart_rx(struct tsi108_prv_data * data,struct net_device * dev)590*4882a593Smuzhiyun static void tsi108_restart_rx(struct tsi108_prv_data * data, struct net_device *dev)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXQ_PTRHIGH,
593*4882a593Smuzhiyun 			     TSI108_EC_RXQ_PTRHIGH_VALID);
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXCTRL, TSI108_EC_RXCTRL_GO
596*4882a593Smuzhiyun 			     | TSI108_EC_RXCTRL_QUEUE0);
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun 
tsi108_restart_tx(struct tsi108_prv_data * data)599*4882a593Smuzhiyun static void tsi108_restart_tx(struct tsi108_prv_data * data)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXQ_PTRHIGH,
602*4882a593Smuzhiyun 			     TSI108_EC_TXQ_PTRHIGH_VALID);
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXCTRL, TSI108_EC_TXCTRL_IDLEINT |
605*4882a593Smuzhiyun 			     TSI108_EC_TXCTRL_GO | TSI108_EC_TXCTRL_QUEUE0);
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun /* txlock must be held by caller, with IRQs disabled, and
609*4882a593Smuzhiyun  * with permission to re-enable them when the lock is dropped.
610*4882a593Smuzhiyun  */
tsi108_complete_tx(struct net_device * dev)611*4882a593Smuzhiyun static void tsi108_complete_tx(struct net_device *dev)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
614*4882a593Smuzhiyun 	int tx;
615*4882a593Smuzhiyun 	struct sk_buff *skb;
616*4882a593Smuzhiyun 	int release = 0;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	while (!data->txfree || data->txhead != data->txtail) {
619*4882a593Smuzhiyun 		tx = data->txtail;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 		if (data->txring[tx].misc & TSI108_TX_OWN)
622*4882a593Smuzhiyun 			break;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 		skb = data->txskbs[tx];
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 		if (!(data->txring[tx].misc & TSI108_TX_OK))
627*4882a593Smuzhiyun 			printk("%s: bad tx packet, misc %x\n",
628*4882a593Smuzhiyun 			       dev->name, data->txring[tx].misc);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 		data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
631*4882a593Smuzhiyun 		data->txfree++;
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 		if (data->txring[tx].misc & TSI108_TX_EOF) {
634*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
635*4882a593Smuzhiyun 			release++;
636*4882a593Smuzhiyun 		}
637*4882a593Smuzhiyun 	}
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	if (release) {
640*4882a593Smuzhiyun 		if (is_valid_ether_addr(dev->dev_addr) && data->link_up)
641*4882a593Smuzhiyun 			netif_wake_queue(dev);
642*4882a593Smuzhiyun 	}
643*4882a593Smuzhiyun }
644*4882a593Smuzhiyun 
tsi108_send_packet(struct sk_buff * skb,struct net_device * dev)645*4882a593Smuzhiyun static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
648*4882a593Smuzhiyun 	int frags = skb_shinfo(skb)->nr_frags + 1;
649*4882a593Smuzhiyun 	int i;
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	if (!data->phy_ok && net_ratelimit())
652*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Transmit while PHY is down!\n", dev->name);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	if (!data->link_up) {
655*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Transmit while link is down!\n",
656*4882a593Smuzhiyun 		       dev->name);
657*4882a593Smuzhiyun 		netif_stop_queue(dev);
658*4882a593Smuzhiyun 		return NETDEV_TX_BUSY;
659*4882a593Smuzhiyun 	}
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	if (data->txfree < MAX_SKB_FRAGS + 1) {
662*4882a593Smuzhiyun 		netif_stop_queue(dev);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 		if (net_ratelimit())
665*4882a593Smuzhiyun 			printk(KERN_ERR "%s: Transmit with full tx ring!\n",
666*4882a593Smuzhiyun 			       dev->name);
667*4882a593Smuzhiyun 		return NETDEV_TX_BUSY;
668*4882a593Smuzhiyun 	}
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	if (data->txfree - frags < MAX_SKB_FRAGS + 1) {
671*4882a593Smuzhiyun 		netif_stop_queue(dev);
672*4882a593Smuzhiyun 	}
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	spin_lock_irq(&data->txlock);
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	for (i = 0; i < frags; i++) {
677*4882a593Smuzhiyun 		int misc = 0;
678*4882a593Smuzhiyun 		int tx = data->txhead;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 		/* This is done to mark every TSI108_TX_INT_FREQ tx buffers with
681*4882a593Smuzhiyun 		 * the interrupt bit.  TX descriptor-complete interrupts are
682*4882a593Smuzhiyun 		 * enabled when the queue fills up, and masked when there is
683*4882a593Smuzhiyun 		 * still free space.  This way, when saturating the outbound
684*4882a593Smuzhiyun 		 * link, the tx interrupts are kept to a reasonable level.
685*4882a593Smuzhiyun 		 * When the queue is not full, reclamation of skbs still occurs
686*4882a593Smuzhiyun 		 * as new packets are transmitted, or on a queue-empty
687*4882a593Smuzhiyun 		 * interrupt.
688*4882a593Smuzhiyun 		 */
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 		if ((tx % TSI108_TX_INT_FREQ == 0) &&
691*4882a593Smuzhiyun 		    ((TSI108_TXRING_LEN - data->txfree) >= TSI108_TX_INT_FREQ))
692*4882a593Smuzhiyun 			misc = TSI108_TX_INT;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 		data->txskbs[tx] = skb;
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 		if (i == 0) {
697*4882a593Smuzhiyun 			data->txring[tx].buf0 = dma_map_single(&data->pdev->dev,
698*4882a593Smuzhiyun 					skb->data, skb_headlen(skb),
699*4882a593Smuzhiyun 					DMA_TO_DEVICE);
700*4882a593Smuzhiyun 			data->txring[tx].len = skb_headlen(skb);
701*4882a593Smuzhiyun 			misc |= TSI108_TX_SOF;
702*4882a593Smuzhiyun 		} else {
703*4882a593Smuzhiyun 			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 			data->txring[tx].buf0 =
706*4882a593Smuzhiyun 				skb_frag_dma_map(&data->pdev->dev, frag,
707*4882a593Smuzhiyun 						0, skb_frag_size(frag),
708*4882a593Smuzhiyun 						DMA_TO_DEVICE);
709*4882a593Smuzhiyun 			data->txring[tx].len = skb_frag_size(frag);
710*4882a593Smuzhiyun 		}
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 		if (i == frags - 1)
713*4882a593Smuzhiyun 			misc |= TSI108_TX_EOF;
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 		if (netif_msg_pktdata(data)) {
716*4882a593Smuzhiyun 			int i;
717*4882a593Smuzhiyun 			printk("%s: Tx Frame contents (%d)\n", dev->name,
718*4882a593Smuzhiyun 			       skb->len);
719*4882a593Smuzhiyun 			for (i = 0; i < skb->len; i++)
720*4882a593Smuzhiyun 				printk(" %2.2x", skb->data[i]);
721*4882a593Smuzhiyun 			printk(".\n");
722*4882a593Smuzhiyun 		}
723*4882a593Smuzhiyun 		data->txring[tx].misc = misc | TSI108_TX_OWN;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 		data->txhead = (data->txhead + 1) % TSI108_TXRING_LEN;
726*4882a593Smuzhiyun 		data->txfree--;
727*4882a593Smuzhiyun 	}
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	tsi108_complete_tx(dev);
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	/* This must be done after the check for completed tx descriptors,
732*4882a593Smuzhiyun 	 * so that the tail pointer is correct.
733*4882a593Smuzhiyun 	 */
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	if (!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_QUEUE0))
736*4882a593Smuzhiyun 		tsi108_restart_tx(data);
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	spin_unlock_irq(&data->txlock);
739*4882a593Smuzhiyun 	return NETDEV_TX_OK;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun 
tsi108_complete_rx(struct net_device * dev,int budget)742*4882a593Smuzhiyun static int tsi108_complete_rx(struct net_device *dev, int budget)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
745*4882a593Smuzhiyun 	int done = 0;
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	while (data->rxfree && done != budget) {
748*4882a593Smuzhiyun 		int rx = data->rxtail;
749*4882a593Smuzhiyun 		struct sk_buff *skb;
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 		if (data->rxring[rx].misc & TSI108_RX_OWN)
752*4882a593Smuzhiyun 			break;
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 		skb = data->rxskbs[rx];
755*4882a593Smuzhiyun 		data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
756*4882a593Smuzhiyun 		data->rxfree--;
757*4882a593Smuzhiyun 		done++;
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 		if (data->rxring[rx].misc & TSI108_RX_BAD) {
760*4882a593Smuzhiyun 			spin_lock_irq(&data->misclock);
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun 			if (data->rxring[rx].misc & TSI108_RX_CRC)
763*4882a593Smuzhiyun 				data->stats.rx_crc_errors++;
764*4882a593Smuzhiyun 			if (data->rxring[rx].misc & TSI108_RX_OVER)
765*4882a593Smuzhiyun 				data->stats.rx_fifo_errors++;
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 			spin_unlock_irq(&data->misclock);
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
770*4882a593Smuzhiyun 			continue;
771*4882a593Smuzhiyun 		}
772*4882a593Smuzhiyun 		if (netif_msg_pktdata(data)) {
773*4882a593Smuzhiyun 			int i;
774*4882a593Smuzhiyun 			printk("%s: Rx Frame contents (%d)\n",
775*4882a593Smuzhiyun 			       dev->name, data->rxring[rx].len);
776*4882a593Smuzhiyun 			for (i = 0; i < data->rxring[rx].len; i++)
777*4882a593Smuzhiyun 				printk(" %2.2x", skb->data[i]);
778*4882a593Smuzhiyun 			printk(".\n");
779*4882a593Smuzhiyun 		}
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 		skb_put(skb, data->rxring[rx].len);
782*4882a593Smuzhiyun 		skb->protocol = eth_type_trans(skb, dev);
783*4882a593Smuzhiyun 		netif_receive_skb(skb);
784*4882a593Smuzhiyun 	}
785*4882a593Smuzhiyun 
786*4882a593Smuzhiyun 	return done;
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun 
tsi108_refill_rx(struct net_device * dev,int budget)789*4882a593Smuzhiyun static int tsi108_refill_rx(struct net_device *dev, int budget)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
792*4882a593Smuzhiyun 	int done = 0;
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	while (data->rxfree != TSI108_RXRING_LEN && done != budget) {
795*4882a593Smuzhiyun 		int rx = data->rxhead;
796*4882a593Smuzhiyun 		struct sk_buff *skb;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 		skb = netdev_alloc_skb_ip_align(dev, TSI108_RXBUF_SIZE);
799*4882a593Smuzhiyun 		data->rxskbs[rx] = skb;
800*4882a593Smuzhiyun 		if (!skb)
801*4882a593Smuzhiyun 			break;
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 		data->rxring[rx].buf0 = dma_map_single(&data->pdev->dev,
804*4882a593Smuzhiyun 				skb->data, TSI108_RX_SKB_SIZE,
805*4882a593Smuzhiyun 				DMA_FROM_DEVICE);
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 		/* Sometimes the hardware sets blen to zero after packet
808*4882a593Smuzhiyun 		 * reception, even though the manual says that it's only ever
809*4882a593Smuzhiyun 		 * modified by the driver.
810*4882a593Smuzhiyun 		 */
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 		data->rxring[rx].blen = TSI108_RX_SKB_SIZE;
813*4882a593Smuzhiyun 		data->rxring[rx].misc = TSI108_RX_OWN | TSI108_RX_INT;
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 		data->rxhead = (data->rxhead + 1) % TSI108_RXRING_LEN;
816*4882a593Smuzhiyun 		data->rxfree++;
817*4882a593Smuzhiyun 		done++;
818*4882a593Smuzhiyun 	}
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	if (done != 0 && !(TSI_READ(TSI108_EC_RXSTAT) &
821*4882a593Smuzhiyun 			   TSI108_EC_RXSTAT_QUEUE0))
822*4882a593Smuzhiyun 		tsi108_restart_rx(data, dev);
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun 	return done;
825*4882a593Smuzhiyun }
826*4882a593Smuzhiyun 
tsi108_poll(struct napi_struct * napi,int budget)827*4882a593Smuzhiyun static int tsi108_poll(struct napi_struct *napi, int budget)
828*4882a593Smuzhiyun {
829*4882a593Smuzhiyun 	struct tsi108_prv_data *data = container_of(napi, struct tsi108_prv_data, napi);
830*4882a593Smuzhiyun 	struct net_device *dev = data->dev;
831*4882a593Smuzhiyun 	u32 estat = TSI_READ(TSI108_EC_RXESTAT);
832*4882a593Smuzhiyun 	u32 intstat = TSI_READ(TSI108_EC_INTSTAT);
833*4882a593Smuzhiyun 	int num_received = 0, num_filled = 0;
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun 	intstat &= TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
836*4882a593Smuzhiyun 	    TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | TSI108_INT_RXWAIT;
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXESTAT, estat);
839*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_INTSTAT, intstat);
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	if (data->rxpending || (estat & TSI108_EC_RXESTAT_Q0_DESCINT))
842*4882a593Smuzhiyun 		num_received = tsi108_complete_rx(dev, budget);
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 	/* This should normally fill no more slots than the number of
845*4882a593Smuzhiyun 	 * packets received in tsi108_complete_rx().  The exception
846*4882a593Smuzhiyun 	 * is when we previously ran out of memory for RX SKBs.  In that
847*4882a593Smuzhiyun 	 * case, it's helpful to obey the budget, not only so that the
848*4882a593Smuzhiyun 	 * CPU isn't hogged, but so that memory (which may still be low)
849*4882a593Smuzhiyun 	 * is not hogged by one device.
850*4882a593Smuzhiyun 	 *
851*4882a593Smuzhiyun 	 * A work unit is considered to be two SKBs to allow us to catch
852*4882a593Smuzhiyun 	 * up when the ring has shrunk due to out-of-memory but we're
853*4882a593Smuzhiyun 	 * still removing the full budget's worth of packets each time.
854*4882a593Smuzhiyun 	 */
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 	if (data->rxfree < TSI108_RXRING_LEN)
857*4882a593Smuzhiyun 		num_filled = tsi108_refill_rx(dev, budget * 2);
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 	if (intstat & TSI108_INT_RXERROR) {
860*4882a593Smuzhiyun 		u32 err = TSI_READ(TSI108_EC_RXERR);
861*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_RXERR, err);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 		if (err) {
864*4882a593Smuzhiyun 			if (net_ratelimit())
865*4882a593Smuzhiyun 				printk(KERN_DEBUG "%s: RX error %x\n",
866*4882a593Smuzhiyun 				       dev->name, err);
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 			if (!(TSI_READ(TSI108_EC_RXSTAT) &
869*4882a593Smuzhiyun 			      TSI108_EC_RXSTAT_QUEUE0))
870*4882a593Smuzhiyun 				tsi108_restart_rx(data, dev);
871*4882a593Smuzhiyun 		}
872*4882a593Smuzhiyun 	}
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun 	if (intstat & TSI108_INT_RXOVERRUN) {
875*4882a593Smuzhiyun 		spin_lock_irq(&data->misclock);
876*4882a593Smuzhiyun 		data->stats.rx_fifo_errors++;
877*4882a593Smuzhiyun 		spin_unlock_irq(&data->misclock);
878*4882a593Smuzhiyun 	}
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun 	if (num_received < budget) {
881*4882a593Smuzhiyun 		data->rxpending = 0;
882*4882a593Smuzhiyun 		napi_complete_done(napi, num_received);
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_INTMASK,
885*4882a593Smuzhiyun 				     TSI_READ(TSI108_EC_INTMASK)
886*4882a593Smuzhiyun 				     & ~(TSI108_INT_RXQUEUE0
887*4882a593Smuzhiyun 					 | TSI108_INT_RXTHRESH |
888*4882a593Smuzhiyun 					 TSI108_INT_RXOVERRUN |
889*4882a593Smuzhiyun 					 TSI108_INT_RXERROR |
890*4882a593Smuzhiyun 					 TSI108_INT_RXWAIT));
891*4882a593Smuzhiyun 	} else {
892*4882a593Smuzhiyun 		data->rxpending = 1;
893*4882a593Smuzhiyun 	}
894*4882a593Smuzhiyun 
895*4882a593Smuzhiyun 	return num_received;
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun 
tsi108_rx_int(struct net_device * dev)898*4882a593Smuzhiyun static void tsi108_rx_int(struct net_device *dev)
899*4882a593Smuzhiyun {
900*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
901*4882a593Smuzhiyun 
902*4882a593Smuzhiyun 	/* A race could cause dev to already be scheduled, so it's not an
903*4882a593Smuzhiyun 	 * error if that happens (and interrupts shouldn't be re-masked,
904*4882a593Smuzhiyun 	 * because that can cause harmful races, if poll has already
905*4882a593Smuzhiyun 	 * unmasked them but not cleared LINK_STATE_SCHED).
906*4882a593Smuzhiyun 	 *
907*4882a593Smuzhiyun 	 * This can happen if this code races with tsi108_poll(), which masks
908*4882a593Smuzhiyun 	 * the interrupts after tsi108_irq_one() read the mask, but before
909*4882a593Smuzhiyun 	 * napi_schedule is called.  It could also happen due to calls
910*4882a593Smuzhiyun 	 * from tsi108_check_rxring().
911*4882a593Smuzhiyun 	 */
912*4882a593Smuzhiyun 
913*4882a593Smuzhiyun 	if (napi_schedule_prep(&data->napi)) {
914*4882a593Smuzhiyun 		/* Mask, rather than ack, the receive interrupts.  The ack
915*4882a593Smuzhiyun 		 * will happen in tsi108_poll().
916*4882a593Smuzhiyun 		 */
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_INTMASK,
919*4882a593Smuzhiyun 				     TSI_READ(TSI108_EC_INTMASK) |
920*4882a593Smuzhiyun 				     TSI108_INT_RXQUEUE0
921*4882a593Smuzhiyun 				     | TSI108_INT_RXTHRESH |
922*4882a593Smuzhiyun 				     TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR |
923*4882a593Smuzhiyun 				     TSI108_INT_RXWAIT);
924*4882a593Smuzhiyun 		__napi_schedule(&data->napi);
925*4882a593Smuzhiyun 	} else {
926*4882a593Smuzhiyun 		if (!netif_running(dev)) {
927*4882a593Smuzhiyun 			/* This can happen if an interrupt occurs while the
928*4882a593Smuzhiyun 			 * interface is being brought down, as the START
929*4882a593Smuzhiyun 			 * bit is cleared before the stop function is called.
930*4882a593Smuzhiyun 			 *
931*4882a593Smuzhiyun 			 * In this case, the interrupts must be masked, or
932*4882a593Smuzhiyun 			 * they will continue indefinitely.
933*4882a593Smuzhiyun 			 *
934*4882a593Smuzhiyun 			 * There's a race here if the interface is brought down
935*4882a593Smuzhiyun 			 * and then up in rapid succession, as the device could
936*4882a593Smuzhiyun 			 * be made running after the above check and before
937*4882a593Smuzhiyun 			 * the masking below.  This will only happen if the IRQ
938*4882a593Smuzhiyun 			 * thread has a lower priority than the task brining
939*4882a593Smuzhiyun 			 * up the interface.  Fixing this race would likely
940*4882a593Smuzhiyun 			 * require changes in generic code.
941*4882a593Smuzhiyun 			 */
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 			TSI_WRITE(TSI108_EC_INTMASK,
944*4882a593Smuzhiyun 					     TSI_READ
945*4882a593Smuzhiyun 					     (TSI108_EC_INTMASK) |
946*4882a593Smuzhiyun 					     TSI108_INT_RXQUEUE0 |
947*4882a593Smuzhiyun 					     TSI108_INT_RXTHRESH |
948*4882a593Smuzhiyun 					     TSI108_INT_RXOVERRUN |
949*4882a593Smuzhiyun 					     TSI108_INT_RXERROR |
950*4882a593Smuzhiyun 					     TSI108_INT_RXWAIT);
951*4882a593Smuzhiyun 		}
952*4882a593Smuzhiyun 	}
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun /* If the RX ring has run out of memory, try periodically
956*4882a593Smuzhiyun  * to allocate some more, as otherwise poll would never
957*4882a593Smuzhiyun  * get called (apart from the initial end-of-queue condition).
958*4882a593Smuzhiyun  *
959*4882a593Smuzhiyun  * This is called once per second (by default) from the thread.
960*4882a593Smuzhiyun  */
961*4882a593Smuzhiyun 
tsi108_check_rxring(struct net_device * dev)962*4882a593Smuzhiyun static void tsi108_check_rxring(struct net_device *dev)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	/* A poll is scheduled, as opposed to caling tsi108_refill_rx
967*4882a593Smuzhiyun 	 * directly, so as to keep the receive path single-threaded
968*4882a593Smuzhiyun 	 * (and thus not needing a lock).
969*4882a593Smuzhiyun 	 */
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	if (netif_running(dev) && data->rxfree < TSI108_RXRING_LEN / 4)
972*4882a593Smuzhiyun 		tsi108_rx_int(dev);
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun 
tsi108_tx_int(struct net_device * dev)975*4882a593Smuzhiyun static void tsi108_tx_int(struct net_device *dev)
976*4882a593Smuzhiyun {
977*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
978*4882a593Smuzhiyun 	u32 estat = TSI_READ(TSI108_EC_TXESTAT);
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXESTAT, estat);
981*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_TXQUEUE0 |
982*4882a593Smuzhiyun 			     TSI108_INT_TXIDLE | TSI108_INT_TXERROR);
983*4882a593Smuzhiyun 	if (estat & TSI108_EC_TXESTAT_Q0_ERR) {
984*4882a593Smuzhiyun 		u32 err = TSI_READ(TSI108_EC_TXERR);
985*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_TXERR, err);
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 		if (err && net_ratelimit())
988*4882a593Smuzhiyun 			printk(KERN_ERR "%s: TX error %x\n", dev->name, err);
989*4882a593Smuzhiyun 	}
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	if (estat & (TSI108_EC_TXESTAT_Q0_DESCINT | TSI108_EC_TXESTAT_Q0_EOQ)) {
992*4882a593Smuzhiyun 		spin_lock(&data->txlock);
993*4882a593Smuzhiyun 		tsi108_complete_tx(dev);
994*4882a593Smuzhiyun 		spin_unlock(&data->txlock);
995*4882a593Smuzhiyun 	}
996*4882a593Smuzhiyun }
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 
tsi108_irq(int irq,void * dev_id)999*4882a593Smuzhiyun static irqreturn_t tsi108_irq(int irq, void *dev_id)
1000*4882a593Smuzhiyun {
1001*4882a593Smuzhiyun 	struct net_device *dev = dev_id;
1002*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1003*4882a593Smuzhiyun 	u32 stat = TSI_READ(TSI108_EC_INTSTAT);
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	if (!(stat & TSI108_INT_ANY))
1006*4882a593Smuzhiyun 		return IRQ_NONE;	/* Not our interrupt */
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	stat &= ~TSI_READ(TSI108_EC_INTMASK);
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	if (stat & (TSI108_INT_TXQUEUE0 | TSI108_INT_TXIDLE |
1011*4882a593Smuzhiyun 		    TSI108_INT_TXERROR))
1012*4882a593Smuzhiyun 		tsi108_tx_int(dev);
1013*4882a593Smuzhiyun 	if (stat & (TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
1014*4882a593Smuzhiyun 		    TSI108_INT_RXWAIT | TSI108_INT_RXOVERRUN |
1015*4882a593Smuzhiyun 		    TSI108_INT_RXERROR))
1016*4882a593Smuzhiyun 		tsi108_rx_int(dev);
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	if (stat & TSI108_INT_SFN) {
1019*4882a593Smuzhiyun 		if (net_ratelimit())
1020*4882a593Smuzhiyun 			printk(KERN_DEBUG "%s: SFN error\n", dev->name);
1021*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_SFN);
1022*4882a593Smuzhiyun 	}
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	if (stat & TSI108_INT_STATCARRY) {
1025*4882a593Smuzhiyun 		tsi108_stat_carry(dev);
1026*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_STATCARRY);
1027*4882a593Smuzhiyun 	}
1028*4882a593Smuzhiyun 
1029*4882a593Smuzhiyun 	return IRQ_HANDLED;
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun 
tsi108_stop_ethernet(struct net_device * dev)1032*4882a593Smuzhiyun static void tsi108_stop_ethernet(struct net_device *dev)
1033*4882a593Smuzhiyun {
1034*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1035*4882a593Smuzhiyun 	int i = 1000;
1036*4882a593Smuzhiyun 	/* Disable all TX and RX queues ... */
1037*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXCTRL, 0);
1038*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXCTRL, 0);
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	/* ...and wait for them to become idle */
1041*4882a593Smuzhiyun 	while(i--) {
1042*4882a593Smuzhiyun 		if(!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_ACTIVE))
1043*4882a593Smuzhiyun 			break;
1044*4882a593Smuzhiyun 		udelay(10);
1045*4882a593Smuzhiyun 	}
1046*4882a593Smuzhiyun 	i = 1000;
1047*4882a593Smuzhiyun 	while(i--){
1048*4882a593Smuzhiyun 		if(!(TSI_READ(TSI108_EC_RXSTAT) & TSI108_EC_RXSTAT_ACTIVE))
1049*4882a593Smuzhiyun 			return;
1050*4882a593Smuzhiyun 		udelay(10);
1051*4882a593Smuzhiyun 	}
1052*4882a593Smuzhiyun 	printk(KERN_ERR "%s function time out\n", __func__);
1053*4882a593Smuzhiyun }
1054*4882a593Smuzhiyun 
tsi108_reset_ether(struct tsi108_prv_data * data)1055*4882a593Smuzhiyun static void tsi108_reset_ether(struct tsi108_prv_data * data)
1056*4882a593Smuzhiyun {
1057*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_CFG1, TSI108_MAC_CFG1_SOFTRST);
1058*4882a593Smuzhiyun 	udelay(100);
1059*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_CFG1, 0);
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATRST);
1062*4882a593Smuzhiyun 	udelay(100);
1063*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_PORTCTRL,
1064*4882a593Smuzhiyun 			     TSI_READ(TSI108_EC_PORTCTRL) &
1065*4882a593Smuzhiyun 			     ~TSI108_EC_PORTCTRL_STATRST);
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXCFG, TSI108_EC_TXCFG_RST);
1068*4882a593Smuzhiyun 	udelay(100);
1069*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXCFG,
1070*4882a593Smuzhiyun 			     TSI_READ(TSI108_EC_TXCFG) &
1071*4882a593Smuzhiyun 			     ~TSI108_EC_TXCFG_RST);
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXCFG, TSI108_EC_RXCFG_RST);
1074*4882a593Smuzhiyun 	udelay(100);
1075*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXCFG,
1076*4882a593Smuzhiyun 			     TSI_READ(TSI108_EC_RXCFG) &
1077*4882a593Smuzhiyun 			     ~TSI108_EC_RXCFG_RST);
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
1080*4882a593Smuzhiyun 			     TSI_READ(TSI108_MAC_MII_MGMT_CFG) |
1081*4882a593Smuzhiyun 			     TSI108_MAC_MII_MGMT_RST);
1082*4882a593Smuzhiyun 	udelay(100);
1083*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
1084*4882a593Smuzhiyun 			     (TSI_READ(TSI108_MAC_MII_MGMT_CFG) &
1085*4882a593Smuzhiyun 			     ~(TSI108_MAC_MII_MGMT_RST |
1086*4882a593Smuzhiyun 			       TSI108_MAC_MII_MGMT_CLK)) | 0x07);
1087*4882a593Smuzhiyun }
1088*4882a593Smuzhiyun 
tsi108_get_mac(struct net_device * dev)1089*4882a593Smuzhiyun static int tsi108_get_mac(struct net_device *dev)
1090*4882a593Smuzhiyun {
1091*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1092*4882a593Smuzhiyun 	u32 word1 = TSI_READ(TSI108_MAC_ADDR1);
1093*4882a593Smuzhiyun 	u32 word2 = TSI_READ(TSI108_MAC_ADDR2);
1094*4882a593Smuzhiyun 
1095*4882a593Smuzhiyun 	/* Note that the octets are reversed from what the manual says,
1096*4882a593Smuzhiyun 	 * producing an even weirder ordering...
1097*4882a593Smuzhiyun 	 */
1098*4882a593Smuzhiyun 	if (word2 == 0 && word1 == 0) {
1099*4882a593Smuzhiyun 		dev->dev_addr[0] = 0x00;
1100*4882a593Smuzhiyun 		dev->dev_addr[1] = 0x06;
1101*4882a593Smuzhiyun 		dev->dev_addr[2] = 0xd2;
1102*4882a593Smuzhiyun 		dev->dev_addr[3] = 0x00;
1103*4882a593Smuzhiyun 		dev->dev_addr[4] = 0x00;
1104*4882a593Smuzhiyun 		if (0x8 == data->phy)
1105*4882a593Smuzhiyun 			dev->dev_addr[5] = 0x01;
1106*4882a593Smuzhiyun 		else
1107*4882a593Smuzhiyun 			dev->dev_addr[5] = 0x02;
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun 		word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 		word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
1112*4882a593Smuzhiyun 		    (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 		TSI_WRITE(TSI108_MAC_ADDR1, word1);
1115*4882a593Smuzhiyun 		TSI_WRITE(TSI108_MAC_ADDR2, word2);
1116*4882a593Smuzhiyun 	} else {
1117*4882a593Smuzhiyun 		dev->dev_addr[0] = (word2 >> 16) & 0xff;
1118*4882a593Smuzhiyun 		dev->dev_addr[1] = (word2 >> 24) & 0xff;
1119*4882a593Smuzhiyun 		dev->dev_addr[2] = (word1 >> 0) & 0xff;
1120*4882a593Smuzhiyun 		dev->dev_addr[3] = (word1 >> 8) & 0xff;
1121*4882a593Smuzhiyun 		dev->dev_addr[4] = (word1 >> 16) & 0xff;
1122*4882a593Smuzhiyun 		dev->dev_addr[5] = (word1 >> 24) & 0xff;
1123*4882a593Smuzhiyun 	}
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	if (!is_valid_ether_addr(dev->dev_addr)) {
1126*4882a593Smuzhiyun 		printk(KERN_ERR
1127*4882a593Smuzhiyun 		       "%s: Invalid MAC address. word1: %08x, word2: %08x\n",
1128*4882a593Smuzhiyun 		       dev->name, word1, word2);
1129*4882a593Smuzhiyun 		return -EINVAL;
1130*4882a593Smuzhiyun 	}
1131*4882a593Smuzhiyun 
1132*4882a593Smuzhiyun 	return 0;
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun 
tsi108_set_mac(struct net_device * dev,void * addr)1135*4882a593Smuzhiyun static int tsi108_set_mac(struct net_device *dev, void *addr)
1136*4882a593Smuzhiyun {
1137*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1138*4882a593Smuzhiyun 	u32 word1, word2;
1139*4882a593Smuzhiyun 	int i;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	if (!is_valid_ether_addr(addr))
1142*4882a593Smuzhiyun 		return -EADDRNOTAVAIL;
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	for (i = 0; i < 6; i++)
1145*4882a593Smuzhiyun 		/* +2 is for the offset of the HW addr type */
1146*4882a593Smuzhiyun 		dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 	word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
1151*4882a593Smuzhiyun 	    (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	spin_lock_irq(&data->misclock);
1154*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_ADDR1, word1);
1155*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_ADDR2, word2);
1156*4882a593Smuzhiyun 	spin_lock(&data->txlock);
1157*4882a593Smuzhiyun 
1158*4882a593Smuzhiyun 	if (data->txfree && data->link_up)
1159*4882a593Smuzhiyun 		netif_wake_queue(dev);
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	spin_unlock(&data->txlock);
1162*4882a593Smuzhiyun 	spin_unlock_irq(&data->misclock);
1163*4882a593Smuzhiyun 	return 0;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun /* Protected by dev->xmit_lock. */
tsi108_set_rx_mode(struct net_device * dev)1167*4882a593Smuzhiyun static void tsi108_set_rx_mode(struct net_device *dev)
1168*4882a593Smuzhiyun {
1169*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1170*4882a593Smuzhiyun 	u32 rxcfg = TSI_READ(TSI108_EC_RXCFG);
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun 	if (dev->flags & IFF_PROMISC) {
1173*4882a593Smuzhiyun 		rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH);
1174*4882a593Smuzhiyun 		rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE;
1175*4882a593Smuzhiyun 		goto out;
1176*4882a593Smuzhiyun 	}
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun 	rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE);
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun 	if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
1181*4882a593Smuzhiyun 		int i;
1182*4882a593Smuzhiyun 		struct netdev_hw_addr *ha;
1183*4882a593Smuzhiyun 		rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH;
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 		memset(data->mc_hash, 0, sizeof(data->mc_hash));
1186*4882a593Smuzhiyun 
1187*4882a593Smuzhiyun 		netdev_for_each_mc_addr(ha, dev) {
1188*4882a593Smuzhiyun 			u32 hash, crc;
1189*4882a593Smuzhiyun 
1190*4882a593Smuzhiyun 			crc = ether_crc(6, ha->addr);
1191*4882a593Smuzhiyun 			hash = crc >> 23;
1192*4882a593Smuzhiyun 			__set_bit(hash, &data->mc_hash[0]);
1193*4882a593Smuzhiyun 		}
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun 		TSI_WRITE(TSI108_EC_HASHADDR,
1196*4882a593Smuzhiyun 				     TSI108_EC_HASHADDR_AUTOINC |
1197*4882a593Smuzhiyun 				     TSI108_EC_HASHADDR_MCAST);
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 		for (i = 0; i < 16; i++) {
1200*4882a593Smuzhiyun 			/* The manual says that the hardware may drop
1201*4882a593Smuzhiyun 			 * back-to-back writes to the data register.
1202*4882a593Smuzhiyun 			 */
1203*4882a593Smuzhiyun 			udelay(1);
1204*4882a593Smuzhiyun 			TSI_WRITE(TSI108_EC_HASHDATA,
1205*4882a593Smuzhiyun 					     data->mc_hash[i]);
1206*4882a593Smuzhiyun 		}
1207*4882a593Smuzhiyun 	}
1208*4882a593Smuzhiyun 
1209*4882a593Smuzhiyun       out:
1210*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXCFG, rxcfg);
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun 
tsi108_init_phy(struct net_device * dev)1213*4882a593Smuzhiyun static void tsi108_init_phy(struct net_device *dev)
1214*4882a593Smuzhiyun {
1215*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1216*4882a593Smuzhiyun 	u32 i = 0;
1217*4882a593Smuzhiyun 	u16 phyval = 0;
1218*4882a593Smuzhiyun 	unsigned long flags;
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 	spin_lock_irqsave(&phy_lock, flags);
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
1223*4882a593Smuzhiyun 	while (--i) {
1224*4882a593Smuzhiyun 		if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
1225*4882a593Smuzhiyun 			break;
1226*4882a593Smuzhiyun 		udelay(10);
1227*4882a593Smuzhiyun 	}
1228*4882a593Smuzhiyun 	if (i == 0)
1229*4882a593Smuzhiyun 		printk(KERN_ERR "%s function time out\n", __func__);
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun 	if (data->phy_type == TSI108_PHY_BCM54XX) {
1232*4882a593Smuzhiyun 		tsi108_write_mii(data, 0x09, 0x0300);
1233*4882a593Smuzhiyun 		tsi108_write_mii(data, 0x10, 0x1020);
1234*4882a593Smuzhiyun 		tsi108_write_mii(data, 0x1c, 0x8c00);
1235*4882a593Smuzhiyun 	}
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	tsi108_write_mii(data,
1238*4882a593Smuzhiyun 			 MII_BMCR,
1239*4882a593Smuzhiyun 			 BMCR_ANENABLE | BMCR_ANRESTART);
1240*4882a593Smuzhiyun 	while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
1241*4882a593Smuzhiyun 		cpu_relax();
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	/* Set G/MII mode and receive clock select in TBI control #2.  The
1244*4882a593Smuzhiyun 	 * second port won't work if this isn't done, even though we don't
1245*4882a593Smuzhiyun 	 * use TBI mode.
1246*4882a593Smuzhiyun 	 */
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	tsi108_write_tbi(data, 0x11, 0x30);
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun 	/* FIXME: It seems to take more than 2 back-to-back reads to the
1251*4882a593Smuzhiyun 	 * PHY_STAT register before the link up status bit is set.
1252*4882a593Smuzhiyun 	 */
1253*4882a593Smuzhiyun 
1254*4882a593Smuzhiyun 	data->link_up = 0;
1255*4882a593Smuzhiyun 
1256*4882a593Smuzhiyun 	while (!((phyval = tsi108_read_mii(data, MII_BMSR)) &
1257*4882a593Smuzhiyun 		 BMSR_LSTATUS)) {
1258*4882a593Smuzhiyun 		if (i++ > (MII_READ_DELAY / 10)) {
1259*4882a593Smuzhiyun 			break;
1260*4882a593Smuzhiyun 		}
1261*4882a593Smuzhiyun 		spin_unlock_irqrestore(&phy_lock, flags);
1262*4882a593Smuzhiyun 		msleep(10);
1263*4882a593Smuzhiyun 		spin_lock_irqsave(&phy_lock, flags);
1264*4882a593Smuzhiyun 	}
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun 	data->mii_if.supports_gmii = mii_check_gmii_support(&data->mii_if);
1267*4882a593Smuzhiyun 	printk(KERN_DEBUG "PHY_STAT reg contains %08x\n", phyval);
1268*4882a593Smuzhiyun 	data->phy_ok = 1;
1269*4882a593Smuzhiyun 	data->init_media = 1;
1270*4882a593Smuzhiyun 	spin_unlock_irqrestore(&phy_lock, flags);
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun 
tsi108_kill_phy(struct net_device * dev)1273*4882a593Smuzhiyun static void tsi108_kill_phy(struct net_device *dev)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1276*4882a593Smuzhiyun 	unsigned long flags;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	spin_lock_irqsave(&phy_lock, flags);
1279*4882a593Smuzhiyun 	tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN);
1280*4882a593Smuzhiyun 	data->phy_ok = 0;
1281*4882a593Smuzhiyun 	spin_unlock_irqrestore(&phy_lock, flags);
1282*4882a593Smuzhiyun }
1283*4882a593Smuzhiyun 
tsi108_open(struct net_device * dev)1284*4882a593Smuzhiyun static int tsi108_open(struct net_device *dev)
1285*4882a593Smuzhiyun {
1286*4882a593Smuzhiyun 	int i;
1287*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1288*4882a593Smuzhiyun 	unsigned int rxring_size = TSI108_RXRING_LEN * sizeof(rx_desc);
1289*4882a593Smuzhiyun 	unsigned int txring_size = TSI108_TXRING_LEN * sizeof(tx_desc);
1290*4882a593Smuzhiyun 
1291*4882a593Smuzhiyun 	i = request_irq(data->irq_num, tsi108_irq, 0, dev->name, dev);
1292*4882a593Smuzhiyun 	if (i != 0) {
1293*4882a593Smuzhiyun 		printk(KERN_ERR "tsi108_eth%d: Could not allocate IRQ%d.\n",
1294*4882a593Smuzhiyun 		       data->id, data->irq_num);
1295*4882a593Smuzhiyun 		return i;
1296*4882a593Smuzhiyun 	} else {
1297*4882a593Smuzhiyun 		dev->irq = data->irq_num;
1298*4882a593Smuzhiyun 		printk(KERN_NOTICE
1299*4882a593Smuzhiyun 		       "tsi108_open : Port %d Assigned IRQ %d to %s\n",
1300*4882a593Smuzhiyun 		       data->id, dev->irq, dev->name);
1301*4882a593Smuzhiyun 	}
1302*4882a593Smuzhiyun 
1303*4882a593Smuzhiyun 	data->rxring = dma_alloc_coherent(&data->pdev->dev, rxring_size,
1304*4882a593Smuzhiyun 					  &data->rxdma, GFP_KERNEL);
1305*4882a593Smuzhiyun 	if (!data->rxring) {
1306*4882a593Smuzhiyun 		free_irq(data->irq_num, dev);
1307*4882a593Smuzhiyun 		return -ENOMEM;
1308*4882a593Smuzhiyun 	}
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	data->txring = dma_alloc_coherent(&data->pdev->dev, txring_size,
1311*4882a593Smuzhiyun 					  &data->txdma, GFP_KERNEL);
1312*4882a593Smuzhiyun 	if (!data->txring) {
1313*4882a593Smuzhiyun 		free_irq(data->irq_num, dev);
1314*4882a593Smuzhiyun 		dma_free_coherent(&data->pdev->dev, rxring_size, data->rxring,
1315*4882a593Smuzhiyun 				    data->rxdma);
1316*4882a593Smuzhiyun 		return -ENOMEM;
1317*4882a593Smuzhiyun 	}
1318*4882a593Smuzhiyun 
1319*4882a593Smuzhiyun 	for (i = 0; i < TSI108_RXRING_LEN; i++) {
1320*4882a593Smuzhiyun 		data->rxring[i].next0 = data->rxdma + (i + 1) * sizeof(rx_desc);
1321*4882a593Smuzhiyun 		data->rxring[i].blen = TSI108_RXBUF_SIZE;
1322*4882a593Smuzhiyun 		data->rxring[i].vlan = 0;
1323*4882a593Smuzhiyun 	}
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun 	data->rxring[TSI108_RXRING_LEN - 1].next0 = data->rxdma;
1326*4882a593Smuzhiyun 
1327*4882a593Smuzhiyun 	data->rxtail = 0;
1328*4882a593Smuzhiyun 	data->rxhead = 0;
1329*4882a593Smuzhiyun 
1330*4882a593Smuzhiyun 	for (i = 0; i < TSI108_RXRING_LEN; i++) {
1331*4882a593Smuzhiyun 		struct sk_buff *skb;
1332*4882a593Smuzhiyun 
1333*4882a593Smuzhiyun 		skb = netdev_alloc_skb_ip_align(dev, TSI108_RXBUF_SIZE);
1334*4882a593Smuzhiyun 		if (!skb) {
1335*4882a593Smuzhiyun 			/* Bah.  No memory for now, but maybe we'll get
1336*4882a593Smuzhiyun 			 * some more later.
1337*4882a593Smuzhiyun 			 * For now, we'll live with the smaller ring.
1338*4882a593Smuzhiyun 			 */
1339*4882a593Smuzhiyun 			printk(KERN_WARNING
1340*4882a593Smuzhiyun 			       "%s: Could only allocate %d receive skb(s).\n",
1341*4882a593Smuzhiyun 			       dev->name, i);
1342*4882a593Smuzhiyun 			data->rxhead = i;
1343*4882a593Smuzhiyun 			break;
1344*4882a593Smuzhiyun 		}
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 		data->rxskbs[i] = skb;
1347*4882a593Smuzhiyun 		data->rxring[i].buf0 = virt_to_phys(data->rxskbs[i]->data);
1348*4882a593Smuzhiyun 		data->rxring[i].misc = TSI108_RX_OWN | TSI108_RX_INT;
1349*4882a593Smuzhiyun 	}
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun 	data->rxfree = i;
1352*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXQ_PTRLOW, data->rxdma);
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun 	for (i = 0; i < TSI108_TXRING_LEN; i++) {
1355*4882a593Smuzhiyun 		data->txring[i].next0 = data->txdma + (i + 1) * sizeof(tx_desc);
1356*4882a593Smuzhiyun 		data->txring[i].misc = 0;
1357*4882a593Smuzhiyun 	}
1358*4882a593Smuzhiyun 
1359*4882a593Smuzhiyun 	data->txring[TSI108_TXRING_LEN - 1].next0 = data->txdma;
1360*4882a593Smuzhiyun 	data->txtail = 0;
1361*4882a593Smuzhiyun 	data->txhead = 0;
1362*4882a593Smuzhiyun 	data->txfree = TSI108_TXRING_LEN;
1363*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXQ_PTRLOW, data->txdma);
1364*4882a593Smuzhiyun 	tsi108_init_phy(dev);
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	napi_enable(&data->napi);
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	timer_setup(&data->timer, tsi108_timed_checker, 0);
1369*4882a593Smuzhiyun 	mod_timer(&data->timer, jiffies + 1);
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	tsi108_restart_rx(data, dev);
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_INTSTAT, ~0);
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_INTMASK,
1376*4882a593Smuzhiyun 			     ~(TSI108_INT_TXQUEUE0 | TSI108_INT_RXERROR |
1377*4882a593Smuzhiyun 			       TSI108_INT_RXTHRESH | TSI108_INT_RXQUEUE0 |
1378*4882a593Smuzhiyun 			       TSI108_INT_RXOVERRUN | TSI108_INT_RXWAIT |
1379*4882a593Smuzhiyun 			       TSI108_INT_SFN | TSI108_INT_STATCARRY));
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_CFG1,
1382*4882a593Smuzhiyun 			     TSI108_MAC_CFG1_RXEN | TSI108_MAC_CFG1_TXEN);
1383*4882a593Smuzhiyun 	netif_start_queue(dev);
1384*4882a593Smuzhiyun 	return 0;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun 
tsi108_close(struct net_device * dev)1387*4882a593Smuzhiyun static int tsi108_close(struct net_device *dev)
1388*4882a593Smuzhiyun {
1389*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 	netif_stop_queue(dev);
1392*4882a593Smuzhiyun 	napi_disable(&data->napi);
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	del_timer_sync(&data->timer);
1395*4882a593Smuzhiyun 
1396*4882a593Smuzhiyun 	tsi108_stop_ethernet(dev);
1397*4882a593Smuzhiyun 	tsi108_kill_phy(dev);
1398*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_INTMASK, ~0);
1399*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_CFG1, 0);
1400*4882a593Smuzhiyun 
1401*4882a593Smuzhiyun 	/* Check for any pending TX packets, and drop them. */
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 	while (!data->txfree || data->txhead != data->txtail) {
1404*4882a593Smuzhiyun 		int tx = data->txtail;
1405*4882a593Smuzhiyun 		struct sk_buff *skb;
1406*4882a593Smuzhiyun 		skb = data->txskbs[tx];
1407*4882a593Smuzhiyun 		data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
1408*4882a593Smuzhiyun 		data->txfree++;
1409*4882a593Smuzhiyun 		dev_kfree_skb(skb);
1410*4882a593Smuzhiyun 	}
1411*4882a593Smuzhiyun 
1412*4882a593Smuzhiyun 	free_irq(data->irq_num, dev);
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	/* Discard the RX ring. */
1415*4882a593Smuzhiyun 
1416*4882a593Smuzhiyun 	while (data->rxfree) {
1417*4882a593Smuzhiyun 		int rx = data->rxtail;
1418*4882a593Smuzhiyun 		struct sk_buff *skb;
1419*4882a593Smuzhiyun 
1420*4882a593Smuzhiyun 		skb = data->rxskbs[rx];
1421*4882a593Smuzhiyun 		data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
1422*4882a593Smuzhiyun 		data->rxfree--;
1423*4882a593Smuzhiyun 		dev_kfree_skb(skb);
1424*4882a593Smuzhiyun 	}
1425*4882a593Smuzhiyun 
1426*4882a593Smuzhiyun 	dma_free_coherent(&data->pdev->dev,
1427*4882a593Smuzhiyun 			    TSI108_RXRING_LEN * sizeof(rx_desc),
1428*4882a593Smuzhiyun 			    data->rxring, data->rxdma);
1429*4882a593Smuzhiyun 	dma_free_coherent(&data->pdev->dev,
1430*4882a593Smuzhiyun 			    TSI108_TXRING_LEN * sizeof(tx_desc),
1431*4882a593Smuzhiyun 			    data->txring, data->txdma);
1432*4882a593Smuzhiyun 
1433*4882a593Smuzhiyun 	return 0;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun 
tsi108_init_mac(struct net_device * dev)1436*4882a593Smuzhiyun static void tsi108_init_mac(struct net_device *dev)
1437*4882a593Smuzhiyun {
1438*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_CFG2, TSI108_MAC_CFG2_DFLT_PREAMBLE |
1441*4882a593Smuzhiyun 			     TSI108_MAC_CFG2_PADCRC);
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXTHRESH,
1444*4882a593Smuzhiyun 			     (192 << TSI108_EC_TXTHRESH_STARTFILL) |
1445*4882a593Smuzhiyun 			     (192 << TSI108_EC_TXTHRESH_STOPFILL));
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun 	TSI_WRITE(TSI108_STAT_CARRYMASK1,
1448*4882a593Smuzhiyun 			     ~(TSI108_STAT_CARRY1_RXBYTES |
1449*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXPKTS |
1450*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXFCS |
1451*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXMCAST |
1452*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXALIGN |
1453*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXLENGTH |
1454*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXRUNT |
1455*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXJUMBO |
1456*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXFRAG |
1457*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXJABBER |
1458*4882a593Smuzhiyun 			       TSI108_STAT_CARRY1_RXDROP));
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 	TSI_WRITE(TSI108_STAT_CARRYMASK2,
1461*4882a593Smuzhiyun 			     ~(TSI108_STAT_CARRY2_TXBYTES |
1462*4882a593Smuzhiyun 			       TSI108_STAT_CARRY2_TXPKTS |
1463*4882a593Smuzhiyun 			       TSI108_STAT_CARRY2_TXEXDEF |
1464*4882a593Smuzhiyun 			       TSI108_STAT_CARRY2_TXEXCOL |
1465*4882a593Smuzhiyun 			       TSI108_STAT_CARRY2_TXTCOL |
1466*4882a593Smuzhiyun 			       TSI108_STAT_CARRY2_TXPAUSE));
1467*4882a593Smuzhiyun 
1468*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATEN);
1469*4882a593Smuzhiyun 	TSI_WRITE(TSI108_MAC_CFG1, 0);
1470*4882a593Smuzhiyun 
1471*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXCFG,
1472*4882a593Smuzhiyun 			     TSI108_EC_RXCFG_SE | TSI108_EC_RXCFG_BFE);
1473*4882a593Smuzhiyun 
1474*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXQ_CFG, TSI108_EC_TXQ_CFG_DESC_INT |
1475*4882a593Smuzhiyun 			     TSI108_EC_TXQ_CFG_EOQ_OWN_INT |
1476*4882a593Smuzhiyun 			     TSI108_EC_TXQ_CFG_WSWP | (TSI108_PBM_PORT <<
1477*4882a593Smuzhiyun 						TSI108_EC_TXQ_CFG_SFNPORT));
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXQ_CFG, TSI108_EC_RXQ_CFG_DESC_INT |
1480*4882a593Smuzhiyun 			     TSI108_EC_RXQ_CFG_EOQ_OWN_INT |
1481*4882a593Smuzhiyun 			     TSI108_EC_RXQ_CFG_WSWP | (TSI108_PBM_PORT <<
1482*4882a593Smuzhiyun 						TSI108_EC_RXQ_CFG_SFNPORT));
1483*4882a593Smuzhiyun 
1484*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_TXQ_BUFCFG,
1485*4882a593Smuzhiyun 			     TSI108_EC_TXQ_BUFCFG_BURST256 |
1486*4882a593Smuzhiyun 			     TSI108_EC_TXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
1487*4882a593Smuzhiyun 						TSI108_EC_TXQ_BUFCFG_SFNPORT));
1488*4882a593Smuzhiyun 
1489*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_RXQ_BUFCFG,
1490*4882a593Smuzhiyun 			     TSI108_EC_RXQ_BUFCFG_BURST256 |
1491*4882a593Smuzhiyun 			     TSI108_EC_RXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
1492*4882a593Smuzhiyun 						TSI108_EC_RXQ_BUFCFG_SFNPORT));
1493*4882a593Smuzhiyun 
1494*4882a593Smuzhiyun 	TSI_WRITE(TSI108_EC_INTMASK, ~0);
1495*4882a593Smuzhiyun }
1496*4882a593Smuzhiyun 
tsi108_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1497*4882a593Smuzhiyun static int tsi108_get_link_ksettings(struct net_device *dev,
1498*4882a593Smuzhiyun 				     struct ethtool_link_ksettings *cmd)
1499*4882a593Smuzhiyun {
1500*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1501*4882a593Smuzhiyun 	unsigned long flags;
1502*4882a593Smuzhiyun 
1503*4882a593Smuzhiyun 	spin_lock_irqsave(&data->txlock, flags);
1504*4882a593Smuzhiyun 	mii_ethtool_get_link_ksettings(&data->mii_if, cmd);
1505*4882a593Smuzhiyun 	spin_unlock_irqrestore(&data->txlock, flags);
1506*4882a593Smuzhiyun 
1507*4882a593Smuzhiyun 	return 0;
1508*4882a593Smuzhiyun }
1509*4882a593Smuzhiyun 
tsi108_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1510*4882a593Smuzhiyun static int tsi108_set_link_ksettings(struct net_device *dev,
1511*4882a593Smuzhiyun 				     const struct ethtool_link_ksettings *cmd)
1512*4882a593Smuzhiyun {
1513*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1514*4882a593Smuzhiyun 	unsigned long flags;
1515*4882a593Smuzhiyun 	int rc;
1516*4882a593Smuzhiyun 
1517*4882a593Smuzhiyun 	spin_lock_irqsave(&data->txlock, flags);
1518*4882a593Smuzhiyun 	rc = mii_ethtool_set_link_ksettings(&data->mii_if, cmd);
1519*4882a593Smuzhiyun 	spin_unlock_irqrestore(&data->txlock, flags);
1520*4882a593Smuzhiyun 
1521*4882a593Smuzhiyun 	return rc;
1522*4882a593Smuzhiyun }
1523*4882a593Smuzhiyun 
tsi108_do_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1524*4882a593Smuzhiyun static int tsi108_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1525*4882a593Smuzhiyun {
1526*4882a593Smuzhiyun 	struct tsi108_prv_data *data = netdev_priv(dev);
1527*4882a593Smuzhiyun 	if (!netif_running(dev))
1528*4882a593Smuzhiyun 		return -EINVAL;
1529*4882a593Smuzhiyun 	return generic_mii_ioctl(&data->mii_if, if_mii(rq), cmd, NULL);
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun static const struct ethtool_ops tsi108_ethtool_ops = {
1533*4882a593Smuzhiyun 	.get_link 	= ethtool_op_get_link,
1534*4882a593Smuzhiyun 	.get_link_ksettings	= tsi108_get_link_ksettings,
1535*4882a593Smuzhiyun 	.set_link_ksettings	= tsi108_set_link_ksettings,
1536*4882a593Smuzhiyun };
1537*4882a593Smuzhiyun 
1538*4882a593Smuzhiyun static const struct net_device_ops tsi108_netdev_ops = {
1539*4882a593Smuzhiyun 	.ndo_open		= tsi108_open,
1540*4882a593Smuzhiyun 	.ndo_stop		= tsi108_close,
1541*4882a593Smuzhiyun 	.ndo_start_xmit		= tsi108_send_packet,
1542*4882a593Smuzhiyun 	.ndo_set_rx_mode	= tsi108_set_rx_mode,
1543*4882a593Smuzhiyun 	.ndo_get_stats		= tsi108_get_stats,
1544*4882a593Smuzhiyun 	.ndo_do_ioctl		= tsi108_do_ioctl,
1545*4882a593Smuzhiyun 	.ndo_set_mac_address	= tsi108_set_mac,
1546*4882a593Smuzhiyun 	.ndo_validate_addr	= eth_validate_addr,
1547*4882a593Smuzhiyun };
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun static int
tsi108_init_one(struct platform_device * pdev)1550*4882a593Smuzhiyun tsi108_init_one(struct platform_device *pdev)
1551*4882a593Smuzhiyun {
1552*4882a593Smuzhiyun 	struct net_device *dev = NULL;
1553*4882a593Smuzhiyun 	struct tsi108_prv_data *data = NULL;
1554*4882a593Smuzhiyun 	hw_info *einfo;
1555*4882a593Smuzhiyun 	int err = 0;
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	einfo = dev_get_platdata(&pdev->dev);
1558*4882a593Smuzhiyun 
1559*4882a593Smuzhiyun 	if (NULL == einfo) {
1560*4882a593Smuzhiyun 		printk(KERN_ERR "tsi-eth %d: Missing additional data!\n",
1561*4882a593Smuzhiyun 		       pdev->id);
1562*4882a593Smuzhiyun 		return -ENODEV;
1563*4882a593Smuzhiyun 	}
1564*4882a593Smuzhiyun 
1565*4882a593Smuzhiyun 	/* Create an ethernet device instance */
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun 	dev = alloc_etherdev(sizeof(struct tsi108_prv_data));
1568*4882a593Smuzhiyun 	if (!dev)
1569*4882a593Smuzhiyun 		return -ENOMEM;
1570*4882a593Smuzhiyun 
1571*4882a593Smuzhiyun 	printk("tsi108_eth%d: probe...\n", pdev->id);
1572*4882a593Smuzhiyun 	data = netdev_priv(dev);
1573*4882a593Smuzhiyun 	data->dev = dev;
1574*4882a593Smuzhiyun 	data->pdev = pdev;
1575*4882a593Smuzhiyun 
1576*4882a593Smuzhiyun 	pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n",
1577*4882a593Smuzhiyun 			pdev->id, einfo->regs, einfo->phyregs,
1578*4882a593Smuzhiyun 			einfo->phy, einfo->irq_num);
1579*4882a593Smuzhiyun 
1580*4882a593Smuzhiyun 	data->regs = ioremap(einfo->regs, 0x400);
1581*4882a593Smuzhiyun 	if (NULL == data->regs) {
1582*4882a593Smuzhiyun 		err = -ENOMEM;
1583*4882a593Smuzhiyun 		goto regs_fail;
1584*4882a593Smuzhiyun 	}
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun 	data->phyregs = ioremap(einfo->phyregs, 0x400);
1587*4882a593Smuzhiyun 	if (NULL == data->phyregs) {
1588*4882a593Smuzhiyun 		err = -ENOMEM;
1589*4882a593Smuzhiyun 		goto phyregs_fail;
1590*4882a593Smuzhiyun 	}
1591*4882a593Smuzhiyun /* MII setup */
1592*4882a593Smuzhiyun 	data->mii_if.dev = dev;
1593*4882a593Smuzhiyun 	data->mii_if.mdio_read = tsi108_mdio_read;
1594*4882a593Smuzhiyun 	data->mii_if.mdio_write = tsi108_mdio_write;
1595*4882a593Smuzhiyun 	data->mii_if.phy_id = einfo->phy;
1596*4882a593Smuzhiyun 	data->mii_if.phy_id_mask = 0x1f;
1597*4882a593Smuzhiyun 	data->mii_if.reg_num_mask = 0x1f;
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 	data->phy = einfo->phy;
1600*4882a593Smuzhiyun 	data->phy_type = einfo->phy_type;
1601*4882a593Smuzhiyun 	data->irq_num = einfo->irq_num;
1602*4882a593Smuzhiyun 	data->id = pdev->id;
1603*4882a593Smuzhiyun 	netif_napi_add(dev, &data->napi, tsi108_poll, 64);
1604*4882a593Smuzhiyun 	dev->netdev_ops = &tsi108_netdev_ops;
1605*4882a593Smuzhiyun 	dev->ethtool_ops = &tsi108_ethtool_ops;
1606*4882a593Smuzhiyun 
1607*4882a593Smuzhiyun 	/* Apparently, the Linux networking code won't use scatter-gather
1608*4882a593Smuzhiyun 	 * if the hardware doesn't do checksums.  However, it's faster
1609*4882a593Smuzhiyun 	 * to checksum in place and use SG, as (among other reasons)
1610*4882a593Smuzhiyun 	 * the cache won't be dirtied (which then has to be flushed
1611*4882a593Smuzhiyun 	 * before DMA).  The checksumming is done by the driver (via
1612*4882a593Smuzhiyun 	 * a new function skb_csum_dev() in net/core/skbuff.c).
1613*4882a593Smuzhiyun 	 */
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 	dev->features = NETIF_F_HIGHDMA;
1616*4882a593Smuzhiyun 
1617*4882a593Smuzhiyun 	spin_lock_init(&data->txlock);
1618*4882a593Smuzhiyun 	spin_lock_init(&data->misclock);
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 	tsi108_reset_ether(data);
1621*4882a593Smuzhiyun 	tsi108_kill_phy(dev);
1622*4882a593Smuzhiyun 
1623*4882a593Smuzhiyun 	if ((err = tsi108_get_mac(dev)) != 0) {
1624*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Invalid MAC address.  Please correct.\n",
1625*4882a593Smuzhiyun 		       dev->name);
1626*4882a593Smuzhiyun 		goto register_fail;
1627*4882a593Smuzhiyun 	}
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 	tsi108_init_mac(dev);
1630*4882a593Smuzhiyun 	err = register_netdev(dev);
1631*4882a593Smuzhiyun 	if (err) {
1632*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1633*4882a593Smuzhiyun 				dev->name);
1634*4882a593Smuzhiyun 		goto register_fail;
1635*4882a593Smuzhiyun 	}
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 	platform_set_drvdata(pdev, dev);
1638*4882a593Smuzhiyun 	printk(KERN_INFO "%s: Tsi108 Gigabit Ethernet, MAC: %pM\n",
1639*4882a593Smuzhiyun 	       dev->name, dev->dev_addr);
1640*4882a593Smuzhiyun #ifdef DEBUG
1641*4882a593Smuzhiyun 	data->msg_enable = DEBUG;
1642*4882a593Smuzhiyun 	dump_eth_one(dev);
1643*4882a593Smuzhiyun #endif
1644*4882a593Smuzhiyun 
1645*4882a593Smuzhiyun 	return 0;
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun register_fail:
1648*4882a593Smuzhiyun 	iounmap(data->phyregs);
1649*4882a593Smuzhiyun 
1650*4882a593Smuzhiyun phyregs_fail:
1651*4882a593Smuzhiyun 	iounmap(data->regs);
1652*4882a593Smuzhiyun 
1653*4882a593Smuzhiyun regs_fail:
1654*4882a593Smuzhiyun 	free_netdev(dev);
1655*4882a593Smuzhiyun 	return err;
1656*4882a593Smuzhiyun }
1657*4882a593Smuzhiyun 
1658*4882a593Smuzhiyun /* There's no way to either get interrupts from the PHY when
1659*4882a593Smuzhiyun  * something changes, or to have the Tsi108 automatically communicate
1660*4882a593Smuzhiyun  * with the PHY to reconfigure itself.
1661*4882a593Smuzhiyun  *
1662*4882a593Smuzhiyun  * Thus, we have to do it using a timer.
1663*4882a593Smuzhiyun  */
1664*4882a593Smuzhiyun 
tsi108_timed_checker(struct timer_list * t)1665*4882a593Smuzhiyun static void tsi108_timed_checker(struct timer_list *t)
1666*4882a593Smuzhiyun {
1667*4882a593Smuzhiyun 	struct tsi108_prv_data *data = from_timer(data, t, timer);
1668*4882a593Smuzhiyun 	struct net_device *dev = data->dev;
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun 	tsi108_check_phy(dev);
1671*4882a593Smuzhiyun 	tsi108_check_rxring(dev);
1672*4882a593Smuzhiyun 	mod_timer(&data->timer, jiffies + CHECK_PHY_INTERVAL);
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun 
tsi108_ether_remove(struct platform_device * pdev)1675*4882a593Smuzhiyun static int tsi108_ether_remove(struct platform_device *pdev)
1676*4882a593Smuzhiyun {
1677*4882a593Smuzhiyun 	struct net_device *dev = platform_get_drvdata(pdev);
1678*4882a593Smuzhiyun 	struct tsi108_prv_data *priv = netdev_priv(dev);
1679*4882a593Smuzhiyun 
1680*4882a593Smuzhiyun 	unregister_netdev(dev);
1681*4882a593Smuzhiyun 	tsi108_stop_ethernet(dev);
1682*4882a593Smuzhiyun 	iounmap(priv->regs);
1683*4882a593Smuzhiyun 	iounmap(priv->phyregs);
1684*4882a593Smuzhiyun 	free_netdev(dev);
1685*4882a593Smuzhiyun 
1686*4882a593Smuzhiyun 	return 0;
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun module_platform_driver(tsi_eth_driver);
1689*4882a593Smuzhiyun 
1690*4882a593Smuzhiyun MODULE_AUTHOR("Tundra Semiconductor Corporation");
1691*4882a593Smuzhiyun MODULE_DESCRIPTION("Tsi108 Gigabit Ethernet driver");
1692*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1693*4882a593Smuzhiyun MODULE_ALIAS("platform:tsi-ethernet");
1694