1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SGMI module initialisation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated
6*4882a593Smuzhiyun * Authors: Sandeep Nair <sandeep_n@ti.com>
7*4882a593Smuzhiyun * Sandeep Paulraj <s-paulraj@ti.com>
8*4882a593Smuzhiyun * Wingman Kwok <w-kwok2@ti.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "netcp.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define SGMII_SRESET_RESET BIT(0)
15*4882a593Smuzhiyun #define SGMII_SRESET_RTRESET BIT(1)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define SGMII_REG_STATUS_LOCK BIT(4)
18*4882a593Smuzhiyun #define SGMII_REG_STATUS_LINK BIT(0)
19*4882a593Smuzhiyun #define SGMII_REG_STATUS_AUTONEG BIT(2)
20*4882a593Smuzhiyun #define SGMII_REG_CONTROL_AUTONEG BIT(0)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SGMII23_OFFSET(x) ((x - 2) * 0x100)
23*4882a593Smuzhiyun #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x)))
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* SGMII registers */
26*4882a593Smuzhiyun #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004)
27*4882a593Smuzhiyun #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010)
28*4882a593Smuzhiyun #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014)
29*4882a593Smuzhiyun #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018)
30*4882a593Smuzhiyun
sgmii_write_reg(void __iomem * base,int reg,u32 val)31*4882a593Smuzhiyun static void sgmii_write_reg(void __iomem *base, int reg, u32 val)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun writel(val, base + reg);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
sgmii_read_reg(void __iomem * base,int reg)36*4882a593Smuzhiyun static u32 sgmii_read_reg(void __iomem *base, int reg)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun return readl(base + reg);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
sgmii_write_reg_bit(void __iomem * base,int reg,u32 val)41*4882a593Smuzhiyun static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun writel((readl(base + reg) | val), base + reg);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* port is 0 based */
netcp_sgmii_reset(void __iomem * sgmii_ofs,int port)47*4882a593Smuzhiyun int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun /* Soft reset */
50*4882a593Smuzhiyun sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port),
51*4882a593Smuzhiyun SGMII_SRESET_RESET);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun while ((sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) &
54*4882a593Smuzhiyun SGMII_SRESET_RESET) != 0x0)
55*4882a593Smuzhiyun ;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* port is 0 based */
netcp_sgmii_rtreset(void __iomem * sgmii_ofs,int port,bool set)61*4882a593Smuzhiyun bool netcp_sgmii_rtreset(void __iomem *sgmii_ofs, int port, bool set)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun u32 reg;
64*4882a593Smuzhiyun bool oldval;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Initiate a soft reset */
67*4882a593Smuzhiyun reg = sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port));
68*4882a593Smuzhiyun oldval = (reg & SGMII_SRESET_RTRESET) != 0x0;
69*4882a593Smuzhiyun if (set)
70*4882a593Smuzhiyun reg |= SGMII_SRESET_RTRESET;
71*4882a593Smuzhiyun else
72*4882a593Smuzhiyun reg &= ~SGMII_SRESET_RTRESET;
73*4882a593Smuzhiyun sgmii_write_reg(sgmii_ofs, SGMII_SRESET_REG(port), reg);
74*4882a593Smuzhiyun wmb();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return oldval;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
netcp_sgmii_get_port_link(void __iomem * sgmii_ofs,int port)79*4882a593Smuzhiyun int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun u32 status = 0, link = 0;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
84*4882a593Smuzhiyun if ((status & SGMII_REG_STATUS_LINK) != 0)
85*4882a593Smuzhiyun link = 1;
86*4882a593Smuzhiyun return link;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
netcp_sgmii_config(void __iomem * sgmii_ofs,int port,u32 interface)89*4882a593Smuzhiyun int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun unsigned int i, status, mask;
92*4882a593Smuzhiyun u32 mr_adv_ability;
93*4882a593Smuzhiyun u32 control;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun switch (interface) {
96*4882a593Smuzhiyun case SGMII_LINK_MAC_MAC_AUTONEG:
97*4882a593Smuzhiyun mr_adv_ability = 0x9801;
98*4882a593Smuzhiyun control = 0x21;
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun case SGMII_LINK_MAC_PHY:
102*4882a593Smuzhiyun case SGMII_LINK_MAC_PHY_NO_MDIO:
103*4882a593Smuzhiyun mr_adv_ability = 1;
104*4882a593Smuzhiyun control = 1;
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun case SGMII_LINK_MAC_MAC_FORCED:
108*4882a593Smuzhiyun mr_adv_ability = 0x9801;
109*4882a593Smuzhiyun control = 0x20;
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun case SGMII_LINK_MAC_FIBER:
113*4882a593Smuzhiyun mr_adv_ability = 0x20;
114*4882a593Smuzhiyun control = 0x1;
115*4882a593Smuzhiyun break;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun default:
118*4882a593Smuzhiyun WARN_ONCE(1, "Invalid sgmii interface: %d\n", interface);
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), 0);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Wait for the SerDes pll to lock */
125*4882a593Smuzhiyun for (i = 0; i < 1000; i++) {
126*4882a593Smuzhiyun usleep_range(1000, 2000);
127*4882a593Smuzhiyun status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
128*4882a593Smuzhiyun if ((status & SGMII_REG_STATUS_LOCK) != 0)
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if ((status & SGMII_REG_STATUS_LOCK) == 0)
133*4882a593Smuzhiyun pr_err("serdes PLL not locked\n");
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun sgmii_write_reg(sgmii_ofs, SGMII_MRADV_REG(port), mr_adv_ability);
136*4882a593Smuzhiyun sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), control);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun mask = SGMII_REG_STATUS_LINK;
139*4882a593Smuzhiyun if (control & SGMII_REG_CONTROL_AUTONEG)
140*4882a593Smuzhiyun mask |= SGMII_REG_STATUS_AUTONEG;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun for (i = 0; i < 1000; i++) {
143*4882a593Smuzhiyun usleep_range(200, 500);
144*4882a593Smuzhiyun status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
145*4882a593Smuzhiyun if ((status & mask) == mask)
146*4882a593Smuzhiyun break;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun }
151