1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Texas Instruments CPDMA Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __DAVINCI_CPDMA_H__ 9*4882a593Smuzhiyun #define __DAVINCI_CPDMA_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CPDMA_MAX_CHANNELS BITS_PER_LONG 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPDMA_RX_VLAN_ENCAP BIT(19) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CPDMA_EOI_RX_THRESH 0x0 18*4882a593Smuzhiyun #define CPDMA_EOI_RX 0x1 19*4882a593Smuzhiyun #define CPDMA_EOI_TX 0x2 20*4882a593Smuzhiyun #define CPDMA_EOI_MISC 0x3 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct cpdma_params { 23*4882a593Smuzhiyun struct device *dev; 24*4882a593Smuzhiyun void __iomem *dmaregs; 25*4882a593Smuzhiyun void __iomem *txhdp, *rxhdp, *txcp, *rxcp; 26*4882a593Smuzhiyun void __iomem *rxthresh, *rxfree; 27*4882a593Smuzhiyun int num_chan; 28*4882a593Smuzhiyun bool has_soft_reset; 29*4882a593Smuzhiyun int min_packet_size; 30*4882a593Smuzhiyun dma_addr_t desc_mem_phys; 31*4882a593Smuzhiyun dma_addr_t desc_hw_addr; 32*4882a593Smuzhiyun int desc_mem_size; 33*4882a593Smuzhiyun int desc_align; 34*4882a593Smuzhiyun u32 bus_freq_mhz; 35*4882a593Smuzhiyun u32 descs_pool_size; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Some instances of embedded cpdma controllers have extra control and 39*4882a593Smuzhiyun * status registers. The following flag enables access to these 40*4882a593Smuzhiyun * "extended" registers. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun bool has_ext_regs; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct cpdma_chan_stats { 46*4882a593Smuzhiyun u32 head_enqueue; 47*4882a593Smuzhiyun u32 tail_enqueue; 48*4882a593Smuzhiyun u32 pad_enqueue; 49*4882a593Smuzhiyun u32 misqueued; 50*4882a593Smuzhiyun u32 desc_alloc_fail; 51*4882a593Smuzhiyun u32 pad_alloc_fail; 52*4882a593Smuzhiyun u32 runt_receive_buff; 53*4882a593Smuzhiyun u32 runt_transmit_buff; 54*4882a593Smuzhiyun u32 empty_dequeue; 55*4882a593Smuzhiyun u32 busy_dequeue; 56*4882a593Smuzhiyun u32 good_dequeue; 57*4882a593Smuzhiyun u32 requeue; 58*4882a593Smuzhiyun u32 teardown_dequeue; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct cpdma_ctlr; 62*4882a593Smuzhiyun struct cpdma_chan; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun typedef void (*cpdma_handler_fn)(void *token, int len, int status); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params); 67*4882a593Smuzhiyun int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr); 68*4882a593Smuzhiyun int cpdma_ctlr_start(struct cpdma_ctlr *ctlr); 69*4882a593Smuzhiyun int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, 72*4882a593Smuzhiyun cpdma_handler_fn handler, int rx_type); 73*4882a593Smuzhiyun int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan); 74*4882a593Smuzhiyun int cpdma_chan_destroy(struct cpdma_chan *chan); 75*4882a593Smuzhiyun int cpdma_chan_start(struct cpdma_chan *chan); 76*4882a593Smuzhiyun int cpdma_chan_stop(struct cpdma_chan *chan); 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun int cpdma_chan_get_stats(struct cpdma_chan *chan, 79*4882a593Smuzhiyun struct cpdma_chan_stats *stats); 80*4882a593Smuzhiyun int cpdma_chan_submit_mapped(struct cpdma_chan *chan, void *token, 81*4882a593Smuzhiyun dma_addr_t data, int len, int directed); 82*4882a593Smuzhiyun int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, 83*4882a593Smuzhiyun int len, int directed); 84*4882a593Smuzhiyun int cpdma_chan_idle_submit_mapped(struct cpdma_chan *chan, void *token, 85*4882a593Smuzhiyun dma_addr_t data, int len, int directed); 86*4882a593Smuzhiyun int cpdma_chan_idle_submit(struct cpdma_chan *chan, void *token, void *data, 87*4882a593Smuzhiyun int len, int directed); 88*4882a593Smuzhiyun int cpdma_chan_process(struct cpdma_chan *chan, int quota); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable); 91*4882a593Smuzhiyun void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value); 92*4882a593Smuzhiyun int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable); 93*4882a593Smuzhiyun u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr); 94*4882a593Smuzhiyun u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr); 95*4882a593Smuzhiyun bool cpdma_check_free_tx_desc(struct cpdma_chan *chan); 96*4882a593Smuzhiyun int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight); 97*4882a593Smuzhiyun int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate); 98*4882a593Smuzhiyun u32 cpdma_chan_get_rate(struct cpdma_chan *ch); 99*4882a593Smuzhiyun u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun enum cpdma_control { 102*4882a593Smuzhiyun CPDMA_TX_RLIM, /* read-write */ 103*4882a593Smuzhiyun CPDMA_CMD_IDLE, /* write-only */ 104*4882a593Smuzhiyun CPDMA_COPY_ERROR_FRAMES, /* read-write */ 105*4882a593Smuzhiyun CPDMA_RX_OFF_LEN_UPDATE, /* read-write */ 106*4882a593Smuzhiyun CPDMA_RX_OWNERSHIP_FLIP, /* read-write */ 107*4882a593Smuzhiyun CPDMA_TX_PRIO_FIXED, /* read-write */ 108*4882a593Smuzhiyun CPDMA_STAT_IDLE, /* read-only */ 109*4882a593Smuzhiyun CPDMA_STAT_TX_ERR_CHAN, /* read-only */ 110*4882a593Smuzhiyun CPDMA_STAT_TX_ERR_CODE, /* read-only */ 111*4882a593Smuzhiyun CPDMA_STAT_RX_ERR_CHAN, /* read-only */ 112*4882a593Smuzhiyun CPDMA_STAT_RX_ERR_CODE, /* read-only */ 113*4882a593Smuzhiyun CPDMA_RX_BUFFER_OFFSET, /* read-write */ 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun int cpdma_control_get(struct cpdma_ctlr *ctlr, int control); 117*4882a593Smuzhiyun int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value); 118*4882a593Smuzhiyun int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr); 119*4882a593Smuzhiyun int cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc); 120*4882a593Smuzhiyun int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr); 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif 123