1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/ 4*4882a593Smuzhiyun * Ethernet MAC Sliver (CPGMAC_SL) APIs 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2019 Texas Instruments 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __TI_CPSW_SL_H__ 11*4882a593Smuzhiyun #define __TI_CPSW_SL_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/device.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum cpsw_sl_regs { 16*4882a593Smuzhiyun CPSW_SL_IDVER, 17*4882a593Smuzhiyun CPSW_SL_MACCONTROL, 18*4882a593Smuzhiyun CPSW_SL_MACSTATUS, 19*4882a593Smuzhiyun CPSW_SL_SOFT_RESET, 20*4882a593Smuzhiyun CPSW_SL_RX_MAXLEN, 21*4882a593Smuzhiyun CPSW_SL_BOFFTEST, 22*4882a593Smuzhiyun CPSW_SL_RX_PAUSE, 23*4882a593Smuzhiyun CPSW_SL_TX_PAUSE, 24*4882a593Smuzhiyun CPSW_SL_EMCONTROL, 25*4882a593Smuzhiyun CPSW_SL_RX_PRI_MAP, 26*4882a593Smuzhiyun CPSW_SL_TX_GAP, 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum { 30*4882a593Smuzhiyun CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */ 31*4882a593Smuzhiyun CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */ 32*4882a593Smuzhiyun CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */ 33*4882a593Smuzhiyun CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */ 34*4882a593Smuzhiyun CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */ 35*4882a593Smuzhiyun CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */ 36*4882a593Smuzhiyun CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */ 37*4882a593Smuzhiyun CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */ 38*4882a593Smuzhiyun CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */ 39*4882a593Smuzhiyun CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */ 40*4882a593Smuzhiyun CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */ 41*4882a593Smuzhiyun CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */ 42*4882a593Smuzhiyun CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */ 43*4882a593Smuzhiyun CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */ 44*4882a593Smuzhiyun CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */ 45*4882a593Smuzhiyun CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */ 46*4882a593Smuzhiyun CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */ 47*4882a593Smuzhiyun CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */ 48*4882a593Smuzhiyun CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */ 49*4882a593Smuzhiyun CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */ 50*4882a593Smuzhiyun CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */ 51*4882a593Smuzhiyun CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */ 52*4882a593Smuzhiyun CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */ 53*4882a593Smuzhiyun CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun CPSW_SL_CTL_FUNCS_COUNT 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct cpsw_sl; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev, 61*4882a593Smuzhiyun void __iomem *sl_base); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs); 66*4882a593Smuzhiyun u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs); 67*4882a593Smuzhiyun void cpsw_sl_ctl_reset(struct cpsw_sl *sl); 68*4882a593Smuzhiyun int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg); 71*4882a593Smuzhiyun void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __TI_CPSW_SL_H__ */ 74