1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef AM65_CPSW_NUSS_H_ 7*4882a593Smuzhiyun #define AM65_CPSW_NUSS_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/kernel.h> 10*4882a593Smuzhiyun #include <linux/module.h> 11*4882a593Smuzhiyun #include <linux/netdevice.h> 12*4882a593Smuzhiyun #include <linux/phy.h> 13*4882a593Smuzhiyun #include <linux/platform_device.h> 14*4882a593Smuzhiyun #include "am65-cpsw-qos.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct am65_cpts; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define HOST_PORT_NUM 0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AM65_CPSW_MAX_TX_QUEUES 8 21*4882a593Smuzhiyun #define AM65_CPSW_MAX_RX_QUEUES 1 22*4882a593Smuzhiyun #define AM65_CPSW_MAX_RX_FLOWS 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct am65_cpsw_slave_data { 25*4882a593Smuzhiyun bool mac_only; 26*4882a593Smuzhiyun struct cpsw_sl *mac_sl; 27*4882a593Smuzhiyun struct device_node *phy_node; 28*4882a593Smuzhiyun struct phy_device *phy; 29*4882a593Smuzhiyun phy_interface_t phy_if; 30*4882a593Smuzhiyun struct phy *ifphy; 31*4882a593Smuzhiyun bool rx_pause; 32*4882a593Smuzhiyun bool tx_pause; 33*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct am65_cpsw_port { 37*4882a593Smuzhiyun struct am65_cpsw_common *common; 38*4882a593Smuzhiyun struct net_device *ndev; 39*4882a593Smuzhiyun const char *name; 40*4882a593Smuzhiyun u32 port_id; 41*4882a593Smuzhiyun void __iomem *port_base; 42*4882a593Smuzhiyun void __iomem *stat_base; 43*4882a593Smuzhiyun void __iomem *fetch_ram_base; 44*4882a593Smuzhiyun bool disabled; 45*4882a593Smuzhiyun struct am65_cpsw_slave_data slave; 46*4882a593Smuzhiyun bool tx_ts_enabled; 47*4882a593Smuzhiyun bool rx_ts_enabled; 48*4882a593Smuzhiyun struct am65_cpsw_qos qos; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct am65_cpsw_host { 52*4882a593Smuzhiyun struct am65_cpsw_common *common; 53*4882a593Smuzhiyun void __iomem *port_base; 54*4882a593Smuzhiyun void __iomem *stat_base; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct am65_cpsw_tx_chn { 58*4882a593Smuzhiyun struct napi_struct napi_tx; 59*4882a593Smuzhiyun struct am65_cpsw_common *common; 60*4882a593Smuzhiyun struct k3_cppi_desc_pool *desc_pool; 61*4882a593Smuzhiyun struct k3_udma_glue_tx_channel *tx_chn; 62*4882a593Smuzhiyun int irq; 63*4882a593Smuzhiyun u32 id; 64*4882a593Smuzhiyun u32 descs_num; 65*4882a593Smuzhiyun char tx_chn_name[128]; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct am65_cpsw_rx_chn { 69*4882a593Smuzhiyun struct device *dev; 70*4882a593Smuzhiyun struct k3_cppi_desc_pool *desc_pool; 71*4882a593Smuzhiyun struct k3_udma_glue_rx_channel *rx_chn; 72*4882a593Smuzhiyun u32 descs_num; 73*4882a593Smuzhiyun int irq; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct am65_cpsw_pdata { 79*4882a593Smuzhiyun u32 quirks; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct am65_cpsw_common { 83*4882a593Smuzhiyun struct device *dev; 84*4882a593Smuzhiyun struct device *mdio_dev; 85*4882a593Smuzhiyun struct am65_cpsw_pdata pdata; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun void __iomem *ss_base; 88*4882a593Smuzhiyun void __iomem *cpsw_base; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun u32 port_num; 91*4882a593Smuzhiyun struct am65_cpsw_host host; 92*4882a593Smuzhiyun struct am65_cpsw_port *ports; 93*4882a593Smuzhiyun u32 disabled_ports_mask; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun int usage_count; /* number of opened ports */ 96*4882a593Smuzhiyun struct cpsw_ale *ale; 97*4882a593Smuzhiyun int tx_ch_num; 98*4882a593Smuzhiyun u32 rx_flow_id_base; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES]; 101*4882a593Smuzhiyun struct completion tdown_complete; 102*4882a593Smuzhiyun atomic_t tdown_cnt; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct am65_cpsw_rx_chn rx_chns; 105*4882a593Smuzhiyun struct napi_struct napi_rx; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun u32 nuss_ver; 108*4882a593Smuzhiyun u32 cpsw_ver; 109*4882a593Smuzhiyun unsigned long bus_freq; 110*4882a593Smuzhiyun bool pf_p0_rx_ptype_rrobin; 111*4882a593Smuzhiyun struct am65_cpts *cpts; 112*4882a593Smuzhiyun int est_enabled; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct am65_cpsw_ndev_stats { 116*4882a593Smuzhiyun u64 tx_packets; 117*4882a593Smuzhiyun u64 tx_bytes; 118*4882a593Smuzhiyun u64 rx_packets; 119*4882a593Smuzhiyun u64 rx_bytes; 120*4882a593Smuzhiyun struct u64_stats_sync syncp; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct am65_cpsw_ndev_priv { 124*4882a593Smuzhiyun u32 msg_enable; 125*4882a593Smuzhiyun struct am65_cpsw_port *port; 126*4882a593Smuzhiyun struct am65_cpsw_ndev_stats __percpu *stats; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define am65_ndev_to_priv(ndev) \ 130*4882a593Smuzhiyun ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev)) 131*4882a593Smuzhiyun #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port) 132*4882a593Smuzhiyun #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common) 133*4882a593Smuzhiyun #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define am65_common_get_host(common) (&(common)->host) 136*4882a593Smuzhiyun #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1]) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define am65_cpsw_napi_to_common(pnapi) \ 139*4882a593Smuzhiyun container_of(pnapi, struct am65_cpsw_common, napi_rx) 140*4882a593Smuzhiyun #define am65_cpsw_napi_to_tx_chn(pnapi) \ 141*4882a593Smuzhiyun container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss" 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun void am65_cpsw_nuss_adjust_link(struct net_device *ndev); 150*4882a593Smuzhiyun void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common); 151*4882a593Smuzhiyun void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common); 152*4882a593Smuzhiyun int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx); 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #endif /* AM65_CPSW_NUSS_H_ */ 155